13a280ed1SRyder Lee /* SPDX-License-Identifier: GPL-2.0 */ 2d6f3710aSGarlic Tseng /* 3d6f3710aSGarlic Tseng * mt2701-afe-clock-ctrl.h -- Mediatek 2701 afe clock ctrl definition 4d6f3710aSGarlic Tseng * 5d6f3710aSGarlic Tseng * Copyright (c) 2016 MediaTek Inc. 6d6f3710aSGarlic Tseng * Author: Garlic Tseng <garlic.tseng@mediatek.com> 7cf870273SRyder Lee * Ryder Lee <ryder.lee@mediatek.com> 8d6f3710aSGarlic Tseng */ 9d6f3710aSGarlic Tseng 10d6f3710aSGarlic Tseng #ifndef _MT2701_AFE_CLOCK_CTRL_H_ 11d6f3710aSGarlic Tseng #define _MT2701_AFE_CLOCK_CTRL_H_ 12d6f3710aSGarlic Tseng 13d6f3710aSGarlic Tseng struct mtk_base_afe; 14cf870273SRyder Lee struct mt2701_i2s_path; 15d6f3710aSGarlic Tseng 16d6f3710aSGarlic Tseng int mt2701_init_clock(struct mtk_base_afe *afe); 17d6f3710aSGarlic Tseng int mt2701_afe_enable_clock(struct mtk_base_afe *afe); 18d8d99d8eSRyder Lee int mt2701_afe_disable_clock(struct mtk_base_afe *afe); 19d6f3710aSGarlic Tseng 20cf870273SRyder Lee int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, 21*57f1379eSPierre-Louis Bossart struct mt2701_i2s_path *i2s_path, 22cf870273SRyder Lee int dir); 23cf870273SRyder Lee void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, 24*57f1379eSPierre-Louis Bossart struct mt2701_i2s_path *i2s_path, 25cf870273SRyder Lee int dir); 26d8d99d8eSRyder Lee int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id); 27d8d99d8eSRyder Lee void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id); 28d6f3710aSGarlic Tseng 29d8d99d8eSRyder Lee int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe); 30d8d99d8eSRyder Lee void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe); 31d6f3710aSGarlic Tseng 32cf870273SRyder Lee int mt2701_mclk_configuration(struct mtk_base_afe *afe, int id); 33d6f3710aSGarlic Tseng 34d6f3710aSGarlic Tseng #endif 35