xref: /linux/sound/soc/jz4740/jz4740-i2s.c (revision da1d9caf95def6f0320819cf941c9fd1069ba9e1) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4  */
5 
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
14 
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 
18 #include <linux/dma-mapping.h>
19 
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/initval.h>
25 #include <sound/dmaengine_pcm.h>
26 
27 #include "jz4740-i2s.h"
28 
29 #define JZ_REG_AIC_CONF		0x00
30 #define JZ_REG_AIC_CTRL		0x04
31 #define JZ_REG_AIC_I2S_FMT	0x10
32 #define JZ_REG_AIC_FIFO_STATUS	0x14
33 #define JZ_REG_AIC_I2S_STATUS	0x1c
34 #define JZ_REG_AIC_CLK_DIV	0x30
35 #define JZ_REG_AIC_FIFO		0x34
36 
37 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
38 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
39 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
40 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
41 #define JZ_AIC_CONF_I2S BIT(4)
42 #define JZ_AIC_CONF_RESET BIT(3)
43 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
44 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
45 #define JZ_AIC_CONF_ENABLE BIT(0)
46 
47 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
48 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
49 #define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
50 #define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
51 
52 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
53 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
54 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
55 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
56 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
57 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
58 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
59 #define JZ_AIC_CTRL_FLUSH		BIT(8)
60 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
61 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
62 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
63 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
64 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
65 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
66 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
67 
68 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
69 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16
70 
71 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
72 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
73 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
74 #define JZ_AIC_I2S_FMT_MSB BIT(0)
75 
76 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
77 
78 #define JZ_AIC_CLK_DIV_MASK 0xf
79 #define I2SDIV_DV_SHIFT 0
80 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
81 #define I2SDIV_IDV_SHIFT 8
82 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)
83 
84 enum jz47xx_i2s_version {
85 	JZ_I2S_JZ4740,
86 	JZ_I2S_JZ4760,
87 	JZ_I2S_JZ4770,
88 	JZ_I2S_JZ4780,
89 };
90 
91 struct i2s_soc_info {
92 	enum jz47xx_i2s_version version;
93 	struct snd_soc_dai_driver *dai;
94 };
95 
96 struct jz4740_i2s {
97 	struct resource *mem;
98 	void __iomem *base;
99 	dma_addr_t phys_base;
100 
101 	struct clk *clk_aic;
102 	struct clk *clk_i2s;
103 
104 	struct snd_dmaengine_dai_dma_data playback_dma_data;
105 	struct snd_dmaengine_dai_dma_data capture_dma_data;
106 
107 	const struct i2s_soc_info *soc_info;
108 };
109 
110 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
111 	unsigned int reg)
112 {
113 	return readl(i2s->base + reg);
114 }
115 
116 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
117 	unsigned int reg, uint32_t value)
118 {
119 	writel(value, i2s->base + reg);
120 }
121 
122 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
123 	struct snd_soc_dai *dai)
124 {
125 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
126 	uint32_t conf, ctrl;
127 	int ret;
128 
129 	if (snd_soc_dai_active(dai))
130 		return 0;
131 
132 	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
133 	ctrl |= JZ_AIC_CTRL_FLUSH;
134 	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
135 
136 	ret = clk_prepare_enable(i2s->clk_i2s);
137 	if (ret)
138 		return ret;
139 
140 	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
141 	conf |= JZ_AIC_CONF_ENABLE;
142 	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
143 
144 	return 0;
145 }
146 
147 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
148 	struct snd_soc_dai *dai)
149 {
150 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
151 	uint32_t conf;
152 
153 	if (snd_soc_dai_active(dai))
154 		return;
155 
156 	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
157 	conf &= ~JZ_AIC_CONF_ENABLE;
158 	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
159 
160 	clk_disable_unprepare(i2s->clk_i2s);
161 }
162 
163 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
164 	struct snd_soc_dai *dai)
165 {
166 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
167 
168 	uint32_t ctrl;
169 	uint32_t mask;
170 
171 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
172 		mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
173 	else
174 		mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
175 
176 	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
177 
178 	switch (cmd) {
179 	case SNDRV_PCM_TRIGGER_START:
180 	case SNDRV_PCM_TRIGGER_RESUME:
181 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
182 		ctrl |= mask;
183 		break;
184 	case SNDRV_PCM_TRIGGER_STOP:
185 	case SNDRV_PCM_TRIGGER_SUSPEND:
186 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
187 		ctrl &= ~mask;
188 		break;
189 	default:
190 		return -EINVAL;
191 	}
192 
193 	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
194 
195 	return 0;
196 }
197 
198 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
199 {
200 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
201 
202 	uint32_t format = 0;
203 	uint32_t conf;
204 
205 	conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
206 
207 	conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
208 
209 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
210 	case SND_SOC_DAIFMT_CBS_CFS:
211 		conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
212 		format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
213 		break;
214 	case SND_SOC_DAIFMT_CBM_CFS:
215 		conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
216 		break;
217 	case SND_SOC_DAIFMT_CBS_CFM:
218 		conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
219 		break;
220 	case SND_SOC_DAIFMT_CBM_CFM:
221 		break;
222 	default:
223 		return -EINVAL;
224 	}
225 
226 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
227 	case SND_SOC_DAIFMT_MSB:
228 		format |= JZ_AIC_I2S_FMT_MSB;
229 		break;
230 	case SND_SOC_DAIFMT_I2S:
231 		break;
232 	default:
233 		return -EINVAL;
234 	}
235 
236 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
237 	case SND_SOC_DAIFMT_NB_NF:
238 		break;
239 	default:
240 		return -EINVAL;
241 	}
242 
243 	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
244 	jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
245 
246 	return 0;
247 }
248 
249 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
250 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
251 {
252 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
253 	unsigned int sample_size;
254 	uint32_t ctrl, div_reg;
255 	int div;
256 
257 	ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
258 
259 	div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
260 	div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
261 
262 	switch (params_format(params)) {
263 	case SNDRV_PCM_FORMAT_S8:
264 		sample_size = 0;
265 		break;
266 	case SNDRV_PCM_FORMAT_S16:
267 		sample_size = 1;
268 		break;
269 	default:
270 		return -EINVAL;
271 	}
272 
273 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
274 		ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
275 		ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
276 		if (params_channels(params) == 1)
277 			ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
278 		else
279 			ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
280 
281 		div_reg &= ~I2SDIV_DV_MASK;
282 		div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
283 	} else {
284 		ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
285 		ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
286 
287 		if (i2s->soc_info->version >= JZ_I2S_JZ4770) {
288 			div_reg &= ~I2SDIV_IDV_MASK;
289 			div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
290 		} else {
291 			div_reg &= ~I2SDIV_DV_MASK;
292 			div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
293 		}
294 	}
295 
296 	jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
297 	jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
298 
299 	return 0;
300 }
301 
302 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
303 	unsigned int freq, int dir)
304 {
305 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
306 	struct clk *parent;
307 	int ret = 0;
308 
309 	switch (clk_id) {
310 	case JZ4740_I2S_CLKSRC_EXT:
311 		parent = clk_get(NULL, "ext");
312 		if (IS_ERR(parent))
313 			return PTR_ERR(parent);
314 		clk_set_parent(i2s->clk_i2s, parent);
315 		break;
316 	case JZ4740_I2S_CLKSRC_PLL:
317 		parent = clk_get(NULL, "pll half");
318 		if (IS_ERR(parent))
319 			return PTR_ERR(parent);
320 		clk_set_parent(i2s->clk_i2s, parent);
321 		ret = clk_set_rate(i2s->clk_i2s, freq);
322 		break;
323 	default:
324 		return -EINVAL;
325 	}
326 	clk_put(parent);
327 
328 	return ret;
329 }
330 
331 static int jz4740_i2s_suspend(struct snd_soc_component *component)
332 {
333 	struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
334 	uint32_t conf;
335 
336 	if (snd_soc_component_active(component)) {
337 		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
338 		conf &= ~JZ_AIC_CONF_ENABLE;
339 		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
340 
341 		clk_disable_unprepare(i2s->clk_i2s);
342 	}
343 
344 	clk_disable_unprepare(i2s->clk_aic);
345 
346 	return 0;
347 }
348 
349 static int jz4740_i2s_resume(struct snd_soc_component *component)
350 {
351 	struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
352 	uint32_t conf;
353 	int ret;
354 
355 	ret = clk_prepare_enable(i2s->clk_aic);
356 	if (ret)
357 		return ret;
358 
359 	if (snd_soc_component_active(component)) {
360 		ret = clk_prepare_enable(i2s->clk_i2s);
361 		if (ret) {
362 			clk_disable_unprepare(i2s->clk_aic);
363 			return ret;
364 		}
365 
366 		conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
367 		conf |= JZ_AIC_CONF_ENABLE;
368 		jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
369 	}
370 
371 	return 0;
372 }
373 
374 static void jz4740_i2s_init_pcm_config(struct jz4740_i2s *i2s)
375 {
376 	struct snd_dmaengine_dai_dma_data *dma_data;
377 
378 	/* Playback */
379 	dma_data = &i2s->playback_dma_data;
380 	dma_data->maxburst = 16;
381 	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
382 
383 	/* Capture */
384 	dma_data = &i2s->capture_dma_data;
385 	dma_data->maxburst = 16;
386 	dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
387 }
388 
389 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
390 {
391 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
392 	uint32_t conf;
393 	int ret;
394 
395 	ret = clk_prepare_enable(i2s->clk_aic);
396 	if (ret)
397 		return ret;
398 
399 	jz4740_i2s_init_pcm_config(i2s);
400 	snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
401 		&i2s->capture_dma_data);
402 
403 	if (i2s->soc_info->version >= JZ_I2S_JZ4760) {
404 		conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
405 			(8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
406 			JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
407 			JZ_AIC_CONF_I2S |
408 			JZ_AIC_CONF_INTERNAL_CODEC;
409 	} else {
410 		conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
411 			(8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
412 			JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
413 			JZ_AIC_CONF_I2S |
414 			JZ_AIC_CONF_INTERNAL_CODEC;
415 	}
416 
417 	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
418 	jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
419 
420 	return 0;
421 }
422 
423 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
424 {
425 	struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
426 
427 	clk_disable_unprepare(i2s->clk_aic);
428 	return 0;
429 }
430 
431 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
432 	.startup = jz4740_i2s_startup,
433 	.shutdown = jz4740_i2s_shutdown,
434 	.trigger = jz4740_i2s_trigger,
435 	.hw_params = jz4740_i2s_hw_params,
436 	.set_fmt = jz4740_i2s_set_fmt,
437 	.set_sysclk = jz4740_i2s_set_sysclk,
438 };
439 
440 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
441 		SNDRV_PCM_FMTBIT_S16_LE)
442 
443 static struct snd_soc_dai_driver jz4740_i2s_dai = {
444 	.probe = jz4740_i2s_dai_probe,
445 	.remove = jz4740_i2s_dai_remove,
446 	.playback = {
447 		.channels_min = 1,
448 		.channels_max = 2,
449 		.rates = SNDRV_PCM_RATE_8000_48000,
450 		.formats = JZ4740_I2S_FMTS,
451 	},
452 	.capture = {
453 		.channels_min = 2,
454 		.channels_max = 2,
455 		.rates = SNDRV_PCM_RATE_8000_48000,
456 		.formats = JZ4740_I2S_FMTS,
457 	},
458 	.symmetric_rate = 1,
459 	.ops = &jz4740_i2s_dai_ops,
460 };
461 
462 static const struct i2s_soc_info jz4740_i2s_soc_info = {
463 	.version = JZ_I2S_JZ4740,
464 	.dai = &jz4740_i2s_dai,
465 };
466 
467 static const struct i2s_soc_info jz4760_i2s_soc_info = {
468 	.version = JZ_I2S_JZ4760,
469 	.dai = &jz4740_i2s_dai,
470 };
471 
472 static struct snd_soc_dai_driver jz4770_i2s_dai = {
473 	.probe = jz4740_i2s_dai_probe,
474 	.remove = jz4740_i2s_dai_remove,
475 	.playback = {
476 		.channels_min = 1,
477 		.channels_max = 2,
478 		.rates = SNDRV_PCM_RATE_8000_48000,
479 		.formats = JZ4740_I2S_FMTS,
480 	},
481 	.capture = {
482 		.channels_min = 2,
483 		.channels_max = 2,
484 		.rates = SNDRV_PCM_RATE_8000_48000,
485 		.formats = JZ4740_I2S_FMTS,
486 	},
487 	.ops = &jz4740_i2s_dai_ops,
488 };
489 
490 static const struct i2s_soc_info jz4770_i2s_soc_info = {
491 	.version = JZ_I2S_JZ4770,
492 	.dai = &jz4770_i2s_dai,
493 };
494 
495 static const struct i2s_soc_info jz4780_i2s_soc_info = {
496 	.version = JZ_I2S_JZ4780,
497 	.dai = &jz4770_i2s_dai,
498 };
499 
500 static const struct snd_soc_component_driver jz4740_i2s_component = {
501 	.name		= "jz4740-i2s",
502 	.suspend	= jz4740_i2s_suspend,
503 	.resume		= jz4740_i2s_resume,
504 };
505 
506 static const struct of_device_id jz4740_of_matches[] = {
507 	{ .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info },
508 	{ .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info },
509 	{ .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info },
510 	{ .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info },
511 	{ /* sentinel */ }
512 };
513 MODULE_DEVICE_TABLE(of, jz4740_of_matches);
514 
515 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
516 {
517 	struct device *dev = &pdev->dev;
518 	struct jz4740_i2s *i2s;
519 	struct resource *mem;
520 	int ret;
521 
522 	i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
523 	if (!i2s)
524 		return -ENOMEM;
525 
526 	i2s->soc_info = device_get_match_data(dev);
527 
528 	i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
529 	if (IS_ERR(i2s->base))
530 		return PTR_ERR(i2s->base);
531 
532 	i2s->phys_base = mem->start;
533 
534 	i2s->clk_aic = devm_clk_get(dev, "aic");
535 	if (IS_ERR(i2s->clk_aic))
536 		return PTR_ERR(i2s->clk_aic);
537 
538 	i2s->clk_i2s = devm_clk_get(dev, "i2s");
539 	if (IS_ERR(i2s->clk_i2s))
540 		return PTR_ERR(i2s->clk_i2s);
541 
542 	platform_set_drvdata(pdev, i2s);
543 
544 	ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component,
545 					      i2s->soc_info->dai, 1);
546 	if (ret)
547 		return ret;
548 
549 	return devm_snd_dmaengine_pcm_register(dev, NULL,
550 		SND_DMAENGINE_PCM_FLAG_COMPAT);
551 }
552 
553 static struct platform_driver jz4740_i2s_driver = {
554 	.probe = jz4740_i2s_dev_probe,
555 	.driver = {
556 		.name = "jz4740-i2s",
557 		.of_match_table = jz4740_of_matches,
558 	},
559 };
560 
561 module_platform_driver(jz4740_i2s_driver);
562 
563 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
564 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
565 MODULE_LICENSE("GPL");
566 MODULE_ALIAS("platform:jz4740-i2s");
567