1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> 4 */ 5 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/platform_device.h> 12 #include <linux/slab.h> 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 17 #include <linux/dma-mapping.h> 18 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/initval.h> 24 #include <sound/dmaengine_pcm.h> 25 26 #include "jz4740-i2s.h" 27 28 #define JZ_REG_AIC_CONF 0x00 29 #define JZ_REG_AIC_CTRL 0x04 30 #define JZ_REG_AIC_I2S_FMT 0x10 31 #define JZ_REG_AIC_FIFO_STATUS 0x14 32 #define JZ_REG_AIC_I2S_STATUS 0x1c 33 #define JZ_REG_AIC_CLK_DIV 0x30 34 #define JZ_REG_AIC_FIFO 0x34 35 36 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12) 37 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8) 38 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) 39 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) 40 #define JZ_AIC_CONF_I2S BIT(4) 41 #define JZ_AIC_CONF_RESET BIT(3) 42 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) 43 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) 44 #define JZ_AIC_CONF_ENABLE BIT(0) 45 46 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12 47 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8 48 #define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24 49 #define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16 50 51 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) 52 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) 53 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) 54 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) 55 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) 56 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) 57 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) 58 #define JZ_AIC_CTRL_FLUSH BIT(8) 59 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) 60 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) 61 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) 62 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) 63 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) 64 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) 65 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) 66 67 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 68 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 69 70 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) 71 #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) 72 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) 73 #define JZ_AIC_I2S_FMT_MSB BIT(0) 74 75 #define JZ_AIC_I2S_STATUS_BUSY BIT(2) 76 77 #define JZ_AIC_CLK_DIV_MASK 0xf 78 #define I2SDIV_DV_SHIFT 0 79 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) 80 #define I2SDIV_IDV_SHIFT 8 81 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) 82 83 enum jz47xx_i2s_version { 84 JZ_I2S_JZ4740, 85 JZ_I2S_JZ4760, 86 JZ_I2S_JZ4770, 87 JZ_I2S_JZ4780, 88 }; 89 90 struct i2s_soc_info { 91 enum jz47xx_i2s_version version; 92 struct snd_soc_dai_driver *dai; 93 }; 94 95 struct jz4740_i2s { 96 struct resource *mem; 97 void __iomem *base; 98 99 struct clk *clk_aic; 100 struct clk *clk_i2s; 101 102 struct snd_dmaengine_dai_dma_data playback_dma_data; 103 struct snd_dmaengine_dai_dma_data capture_dma_data; 104 105 const struct i2s_soc_info *soc_info; 106 }; 107 108 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, 109 unsigned int reg) 110 { 111 return readl(i2s->base + reg); 112 } 113 114 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, 115 unsigned int reg, uint32_t value) 116 { 117 writel(value, i2s->base + reg); 118 } 119 120 static int jz4740_i2s_startup(struct snd_pcm_substream *substream, 121 struct snd_soc_dai *dai) 122 { 123 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 124 uint32_t conf, ctrl; 125 int ret; 126 127 if (snd_soc_dai_active(dai)) 128 return 0; 129 130 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); 131 ctrl |= JZ_AIC_CTRL_FLUSH; 132 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); 133 134 ret = clk_prepare_enable(i2s->clk_i2s); 135 if (ret) 136 return ret; 137 138 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 139 conf |= JZ_AIC_CONF_ENABLE; 140 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 141 142 return 0; 143 } 144 145 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, 146 struct snd_soc_dai *dai) 147 { 148 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 149 uint32_t conf; 150 151 if (snd_soc_dai_active(dai)) 152 return; 153 154 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 155 conf &= ~JZ_AIC_CONF_ENABLE; 156 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 157 158 clk_disable_unprepare(i2s->clk_i2s); 159 } 160 161 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 162 struct snd_soc_dai *dai) 163 { 164 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 165 166 uint32_t ctrl; 167 uint32_t mask; 168 169 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 170 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA; 171 else 172 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; 173 174 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); 175 176 switch (cmd) { 177 case SNDRV_PCM_TRIGGER_START: 178 case SNDRV_PCM_TRIGGER_RESUME: 179 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 180 ctrl |= mask; 181 break; 182 case SNDRV_PCM_TRIGGER_STOP: 183 case SNDRV_PCM_TRIGGER_SUSPEND: 184 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 185 ctrl &= ~mask; 186 break; 187 default: 188 return -EINVAL; 189 } 190 191 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); 192 193 return 0; 194 } 195 196 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 197 { 198 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 199 200 uint32_t format = 0; 201 uint32_t conf; 202 203 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 204 205 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER); 206 207 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 208 case SND_SOC_DAIFMT_BP_FP: 209 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER; 210 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK; 211 break; 212 case SND_SOC_DAIFMT_BC_FP: 213 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER; 214 break; 215 case SND_SOC_DAIFMT_BP_FC: 216 conf |= JZ_AIC_CONF_BIT_CLK_MASTER; 217 break; 218 case SND_SOC_DAIFMT_BC_FC: 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 225 case SND_SOC_DAIFMT_MSB: 226 format |= JZ_AIC_I2S_FMT_MSB; 227 break; 228 case SND_SOC_DAIFMT_I2S: 229 break; 230 default: 231 return -EINVAL; 232 } 233 234 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 235 case SND_SOC_DAIFMT_NB_NF: 236 break; 237 default: 238 return -EINVAL; 239 } 240 241 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 242 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format); 243 244 return 0; 245 } 246 247 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, 248 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 249 { 250 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 251 unsigned int sample_size; 252 uint32_t ctrl, div_reg; 253 int div; 254 255 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); 256 257 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); 258 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); 259 260 switch (params_format(params)) { 261 case SNDRV_PCM_FORMAT_S8: 262 sample_size = 0; 263 break; 264 case SNDRV_PCM_FORMAT_S16: 265 sample_size = 1; 266 break; 267 default: 268 return -EINVAL; 269 } 270 271 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 272 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK; 273 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET; 274 if (params_channels(params) == 1) 275 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; 276 else 277 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; 278 279 div_reg &= ~I2SDIV_DV_MASK; 280 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; 281 } else { 282 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; 283 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; 284 285 if (i2s->soc_info->version >= JZ_I2S_JZ4770) { 286 div_reg &= ~I2SDIV_IDV_MASK; 287 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; 288 } else { 289 div_reg &= ~I2SDIV_DV_MASK; 290 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; 291 } 292 } 293 294 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); 295 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); 296 297 return 0; 298 } 299 300 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, 301 unsigned int freq, int dir) 302 { 303 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 304 struct clk *parent; 305 int ret = 0; 306 307 switch (clk_id) { 308 case JZ4740_I2S_CLKSRC_EXT: 309 parent = clk_get(NULL, "ext"); 310 if (IS_ERR(parent)) 311 return PTR_ERR(parent); 312 clk_set_parent(i2s->clk_i2s, parent); 313 break; 314 case JZ4740_I2S_CLKSRC_PLL: 315 parent = clk_get(NULL, "pll half"); 316 if (IS_ERR(parent)) 317 return PTR_ERR(parent); 318 clk_set_parent(i2s->clk_i2s, parent); 319 ret = clk_set_rate(i2s->clk_i2s, freq); 320 break; 321 default: 322 return -EINVAL; 323 } 324 clk_put(parent); 325 326 return ret; 327 } 328 329 static int jz4740_i2s_suspend(struct snd_soc_component *component) 330 { 331 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 332 uint32_t conf; 333 334 if (snd_soc_component_active(component)) { 335 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 336 conf &= ~JZ_AIC_CONF_ENABLE; 337 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 338 339 clk_disable_unprepare(i2s->clk_i2s); 340 } 341 342 clk_disable_unprepare(i2s->clk_aic); 343 344 return 0; 345 } 346 347 static int jz4740_i2s_resume(struct snd_soc_component *component) 348 { 349 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); 350 uint32_t conf; 351 int ret; 352 353 ret = clk_prepare_enable(i2s->clk_aic); 354 if (ret) 355 return ret; 356 357 if (snd_soc_component_active(component)) { 358 ret = clk_prepare_enable(i2s->clk_i2s); 359 if (ret) { 360 clk_disable_unprepare(i2s->clk_aic); 361 return ret; 362 } 363 364 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); 365 conf |= JZ_AIC_CONF_ENABLE; 366 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 367 } 368 369 return 0; 370 } 371 372 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) 373 { 374 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 375 uint32_t conf; 376 int ret; 377 378 ret = clk_prepare_enable(i2s->clk_aic); 379 if (ret) 380 return ret; 381 382 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, 383 &i2s->capture_dma_data); 384 385 if (i2s->soc_info->version >= JZ_I2S_JZ4760) { 386 conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | 387 (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | 388 JZ_AIC_CONF_OVERFLOW_PLAY_LAST | 389 JZ_AIC_CONF_I2S | 390 JZ_AIC_CONF_INTERNAL_CODEC; 391 } else { 392 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | 393 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | 394 JZ_AIC_CONF_OVERFLOW_PLAY_LAST | 395 JZ_AIC_CONF_I2S | 396 JZ_AIC_CONF_INTERNAL_CODEC; 397 } 398 399 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); 400 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); 401 402 return 0; 403 } 404 405 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) 406 { 407 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); 408 409 clk_disable_unprepare(i2s->clk_aic); 410 return 0; 411 } 412 413 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { 414 .startup = jz4740_i2s_startup, 415 .shutdown = jz4740_i2s_shutdown, 416 .trigger = jz4740_i2s_trigger, 417 .hw_params = jz4740_i2s_hw_params, 418 .set_fmt = jz4740_i2s_set_fmt, 419 .set_sysclk = jz4740_i2s_set_sysclk, 420 }; 421 422 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 423 SNDRV_PCM_FMTBIT_S16_LE) 424 425 static struct snd_soc_dai_driver jz4740_i2s_dai = { 426 .probe = jz4740_i2s_dai_probe, 427 .remove = jz4740_i2s_dai_remove, 428 .playback = { 429 .channels_min = 1, 430 .channels_max = 2, 431 .rates = SNDRV_PCM_RATE_8000_48000, 432 .formats = JZ4740_I2S_FMTS, 433 }, 434 .capture = { 435 .channels_min = 2, 436 .channels_max = 2, 437 .rates = SNDRV_PCM_RATE_8000_48000, 438 .formats = JZ4740_I2S_FMTS, 439 }, 440 .symmetric_rate = 1, 441 .ops = &jz4740_i2s_dai_ops, 442 }; 443 444 static const struct i2s_soc_info jz4740_i2s_soc_info = { 445 .version = JZ_I2S_JZ4740, 446 .dai = &jz4740_i2s_dai, 447 }; 448 449 static const struct i2s_soc_info jz4760_i2s_soc_info = { 450 .version = JZ_I2S_JZ4760, 451 .dai = &jz4740_i2s_dai, 452 }; 453 454 static struct snd_soc_dai_driver jz4770_i2s_dai = { 455 .probe = jz4740_i2s_dai_probe, 456 .remove = jz4740_i2s_dai_remove, 457 .playback = { 458 .channels_min = 1, 459 .channels_max = 2, 460 .rates = SNDRV_PCM_RATE_8000_48000, 461 .formats = JZ4740_I2S_FMTS, 462 }, 463 .capture = { 464 .channels_min = 2, 465 .channels_max = 2, 466 .rates = SNDRV_PCM_RATE_8000_48000, 467 .formats = JZ4740_I2S_FMTS, 468 }, 469 .ops = &jz4740_i2s_dai_ops, 470 }; 471 472 static const struct i2s_soc_info jz4770_i2s_soc_info = { 473 .version = JZ_I2S_JZ4770, 474 .dai = &jz4770_i2s_dai, 475 }; 476 477 static const struct i2s_soc_info jz4780_i2s_soc_info = { 478 .version = JZ_I2S_JZ4780, 479 .dai = &jz4770_i2s_dai, 480 }; 481 482 static const struct snd_soc_component_driver jz4740_i2s_component = { 483 .name = "jz4740-i2s", 484 .suspend = jz4740_i2s_suspend, 485 .resume = jz4740_i2s_resume, 486 .legacy_dai_naming = 1, 487 }; 488 489 static const struct of_device_id jz4740_of_matches[] = { 490 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info }, 491 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info }, 492 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info }, 493 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info }, 494 { /* sentinel */ } 495 }; 496 MODULE_DEVICE_TABLE(of, jz4740_of_matches); 497 498 static int jz4740_i2s_dev_probe(struct platform_device *pdev) 499 { 500 struct device *dev = &pdev->dev; 501 struct jz4740_i2s *i2s; 502 struct resource *mem; 503 int ret; 504 505 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); 506 if (!i2s) 507 return -ENOMEM; 508 509 i2s->soc_info = device_get_match_data(dev); 510 511 i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 512 if (IS_ERR(i2s->base)) 513 return PTR_ERR(i2s->base); 514 515 i2s->playback_dma_data.maxburst = 16; 516 i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 517 518 i2s->capture_dma_data.maxburst = 16; 519 i2s->capture_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; 520 521 i2s->clk_aic = devm_clk_get(dev, "aic"); 522 if (IS_ERR(i2s->clk_aic)) 523 return PTR_ERR(i2s->clk_aic); 524 525 i2s->clk_i2s = devm_clk_get(dev, "i2s"); 526 if (IS_ERR(i2s->clk_i2s)) 527 return PTR_ERR(i2s->clk_i2s); 528 529 platform_set_drvdata(pdev, i2s); 530 531 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, 532 i2s->soc_info->dai, 1); 533 if (ret) 534 return ret; 535 536 return devm_snd_dmaengine_pcm_register(dev, NULL, 537 SND_DMAENGINE_PCM_FLAG_COMPAT); 538 } 539 540 static struct platform_driver jz4740_i2s_driver = { 541 .probe = jz4740_i2s_dev_probe, 542 .driver = { 543 .name = "jz4740-i2s", 544 .of_match_table = jz4740_of_matches, 545 }, 546 }; 547 548 module_platform_driver(jz4740_i2s_driver); 549 550 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>"); 551 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver"); 552 MODULE_LICENSE("GPL"); 553 MODULE_ALIAS("platform:jz4740-i2s"); 554