1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2021-2025 Intel Corporation 4 * 5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 */ 8 9 #include <sound/hdaudio_ext.h> 10 #include "avs.h" 11 #include "registers.h" 12 #include "trace.h" 13 14 #define MTL_HfDSSGBL_BASE 0x1000 15 #define MTL_REG_HfDSSCS (MTL_HfDSSGBL_BASE + 0x0) 16 #define MTL_HfDSSCS_SPA BIT(16) 17 #define MTL_HfDSSCS_CPA BIT(24) 18 19 #define MTL_DSPCS_BASE 0x178D00 20 #define MTL_REG_DSPCCTL (MTL_DSPCS_BASE + 0x4) 21 #define MTL_DSPCCTL_SPA BIT(0) 22 #define MTL_DSPCCTL_CPA BIT(8) 23 #define MTL_DSPCCTL_OSEL GENMASK(25, 24) 24 #define MTL_DSPCCTL_OSEL_HOST BIT(25) 25 26 #define MTL_HfINT_BASE 0x1100 27 #define MTL_REG_HfINTIPPTR (MTL_HfINT_BASE + 0x8) 28 #define MTL_REG_HfHIPCIE (MTL_HfINT_BASE + 0x40) 29 #define MTL_HfINTIPPTR_PTR GENMASK(20, 0) 30 #define MTL_HfHIPCIE_IE BIT(0) 31 32 #define MTL_DWICTL_INTENL_IE BIT(0) 33 #define MTL_DWICTL_FINALSTATUSL_IPC BIT(0) /* same as ADSPIS_IPC */ 34 35 static int avs_mtl_core_power_on(struct avs_dev *adev) 36 { 37 u32 reg; 38 int ret; 39 40 /* Power up DSP domain. */ 41 snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, MTL_HfDSSCS_SPA); 42 trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "power dsp", true); 43 44 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg, 45 (reg & MTL_HfDSSCS_CPA) == MTL_HfDSSCS_CPA, 46 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 47 if (ret) { 48 dev_err(adev->dev, "power on domain dsp failed: %d\n", ret); 49 return ret; 50 } 51 52 /* Prevent power gating of DSP domain. */ 53 snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL, MTL_HfPWRCTL_WPDSPHPxPG, 54 MTL_HfPWRCTL_WPDSPHPxPG); 55 trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "prevent dsp PG", true); 56 57 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfPWRSTS, reg, 58 (reg & MTL_HfPWRSTS_DSPHPxPGS) == MTL_HfPWRSTS_DSPHPxPGS, 59 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 60 61 /* Set ownership to HOST. */ 62 snd_hdac_adsp_updatel(adev, MTL_REG_DSPCCTL, MTL_DSPCCTL_OSEL, MTL_DSPCCTL_OSEL_HOST); 63 return ret; 64 } 65 66 static int avs_mtl_core_power_off(struct avs_dev *adev) 67 { 68 u32 reg; 69 70 /* Allow power gating of DSP domain. No STS polling as HOST is only one of its users. */ 71 snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL, MTL_HfPWRCTL_WPDSPHPxPG, 0); 72 trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "allow dsp pg", false); 73 74 /* Power down DSP domain. */ 75 snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, 0); 76 trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "power dsp", false); 77 78 return snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg, 79 (reg & MTL_HfDSSCS_CPA) == 0, 80 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 81 } 82 83 int avs_mtl_core_power(struct avs_dev *adev, u32 core_mask, bool power) 84 { 85 core_mask &= AVS_MAIN_CORE_MASK; 86 if (!core_mask) 87 return 0; 88 89 if (power) 90 return avs_mtl_core_power_on(adev); 91 return avs_mtl_core_power_off(adev); 92 } 93 94 int avs_mtl_core_reset(struct avs_dev *adev, u32 core_mask, bool power) 95 { 96 /* No logical equivalent on ACE 1.x. */ 97 return 0; 98 } 99 100 int avs_mtl_core_stall(struct avs_dev *adev, u32 core_mask, bool stall) 101 { 102 u32 value, reg; 103 int ret; 104 105 core_mask &= AVS_MAIN_CORE_MASK; 106 if (!core_mask) 107 return 0; 108 109 value = snd_hdac_adsp_readl(adev, MTL_REG_DSPCCTL); 110 trace_avs_dsp_core_op(value, core_mask, "stall", stall); 111 if (value == UINT_MAX) 112 return 0; 113 114 value = stall ? 0 : MTL_DSPCCTL_SPA; 115 snd_hdac_adsp_updatel(adev, MTL_REG_DSPCCTL, MTL_DSPCCTL_SPA, value); 116 117 value = stall ? 0 : MTL_DSPCCTL_CPA; 118 ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_DSPCCTL, 119 reg, (reg & MTL_DSPCCTL_CPA) == value, 120 AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US); 121 if (ret) 122 dev_err(adev->dev, "core_mask %d %sstall failed: %d\n", 123 core_mask, stall ? "" : "un", ret); 124 return ret; 125 } 126 127 static void avs_mtl_ipc_interrupt(struct avs_dev *adev) 128 { 129 const struct avs_spec *spec = adev->spec; 130 u32 hipc_ack, hipc_rsp; 131 132 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset, 133 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY, 0); 134 135 hipc_ack = snd_hdac_adsp_readl(adev, spec->hipc->ack_offset); 136 hipc_rsp = snd_hdac_adsp_readl(adev, spec->hipc->rsp_offset); 137 138 /* DSP acked host's request. */ 139 if (hipc_ack & spec->hipc->ack_done_mask) { 140 complete(&adev->ipc->done_completion); 141 142 /* Tell DSP it has our attention. */ 143 snd_hdac_adsp_updatel(adev, spec->hipc->ack_offset, spec->hipc->ack_done_mask, 144 spec->hipc->ack_done_mask); 145 } 146 147 /* DSP sent new response to process. */ 148 if (hipc_rsp & spec->hipc->rsp_busy_mask) { 149 union avs_reply_msg msg; 150 151 msg.primary = snd_hdac_adsp_readl(adev, MTL_REG_HfIPCxTDR); 152 msg.ext.val = snd_hdac_adsp_readl(adev, MTL_REG_HfIPCxTDD); 153 154 avs_dsp_process_response(adev, msg.val); 155 156 /* Tell DSP we accepted its message. */ 157 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxTDR, 158 MTL_HfIPCxTDR_BUSY, MTL_HfIPCxTDR_BUSY); 159 /* Ack this response. */ 160 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxTDA, MTL_HfIPCxTDA_BUSY, 0); 161 } 162 163 snd_hdac_adsp_updatel(adev, spec->hipc->ctl_offset, 164 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY, 165 AVS_ADSP_HIPCCTL_DONE | AVS_ADSP_HIPCCTL_BUSY); 166 } 167 168 irqreturn_t avs_mtl_dsp_interrupt(struct avs_dev *adev) 169 { 170 u32 adspis = snd_hdac_adsp_readl(adev, MTL_DWICTL_REG_FINALSTATUSL); 171 irqreturn_t ret = IRQ_NONE; 172 173 if (adspis == UINT_MAX) 174 return ret; 175 176 if (adspis & MTL_DWICTL_FINALSTATUSL_IPC) { 177 avs_mtl_ipc_interrupt(adev); 178 ret = IRQ_HANDLED; 179 } 180 181 return ret; 182 } 183 184 void avs_mtl_interrupt_control(struct avs_dev *adev, bool enable) 185 { 186 if (enable) { 187 snd_hdac_adsp_updatel(adev, MTL_DWICTL_REG_INTENL, MTL_DWICTL_INTENL_IE, 188 MTL_DWICTL_INTENL_IE); 189 snd_hdac_adsp_updatew(adev, MTL_REG_HfHIPCIE, MTL_HfHIPCIE_IE, MTL_HfHIPCIE_IE); 190 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_DONE, 191 AVS_ADSP_HIPCCTL_DONE); 192 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_BUSY, 193 AVS_ADSP_HIPCCTL_BUSY); 194 } else { 195 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_BUSY, 0); 196 snd_hdac_adsp_updatel(adev, MTL_REG_HfIPCxCTL, AVS_ADSP_HIPCCTL_DONE, 0); 197 snd_hdac_adsp_updatew(adev, MTL_REG_HfHIPCIE, MTL_HfHIPCIE_IE, 0); 198 snd_hdac_adsp_updatel(adev, MTL_DWICTL_REG_INTENL, MTL_DWICTL_INTENL_IE, 0); 199 } 200 } 201