1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved. 4 // 5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 // 8 // Special thanks to: 9 // Krzysztof Hejmowski <krzysztof.hejmowski@intel.com> 10 // Michal Sienkiewicz <michal.sienkiewicz@intel.com> 11 // Filip Proborszcz 12 // 13 // for sharing Intel AudioDSP expertise and helping shape the very 14 // foundation of this driver 15 // 16 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <sound/hda_codec.h> 20 #include <sound/hda_i915.h> 21 #include <sound/hda_register.h> 22 #include <sound/hdaudio.h> 23 #include <sound/hdaudio_ext.h> 24 #include <sound/intel-dsp-config.h> 25 #include <sound/intel-nhlt.h> 26 #include "../../codecs/hda.h" 27 #include "avs.h" 28 #include "cldma.h" 29 #include "messages.h" 30 31 static u32 pgctl_mask = AZX_PGCTL_LSRMD_MASK; 32 module_param(pgctl_mask, uint, 0444); 33 MODULE_PARM_DESC(pgctl_mask, "PCI PGCTL policy override"); 34 35 static u32 cgctl_mask = AZX_CGCTL_MISCBDCGE_MASK; 36 module_param(cgctl_mask, uint, 0444); 37 MODULE_PARM_DESC(cgctl_mask, "PCI CGCTL policy override"); 38 39 static void 40 avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value) 41 { 42 struct pci_dev *pci = to_pci_dev(bus->dev); 43 u32 data; 44 45 pci_read_config_dword(pci, reg, &data); 46 data &= ~mask; 47 data |= (value & mask); 48 pci_write_config_dword(pci, reg, data); 49 } 50 51 void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable) 52 { 53 u32 value = enable ? 0 : pgctl_mask; 54 55 avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL, pgctl_mask, value); 56 } 57 58 static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable) 59 { 60 u32 value = enable ? cgctl_mask : 0; 61 62 avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, cgctl_mask, value); 63 } 64 65 void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable) 66 { 67 avs_hdac_clock_gating_enable(&adev->base.core, enable); 68 } 69 70 void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable) 71 { 72 u32 value = enable ? AZX_VS_EM2_L1SEN : 0; 73 74 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value); 75 } 76 77 static int avs_hdac_bus_init_streams(struct hdac_bus *bus) 78 { 79 unsigned int cp_streams, pb_streams; 80 unsigned int gcap; 81 82 gcap = snd_hdac_chip_readw(bus, GCAP); 83 cp_streams = (gcap >> 8) & 0x0F; 84 pb_streams = (gcap >> 12) & 0x0F; 85 bus->num_streams = cp_streams + pb_streams; 86 87 snd_hdac_ext_stream_init_all(bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE); 88 snd_hdac_ext_stream_init_all(bus, cp_streams, pb_streams, SNDRV_PCM_STREAM_PLAYBACK); 89 90 return snd_hdac_bus_alloc_stream_pages(bus); 91 } 92 93 static bool avs_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset) 94 { 95 struct hdac_ext_link *hlink; 96 bool ret; 97 98 avs_hdac_clock_gating_enable(bus, false); 99 ret = snd_hdac_bus_init_chip(bus, full_reset); 100 101 /* Reset stream-to-link mapping */ 102 list_for_each_entry(hlink, &bus->hlink_list, list) 103 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 104 105 avs_hdac_clock_gating_enable(bus, true); 106 107 /* Set DUM bit to address incorrect position reporting for capture 108 * streams. In order to do so, CTRL needs to be out of reset state 109 */ 110 snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM); 111 112 return ret; 113 } 114 115 static int probe_codec(struct hdac_bus *bus, int addr) 116 { 117 struct hda_codec *codec; 118 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 119 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 120 unsigned int res = -1; 121 int ret; 122 123 mutex_lock(&bus->cmd_mutex); 124 snd_hdac_bus_send_cmd(bus, cmd); 125 snd_hdac_bus_get_response(bus, addr, &res); 126 mutex_unlock(&bus->cmd_mutex); 127 if (res == -1) 128 return -EIO; 129 130 dev_dbg(bus->dev, "codec #%d probed OK: 0x%x\n", addr, res); 131 132 codec = snd_hda_codec_device_init(to_hda_bus(bus), addr, "hdaudioB%dD%d", bus->idx, addr); 133 if (IS_ERR(codec)) { 134 dev_err(bus->dev, "init codec failed: %ld\n", PTR_ERR(codec)); 135 return PTR_ERR(codec); 136 } 137 /* 138 * Allow avs_core suspend by forcing suspended state on all 139 * of its codec child devices. Component interested in 140 * dealing with hda codecs directly takes pm responsibilities 141 */ 142 pm_runtime_set_suspended(hda_codec_dev(codec)); 143 144 /* configure effectively creates new ASoC component */ 145 ret = snd_hda_codec_configure(codec); 146 if (ret < 0) { 147 dev_err(bus->dev, "failed to config codec %d\n", ret); 148 return ret; 149 } 150 151 return 0; 152 } 153 154 static void avs_hdac_bus_probe_codecs(struct hdac_bus *bus) 155 { 156 int c; 157 158 /* First try to probe all given codec slots */ 159 for (c = 0; c < HDA_MAX_CODECS; c++) { 160 if (!(bus->codec_mask & BIT(c))) 161 continue; 162 163 if (!probe_codec(bus, c)) 164 /* success, continue probing */ 165 continue; 166 167 /* 168 * Some BIOSen give you wrong codec addresses 169 * that don't exist 170 */ 171 dev_warn(bus->dev, "Codec #%d probe error; disabling it...\n", c); 172 bus->codec_mask &= ~BIT(c); 173 /* 174 * More badly, accessing to a non-existing 175 * codec often screws up the controller bus, 176 * and disturbs the further communications. 177 * Thus if an error occurs during probing, 178 * better to reset the controller bus to get 179 * back to the sanity state. 180 */ 181 snd_hdac_bus_stop_chip(bus); 182 avs_hdac_bus_init_chip(bus, true); 183 } 184 } 185 186 static void avs_hda_probe_work(struct work_struct *work) 187 { 188 struct avs_dev *adev = container_of(work, struct avs_dev, probe_work); 189 struct hdac_bus *bus = &adev->base.core; 190 struct hdac_ext_link *hlink; 191 int ret; 192 193 pm_runtime_set_active(bus->dev); /* clear runtime_error flag */ 194 195 ret = snd_hdac_i915_init(bus); 196 if (ret < 0) 197 dev_info(bus->dev, "i915 init unsuccessful: %d\n", ret); 198 199 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); 200 avs_hdac_bus_init_chip(bus, true); 201 avs_hdac_bus_probe_codecs(bus); 202 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 203 204 /* with all codecs probed, links can be powered down */ 205 list_for_each_entry(hlink, &bus->hlink_list, list) 206 snd_hdac_ext_bus_link_put(bus, hlink); 207 208 snd_hdac_ext_bus_ppcap_enable(bus, true); 209 snd_hdac_ext_bus_ppcap_int_enable(bus, true); 210 211 ret = avs_dsp_first_boot_firmware(adev); 212 if (ret < 0) 213 return; 214 215 adev->nhlt = intel_nhlt_init(adev->dev); 216 if (!adev->nhlt) 217 dev_info(bus->dev, "platform has no NHLT\n"); 218 avs_debugfs_init(adev); 219 220 avs_register_all_boards(adev); 221 222 /* configure PM */ 223 pm_runtime_set_autosuspend_delay(bus->dev, 2000); 224 pm_runtime_use_autosuspend(bus->dev); 225 pm_runtime_mark_last_busy(bus->dev); 226 pm_runtime_put_autosuspend(bus->dev); 227 pm_runtime_allow(bus->dev); 228 } 229 230 static void hdac_stream_update_pos(struct hdac_stream *stream, u64 buffer_size) 231 { 232 u64 prev_pos, pos, num_bytes; 233 234 div64_u64_rem(stream->curr_pos, buffer_size, &prev_pos); 235 pos = snd_hdac_stream_get_pos_posbuf(stream); 236 237 if (pos < prev_pos) 238 num_bytes = (buffer_size - prev_pos) + pos; 239 else 240 num_bytes = pos - prev_pos; 241 242 stream->curr_pos += num_bytes; 243 } 244 245 /* called from IRQ */ 246 static void hdac_update_stream(struct hdac_bus *bus, struct hdac_stream *stream) 247 { 248 if (stream->substream) { 249 snd_pcm_period_elapsed(stream->substream); 250 } else if (stream->cstream) { 251 u64 buffer_size = stream->cstream->runtime->buffer_size; 252 253 hdac_stream_update_pos(stream, buffer_size); 254 snd_compr_fragment_elapsed(stream->cstream); 255 } 256 } 257 258 static irqreturn_t hdac_bus_irq_handler(int irq, void *context) 259 { 260 struct hdac_bus *bus = context; 261 u32 mask, int_enable; 262 u32 status; 263 int ret = IRQ_NONE; 264 265 if (!pm_runtime_active(bus->dev)) 266 return ret; 267 268 spin_lock(&bus->reg_lock); 269 270 status = snd_hdac_chip_readl(bus, INTSTS); 271 if (status == 0 || status == UINT_MAX) { 272 spin_unlock(&bus->reg_lock); 273 return ret; 274 } 275 276 /* clear rirb int */ 277 status = snd_hdac_chip_readb(bus, RIRBSTS); 278 if (status & RIRB_INT_MASK) { 279 if (status & RIRB_INT_RESPONSE) 280 snd_hdac_bus_update_rirb(bus); 281 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 282 } 283 284 mask = (0x1 << bus->num_streams) - 1; 285 286 status = snd_hdac_chip_readl(bus, INTSTS); 287 status &= mask; 288 if (status) { 289 /* Disable stream interrupts; Re-enable in bottom half */ 290 int_enable = snd_hdac_chip_readl(bus, INTCTL); 291 snd_hdac_chip_writel(bus, INTCTL, (int_enable & (~mask))); 292 ret = IRQ_WAKE_THREAD; 293 } else { 294 ret = IRQ_HANDLED; 295 } 296 297 spin_unlock(&bus->reg_lock); 298 return ret; 299 } 300 301 static irqreturn_t hdac_bus_irq_thread(int irq, void *context) 302 { 303 struct hdac_bus *bus = context; 304 u32 status; 305 u32 int_enable; 306 u32 mask; 307 unsigned long flags; 308 309 status = snd_hdac_chip_readl(bus, INTSTS); 310 311 snd_hdac_bus_handle_stream_irq(bus, status, hdac_update_stream); 312 313 /* Re-enable stream interrupts */ 314 mask = (0x1 << bus->num_streams) - 1; 315 spin_lock_irqsave(&bus->reg_lock, flags); 316 int_enable = snd_hdac_chip_readl(bus, INTCTL); 317 snd_hdac_chip_writel(bus, INTCTL, (int_enable | mask)); 318 spin_unlock_irqrestore(&bus->reg_lock, flags); 319 320 return IRQ_HANDLED; 321 } 322 323 static int avs_hdac_acquire_irq(struct avs_dev *adev) 324 { 325 struct hdac_bus *bus = &adev->base.core; 326 struct pci_dev *pci = to_pci_dev(bus->dev); 327 int ret; 328 329 /* request one and check that we only got one interrupt */ 330 ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI | PCI_IRQ_LEGACY); 331 if (ret != 1) { 332 dev_err(adev->dev, "Failed to allocate IRQ vector: %d\n", ret); 333 return ret; 334 } 335 336 ret = pci_request_irq(pci, 0, hdac_bus_irq_handler, hdac_bus_irq_thread, bus, 337 KBUILD_MODNAME); 338 if (ret < 0) { 339 dev_err(adev->dev, "Failed to request stream IRQ handler: %d\n", ret); 340 goto free_vector; 341 } 342 343 ret = pci_request_irq(pci, 0, avs_dsp_irq_handler, avs_dsp_irq_thread, adev, 344 KBUILD_MODNAME); 345 if (ret < 0) { 346 dev_err(adev->dev, "Failed to request IPC IRQ handler: %d\n", ret); 347 goto free_stream_irq; 348 } 349 350 return 0; 351 352 free_stream_irq: 353 pci_free_irq(pci, 0, bus); 354 free_vector: 355 pci_free_irq_vectors(pci); 356 return ret; 357 } 358 359 static int avs_bus_init(struct avs_dev *adev, struct pci_dev *pci, const struct pci_device_id *id) 360 { 361 struct hda_bus *bus = &adev->base; 362 struct avs_ipc *ipc; 363 struct device *dev = &pci->dev; 364 int ret; 365 366 ret = snd_hdac_ext_bus_init(&bus->core, dev, NULL, &soc_hda_ext_bus_ops); 367 if (ret < 0) 368 return ret; 369 370 bus->core.use_posbuf = 1; 371 bus->core.bdl_pos_adj = 0; 372 bus->core.sync_write = 1; 373 bus->pci = pci; 374 bus->mixer_assigned = -1; 375 mutex_init(&bus->prepare_mutex); 376 377 ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL); 378 if (!ipc) 379 return -ENOMEM; 380 ret = avs_ipc_init(ipc, dev); 381 if (ret < 0) 382 return ret; 383 384 adev->modcfg_buf = devm_kzalloc(dev, AVS_MAILBOX_SIZE, GFP_KERNEL); 385 if (!adev->modcfg_buf) 386 return -ENOMEM; 387 388 adev->dev = dev; 389 adev->spec = (const struct avs_spec *)id->driver_data; 390 adev->ipc = ipc; 391 adev->hw_cfg.dsp_cores = hweight_long(AVS_MAIN_CORE_MASK); 392 INIT_WORK(&adev->probe_work, avs_hda_probe_work); 393 INIT_LIST_HEAD(&adev->comp_list); 394 INIT_LIST_HEAD(&adev->path_list); 395 INIT_LIST_HEAD(&adev->fw_list); 396 init_completion(&adev->fw_ready); 397 spin_lock_init(&adev->path_list_lock); 398 mutex_init(&adev->modres_mutex); 399 mutex_init(&adev->comp_list_mutex); 400 mutex_init(&adev->path_mutex); 401 402 return 0; 403 } 404 405 static int avs_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 406 { 407 struct hdac_bus *bus; 408 struct avs_dev *adev; 409 struct device *dev = &pci->dev; 410 int ret; 411 412 ret = snd_intel_dsp_driver_probe(pci); 413 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_AVS) 414 return -ENODEV; 415 416 ret = pcim_enable_device(pci); 417 if (ret < 0) 418 return ret; 419 420 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL); 421 if (!adev) 422 return -ENOMEM; 423 ret = avs_bus_init(adev, pci, id); 424 if (ret < 0) { 425 dev_err(dev, "failed to init avs bus: %d\n", ret); 426 return ret; 427 } 428 429 ret = pci_request_regions(pci, "AVS HDAudio"); 430 if (ret < 0) 431 return ret; 432 433 bus = &adev->base.core; 434 bus->addr = pci_resource_start(pci, 0); 435 bus->remap_addr = pci_ioremap_bar(pci, 0); 436 if (!bus->remap_addr) { 437 dev_err(bus->dev, "ioremap error\n"); 438 ret = -ENXIO; 439 goto err_remap_bar0; 440 } 441 442 adev->dsp_ba = pci_ioremap_bar(pci, 4); 443 if (!adev->dsp_ba) { 444 dev_err(bus->dev, "ioremap error\n"); 445 ret = -ENXIO; 446 goto err_remap_bar4; 447 } 448 449 snd_hdac_bus_parse_capabilities(bus); 450 if (bus->mlcap) 451 snd_hdac_ext_bus_get_ml_capabilities(bus); 452 453 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) 454 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 455 dma_set_max_seg_size(dev, UINT_MAX); 456 457 ret = avs_hdac_bus_init_streams(bus); 458 if (ret < 0) { 459 dev_err(dev, "failed to init streams: %d\n", ret); 460 goto err_init_streams; 461 } 462 463 ret = avs_hdac_acquire_irq(adev); 464 if (ret < 0) { 465 dev_err(bus->dev, "failed to acquire irq: %d\n", ret); 466 goto err_acquire_irq; 467 } 468 469 pci_set_master(pci); 470 pci_set_drvdata(pci, bus); 471 device_disable_async_suspend(dev); 472 473 schedule_work(&adev->probe_work); 474 475 return 0; 476 477 err_acquire_irq: 478 snd_hdac_bus_free_stream_pages(bus); 479 snd_hdac_ext_stream_free_all(bus); 480 err_init_streams: 481 iounmap(adev->dsp_ba); 482 err_remap_bar4: 483 iounmap(bus->remap_addr); 484 err_remap_bar0: 485 pci_release_regions(pci); 486 return ret; 487 } 488 489 static void avs_pci_shutdown(struct pci_dev *pci) 490 { 491 struct hdac_bus *bus = pci_get_drvdata(pci); 492 struct avs_dev *adev = hdac_to_avs(bus); 493 494 cancel_work_sync(&adev->probe_work); 495 avs_ipc_block(adev->ipc); 496 497 snd_hdac_stop_streams(bus); 498 avs_dsp_op(adev, int_control, false); 499 snd_hdac_ext_bus_ppcap_int_enable(bus, false); 500 snd_hdac_ext_bus_link_power_down_all(bus); 501 502 snd_hdac_bus_stop_chip(bus); 503 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 504 505 if (avs_platattr_test(adev, CLDMA)) 506 pci_free_irq(pci, 0, &code_loader); 507 pci_free_irq(pci, 0, adev); 508 pci_free_irq(pci, 0, bus); 509 pci_free_irq_vectors(pci); 510 } 511 512 static void avs_pci_remove(struct pci_dev *pci) 513 { 514 struct hdac_device *hdev, *save; 515 struct hdac_bus *bus = pci_get_drvdata(pci); 516 struct avs_dev *adev = hdac_to_avs(bus); 517 518 cancel_work_sync(&adev->probe_work); 519 avs_ipc_block(adev->ipc); 520 521 avs_unregister_all_boards(adev); 522 523 avs_debugfs_exit(adev); 524 if (adev->nhlt) 525 intel_nhlt_free(adev->nhlt); 526 527 if (avs_platattr_test(adev, CLDMA)) 528 hda_cldma_free(&code_loader); 529 530 snd_hdac_stop_streams_and_chip(bus); 531 avs_dsp_op(adev, int_control, false); 532 snd_hdac_ext_bus_ppcap_int_enable(bus, false); 533 534 /* it is safe to remove all codecs from the system now */ 535 list_for_each_entry_safe(hdev, save, &bus->codec_list, list) 536 snd_hda_codec_unregister(hdac_to_hda_codec(hdev)); 537 538 snd_hdac_bus_free_stream_pages(bus); 539 snd_hdac_ext_stream_free_all(bus); 540 /* reverse ml_capabilities */ 541 snd_hdac_ext_link_free_all(bus); 542 snd_hdac_ext_bus_exit(bus); 543 544 avs_dsp_core_disable(adev, GENMASK(adev->hw_cfg.dsp_cores - 1, 0)); 545 snd_hdac_ext_bus_ppcap_enable(bus, false); 546 547 /* snd_hdac_stop_streams_and_chip does that already? */ 548 snd_hdac_bus_stop_chip(bus); 549 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 550 if (bus->audio_component) 551 snd_hdac_i915_exit(bus); 552 553 avs_module_info_free(adev); 554 pci_free_irq(pci, 0, adev); 555 pci_free_irq(pci, 0, bus); 556 pci_free_irq_vectors(pci); 557 iounmap(bus->remap_addr); 558 iounmap(adev->dsp_ba); 559 pci_release_regions(pci); 560 561 /* Firmware is not needed anymore */ 562 avs_release_firmwares(adev); 563 564 /* pm_runtime_forbid() can rpm_resume() which we do not want */ 565 pm_runtime_disable(&pci->dev); 566 pm_runtime_forbid(&pci->dev); 567 pm_runtime_enable(&pci->dev); 568 pm_runtime_get_noresume(&pci->dev); 569 } 570 571 static int avs_suspend_standby(struct avs_dev *adev) 572 { 573 struct hdac_bus *bus = &adev->base.core; 574 struct pci_dev *pci = adev->base.pci; 575 576 if (bus->cmd_dma_state) 577 snd_hdac_bus_stop_cmd_io(bus); 578 579 snd_hdac_ext_bus_link_power_down_all(bus); 580 581 enable_irq_wake(pci->irq); 582 pci_save_state(pci); 583 584 return 0; 585 } 586 587 static int __maybe_unused avs_suspend_common(struct avs_dev *adev, bool low_power) 588 { 589 struct hdac_bus *bus = &adev->base.core; 590 int ret; 591 592 flush_work(&adev->probe_work); 593 if (low_power && adev->num_lp_paths) 594 return avs_suspend_standby(adev); 595 596 snd_hdac_ext_bus_link_power_down_all(bus); 597 598 ret = avs_ipc_set_dx(adev, AVS_MAIN_CORE_MASK, false); 599 /* 600 * pm_runtime is blocked on DSP failure but system-wide suspend is not. 601 * Do not block entire system from suspending if that's the case. 602 */ 603 if (ret && ret != -EPERM) { 604 dev_err(adev->dev, "set dx failed: %d\n", ret); 605 return AVS_IPC_RET(ret); 606 } 607 608 avs_ipc_block(adev->ipc); 609 avs_dsp_op(adev, int_control, false); 610 snd_hdac_ext_bus_ppcap_int_enable(bus, false); 611 612 ret = avs_dsp_core_disable(adev, AVS_MAIN_CORE_MASK); 613 if (ret < 0) { 614 dev_err(adev->dev, "core_mask %ld disable failed: %d\n", AVS_MAIN_CORE_MASK, ret); 615 return ret; 616 } 617 618 snd_hdac_ext_bus_ppcap_enable(bus, false); 619 /* disable LP SRAM retention */ 620 avs_hda_power_gating_enable(adev, false); 621 snd_hdac_bus_stop_chip(bus); 622 /* disable CG when putting controller to reset */ 623 avs_hdac_clock_gating_enable(bus, false); 624 snd_hdac_bus_enter_link_reset(bus); 625 avs_hdac_clock_gating_enable(bus, true); 626 627 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false); 628 629 return 0; 630 } 631 632 static int avs_resume_standby(struct avs_dev *adev) 633 { 634 struct hdac_bus *bus = &adev->base.core; 635 struct pci_dev *pci = adev->base.pci; 636 637 pci_restore_state(pci); 638 disable_irq_wake(pci->irq); 639 640 snd_hdac_ext_bus_link_power_up_all(bus); 641 642 if (bus->cmd_dma_state) 643 snd_hdac_bus_init_cmd_io(bus); 644 645 return 0; 646 } 647 648 static int __maybe_unused avs_resume_common(struct avs_dev *adev, bool low_power, bool purge) 649 { 650 struct hdac_bus *bus = &adev->base.core; 651 int ret; 652 653 if (low_power && adev->num_lp_paths) 654 return avs_resume_standby(adev); 655 656 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true); 657 avs_hdac_bus_init_chip(bus, true); 658 659 snd_hdac_ext_bus_ppcap_enable(bus, true); 660 snd_hdac_ext_bus_ppcap_int_enable(bus, true); 661 662 ret = avs_dsp_boot_firmware(adev, purge); 663 if (ret < 0) { 664 dev_err(adev->dev, "firmware boot failed: %d\n", ret); 665 return ret; 666 } 667 668 return 0; 669 } 670 671 static int __maybe_unused avs_suspend(struct device *dev) 672 { 673 return avs_suspend_common(to_avs_dev(dev), true); 674 } 675 676 static int __maybe_unused avs_resume(struct device *dev) 677 { 678 return avs_resume_common(to_avs_dev(dev), true, true); 679 } 680 681 static int __maybe_unused avs_runtime_suspend(struct device *dev) 682 { 683 return avs_suspend_common(to_avs_dev(dev), true); 684 } 685 686 static int __maybe_unused avs_runtime_resume(struct device *dev) 687 { 688 return avs_resume_common(to_avs_dev(dev), true, false); 689 } 690 691 static int __maybe_unused avs_freeze(struct device *dev) 692 { 693 return avs_suspend_common(to_avs_dev(dev), false); 694 } 695 static int __maybe_unused avs_thaw(struct device *dev) 696 { 697 return avs_resume_common(to_avs_dev(dev), false, true); 698 } 699 700 static int __maybe_unused avs_poweroff(struct device *dev) 701 { 702 return avs_suspend_common(to_avs_dev(dev), false); 703 } 704 705 static int __maybe_unused avs_restore(struct device *dev) 706 { 707 return avs_resume_common(to_avs_dev(dev), false, true); 708 } 709 710 static const struct dev_pm_ops avs_dev_pm = { 711 .suspend = avs_suspend, 712 .resume = avs_resume, 713 .freeze = avs_freeze, 714 .thaw = avs_thaw, 715 .poweroff = avs_poweroff, 716 .restore = avs_restore, 717 SET_RUNTIME_PM_OPS(avs_runtime_suspend, avs_runtime_resume, NULL) 718 }; 719 720 static const struct avs_spec skl_desc = { 721 .name = "skl", 722 .min_fw_version = { 723 .major = 9, 724 .minor = 21, 725 .hotfix = 0, 726 .build = 4732, 727 }, 728 .dsp_ops = &skl_dsp_ops, 729 .core_init_mask = 1, 730 .attributes = AVS_PLATATTR_CLDMA, 731 .sram_base_offset = SKL_ADSP_SRAM_BASE_OFFSET, 732 .sram_window_size = SKL_ADSP_SRAM_WINDOW_SIZE, 733 .rom_status = SKL_ADSP_SRAM_BASE_OFFSET, 734 }; 735 736 static const struct avs_spec apl_desc = { 737 .name = "apl", 738 .min_fw_version = { 739 .major = 9, 740 .minor = 22, 741 .hotfix = 1, 742 .build = 4323, 743 }, 744 .dsp_ops = &apl_dsp_ops, 745 .core_init_mask = 3, 746 .attributes = AVS_PLATATTR_IMR, 747 .sram_base_offset = APL_ADSP_SRAM_BASE_OFFSET, 748 .sram_window_size = APL_ADSP_SRAM_WINDOW_SIZE, 749 .rom_status = APL_ADSP_SRAM_BASE_OFFSET, 750 }; 751 752 static const struct pci_device_id avs_ids[] = { 753 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, &skl_desc) }, 754 { PCI_DEVICE_DATA(INTEL, HDA_SKL, &skl_desc) }, 755 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, &skl_desc) }, 756 { PCI_DEVICE_DATA(INTEL, HDA_KBL, &skl_desc) }, 757 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, &skl_desc) }, 758 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, &skl_desc) }, 759 { PCI_DEVICE_DATA(INTEL, HDA_APL, &apl_desc) }, 760 { PCI_DEVICE_DATA(INTEL, HDA_GML, &apl_desc) }, 761 { 0 } 762 }; 763 MODULE_DEVICE_TABLE(pci, avs_ids); 764 765 static struct pci_driver avs_pci_driver = { 766 .name = KBUILD_MODNAME, 767 .id_table = avs_ids, 768 .probe = avs_pci_probe, 769 .remove = avs_pci_remove, 770 .shutdown = avs_pci_shutdown, 771 .driver = { 772 .pm = &avs_dev_pm, 773 }, 774 }; 775 module_pci_driver(avs_pci_driver); 776 777 MODULE_AUTHOR("Cezary Rojewski <cezary.rojewski@intel.com>"); 778 MODULE_AUTHOR("Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>"); 779 MODULE_DESCRIPTION("Intel cAVS sound driver"); 780 MODULE_LICENSE("GPL"); 781