128564486SViorel Suman /* SPDX-License-Identifier: GPL-2.0 */ 228564486SViorel Suman /* 328564486SViorel Suman * NXP XCVR ALSA SoC Digital Audio Interface (DAI) driver 428564486SViorel Suman * 528564486SViorel Suman * Copyright 2019 NXP 628564486SViorel Suman */ 728564486SViorel Suman 828564486SViorel Suman #ifndef __FSL_XCVR_H 928564486SViorel Suman #define __FSL_XCVR_H 1028564486SViorel Suman 1128564486SViorel Suman #define FSL_XCVR_MODE_SPDIF 0 1228564486SViorel Suman #define FSL_XCVR_MODE_ARC 1 1328564486SViorel Suman #define FSL_XCVR_MODE_EARC 2 1428564486SViorel Suman 1528564486SViorel Suman /* XCVR Registers */ 1628564486SViorel Suman #define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */ 1728564486SViorel Suman #define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */ 1828564486SViorel Suman #define FSL_XCVR_FIFO_WMK_RX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */ 1928564486SViorel Suman #define FSL_XCVR_FIFO_WMK_TX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */ 2028564486SViorel Suman #define FSL_XCVR_MAXBURST_RX (FSL_XCVR_FIFO_WMK_RX >> 2) /* 16 */ 2128564486SViorel Suman #define FSL_XCVR_MAXBURST_TX (FSL_XCVR_FIFO_WMK_TX >> 2) /* 16 */ 2228564486SViorel Suman 2328564486SViorel Suman #define FSL_XCVR_RX_FIFO_ADDR 0x0C00 2428564486SViorel Suman #define FSL_XCVR_TX_FIFO_ADDR 0x0E00 2528564486SViorel Suman 2628564486SViorel Suman #define FSL_XCVR_VERSION 0x00 /* Version */ 2728564486SViorel Suman #define FSL_XCVR_EXT_CTRL 0x10 /* Control */ 2828564486SViorel Suman #define FSL_XCVR_EXT_STATUS 0x20 /* Status */ 2928564486SViorel Suman #define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */ 3028564486SViorel Suman #define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */ 3128564486SViorel Suman #define FSL_XCVR_EXT_ISR 0x50 /* Interrupt status */ 3228564486SViorel Suman #define FSL_XCVR_EXT_ISR_SET 0x54 /* Interrupt status */ 3328564486SViorel Suman #define FSL_XCVR_EXT_ISR_CLR 0x58 /* Interrupt status */ 3428564486SViorel Suman #define FSL_XCVR_EXT_ISR_TOG 0x5C /* Interrupt status */ 3528564486SViorel Suman #define FSL_XCVR_IER 0x70 /* Interrupt en for M0+ */ 3628564486SViorel Suman #define FSL_XCVR_ISR 0x80 /* Interrupt status */ 3728564486SViorel Suman #define FSL_XCVR_ISR_SET 0x84 /* Interrupt status set */ 3828564486SViorel Suman #define FSL_XCVR_ISR_CLR 0x88 /* Interrupt status clear */ 3928564486SViorel Suman #define FSL_XCVR_ISR_TOG 0x8C /* Interrupt status toggle */ 4028564486SViorel Suman #define FSL_XCVR_PHY_AI_CTRL 0x90 4128564486SViorel Suman #define FSL_XCVR_PHY_AI_CTRL_SET 0x94 4228564486SViorel Suman #define FSL_XCVR_PHY_AI_CTRL_CLR 0x98 4328564486SViorel Suman #define FSL_XCVR_PHY_AI_CTRL_TOG 0x9C 4428564486SViorel Suman #define FSL_XCVR_PHY_AI_WDATA 0xA0 4528564486SViorel Suman #define FSL_XCVR_PHY_AI_RDATA 0xA4 4628564486SViorel Suman #define FSL_XCVR_CLK_CTRL 0xB0 4728564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL 0x180 /* RX datapath ctrl reg */ 4828564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_SET 0x184 4928564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_CLR 0x188 5028564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c 5128564486SViorel Suman 52e240b932SChancel Liu #define FSL_XCVR_RX_CS_DATA_0 0x190 53e240b932SChancel Liu #define FSL_XCVR_RX_CS_DATA_1 0x194 54e240b932SChancel Liu #define FSL_XCVR_RX_CS_DATA_2 0x198 55e240b932SChancel Liu #define FSL_XCVR_RX_CS_DATA_3 0x19C 56e240b932SChancel Liu #define FSL_XCVR_RX_CS_DATA_4 0x1A0 57e240b932SChancel Liu #define FSL_XCVR_RX_CS_DATA_5 0x1A4 58e240b932SChancel Liu 59107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_CNTR_CTRL 0x1C0 60107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET 0x1C4 61107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR 0x1C8 62107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG 0x1CC 63107d170dSShengjiu Wang 64107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_TSCR 0x1D0 65107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_BCR 0x1D4 66107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_BCTR 0x1D8 67107d170dSShengjiu Wang #define FSL_XCVR_RX_DPTH_BCRR 0x1DC 68107d170dSShengjiu Wang 6928564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL 0x220 /* TX datapath ctrl reg */ 7028564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_SET 0x224 7128564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_CLR 0x228 7228564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_TOG 0x22C 7328564486SViorel Suman #define FSL_XCVR_TX_CS_DATA_0 0x230 /* TX channel status bits regs */ 7428564486SViorel Suman #define FSL_XCVR_TX_CS_DATA_1 0x234 7528564486SViorel Suman #define FSL_XCVR_TX_CS_DATA_2 0x238 7628564486SViorel Suman #define FSL_XCVR_TX_CS_DATA_3 0x23C 7728564486SViorel Suman #define FSL_XCVR_TX_CS_DATA_4 0x240 7828564486SViorel Suman #define FSL_XCVR_TX_CS_DATA_5 0x244 79107d170dSShengjiu Wang 80107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_CNTR_CTRL 0x260 81107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_CNTR_CTRL_SET 0x264 82107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR 0x268 83107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG 0x26C 84107d170dSShengjiu Wang 85107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_TSCR 0x270 86107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_BCR 0x274 87107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_BCTR 0x278 88107d170dSShengjiu Wang #define FSL_XCVR_TX_DPTH_BCRR 0x27C 89107d170dSShengjiu Wang 9028564486SViorel Suman #define FSL_XCVR_DEBUG_REG_0 0x2E0 9128564486SViorel Suman #define FSL_XCVR_DEBUG_REG_1 0x2F0 9228564486SViorel Suman 9328564486SViorel Suman #define FSL_XCVR_MAX_REG FSL_XCVR_DEBUG_REG_1 9428564486SViorel Suman 9528564486SViorel Suman #define FSL_XCVR_EXT_CTRL_CORE_RESET BIT(31) 9628564486SViorel Suman 9728564486SViorel Suman #define FSL_XCVR_EXT_CTRL_RX_CMDC_RESET BIT(30) 9828564486SViorel Suman #define FSL_XCVR_EXT_CTRL_TX_CMDC_RESET BIT(29) 9928564486SViorel Suman #define FSL_XCVR_EXT_CTRL_CMDC_RESET(t) (t ? BIT(29) : BIT(30)) 10028564486SViorel Suman 10128564486SViorel Suman #define FSL_XCVR_EXT_CTRL_RX_DPTH_RESET BIT(28) 10228564486SViorel Suman #define FSL_XCVR_EXT_CTRL_TX_DPTH_RESET BIT(27) 10328564486SViorel Suman #define FSL_XCVR_EXT_CTRL_DPTH_RESET(t) (t ? BIT(27) : BIT(28)) 10428564486SViorel Suman 10528564486SViorel Suman #define FSL_XCVR_EXT_CTRL_TX_RX_MODE BIT(26) 10628564486SViorel Suman #define FSL_XCVR_EXT_CTRL_DMA_RD_DIS BIT(25) 10728564486SViorel Suman #define FSL_XCVR_EXT_CTRL_DMA_WR_DIS BIT(24) 10828564486SViorel Suman #define FSL_XCVR_EXT_CTRL_DMA_DIS(t) (t ? BIT(24) : BIT(25)) 10928564486SViorel Suman #define FSL_XCVR_EXT_CTRL_SPDIF_MODE BIT(23) 11028564486SViorel Suman #define FSL_XCVR_EXT_CTRL_SLEEP_MODE BIT(21) 11128564486SViorel Suman 11228564486SViorel Suman #define FSL_XCVR_EXT_CTRL_TX_FWM_SHFT 0 11328564486SViorel Suman #define FSL_XCVR_EXT_CTRL_TX_FWM_MASK GENMASK(6, 0) 11428564486SViorel Suman #define FSL_XCVR_EXT_CTRL_TX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_TX_FWM_SHFT) \ 11528564486SViorel Suman & FSL_XCVR_EXT_CTRL_TX_FWM_MASK) 11628564486SViorel Suman #define FSL_XCVR_EXT_CTRL_RX_FWM_SHFT 8 11728564486SViorel Suman #define FSL_XCVR_EXT_CTRL_RX_FWM_MASK GENMASK(14, 8) 11828564486SViorel Suman #define FSL_XCVR_EXT_CTRL_RX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_RX_FWM_SHFT) \ 11928564486SViorel Suman & FSL_XCVR_EXT_CTRL_RX_FWM_MASK) 12028564486SViorel Suman #define FSL_XCVR_EXT_CTRL_PAGE_SHFT 16 12128564486SViorel Suman #define FSL_XCVR_EXT_CTRL_PAGE_MASK GENMASK(19, 16) 12228564486SViorel Suman #define FSL_XCVR_EXT_CTRL_PAGE(i) (((i) << FSL_XCVR_EXT_CTRL_PAGE_SHFT) \ 12328564486SViorel Suman & FSL_XCVR_EXT_CTRL_PAGE_MASK) 12428564486SViorel Suman 12528564486SViorel Suman #define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR GENMASK(7, 0) 12628564486SViorel Suman #define FSL_XCVR_EXT_STUS_NR_FIFO_ENTR GENMASK(15, 8) 12728564486SViorel Suman #define FSL_XCVR_EXT_STUS_CM0_SLEEPING BIT(16) 12828564486SViorel Suman #define FSL_XCVR_EXT_STUS_CM0_DEEP_SLP BIT(17) 12928564486SViorel Suman #define FSL_XCVR_EXT_STUS_CM0_SLP_HACK BIT(18) 13028564486SViorel Suman #define FSL_XCVR_EXT_STUS_RX_CMDC_RSTO BIT(23) 13128564486SViorel Suman #define FSL_XCVR_EXT_STUS_TX_CMDC_RSTO BIT(24) 13228564486SViorel Suman #define FSL_XCVR_EXT_STUS_RX_CMDC_COTO BIT(25) 13328564486SViorel Suman #define FSL_XCVR_EXT_STUS_TX_CMDC_COTO BIT(26) 13428564486SViorel Suman #define FSL_XCVR_EXT_STUS_HB_STATUS BIT(27) 13528564486SViorel Suman #define FSL_XCVR_EXT_STUS_NEW_UD4_REC BIT(28) 13628564486SViorel Suman #define FSL_XCVR_EXT_STUS_NEW_UD5_REC BIT(29) 13728564486SViorel Suman #define FSL_XCVR_EXT_STUS_NEW_UD6_REC BIT(30) 13828564486SViorel Suman #define FSL_XCVR_EXT_STUS_HPD_INPUT BIT(31) 13928564486SViorel Suman 14028564486SViorel Suman #define FSL_XCVR_IRQ_NEW_CS BIT(0) 14128564486SViorel Suman #define FSL_XCVR_IRQ_NEW_UD BIT(1) 14228564486SViorel Suman #define FSL_XCVR_IRQ_MUTE BIT(2) 14328564486SViorel Suman #define FSL_XCVR_IRQ_CMDC_RESP_TO BIT(3) 14428564486SViorel Suman #define FSL_XCVR_IRQ_ECC_ERR BIT(4) 14528564486SViorel Suman #define FSL_XCVR_IRQ_PREAMBLE_MISMATCH BIT(5) 14628564486SViorel Suman #define FSL_XCVR_IRQ_FIFO_UOFL_ERR BIT(6) 14728564486SViorel Suman #define FSL_XCVR_IRQ_HOST_WAKEUP BIT(7) 14828564486SViorel Suman #define FSL_XCVR_IRQ_HOST_OHPD BIT(8) 14928564486SViorel Suman #define FSL_XCVR_IRQ_DMAC_NO_DATA_REC BIT(9) 15028564486SViorel Suman #define FSL_XCVR_IRQ_DMAC_FMT_CHG_DET BIT(10) 15128564486SViorel Suman #define FSL_XCVR_IRQ_HB_STATE_CHG BIT(11) 15228564486SViorel Suman #define FSL_XCVR_IRQ_CMDC_STATUS_UPD BIT(12) 15328564486SViorel Suman #define FSL_XCVR_IRQ_TEMP_UPD BIT(13) 15428564486SViorel Suman #define FSL_XCVR_IRQ_DMA_RD_REQ BIT(14) 15528564486SViorel Suman #define FSL_XCVR_IRQ_DMA_WR_REQ BIT(15) 15628564486SViorel Suman #define FSL_XCVR_IRQ_DMAC_BME_BIT_ERR BIT(16) 15728564486SViorel Suman #define FSL_XCVR_IRQ_PREAMBLE_MATCH BIT(17) 15828564486SViorel Suman #define FSL_XCVR_IRQ_M_W_PRE_MISMATCH BIT(18) 15928564486SViorel Suman #define FSL_XCVR_IRQ_B_PRE_MISMATCH BIT(19) 16028564486SViorel Suman #define FSL_XCVR_IRQ_UNEXP_PRE_REC BIT(20) 16128564486SViorel Suman #define FSL_XCVR_IRQ_ARC_MODE BIT(21) 16228564486SViorel Suman #define FSL_XCVR_IRQ_CH_UD_OFLOW BIT(22) 16328564486SViorel Suman #define FSL_XCVR_IRQ_EARC_ALL (FSL_XCVR_IRQ_NEW_CS | \ 16428564486SViorel Suman FSL_XCVR_IRQ_NEW_UD | \ 16528564486SViorel Suman FSL_XCVR_IRQ_MUTE | \ 16628564486SViorel Suman FSL_XCVR_IRQ_FIFO_UOFL_ERR | \ 16728564486SViorel Suman FSL_XCVR_IRQ_HOST_WAKEUP | \ 16828564486SViorel Suman FSL_XCVR_IRQ_ARC_MODE) 16928564486SViorel Suman 17028564486SViorel Suman #define FSL_XCVR_ISR_CMDC_TX_EN BIT(3) 17128564486SViorel Suman #define FSL_XCVR_ISR_HPD_TGL BIT(15) 17228564486SViorel Suman #define FSL_XCVR_ISR_DMAC_SPARE_INT BIT(19) 17328564486SViorel Suman #define FSL_XCVR_ISR_SET_SPDIF_RX_INT BIT(20) 17428564486SViorel Suman #define FSL_XCVR_ISR_SET_SPDIF_TX_INT BIT(21) 17528564486SViorel Suman #define FSL_XCVR_ISR_SET_SPDIF_MODE(t) (t ? BIT(21) : BIT(20)) 17628564486SViorel Suman #define FSL_XCVR_ISR_SET_ARC_CM_INT BIT(22) 17728564486SViorel Suman #define FSL_XCVR_ISR_SET_ARC_SE_INT BIT(23) 17828564486SViorel Suman 17928564486SViorel Suman #define FSL_XCVR_PHY_AI_ADDR_MASK GENMASK(7, 0) 18028564486SViorel Suman #define FSL_XCVR_PHY_AI_RESETN BIT(15) 18128564486SViorel Suman #define FSL_XCVR_PHY_AI_TOG_PLL BIT(24) 18228564486SViorel Suman #define FSL_XCVR_PHY_AI_TOG_DONE_PLL BIT(25) 18328564486SViorel Suman #define FSL_XCVR_PHY_AI_TOG_PHY BIT(26) 18428564486SViorel Suman #define FSL_XCVR_PHY_AI_TOG_DONE_PHY BIT(27) 18528564486SViorel Suman #define FSL_XCVR_PHY_AI_RW_MASK BIT(31) 18628564486SViorel Suman 18728564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_PAPB_FIFO_STATUS BIT(0) 18828564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_DIS_PRE_ERR_CHK BIT(1) 18928564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_DIS_NOD_REC_CHK BIT(2) 19028564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_ECC_VUC_BIT_CHK BIT(3) 19128564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_EN_CMP_PAR_CALC BIT(4) 19228564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_RST_PKT_CNT_FIFO BIT(5) 19328564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_STORE_FMT BIT(6) 19428564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_EN_PAR_CALC BIT(7) 19528564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_UDR BIT(8) 19628564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_CSR BIT(9) 19728564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_UDA BIT(10) 19828564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_CSA BIT(11) 19928564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO BIT(12) 20028564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_DIS_B_PRE_ERR_CHK BIT(13) 20128564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_PABS BIT(19) 20228564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_DTS_CDS BIT(20) 20328564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_BLKC BIT(21) 20428564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_MUTE_CTRL BIT(22) 20528564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_MUTE_MODE BIT(23) 20628564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_CTRL BIT(24) 20728564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_MODE BIT(25) 20828564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL BIT(26) 20928564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_LAYB_MODE BIT(27) 21028564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_PRC BIT(28) 21128564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_COMP BIT(29) 21228564486SViorel Suman #define FSL_XCVR_RX_DPTH_CTRL_FSM GENMASK(31, 30) 21328564486SViorel Suman 21428564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_CS_ACK BIT(0) 21528564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_UD_ACK BIT(1) 21628564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_CS_MOD BIT(2) 21728564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_UD_MOD BIT(3) 21828564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_VLD_MOD BIT(4) 21928564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_FRM_VLD BIT(5) 22028564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_EN_PARITY BIT(6) 22128564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_EN_PREAMBLE BIT(7) 22228564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_EN_ECC_INTER BIT(8) 22328564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM BIT(10) 22428564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_FRM_FMT BIT(11) 22528564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX BIT(14) 22628564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_STR BIT(15) 22728564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_END BIT(16) 22828564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29) 22928564486SViorel Suman #define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30) 23028564486SViorel Suman 23128564486SViorel Suman #define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15) 23228564486SViorel Suman 23328564486SViorel Suman #define FSL_XCVR_PLL_CTRL0 0x00 23428564486SViorel Suman #define FSL_XCVR_PLL_CTRL0_SET 0x04 23528564486SViorel Suman #define FSL_XCVR_PLL_CTRL0_CLR 0x08 23628564486SViorel Suman #define FSL_XCVR_PLL_NUM 0x20 23728564486SViorel Suman #define FSL_XCVR_PLL_DEN 0x30 23828564486SViorel Suman #define FSL_XCVR_PLL_PDIV 0x40 23928564486SViorel Suman #define FSL_XCVR_PLL_BANDGAP_SET 0x54 24028564486SViorel Suman #define FSL_XCVR_PHY_CTRL 0x00 24128564486SViorel Suman #define FSL_XCVR_PHY_CTRL_SET 0x04 24228564486SViorel Suman #define FSL_XCVR_PHY_CTRL_CLR 0x08 24328564486SViorel Suman #define FSL_XCVR_PHY_CTRL2 0x70 24428564486SViorel Suman #define FSL_XCVR_PHY_CTRL2_SET 0x74 24528564486SViorel Suman #define FSL_XCVR_PHY_CTRL2_CLR 0x78 24628564486SViorel Suman 24728564486SViorel Suman #define FSL_XCVR_PLL_BANDGAP_EN_VBG BIT(0) 24828564486SViorel Suman #define FSL_XCVR_PLL_CTRL0_HROFF BIT(13) 24928564486SViorel Suman #define FSL_XCVR_PLL_CTRL0_PWP BIT(14) 25028564486SViorel Suman #define FSL_XCVR_PLL_CTRL0_CM0_EN BIT(24) 25128564486SViorel Suman #define FSL_XCVR_PLL_CTRL0_CM1_EN BIT(25) 25228564486SViorel Suman #define FSL_XCVR_PLL_CTRL0_CM2_EN BIT(26) 25328564486SViorel Suman #define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i)) 25428564486SViorel Suman 25528564486SViorel Suman #define FSL_XCVR_PHY_CTRL_PHY_EN BIT(0) 25628564486SViorel Suman #define FSL_XCVR_PHY_CTRL_RX_CM_EN BIT(1) 25728564486SViorel Suman #define FSL_XCVR_PHY_CTRL_TSDIFF_OE BIT(5) 25828564486SViorel Suman #define FSL_XCVR_PHY_CTRL_SPDIF_EN BIT(8) 25928564486SViorel Suman #define FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN BIT(9) 26028564486SViorel Suman #define FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN BIT(10) 26128564486SViorel Suman #define FSL_XCVR_PHY_CTRL_TX_CLK_MASK GENMASK(26, 25) 26228564486SViorel Suman #define FSL_XCVR_PHY_CTRL_TX_CLK_HDMI_SS BIT(25) 26328564486SViorel Suman #define FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS BIT(26) 26428564486SViorel Suman #define FSL_XCVR_PHY_CTRL2_EARC_TXMS BIT(14) 26528564486SViorel Suman 26628564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_MASK GENMASK(31, 24) 26728564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_32000 0x3000000 26828564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_44100 0x0000000 26928564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_48000 0x2000000 27028564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_64000 0xB000000 27128564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_88200 0x8000000 27228564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_96000 0xA000000 27328564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_176400 0xC000000 27428564486SViorel Suman #define FSL_XCVR_CS_DATA_0_FS_192000 0xE000000 27528564486SViorel Suman 27628564486SViorel Suman #define FSL_XCVR_CS_DATA_0_CH_MASK 0x3A 27728564486SViorel Suman #define FSL_XCVR_CS_DATA_0_CH_U2LPCM 0x00 27828564486SViorel Suman #define FSL_XCVR_CS_DATA_0_CH_UMLPCM 0x20 27928564486SViorel Suman #define FSL_XCVR_CS_DATA_0_CH_U1BAUD 0x30 28028564486SViorel Suman 28128564486SViorel Suman #define FSL_XCVR_CS_DATA_1_CH_MASK 0xF000 28228564486SViorel Suman #define FSL_XCVR_CS_DATA_1_CH_2 0x0000 28328564486SViorel Suman #define FSL_XCVR_CS_DATA_1_CH_8 0x7000 28428564486SViorel Suman #define FSL_XCVR_CS_DATA_1_CH_16 0xB000 28528564486SViorel Suman #define FSL_XCVR_CS_DATA_1_CH_32 0x3000 28628564486SViorel Suman 28728564486SViorel Suman /* Data memory structures */ 28828564486SViorel Suman #define FSL_XCVR_RX_CS_CTRL_0 0x20 /* First RX CS control register */ 28928564486SViorel Suman #define FSL_XCVR_RX_CS_CTRL_1 0x24 /* Second RX CS control register */ 29028564486SViorel Suman #define FSL_XCVR_RX_CS_BUFF_0 0x80 /* First RX CS buffer */ 29128564486SViorel Suman #define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */ 29228564486SViorel Suman #define FSL_XCVR_CAP_DATA_STR 0x300 /* Capabilities data structure */ 29328564486SViorel Suman 294*f13b349eSShengjiu Wang /* GP PLL Registers */ 295*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL 0x00 296*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_SET 0x04 297*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_CLR 0x08 298*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_TOG 0x0C 299*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_ANA_PRG 0x10 300*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_ANA_PRG_SET 0x14 301*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_ANA_PRG_CLR 0x18 302*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_ANA_PRG_TOG 0x1C 303*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_TEST 0x20 304*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_TEST_SET 0x24 305*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_TEST_CLR 0x28 306*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_TEST_TOG 0x2C 307*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM 0x30 308*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_SET 0x34 309*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_CLR 0x38 310*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_TOG 0x3C 311*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_NUMERATOR 0x40 312*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_NUMERATOR_SET 0x44 313*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_NUMERATOR_CLR 0x48 314*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_NUMERATOR_TOG 0x4C 315*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DENOMINATOR 0x50 316*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DENOMINATOR_SET 0x54 317*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DENOMINATOR_CLR 0x58 318*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DENOMINATOR_TOG 0x5C 319*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV 0x60 320*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV_SET 0x64 321*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV_CLR 0x68 322*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV_TOG 0x6C 323*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL0 0x70 324*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL0_SET 0x74 325*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL0_CLR 0x78 326*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL0_TOG 0x7C 327*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV0 0x80 328*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV0_SET 0x84 329*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV0_CLR 0x88 330*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV0_TOG 0x8C 331*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL1 0x90 332*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL1_SET 0x94 333*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL1_CLR 0x98 334*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL1_TOG 0x9C 335*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV1 0xA0 336*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV1_SET 0xA4 337*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV1_CLR 0xA8 338*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV1_TOG 0xAC 339*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL2 0xB0 340*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL2_SET 0xB4 341*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL2_CLR 0xB8 342*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL2_TOG 0xBC 343*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV2 0xC0 344*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV2_SET 0xC4 345*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV2_CLR 0xC8 346*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV2_TOG 0xCC 347*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL3 0xD0 348*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL3_SET 0xD4 349*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL3_CLR 0xD8 350*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_CTRL3_TOG 0xDC 351*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV3 0xE0 352*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV3_SET 0xE4 353*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV3_CLR 0xE8 354*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DFS_DIV3_TOG 0xEC 355*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_STATUS 0xF0 356*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_STATUS_SET 0xF4 357*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_STATUS_CLR 0xF8 358*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_STATUS_TOG 0xFC 359*f13b349eSShengjiu Wang 360*f13b349eSShengjiu Wang /* GP PLL Control Register */ 361*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_LBYPASS BIT(31) 362*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_HCS BIT(16) 363*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_MSD BIT(12) 364*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_DITHER_EN3 BIT(11) 365*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_DITHER_EN2 BIT(10) 366*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_DITHER_EN1 BIT(9) 367*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_SPREADCTL BIT(8) 368*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_CLKMUX_BYPASS BIT(2) 369*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN BIT(1) 370*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_CTRL_POWERUP BIT(0) 371*f13b349eSShengjiu Wang 372*f13b349eSShengjiu Wang /* GP PLL Numerator Register */ 373*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT 2 374*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_NUMERATOR_MFN GENMASK(31, 2) 375*f13b349eSShengjiu Wang 376*f13b349eSShengjiu Wang /* GP PLL Denominator Register */ 377*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DENOMINATOR_MFD GENMASK(29, 0) 378*f13b349eSShengjiu Wang 379*f13b349eSShengjiu Wang /* GP PLL Dividers Register */ 380*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV_MFI_SHIFT 16 381*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV_MFI GENMASK(24, 16) 382*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV_RDIV GENMASK(15, 13) 383*f13b349eSShengjiu Wang #define FSL_XCVR_GP_PLL_DIV_ODIV GENMASK(7, 0) 384*f13b349eSShengjiu Wang 38528564486SViorel Suman #endif /* __FSL_XCVR_H */ 386