1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2019 NXP 3 4 #include <linux/bitrev.h> 5 #include <linux/clk.h> 6 #include <linux/firmware.h> 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of_platform.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 #include <linux/reset.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_iec958.h> 15 #include <sound/pcm_params.h> 16 17 #include "fsl_xcvr.h" 18 #include "fsl_utils.h" 19 #include "imx-pcm.h" 20 21 #define FSL_XCVR_CAPDS_SIZE 256 22 #define SPDIF_NUM_RATES 7 23 24 enum fsl_xcvr_pll_verison { 25 PLL_MX8MP, 26 PLL_MX95, 27 }; 28 29 struct fsl_xcvr_soc_data { 30 const char *fw_name; 31 bool spdif_only; 32 bool use_edma; 33 bool use_phy; 34 enum fsl_xcvr_pll_verison pll_ver; 35 }; 36 37 struct fsl_xcvr { 38 const struct fsl_xcvr_soc_data *soc_data; 39 struct platform_device *pdev; 40 struct regmap *regmap; 41 struct regmap *regmap_phy; 42 struct regmap *regmap_pll; 43 struct clk *ipg_clk; 44 struct clk *pll_ipg_clk; 45 struct clk *phy_clk; 46 struct clk *spba_clk; 47 struct clk *pll8k_clk; 48 struct clk *pll11k_clk; 49 struct reset_control *reset; 50 u8 streams; 51 u32 mode; 52 u32 arc_mode; 53 void __iomem *ram_addr; 54 struct snd_dmaengine_dai_dma_data dma_prms_rx; 55 struct snd_dmaengine_dai_dma_data dma_prms_tx; 56 struct snd_aes_iec958 rx_iec958; 57 struct snd_aes_iec958 tx_iec958; 58 u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; 59 struct work_struct work_rst; 60 spinlock_t lock; /* Protect hw_reset and trigger */ 61 struct snd_pcm_hw_constraint_list spdif_constr_rates; 62 u32 spdif_constr_rates_list[SPDIF_NUM_RATES]; 63 }; 64 65 static const struct fsl_xcvr_pll_conf { 66 u8 mfi; /* min=0x18, max=0x38 */ 67 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ 68 u32 mfd; /* unsigned int */ 69 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */ 70 } fsl_xcvr_pll_cfg[] = { 71 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */ 72 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */ 73 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */ 74 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */ 75 }; 76 77 /* 78 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio 79 * stream. Todo: to check how this case can be considered below 80 */ 81 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; 82 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = { 83 .count = ARRAY_SIZE(fsl_xcvr_earc_channels), 84 .list = fsl_xcvr_earc_channels, 85 }; 86 87 static const u32 fsl_xcvr_earc_rates[] = { 88 32000, 44100, 48000, 64000, 88200, 96000, 89 128000, 176400, 192000, 256000, 352800, 384000, 90 512000, 705600, 768000, 1024000, 1411200, 1536000, 91 }; 92 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = { 93 .count = ARRAY_SIZE(fsl_xcvr_earc_rates), 94 .list = fsl_xcvr_earc_rates, 95 }; 96 97 static const u32 fsl_xcvr_spdif_channels[] = { 2, }; 98 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = { 99 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels), 100 .list = fsl_xcvr_spdif_channels, 101 }; 102 103 static const u32 fsl_xcvr_spdif_rates[] = { 104 32000, 44100, 48000, 88200, 96000, 176400, 192000, 105 }; 106 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = { 107 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates), 108 .list = fsl_xcvr_spdif_rates, 109 }; 110 111 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol, 112 struct snd_ctl_elem_value *ucontrol) 113 { 114 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 115 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 117 unsigned int *item = ucontrol->value.enumerated.item; 118 119 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); 120 121 return 0; 122 } 123 124 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol, 125 struct snd_ctl_elem_value *ucontrol) 126 { 127 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 128 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 129 130 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; 131 132 return 0; 133 } 134 135 static const u32 fsl_xcvr_phy_arc_cfg[] = { 136 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN, 137 }; 138 139 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", }; 140 static const struct soc_enum fsl_xcvr_arc_mode_enum = 141 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode); 142 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl = 143 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum, 144 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put); 145 146 /* Capabilities data structure, bytes */ 147 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol, 148 struct snd_ctl_elem_info *uinfo) 149 { 150 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 151 uinfo->count = FSL_XCVR_CAPDS_SIZE; 152 153 return 0; 154 } 155 156 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol, 157 struct snd_ctl_elem_value *ucontrol) 158 { 159 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 160 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 161 162 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); 163 164 return 0; 165 } 166 167 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol, 168 struct snd_ctl_elem_value *ucontrol) 169 { 170 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 171 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 172 173 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); 174 175 return 0; 176 } 177 178 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = { 179 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 180 .name = "Capabilities Data Structure", 181 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 182 .info = fsl_xcvr_type_capds_bytes_info, 183 .get = fsl_xcvr_capds_get, 184 .put = fsl_xcvr_capds_put, 185 }; 186 187 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name, 188 bool active) 189 { 190 struct snd_soc_card *card = dai->component->card; 191 struct snd_kcontrol *kctl; 192 bool enabled; 193 194 lockdep_assert_held(&card->snd_card->controls_rwsem); 195 196 kctl = snd_soc_card_get_kcontrol(card, name); 197 if (kctl == NULL) 198 return -ENOENT; 199 200 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); 201 if (active == enabled) 202 return 0; /* nothing to do */ 203 204 if (active) 205 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 206 else 207 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; 208 209 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); 210 211 return 1; 212 } 213 214 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol, 215 struct snd_ctl_elem_value *ucontrol) 216 { 217 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 218 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 219 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 220 unsigned int *item = ucontrol->value.enumerated.item; 221 struct snd_soc_card *card = dai->component->card; 222 struct snd_soc_pcm_runtime *rtd; 223 224 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); 225 226 down_read(&card->snd_card->controls_rwsem); 227 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 228 (xcvr->mode == FSL_XCVR_MODE_ARC)); 229 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 230 (xcvr->mode == FSL_XCVR_MODE_EARC)); 231 up_read(&card->snd_card->controls_rwsem); 232 233 /* Allow playback for SPDIF only */ 234 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 235 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = 236 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); 237 return 0; 238 } 239 240 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol, 241 struct snd_ctl_elem_value *ucontrol) 242 { 243 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 244 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 245 246 ucontrol->value.enumerated.item[0] = xcvr->mode; 247 248 return 0; 249 } 250 251 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", }; 252 static const struct soc_enum fsl_xcvr_mode_enum = 253 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode); 254 static struct snd_kcontrol_new fsl_xcvr_mode_kctl = 255 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum, 256 fsl_xcvr_mode_get, fsl_xcvr_mode_put); 257 258 /** phy: true => phy, false => pll */ 259 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) 260 { 261 struct device *dev = &xcvr->pdev->dev; 262 u32 val, idx, tidx; 263 int ret; 264 265 idx = BIT(phy ? 26 : 24); 266 tidx = BIT(phy ? 27 : 25); 267 268 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 269 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); 270 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); 271 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 272 273 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 274 (val & idx) == ((val & tidx) >> 1), 275 10, 10000); 276 if (ret) 277 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n", 278 phy ? "PHY" : "PLL", reg, data); 279 return ret; 280 } 281 282 static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy) 283 { 284 struct device *dev = &xcvr->pdev->dev; 285 u32 val, idx, tidx; 286 int ret; 287 288 idx = BIT(phy ? 26 : 24); 289 tidx = BIT(phy ? 27 : 25); 290 291 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 292 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB); 293 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 294 295 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 296 (val & idx) == ((val & tidx) >> 1), 297 10, 10000); 298 if (ret) 299 dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n", 300 phy ? "PHY" : "PLL", reg); 301 302 regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data); 303 304 return ret; 305 } 306 307 static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val) 308 { 309 struct fsl_xcvr *xcvr = context; 310 311 return fsl_xcvr_ai_read(xcvr, reg, val, 1); 312 } 313 314 static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val) 315 { 316 struct fsl_xcvr *xcvr = context; 317 318 return fsl_xcvr_ai_write(xcvr, reg, val, 1); 319 } 320 321 static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val) 322 { 323 struct fsl_xcvr *xcvr = context; 324 325 return fsl_xcvr_ai_read(xcvr, reg, val, 0); 326 } 327 328 static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val) 329 { 330 struct fsl_xcvr *xcvr = context; 331 332 return fsl_xcvr_ai_write(xcvr, reg, val, 0); 333 } 334 335 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) 336 { 337 struct device *dev = &xcvr->pdev->dev; 338 u32 i, div = 0, log2, val; 339 int ret; 340 341 if (!xcvr->soc_data->use_phy) 342 return 0; 343 344 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) { 345 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) { 346 div = fsl_xcvr_pll_cfg[i].fout / freq; 347 break; 348 } 349 } 350 351 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg)) 352 return -EINVAL; 353 354 log2 = ilog2(div); 355 356 /* Release AI interface from reset */ 357 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 358 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 359 if (ret < 0) { 360 dev_err(dev, "Error while setting IER0: %d\n", ret); 361 return ret; 362 } 363 364 switch (xcvr->soc_data->pll_ver) { 365 case PLL_MX8MP: 366 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ 367 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP, 368 FSL_XCVR_PLL_BANDGAP_EN_VBG); 369 370 /* PLL: CTRL0: DIV_INTEGER */ 371 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi); 372 /* PLL: NUMERATOR: MFN */ 373 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn); 374 /* PLL: DENOMINATOR: MFD */ 375 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd); 376 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ 377 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 378 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP); 379 udelay(25); 380 /* PLL: CTRL0: Clear Hold Ring Off */ 381 regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 382 FSL_XCVR_PLL_CTRL0_HROFF); 383 udelay(100); 384 if (tx) { /* TX is enabled for SPDIF only */ 385 /* PLL: POSTDIV: PDIV0 */ 386 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 387 FSL_XCVR_PLL_PDIVx(log2, 0)); 388 /* PLL: CTRL_SET: CLKMUX0_EN */ 389 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 390 FSL_XCVR_PLL_CTRL0_CM0_EN); 391 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ 392 /* PLL: POSTDIV: PDIV1 */ 393 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 394 FSL_XCVR_PLL_PDIVx(log2, 1)); 395 /* PLL: CTRL_SET: CLKMUX1_EN */ 396 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 397 FSL_XCVR_PLL_CTRL0_CM1_EN); 398 } else { /* SPDIF / ARC RX */ 399 /* PLL: POSTDIV: PDIV2 */ 400 regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, 401 FSL_XCVR_PLL_PDIVx(log2, 2)); 402 /* PLL: CTRL_SET: CLKMUX2_EN */ 403 regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, 404 FSL_XCVR_PLL_CTRL0_CM2_EN); 405 } 406 break; 407 case PLL_MX95: 408 val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div; 409 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val); 410 val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT; 411 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val); 412 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR, 413 fsl_xcvr_pll_cfg[i].mfd); 414 val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN; 415 regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val); 416 break; 417 default: 418 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); 419 return -EINVAL; 420 } 421 422 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 423 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 424 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 425 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 426 FSL_XCVR_PHY_CTRL_PHY_EN); 427 /* PHY: CTRL2_SET: EARC_TX_MODE */ 428 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 429 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 430 } else if (!tx) { /* SPDIF / ARC RX mode */ 431 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 432 /* PHY: CTRL_SET: SPDIF_EN */ 433 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 434 FSL_XCVR_PHY_CTRL_SPDIF_EN); 435 else /* PHY: CTRL_SET: ARC RX setup */ 436 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 437 FSL_XCVR_PHY_CTRL_PHY_EN | 438 FSL_XCVR_PHY_CTRL_RX_CM_EN | 439 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]); 440 } 441 442 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", 443 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi, 444 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2); 445 return 0; 446 } 447 448 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) 449 { 450 struct device *dev = &xcvr->pdev->dev; 451 int ret; 452 453 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; 454 clk_disable_unprepare(xcvr->phy_clk); 455 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk, 456 xcvr->pll8k_clk, xcvr->pll11k_clk, freq); 457 ret = clk_set_rate(xcvr->phy_clk, freq); 458 if (ret < 0) { 459 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret); 460 return ret; 461 } 462 ret = clk_prepare_enable(xcvr->phy_clk); 463 if (ret) { 464 dev_err(dev, "failed to start PHY clock: %d\n", ret); 465 return ret; 466 } 467 468 if (!xcvr->soc_data->use_phy) 469 return 0; 470 /* Release AI interface from reset */ 471 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 472 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 473 if (ret < 0) { 474 dev_err(dev, "Error while setting IER0: %d\n", ret); 475 return ret; 476 } 477 478 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 479 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 480 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 481 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 482 FSL_XCVR_PHY_CTRL_PHY_EN); 483 /* PHY: CTRL2_SET: EARC_TX_MODE */ 484 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, 485 FSL_XCVR_PHY_CTRL2_EARC_TXMS); 486 } else { /* SPDIF mode */ 487 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ 488 regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, 489 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | 490 FSL_XCVR_PHY_CTRL_SPDIF_EN); 491 } 492 493 dev_dbg(dev, "PLL Fexp: %u\n", freq); 494 495 return 0; 496 } 497 498 #define FSL_XCVR_SPDIF_RX_FREQ 175000000 499 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, 500 struct snd_soc_dai *dai) 501 { 502 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 503 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 504 u32 m_ctl = 0, v_ctl = 0; 505 u32 r = substream->runtime->rate, ch = substream->runtime->channels; 506 u32 fout = 32 * r * ch * 10; 507 int ret = 0; 508 509 switch (xcvr->mode) { 510 case FSL_XCVR_MODE_SPDIF: 511 if (xcvr->soc_data->spdif_only && tx) { 512 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 513 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, 514 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); 515 if (ret < 0) { 516 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); 517 return ret; 518 } 519 } 520 fallthrough; 521 case FSL_XCVR_MODE_ARC: 522 if (tx) { 523 ret = fsl_xcvr_en_aud_pll(xcvr, fout); 524 if (ret < 0) { 525 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", 526 fout, ret); 527 return ret; 528 } 529 530 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, 531 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); 532 if (ret < 0) { 533 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); 534 return ret; 535 } 536 537 /** 538 * set SPDIF MODE - this flag is used to gate 539 * SPDIF output, useless for SPDIF RX 540 */ 541 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 542 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 543 } else { 544 /** 545 * Clear RX FIFO, flip RX FIFO bits, 546 * disable eARC related HW mode detects 547 */ 548 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 549 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 550 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | 551 FSL_XCVR_RX_DPTH_CTRL_COMP | 552 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 553 if (ret < 0) { 554 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 555 return ret; 556 } 557 558 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); 559 if (ret < 0) { 560 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", 561 FSL_XCVR_SPDIF_RX_FREQ, ret); 562 return ret; 563 } 564 } 565 break; 566 case FSL_XCVR_MODE_EARC: 567 if (!tx) { 568 /** Clear RX FIFO, flip RX FIFO bits */ 569 ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 570 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 571 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); 572 if (ret < 0) { 573 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 574 return ret; 575 } 576 577 /** Enable eARC related HW mode detects */ 578 ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 579 FSL_XCVR_RX_DPTH_CTRL_COMP | 580 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 581 if (ret < 0) { 582 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); 583 return ret; 584 } 585 } 586 587 /* clear CMDC RESET */ 588 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 589 /* set TX_RX_MODE */ 590 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE; 591 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0); 592 break; 593 } 594 595 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); 596 if (ret < 0) { 597 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); 598 return ret; 599 } 600 601 return 0; 602 } 603 604 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream, 605 const struct snd_pcm_hw_constraint_list *channels, 606 const struct snd_pcm_hw_constraint_list *rates) 607 { 608 struct snd_pcm_runtime *rt = substream->runtime; 609 int ret; 610 611 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 612 channels); 613 if (ret < 0) 614 return ret; 615 616 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE, 617 rates); 618 if (ret < 0) 619 return ret; 620 621 return 0; 622 } 623 624 static int fsl_xcvr_startup(struct snd_pcm_substream *substream, 625 struct snd_soc_dai *dai) 626 { 627 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 628 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 629 int ret = 0; 630 631 if (xcvr->streams & BIT(substream->stream)) { 632 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); 633 return -EBUSY; 634 } 635 636 /* 637 * EDMA controller needs period size to be a multiple of 638 * tx/rx maxburst 639 */ 640 if (xcvr->soc_data->use_edma) 641 snd_pcm_hw_constraint_step(substream->runtime, 0, 642 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 643 tx ? xcvr->dma_prms_tx.maxburst : 644 xcvr->dma_prms_rx.maxburst); 645 646 switch (xcvr->mode) { 647 case FSL_XCVR_MODE_SPDIF: 648 case FSL_XCVR_MODE_ARC: 649 if (xcvr->soc_data->spdif_only && tx) 650 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 651 &xcvr->spdif_constr_rates); 652 else 653 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 654 &fsl_xcvr_spdif_rates_constr); 655 break; 656 case FSL_XCVR_MODE_EARC: 657 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr, 658 &fsl_xcvr_earc_rates_constr); 659 break; 660 } 661 if (ret < 0) 662 return ret; 663 664 xcvr->streams |= BIT(substream->stream); 665 666 if (!xcvr->soc_data->spdif_only) { 667 struct snd_soc_card *card = dai->component->card; 668 669 /* Disable XCVR controls if there is stream started */ 670 down_read(&card->snd_card->controls_rwsem); 671 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false); 672 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false); 673 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false); 674 up_read(&card->snd_card->controls_rwsem); 675 } 676 677 return 0; 678 } 679 680 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream, 681 struct snd_soc_dai *dai) 682 { 683 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 684 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 685 u32 mask = 0, val = 0; 686 int ret; 687 688 xcvr->streams &= ~BIT(substream->stream); 689 690 /* Enable XCVR controls if there is no stream started */ 691 if (!xcvr->streams) { 692 if (!xcvr->soc_data->spdif_only) { 693 struct snd_soc_card *card = dai->component->card; 694 695 down_read(&card->snd_card->controls_rwsem); 696 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true); 697 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 698 (xcvr->mode == FSL_XCVR_MODE_ARC)); 699 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 700 (xcvr->mode == FSL_XCVR_MODE_EARC)); 701 up_read(&card->snd_card->controls_rwsem); 702 } 703 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 704 FSL_XCVR_IRQ_EARC_ALL, 0); 705 if (ret < 0) { 706 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); 707 return; 708 } 709 710 /* clear SPDIF MODE */ 711 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 712 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 713 } 714 715 if (xcvr->mode == FSL_XCVR_MODE_EARC) { 716 /* set CMDC RESET */ 717 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 718 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 719 } 720 721 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 722 if (ret < 0) { 723 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); 724 return; 725 } 726 } 727 728 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, 729 struct snd_soc_dai *dai) 730 { 731 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 732 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 733 unsigned long lock_flags; 734 int ret = 0; 735 736 spin_lock_irqsave(&xcvr->lock, lock_flags); 737 738 switch (cmd) { 739 case SNDRV_PCM_TRIGGER_START: 740 case SNDRV_PCM_TRIGGER_RESUME: 741 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 742 /* set DPATH RESET */ 743 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 744 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 745 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx)); 746 if (ret < 0) { 747 dev_err(dai->dev, "Failed to set DPATH RESET: %d\n", ret); 748 goto release_lock; 749 } 750 751 if (tx) { 752 switch (xcvr->mode) { 753 case FSL_XCVR_MODE_EARC: 754 /* set isr_cmdc_tx_en, w1c */ 755 ret = regmap_write(xcvr->regmap, 756 FSL_XCVR_ISR_SET, 757 FSL_XCVR_ISR_CMDC_TX_EN); 758 if (ret < 0) { 759 dev_err(dai->dev, "err updating isr %d\n", ret); 760 goto release_lock; 761 } 762 fallthrough; 763 case FSL_XCVR_MODE_SPDIF: 764 ret = regmap_set_bits(xcvr->regmap, 765 FSL_XCVR_TX_DPTH_CTRL, 766 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 767 if (ret < 0) { 768 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); 769 goto release_lock; 770 } 771 break; 772 } 773 } 774 775 /* enable DMA RD/WR */ 776 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 777 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0); 778 if (ret < 0) { 779 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); 780 goto release_lock; 781 } 782 783 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 784 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL); 785 if (ret < 0) { 786 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); 787 goto release_lock; 788 } 789 790 /* clear DPATH RESET */ 791 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 792 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 793 0); 794 if (ret < 0) { 795 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); 796 goto release_lock; 797 } 798 799 break; 800 case SNDRV_PCM_TRIGGER_STOP: 801 case SNDRV_PCM_TRIGGER_SUSPEND: 802 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 803 /* disable DMA RD/WR */ 804 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 805 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 806 FSL_XCVR_EXT_CTRL_DMA_DIS(tx)); 807 if (ret < 0) { 808 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); 809 goto release_lock; 810 } 811 812 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 813 FSL_XCVR_IRQ_EARC_ALL, 0); 814 if (ret < 0) { 815 dev_err(dai->dev, "Failed to clear IER0: %d\n", ret); 816 goto release_lock; 817 } 818 819 if (tx) { 820 switch (xcvr->mode) { 821 case FSL_XCVR_MODE_SPDIF: 822 ret = regmap_clear_bits(xcvr->regmap, 823 FSL_XCVR_TX_DPTH_CTRL, 824 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 825 if (ret < 0) { 826 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); 827 goto release_lock; 828 } 829 if (xcvr->soc_data->spdif_only) 830 break; 831 else 832 fallthrough; 833 case FSL_XCVR_MODE_EARC: 834 /* clear ISR_CMDC_TX_EN, W1C */ 835 ret = regmap_write(xcvr->regmap, 836 FSL_XCVR_ISR_CLR, 837 FSL_XCVR_ISR_CMDC_TX_EN); 838 if (ret < 0) { 839 dev_err(dai->dev, 840 "Err updating ISR %d\n", ret); 841 goto release_lock; 842 } 843 break; 844 } 845 } 846 break; 847 default: 848 ret = -EINVAL; 849 break; 850 } 851 852 release_lock: 853 spin_unlock_irqrestore(&xcvr->lock, lock_flags); 854 return ret; 855 } 856 857 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) 858 { 859 struct device *dev = &xcvr->pdev->dev; 860 const struct firmware *fw; 861 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET; 862 u32 mask, val; 863 864 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); 865 if (ret) { 866 dev_err(dev, "failed to request firmware.\n"); 867 return ret; 868 } 869 870 rem = fw->size; 871 872 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */ 873 if (rem > 16384) { 874 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem); 875 release_firmware(fw); 876 return -ENOMEM; 877 } 878 879 for (page = 0; page < 10; page++) { 880 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 881 FSL_XCVR_EXT_CTRL_PAGE_MASK, 882 FSL_XCVR_EXT_CTRL_PAGE(page)); 883 if (ret < 0) { 884 dev_err(dev, "FW: failed to set page %d, err=%d\n", 885 page, ret); 886 goto err_firmware; 887 } 888 889 off = page * size; 890 out = min(rem, size); 891 /* IPG clock is assumed to be running, otherwise it will hang */ 892 if (out > 0) { 893 /* write firmware into code memory */ 894 memcpy_toio(xcvr->ram_addr, fw->data + off, out); 895 rem -= out; 896 if (rem == 0) { 897 /* last part of firmware written */ 898 /* clean remaining part of code memory page */ 899 memset_io(xcvr->ram_addr + out, 0, size - out); 900 } 901 } else { 902 /* clean current page, including data memory */ 903 memset_io(xcvr->ram_addr, 0, size); 904 } 905 } 906 907 err_firmware: 908 release_firmware(fw); 909 if (ret < 0) 910 return ret; 911 912 /* configure watermarks */ 913 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK; 914 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX); 915 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX); 916 /* disable DMA RD/WR */ 917 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 918 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 919 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 920 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK; 921 val |= FSL_XCVR_EXT_CTRL_PAGE(8); 922 923 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 924 if (ret < 0) { 925 dev_err(dev, "Failed to set watermarks: %d\n", ret); 926 return ret; 927 } 928 929 /* Store Capabilities Data Structure into Data RAM */ 930 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, 931 FSL_XCVR_CAPDS_SIZE); 932 return 0; 933 } 934 935 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol, 936 struct snd_ctl_elem_info *uinfo) 937 { 938 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 939 uinfo->count = 1; 940 941 return 0; 942 } 943 944 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol, 945 struct snd_ctl_elem_info *uinfo) 946 { 947 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 948 uinfo->count = sizeof_field(struct snd_aes_iec958, status); 949 950 return 0; 951 } 952 953 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol, 954 struct snd_ctl_elem_value *ucontrol) 955 { 956 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 957 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 958 959 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); 960 961 return 0; 962 } 963 964 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol, 965 struct snd_ctl_elem_value *ucontrol) 966 { 967 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 968 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 969 970 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); 971 972 return 0; 973 } 974 975 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol, 976 struct snd_ctl_elem_value *ucontrol) 977 { 978 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 979 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 980 981 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); 982 983 return 0; 984 } 985 986 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = { 987 /* Channel status controller */ 988 { 989 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 990 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 991 .access = SNDRV_CTL_ELEM_ACCESS_READ, 992 .info = fsl_xcvr_type_iec958_info, 993 .get = fsl_xcvr_rx_cs_get, 994 }, 995 /* Capture channel status, bytes */ 996 { 997 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 998 .name = "Capture Channel Status", 999 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1000 .info = fsl_xcvr_type_iec958_bytes_info, 1001 .get = fsl_xcvr_rx_cs_get, 1002 }, 1003 }; 1004 1005 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = { 1006 /* Channel status controller */ 1007 { 1008 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1009 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1010 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1011 .info = fsl_xcvr_type_iec958_info, 1012 .get = fsl_xcvr_tx_cs_get, 1013 .put = fsl_xcvr_tx_cs_put, 1014 }, 1015 /* Playback channel status, bytes */ 1016 { 1017 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1018 .name = "Playback Channel Status", 1019 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1020 .info = fsl_xcvr_type_iec958_bytes_info, 1021 .get = fsl_xcvr_tx_cs_get, 1022 .put = fsl_xcvr_tx_cs_put, 1023 }, 1024 }; 1025 1026 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai) 1027 { 1028 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 1029 1030 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); 1031 1032 if (xcvr->soc_data->spdif_only) 1033 xcvr->mode = FSL_XCVR_MODE_SPDIF; 1034 else { 1035 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1); 1036 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1); 1037 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1); 1038 } 1039 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls, 1040 ARRAY_SIZE(fsl_xcvr_tx_ctls)); 1041 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls, 1042 ARRAY_SIZE(fsl_xcvr_rx_ctls)); 1043 return 0; 1044 } 1045 1046 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = { 1047 .probe = fsl_xcvr_dai_probe, 1048 .prepare = fsl_xcvr_prepare, 1049 .startup = fsl_xcvr_startup, 1050 .shutdown = fsl_xcvr_shutdown, 1051 .trigger = fsl_xcvr_trigger, 1052 }; 1053 1054 static struct snd_soc_dai_driver fsl_xcvr_dai = { 1055 .ops = &fsl_xcvr_dai_ops, 1056 .playback = { 1057 .stream_name = "CPU-Playback", 1058 .channels_min = 1, 1059 .channels_max = 32, 1060 .rate_min = 32000, 1061 .rate_max = 1536000, 1062 .rates = SNDRV_PCM_RATE_KNOT, 1063 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1064 }, 1065 .capture = { 1066 .stream_name = "CPU-Capture", 1067 .channels_min = 1, 1068 .channels_max = 32, 1069 .rate_min = 32000, 1070 .rate_max = 1536000, 1071 .rates = SNDRV_PCM_RATE_KNOT, 1072 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1073 }, 1074 }; 1075 1076 static const struct snd_soc_component_driver fsl_xcvr_comp = { 1077 .name = "fsl-xcvr-dai", 1078 .legacy_dai_naming = 1, 1079 }; 1080 1081 static const struct reg_default fsl_xcvr_reg_defaults[] = { 1082 { FSL_XCVR_VERSION, 0x00000000 }, 1083 { FSL_XCVR_EXT_CTRL, 0xF8204040 }, 1084 { FSL_XCVR_EXT_STATUS, 0x00000000 }, 1085 { FSL_XCVR_EXT_IER0, 0x00000000 }, 1086 { FSL_XCVR_EXT_IER1, 0x00000000 }, 1087 { FSL_XCVR_EXT_ISR, 0x00000000 }, 1088 { FSL_XCVR_EXT_ISR_SET, 0x00000000 }, 1089 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 }, 1090 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 }, 1091 { FSL_XCVR_IER, 0x00000000 }, 1092 { FSL_XCVR_ISR, 0x00000000 }, 1093 { FSL_XCVR_ISR_SET, 0x00000000 }, 1094 { FSL_XCVR_ISR_CLR, 0x00000000 }, 1095 { FSL_XCVR_ISR_TOG, 0x00000000 }, 1096 { FSL_XCVR_CLK_CTRL, 0x0000018F }, 1097 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 }, 1098 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 }, 1099 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 }, 1100 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 }, 1101 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 }, 1102 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1103 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1104 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1105 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 }, 1106 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 }, 1107 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 }, 1108 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 }, 1109 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 }, 1110 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 }, 1111 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 }, 1112 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 }, 1113 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 }, 1114 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 }, 1115 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 }, 1116 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 }, 1117 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 }, 1118 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 }, 1119 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 }, 1120 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1121 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1122 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1123 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 }, 1124 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 }, 1125 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 }, 1126 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 }, 1127 { FSL_XCVR_DEBUG_REG_0, 0x00000000 }, 1128 { FSL_XCVR_DEBUG_REG_1, 0x00000000 }, 1129 }; 1130 1131 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) 1132 { 1133 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1134 1135 if (!xcvr->soc_data->use_phy) 1136 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) || 1137 reg > FSL_XCVR_TX_DPTH_BCRR) 1138 return false; 1139 switch (reg) { 1140 case FSL_XCVR_VERSION: 1141 case FSL_XCVR_EXT_CTRL: 1142 case FSL_XCVR_EXT_STATUS: 1143 case FSL_XCVR_EXT_IER0: 1144 case FSL_XCVR_EXT_IER1: 1145 case FSL_XCVR_EXT_ISR: 1146 case FSL_XCVR_EXT_ISR_SET: 1147 case FSL_XCVR_EXT_ISR_CLR: 1148 case FSL_XCVR_EXT_ISR_TOG: 1149 case FSL_XCVR_IER: 1150 case FSL_XCVR_ISR: 1151 case FSL_XCVR_ISR_SET: 1152 case FSL_XCVR_ISR_CLR: 1153 case FSL_XCVR_ISR_TOG: 1154 case FSL_XCVR_PHY_AI_CTRL: 1155 case FSL_XCVR_PHY_AI_CTRL_SET: 1156 case FSL_XCVR_PHY_AI_CTRL_CLR: 1157 case FSL_XCVR_PHY_AI_CTRL_TOG: 1158 case FSL_XCVR_PHY_AI_RDATA: 1159 case FSL_XCVR_CLK_CTRL: 1160 case FSL_XCVR_RX_DPTH_CTRL: 1161 case FSL_XCVR_RX_DPTH_CTRL_SET: 1162 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1163 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1164 case FSL_XCVR_RX_CS_DATA_0: 1165 case FSL_XCVR_RX_CS_DATA_1: 1166 case FSL_XCVR_RX_CS_DATA_2: 1167 case FSL_XCVR_RX_CS_DATA_3: 1168 case FSL_XCVR_RX_CS_DATA_4: 1169 case FSL_XCVR_RX_CS_DATA_5: 1170 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1171 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1172 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1173 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1174 case FSL_XCVR_RX_DPTH_TSCR: 1175 case FSL_XCVR_RX_DPTH_BCR: 1176 case FSL_XCVR_RX_DPTH_BCTR: 1177 case FSL_XCVR_RX_DPTH_BCRR: 1178 case FSL_XCVR_TX_DPTH_CTRL: 1179 case FSL_XCVR_TX_DPTH_CTRL_SET: 1180 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1181 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1182 case FSL_XCVR_TX_CS_DATA_0: 1183 case FSL_XCVR_TX_CS_DATA_1: 1184 case FSL_XCVR_TX_CS_DATA_2: 1185 case FSL_XCVR_TX_CS_DATA_3: 1186 case FSL_XCVR_TX_CS_DATA_4: 1187 case FSL_XCVR_TX_CS_DATA_5: 1188 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1189 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1190 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1191 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1192 case FSL_XCVR_TX_DPTH_TSCR: 1193 case FSL_XCVR_TX_DPTH_BCR: 1194 case FSL_XCVR_TX_DPTH_BCTR: 1195 case FSL_XCVR_TX_DPTH_BCRR: 1196 case FSL_XCVR_DEBUG_REG_0: 1197 case FSL_XCVR_DEBUG_REG_1: 1198 return true; 1199 default: 1200 return false; 1201 } 1202 } 1203 1204 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) 1205 { 1206 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1207 1208 if (!xcvr->soc_data->use_phy) 1209 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) 1210 return false; 1211 switch (reg) { 1212 case FSL_XCVR_EXT_CTRL: 1213 case FSL_XCVR_EXT_IER0: 1214 case FSL_XCVR_EXT_IER1: 1215 case FSL_XCVR_EXT_ISR: 1216 case FSL_XCVR_EXT_ISR_SET: 1217 case FSL_XCVR_EXT_ISR_CLR: 1218 case FSL_XCVR_EXT_ISR_TOG: 1219 case FSL_XCVR_IER: 1220 case FSL_XCVR_ISR_SET: 1221 case FSL_XCVR_ISR_CLR: 1222 case FSL_XCVR_ISR_TOG: 1223 case FSL_XCVR_PHY_AI_CTRL: 1224 case FSL_XCVR_PHY_AI_CTRL_SET: 1225 case FSL_XCVR_PHY_AI_CTRL_CLR: 1226 case FSL_XCVR_PHY_AI_CTRL_TOG: 1227 case FSL_XCVR_PHY_AI_WDATA: 1228 case FSL_XCVR_CLK_CTRL: 1229 case FSL_XCVR_RX_DPTH_CTRL: 1230 case FSL_XCVR_RX_DPTH_CTRL_SET: 1231 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1232 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1233 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1234 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1235 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1236 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1237 case FSL_XCVR_TX_DPTH_CTRL: 1238 case FSL_XCVR_TX_DPTH_CTRL_SET: 1239 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1240 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1241 case FSL_XCVR_TX_CS_DATA_0: 1242 case FSL_XCVR_TX_CS_DATA_1: 1243 case FSL_XCVR_TX_CS_DATA_2: 1244 case FSL_XCVR_TX_CS_DATA_3: 1245 case FSL_XCVR_TX_CS_DATA_4: 1246 case FSL_XCVR_TX_CS_DATA_5: 1247 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1248 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1249 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1250 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1251 return true; 1252 default: 1253 return false; 1254 } 1255 } 1256 1257 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) 1258 { 1259 switch (reg) { 1260 case FSL_XCVR_EXT_STATUS: 1261 case FSL_XCVR_EXT_ISR: 1262 case FSL_XCVR_EXT_ISR_SET: 1263 case FSL_XCVR_EXT_ISR_CLR: 1264 case FSL_XCVR_EXT_ISR_TOG: 1265 case FSL_XCVR_ISR: 1266 case FSL_XCVR_ISR_SET: 1267 case FSL_XCVR_ISR_CLR: 1268 case FSL_XCVR_ISR_TOG: 1269 case FSL_XCVR_PHY_AI_CTRL: 1270 case FSL_XCVR_PHY_AI_CTRL_SET: 1271 case FSL_XCVR_PHY_AI_CTRL_CLR: 1272 case FSL_XCVR_PHY_AI_CTRL_TOG: 1273 case FSL_XCVR_PHY_AI_RDATA: 1274 case FSL_XCVR_RX_CS_DATA_0: 1275 case FSL_XCVR_RX_CS_DATA_1: 1276 case FSL_XCVR_RX_CS_DATA_2: 1277 case FSL_XCVR_RX_CS_DATA_3: 1278 case FSL_XCVR_RX_CS_DATA_4: 1279 case FSL_XCVR_RX_CS_DATA_5: 1280 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1281 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1282 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1283 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1284 case FSL_XCVR_RX_DPTH_TSCR: 1285 case FSL_XCVR_RX_DPTH_BCR: 1286 case FSL_XCVR_RX_DPTH_BCTR: 1287 case FSL_XCVR_RX_DPTH_BCRR: 1288 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1289 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1290 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1291 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1292 case FSL_XCVR_TX_DPTH_TSCR: 1293 case FSL_XCVR_TX_DPTH_BCR: 1294 case FSL_XCVR_TX_DPTH_BCTR: 1295 case FSL_XCVR_TX_DPTH_BCRR: 1296 case FSL_XCVR_DEBUG_REG_0: 1297 case FSL_XCVR_DEBUG_REG_1: 1298 return true; 1299 default: 1300 return false; 1301 } 1302 } 1303 1304 static const struct regmap_config fsl_xcvr_regmap_cfg = { 1305 .reg_bits = 32, 1306 .reg_stride = 4, 1307 .val_bits = 32, 1308 .max_register = FSL_XCVR_MAX_REG, 1309 .reg_defaults = fsl_xcvr_reg_defaults, 1310 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults), 1311 .readable_reg = fsl_xcvr_readable_reg, 1312 .volatile_reg = fsl_xcvr_volatile_reg, 1313 .writeable_reg = fsl_xcvr_writeable_reg, 1314 .cache_type = REGCACHE_FLAT, 1315 }; 1316 1317 static const struct reg_default fsl_xcvr_phy_reg_defaults[] = { 1318 { FSL_XCVR_PHY_CTRL, 0x58200804 }, 1319 { FSL_XCVR_PHY_STATUS, 0x00000000 }, 1320 { FSL_XCVR_PHY_ANALOG_TRIM, 0x00260F13 }, 1321 { FSL_XCVR_PHY_SLEW_RATE_TRIM, 0x00000411 }, 1322 { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 }, 1323 { FSL_XCVR_PHY_TEST_CTRL, 0x00000000 }, 1324 { FSL_XCVR_PHY_DIFF_CDR_CTRL, 0x016D0009 }, 1325 { FSL_XCVR_PHY_CTRL2, 0x80000000 }, 1326 }; 1327 1328 static const struct regmap_config fsl_xcvr_regmap_phy_cfg = { 1329 .name = "phy", 1330 .reg_bits = 8, 1331 .reg_stride = 4, 1332 .val_bits = 32, 1333 .max_register = FSL_XCVR_PHY_CTRL2_TOG, 1334 .reg_defaults = fsl_xcvr_phy_reg_defaults, 1335 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults), 1336 .cache_type = REGCACHE_FLAT, 1337 .reg_read = fsl_xcvr_phy_reg_read, 1338 .reg_write = fsl_xcvr_phy_reg_write, 1339 }; 1340 1341 static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = { 1342 .name = "pllv0", 1343 .reg_bits = 8, 1344 .reg_stride = 4, 1345 .val_bits = 32, 1346 .max_register = FSL_XCVR_PLL_STAT0_TOG, 1347 .cache_type = REGCACHE_FLAT, 1348 .reg_read = fsl_xcvr_pll_reg_read, 1349 .reg_write = fsl_xcvr_pll_reg_write, 1350 }; 1351 1352 static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = { 1353 .name = "pllv1", 1354 .reg_bits = 8, 1355 .reg_stride = 4, 1356 .val_bits = 32, 1357 .max_register = FSL_XCVR_GP_PLL_STATUS_TOG, 1358 .cache_type = REGCACHE_FLAT, 1359 .reg_read = fsl_xcvr_pll_reg_read, 1360 .reg_write = fsl_xcvr_pll_reg_write, 1361 }; 1362 1363 static void reset_rx_work(struct work_struct *work) 1364 { 1365 struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst); 1366 struct device *dev = &xcvr->pdev->dev; 1367 unsigned long lock_flags; 1368 u32 ext_ctrl; 1369 1370 dev_dbg(dev, "reset rx path\n"); 1371 spin_lock_irqsave(&xcvr->lock, lock_flags); 1372 regmap_read(xcvr->regmap, FSL_XCVR_EXT_CTRL, &ext_ctrl); 1373 1374 if (!(ext_ctrl & FSL_XCVR_EXT_CTRL_DMA_RD_DIS)) { 1375 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1376 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1377 FSL_XCVR_EXT_CTRL_DMA_RD_DIS); 1378 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1379 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1380 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET); 1381 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1382 FSL_XCVR_EXT_CTRL_DMA_RD_DIS, 1383 0); 1384 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1385 FSL_XCVR_EXT_CTRL_RX_DPTH_RESET, 1386 0); 1387 } 1388 spin_unlock_irqrestore(&xcvr->lock, lock_flags); 1389 } 1390 1391 static irqreturn_t irq0_isr(int irq, void *devid) 1392 { 1393 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; 1394 struct device *dev = &xcvr->pdev->dev; 1395 struct regmap *regmap = xcvr->regmap; 1396 void __iomem *reg_ctrl, *reg_buff; 1397 u32 isr, isr_clr = 0, val, i; 1398 1399 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr); 1400 1401 if (isr & FSL_XCVR_IRQ_NEW_CS) { 1402 dev_dbg(dev, "Received new CS block\n"); 1403 isr_clr |= FSL_XCVR_IRQ_NEW_CS; 1404 if (xcvr->soc_data->fw_name) { 1405 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 1406 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1407 FSL_XCVR_EXT_CTRL_PAGE_MASK, 1408 FSL_XCVR_EXT_CTRL_PAGE(8)); 1409 1410 /* Find updated CS buffer */ 1411 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; 1412 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; 1413 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1414 if (!val) { 1415 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; 1416 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; 1417 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1418 } 1419 1420 if (val) { 1421 /* copy CS buffer */ 1422 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, 1423 sizeof(xcvr->rx_iec958.status)); 1424 for (i = 0; i < 6; i++) { 1425 val = *(u32 *)(xcvr->rx_iec958.status + i*4); 1426 *(u32 *)(xcvr->rx_iec958.status + i*4) = 1427 bitrev32(val); 1428 } 1429 /* clear CS control register */ 1430 writel_relaxed(0, reg_ctrl); 1431 } 1432 } else { 1433 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0, 1434 (u32 *)&xcvr->rx_iec958.status[0]); 1435 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1, 1436 (u32 *)&xcvr->rx_iec958.status[4]); 1437 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2, 1438 (u32 *)&xcvr->rx_iec958.status[8]); 1439 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3, 1440 (u32 *)&xcvr->rx_iec958.status[12]); 1441 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4, 1442 (u32 *)&xcvr->rx_iec958.status[16]); 1443 regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5, 1444 (u32 *)&xcvr->rx_iec958.status[20]); 1445 for (i = 0; i < 6; i++) { 1446 val = *(u32 *)(xcvr->rx_iec958.status + i * 4); 1447 *(u32 *)(xcvr->rx_iec958.status + i * 4) = 1448 bitrev32(val); 1449 } 1450 regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, 1451 FSL_XCVR_RX_DPTH_CTRL_CSA); 1452 } 1453 } 1454 if (isr & FSL_XCVR_IRQ_NEW_UD) { 1455 dev_dbg(dev, "Received new UD block\n"); 1456 isr_clr |= FSL_XCVR_IRQ_NEW_UD; 1457 } 1458 if (isr & FSL_XCVR_IRQ_MUTE) { 1459 dev_dbg(dev, "HW mute bit detected\n"); 1460 isr_clr |= FSL_XCVR_IRQ_MUTE; 1461 } 1462 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) { 1463 dev_dbg(dev, "RX/TX FIFO full/empty\n"); 1464 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR; 1465 } 1466 if (isr & FSL_XCVR_IRQ_ARC_MODE) { 1467 dev_dbg(dev, "CMDC SM falls out of eARC mode\n"); 1468 isr_clr |= FSL_XCVR_IRQ_ARC_MODE; 1469 } 1470 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) { 1471 dev_dbg(dev, "DMA read request\n"); 1472 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ; 1473 } 1474 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) { 1475 dev_dbg(dev, "DMA write request\n"); 1476 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ; 1477 } 1478 if (isr & FSL_XCVR_IRQ_CMDC_STATUS_UPD) { 1479 dev_dbg(dev, "CMDC status update\n"); 1480 isr_clr |= FSL_XCVR_IRQ_CMDC_STATUS_UPD; 1481 } 1482 if (isr & FSL_XCVR_IRQ_PREAMBLE_MISMATCH) { 1483 dev_dbg(dev, "Preamble mismatch\n"); 1484 isr_clr |= FSL_XCVR_IRQ_PREAMBLE_MISMATCH; 1485 } 1486 if (isr & FSL_XCVR_IRQ_UNEXP_PRE_REC) { 1487 dev_dbg(dev, "Unexpected preamble received\n"); 1488 isr_clr |= FSL_XCVR_IRQ_UNEXP_PRE_REC; 1489 } 1490 if (isr & FSL_XCVR_IRQ_M_W_PRE_MISMATCH) { 1491 dev_dbg(dev, "M/W preamble mismatch\n"); 1492 isr_clr |= FSL_XCVR_IRQ_M_W_PRE_MISMATCH; 1493 } 1494 if (isr & FSL_XCVR_IRQ_B_PRE_MISMATCH) { 1495 dev_dbg(dev, "B preamble mismatch\n"); 1496 isr_clr |= FSL_XCVR_IRQ_B_PRE_MISMATCH; 1497 } 1498 1499 if (isr & (FSL_XCVR_IRQ_PREAMBLE_MISMATCH | 1500 FSL_XCVR_IRQ_UNEXP_PRE_REC | 1501 FSL_XCVR_IRQ_M_W_PRE_MISMATCH | 1502 FSL_XCVR_IRQ_B_PRE_MISMATCH)) { 1503 schedule_work(&xcvr->work_rst); 1504 } 1505 1506 if (isr_clr) { 1507 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr); 1508 return IRQ_HANDLED; 1509 } 1510 1511 return IRQ_NONE; 1512 } 1513 1514 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = { 1515 .fw_name = "imx/xcvr/xcvr-imx8mp.bin", 1516 .use_phy = true, 1517 .pll_ver = PLL_MX8MP, 1518 }; 1519 1520 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = { 1521 .spdif_only = true, 1522 .use_edma = true, 1523 }; 1524 1525 static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = { 1526 .fw_name = "imx/xcvr/xcvr-imx95.bin", 1527 .spdif_only = true, 1528 .use_phy = true, 1529 .use_edma = true, 1530 .pll_ver = PLL_MX95, 1531 }; 1532 1533 static const struct of_device_id fsl_xcvr_dt_ids[] = { 1534 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data }, 1535 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data}, 1536 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data}, 1537 { /* sentinel */ } 1538 }; 1539 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids); 1540 1541 static int fsl_xcvr_probe(struct platform_device *pdev) 1542 { 1543 struct device *dev = &pdev->dev; 1544 struct fsl_xcvr *xcvr; 1545 struct resource *rx_res, *tx_res; 1546 void __iomem *regs; 1547 int ret, irq; 1548 1549 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); 1550 if (!xcvr) 1551 return -ENOMEM; 1552 1553 xcvr->pdev = pdev; 1554 xcvr->soc_data = of_device_get_match_data(&pdev->dev); 1555 1556 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); 1557 if (IS_ERR(xcvr->ipg_clk)) 1558 return dev_err_probe(dev, PTR_ERR(xcvr->ipg_clk), 1559 "failed to get ipg clock\n"); 1560 1561 xcvr->phy_clk = devm_clk_get(dev, "phy"); 1562 if (IS_ERR(xcvr->phy_clk)) 1563 return dev_err_probe(dev, PTR_ERR(xcvr->phy_clk), 1564 "failed to get phy clock\n"); 1565 1566 xcvr->spba_clk = devm_clk_get(dev, "spba"); 1567 if (IS_ERR(xcvr->spba_clk)) 1568 return dev_err_probe(dev, PTR_ERR(xcvr->spba_clk), 1569 "failed to get spba clock\n"); 1570 1571 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); 1572 if (IS_ERR(xcvr->pll_ipg_clk)) 1573 return dev_err_probe(dev, PTR_ERR(xcvr->pll_ipg_clk), 1574 "failed to get pll_ipg clock\n"); 1575 1576 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, 1577 &xcvr->pll11k_clk); 1578 1579 if (xcvr->soc_data->spdif_only) { 1580 if (!(xcvr->pll8k_clk || xcvr->pll11k_clk)) 1581 xcvr->pll8k_clk = xcvr->phy_clk; 1582 fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates, 1583 &fsl_xcvr_spdif_rates_constr, 1584 xcvr->pll8k_clk, xcvr->pll11k_clk, NULL, 1585 xcvr->spdif_constr_rates_list); 1586 } 1587 1588 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); 1589 if (IS_ERR(xcvr->ram_addr)) 1590 return PTR_ERR(xcvr->ram_addr); 1591 1592 regs = devm_platform_ioremap_resource_byname(pdev, "regs"); 1593 if (IS_ERR(regs)) 1594 return PTR_ERR(regs); 1595 1596 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, 1597 &fsl_xcvr_regmap_cfg); 1598 if (IS_ERR(xcvr->regmap)) 1599 return dev_err_probe(dev, PTR_ERR(xcvr->regmap), "failed to init XCVR regmap\n"); 1600 1601 if (xcvr->soc_data->use_phy) { 1602 xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr, 1603 &fsl_xcvr_regmap_phy_cfg); 1604 if (IS_ERR(xcvr->regmap_phy)) 1605 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_phy), 1606 "failed to init XCVR PHY regmap\n"); 1607 1608 switch (xcvr->soc_data->pll_ver) { 1609 case PLL_MX8MP: 1610 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1611 &fsl_xcvr_regmap_pllv0_cfg); 1612 if (IS_ERR(xcvr->regmap_pll)) 1613 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1614 "failed to init XCVR PLL regmap\n"); 1615 break; 1616 case PLL_MX95: 1617 xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, 1618 &fsl_xcvr_regmap_pllv1_cfg); 1619 if (IS_ERR(xcvr->regmap_pll)) 1620 return dev_err_probe(dev, PTR_ERR(xcvr->regmap_pll), 1621 "failed to init XCVR PLL regmap\n"); 1622 break; 1623 default: 1624 return dev_err_probe(dev, -EINVAL, 1625 "Error for PLL version %d\n", 1626 xcvr->soc_data->pll_ver); 1627 } 1628 } 1629 1630 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 1631 if (IS_ERR(xcvr->reset)) 1632 return dev_err_probe(dev, PTR_ERR(xcvr->reset), 1633 "failed to get XCVR reset control\n"); 1634 1635 /* get IRQs */ 1636 irq = platform_get_irq(pdev, 0); 1637 if (irq < 0) 1638 return irq; 1639 1640 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); 1641 if (ret) 1642 return dev_err_probe(dev, ret, "failed to claim IRQ0\n"); 1643 1644 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo"); 1645 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo"); 1646 if (!rx_res || !tx_res) 1647 return dev_err_probe(dev, -EINVAL, "could not find rxfifo or txfifo resource\n"); 1648 xcvr->dma_prms_rx.chan_name = "rx"; 1649 xcvr->dma_prms_tx.chan_name = "tx"; 1650 xcvr->dma_prms_rx.addr = rx_res->start; 1651 xcvr->dma_prms_tx.addr = tx_res->start; 1652 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; 1653 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; 1654 1655 platform_set_drvdata(pdev, xcvr); 1656 pm_runtime_enable(dev); 1657 regcache_cache_only(xcvr->regmap, true); 1658 if (xcvr->soc_data->use_phy) { 1659 regcache_cache_only(xcvr->regmap_phy, true); 1660 regcache_cache_only(xcvr->regmap_pll, true); 1661 } 1662 1663 /* 1664 * Register platform component before registering cpu dai for there 1665 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1666 */ 1667 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1668 if (ret) { 1669 pm_runtime_disable(dev); 1670 return dev_err_probe(dev, ret, "failed to pcm register\n"); 1671 } 1672 1673 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp, 1674 &fsl_xcvr_dai, 1); 1675 if (ret) { 1676 pm_runtime_disable(dev); 1677 dev_err(dev, "failed to register component %s\n", 1678 fsl_xcvr_comp.name); 1679 } 1680 1681 INIT_WORK(&xcvr->work_rst, reset_rx_work); 1682 spin_lock_init(&xcvr->lock); 1683 return ret; 1684 } 1685 1686 static void fsl_xcvr_remove(struct platform_device *pdev) 1687 { 1688 struct fsl_xcvr *xcvr = dev_get_drvdata(&pdev->dev); 1689 1690 cancel_work_sync(&xcvr->work_rst); 1691 pm_runtime_disable(&pdev->dev); 1692 } 1693 1694 static int fsl_xcvr_runtime_suspend(struct device *dev) 1695 { 1696 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1697 int ret; 1698 1699 if (!xcvr->soc_data->spdif_only && 1700 xcvr->mode == FSL_XCVR_MODE_EARC) { 1701 /* Assert M0+ reset */ 1702 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1703 FSL_XCVR_EXT_CTRL_CORE_RESET, 1704 FSL_XCVR_EXT_CTRL_CORE_RESET); 1705 if (ret < 0) 1706 dev_err(dev, "Failed to assert M0+ core: %d\n", ret); 1707 } 1708 1709 regcache_cache_only(xcvr->regmap, true); 1710 if (xcvr->soc_data->use_phy) { 1711 regcache_cache_only(xcvr->regmap_phy, true); 1712 regcache_cache_only(xcvr->regmap_pll, true); 1713 } 1714 1715 clk_disable_unprepare(xcvr->spba_clk); 1716 clk_disable_unprepare(xcvr->phy_clk); 1717 clk_disable_unprepare(xcvr->pll_ipg_clk); 1718 clk_disable_unprepare(xcvr->ipg_clk); 1719 1720 return 0; 1721 } 1722 1723 static int fsl_xcvr_runtime_resume(struct device *dev) 1724 { 1725 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1726 int ret; 1727 1728 ret = reset_control_assert(xcvr->reset); 1729 if (ret < 0) { 1730 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); 1731 return ret; 1732 } 1733 1734 ret = clk_prepare_enable(xcvr->ipg_clk); 1735 if (ret) { 1736 dev_err(dev, "failed to start IPG clock.\n"); 1737 return ret; 1738 } 1739 1740 ret = clk_prepare_enable(xcvr->pll_ipg_clk); 1741 if (ret) { 1742 dev_err(dev, "failed to start PLL IPG clock.\n"); 1743 goto stop_ipg_clk; 1744 } 1745 1746 ret = clk_prepare_enable(xcvr->phy_clk); 1747 if (ret) { 1748 dev_err(dev, "failed to start PHY clock: %d\n", ret); 1749 goto stop_pll_ipg_clk; 1750 } 1751 1752 ret = clk_prepare_enable(xcvr->spba_clk); 1753 if (ret) { 1754 dev_err(dev, "failed to start SPBA clock.\n"); 1755 goto stop_phy_clk; 1756 } 1757 1758 ret = reset_control_deassert(xcvr->reset); 1759 if (ret) { 1760 dev_err(dev, "failed to deassert M0+ reset.\n"); 1761 goto stop_spba_clk; 1762 } 1763 1764 regcache_cache_only(xcvr->regmap, false); 1765 regcache_mark_dirty(xcvr->regmap); 1766 ret = regcache_sync(xcvr->regmap); 1767 1768 if (ret) { 1769 dev_err(dev, "failed to sync regcache.\n"); 1770 goto stop_spba_clk; 1771 } 1772 1773 if (xcvr->soc_data->use_phy) { 1774 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 1775 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 1776 if (ret < 0) { 1777 dev_err(dev, "Error while release PHY reset: %d\n", ret); 1778 goto stop_spba_clk; 1779 } 1780 1781 regcache_cache_only(xcvr->regmap_phy, false); 1782 regcache_mark_dirty(xcvr->regmap_phy); 1783 ret = regcache_sync(xcvr->regmap_phy); 1784 if (ret) { 1785 dev_err(dev, "failed to sync phy regcache.\n"); 1786 goto stop_spba_clk; 1787 } 1788 1789 regcache_cache_only(xcvr->regmap_pll, false); 1790 regcache_mark_dirty(xcvr->regmap_pll); 1791 ret = regcache_sync(xcvr->regmap_pll); 1792 if (ret) { 1793 dev_err(dev, "failed to sync pll regcache.\n"); 1794 goto stop_spba_clk; 1795 } 1796 } 1797 1798 if (xcvr->soc_data->fw_name) { 1799 ret = fsl_xcvr_load_firmware(xcvr); 1800 if (ret) { 1801 dev_err(dev, "failed to load firmware.\n"); 1802 goto stop_spba_clk; 1803 } 1804 1805 /* Release M0+ reset */ 1806 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1807 FSL_XCVR_EXT_CTRL_CORE_RESET, 0); 1808 if (ret < 0) { 1809 dev_err(dev, "M0+ core release failed: %d\n", ret); 1810 goto stop_spba_clk; 1811 } 1812 1813 /* Let M0+ core complete firmware initialization */ 1814 msleep(50); 1815 } 1816 1817 return 0; 1818 1819 stop_spba_clk: 1820 clk_disable_unprepare(xcvr->spba_clk); 1821 stop_phy_clk: 1822 clk_disable_unprepare(xcvr->phy_clk); 1823 stop_pll_ipg_clk: 1824 clk_disable_unprepare(xcvr->pll_ipg_clk); 1825 stop_ipg_clk: 1826 clk_disable_unprepare(xcvr->ipg_clk); 1827 1828 return ret; 1829 } 1830 1831 static const struct dev_pm_ops fsl_xcvr_pm_ops = { 1832 RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, fsl_xcvr_runtime_resume, NULL) 1833 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1834 }; 1835 1836 static struct platform_driver fsl_xcvr_driver = { 1837 .probe = fsl_xcvr_probe, 1838 .driver = { 1839 .name = "fsl-xcvr", 1840 .pm = pm_ptr(&fsl_xcvr_pm_ops), 1841 .of_match_table = fsl_xcvr_dt_ids, 1842 }, 1843 .remove = fsl_xcvr_remove, 1844 }; 1845 module_platform_driver(fsl_xcvr_driver); 1846 1847 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>"); 1848 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver"); 1849 MODULE_LICENSE("GPL v2"); 1850