1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2019 NXP 3 4 #include <linux/bitrev.h> 5 #include <linux/clk.h> 6 #include <linux/firmware.h> 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of_platform.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 #include <linux/reset.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_iec958.h> 15 #include <sound/pcm_params.h> 16 17 #include "fsl_xcvr.h" 18 #include "fsl_utils.h" 19 #include "imx-pcm.h" 20 21 #define FSL_XCVR_CAPDS_SIZE 256 22 23 enum fsl_xcvr_pll_verison { 24 PLL_MX8MP, 25 PLL_MX95, 26 }; 27 28 struct fsl_xcvr_soc_data { 29 const char *fw_name; 30 bool spdif_only; 31 bool use_edma; 32 bool use_phy; 33 enum fsl_xcvr_pll_verison pll_ver; 34 }; 35 36 struct fsl_xcvr { 37 const struct fsl_xcvr_soc_data *soc_data; 38 struct platform_device *pdev; 39 struct regmap *regmap; 40 struct clk *ipg_clk; 41 struct clk *pll_ipg_clk; 42 struct clk *phy_clk; 43 struct clk *spba_clk; 44 struct clk *pll8k_clk; 45 struct clk *pll11k_clk; 46 struct reset_control *reset; 47 u8 streams; 48 u32 mode; 49 u32 arc_mode; 50 void __iomem *ram_addr; 51 struct snd_dmaengine_dai_dma_data dma_prms_rx; 52 struct snd_dmaengine_dai_dma_data dma_prms_tx; 53 struct snd_aes_iec958 rx_iec958; 54 struct snd_aes_iec958 tx_iec958; 55 u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; 56 }; 57 58 static const struct fsl_xcvr_pll_conf { 59 u8 mfi; /* min=0x18, max=0x38 */ 60 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ 61 u32 mfd; /* unsigned int */ 62 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */ 63 } fsl_xcvr_pll_cfg[] = { 64 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */ 65 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */ 66 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */ 67 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */ 68 }; 69 70 /* 71 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio 72 * stream. Todo: to check how this case can be considered below 73 */ 74 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; 75 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = { 76 .count = ARRAY_SIZE(fsl_xcvr_earc_channels), 77 .list = fsl_xcvr_earc_channels, 78 }; 79 80 static const u32 fsl_xcvr_earc_rates[] = { 81 32000, 44100, 48000, 64000, 88200, 96000, 82 128000, 176400, 192000, 256000, 352800, 384000, 83 512000, 705600, 768000, 1024000, 1411200, 1536000, 84 }; 85 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = { 86 .count = ARRAY_SIZE(fsl_xcvr_earc_rates), 87 .list = fsl_xcvr_earc_rates, 88 }; 89 90 static const u32 fsl_xcvr_spdif_channels[] = { 2, }; 91 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = { 92 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels), 93 .list = fsl_xcvr_spdif_channels, 94 }; 95 96 static const u32 fsl_xcvr_spdif_rates[] = { 97 32000, 44100, 48000, 88200, 96000, 176400, 192000, 98 }; 99 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = { 100 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates), 101 .list = fsl_xcvr_spdif_rates, 102 }; 103 104 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol, 105 struct snd_ctl_elem_value *ucontrol) 106 { 107 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 108 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 109 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 110 unsigned int *item = ucontrol->value.enumerated.item; 111 112 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); 113 114 return 0; 115 } 116 117 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol, 118 struct snd_ctl_elem_value *ucontrol) 119 { 120 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 121 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 122 123 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; 124 125 return 0; 126 } 127 128 static const u32 fsl_xcvr_phy_arc_cfg[] = { 129 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN, 130 }; 131 132 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", }; 133 static const struct soc_enum fsl_xcvr_arc_mode_enum = 134 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode); 135 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl = 136 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum, 137 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put); 138 139 /* Capabilities data structure, bytes */ 140 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol, 141 struct snd_ctl_elem_info *uinfo) 142 { 143 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 144 uinfo->count = FSL_XCVR_CAPDS_SIZE; 145 146 return 0; 147 } 148 149 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol, 150 struct snd_ctl_elem_value *ucontrol) 151 { 152 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 153 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 154 155 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); 156 157 return 0; 158 } 159 160 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol, 161 struct snd_ctl_elem_value *ucontrol) 162 { 163 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 164 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 165 166 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); 167 168 return 0; 169 } 170 171 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = { 172 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 173 .name = "Capabilities Data Structure", 174 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 175 .info = fsl_xcvr_type_capds_bytes_info, 176 .get = fsl_xcvr_capds_get, 177 .put = fsl_xcvr_capds_put, 178 }; 179 180 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name, 181 bool active) 182 { 183 struct snd_soc_card *card = dai->component->card; 184 struct snd_kcontrol *kctl; 185 bool enabled; 186 187 lockdep_assert_held(&card->snd_card->controls_rwsem); 188 189 kctl = snd_soc_card_get_kcontrol_locked(card, name); 190 if (kctl == NULL) 191 return -ENOENT; 192 193 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); 194 if (active == enabled) 195 return 0; /* nothing to do */ 196 197 if (active) 198 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 199 else 200 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; 201 202 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); 203 204 return 1; 205 } 206 207 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol, 208 struct snd_ctl_elem_value *ucontrol) 209 { 210 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 211 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 212 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 213 unsigned int *item = ucontrol->value.enumerated.item; 214 struct snd_soc_card *card = dai->component->card; 215 struct snd_soc_pcm_runtime *rtd; 216 217 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); 218 219 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 220 (xcvr->mode == FSL_XCVR_MODE_ARC)); 221 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 222 (xcvr->mode == FSL_XCVR_MODE_EARC)); 223 /* Allow playback for SPDIF only */ 224 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 225 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = 226 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); 227 return 0; 228 } 229 230 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol, 231 struct snd_ctl_elem_value *ucontrol) 232 { 233 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 234 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 235 236 ucontrol->value.enumerated.item[0] = xcvr->mode; 237 238 return 0; 239 } 240 241 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", }; 242 static const struct soc_enum fsl_xcvr_mode_enum = 243 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode); 244 static struct snd_kcontrol_new fsl_xcvr_mode_kctl = 245 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum, 246 fsl_xcvr_mode_get, fsl_xcvr_mode_put); 247 248 /** phy: true => phy, false => pll */ 249 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) 250 { 251 struct device *dev = &xcvr->pdev->dev; 252 u32 val, idx, tidx; 253 int ret; 254 255 idx = BIT(phy ? 26 : 24); 256 tidx = BIT(phy ? 27 : 25); 257 258 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF); 259 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); 260 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); 261 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 262 263 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 264 (val & idx) == ((val & tidx) >> 1), 265 10, 10000); 266 if (ret) 267 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n", 268 phy ? "PHY" : "PLL", reg, data); 269 return ret; 270 } 271 272 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) 273 { 274 struct device *dev = &xcvr->pdev->dev; 275 u32 i, div = 0, log2, val; 276 int ret; 277 278 if (!xcvr->soc_data->use_phy) 279 return 0; 280 281 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) { 282 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) { 283 div = fsl_xcvr_pll_cfg[i].fout / freq; 284 break; 285 } 286 } 287 288 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg)) 289 return -EINVAL; 290 291 log2 = ilog2(div); 292 293 /* Release AI interface from reset */ 294 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 295 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 296 if (ret < 0) { 297 dev_err(dev, "Error while setting IER0: %d\n", ret); 298 return ret; 299 } 300 301 switch (xcvr->soc_data->pll_ver) { 302 case PLL_MX8MP: 303 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ 304 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET, 305 FSL_XCVR_PLL_BANDGAP_EN_VBG, 0); 306 307 /* PLL: CTRL0: DIV_INTEGER */ 308 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0); 309 /* PLL: NUMERATOR: MFN */ 310 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0); 311 /* PLL: DENOMINATOR: MFD */ 312 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0); 313 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ 314 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 315 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0); 316 udelay(25); 317 /* PLL: CTRL0: Clear Hold Ring Off */ 318 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR, 319 FSL_XCVR_PLL_CTRL0_HROFF, 0); 320 udelay(100); 321 if (tx) { /* TX is enabled for SPDIF only */ 322 /* PLL: POSTDIV: PDIV0 */ 323 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, 324 FSL_XCVR_PLL_PDIVx(log2, 0), 0); 325 /* PLL: CTRL_SET: CLKMUX0_EN */ 326 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 327 FSL_XCVR_PLL_CTRL0_CM0_EN, 0); 328 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ 329 /* PLL: POSTDIV: PDIV1 */ 330 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, 331 FSL_XCVR_PLL_PDIVx(log2, 1), 0); 332 /* PLL: CTRL_SET: CLKMUX1_EN */ 333 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 334 FSL_XCVR_PLL_CTRL0_CM1_EN, 0); 335 } else { /* SPDIF / ARC RX */ 336 /* PLL: POSTDIV: PDIV2 */ 337 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, 338 FSL_XCVR_PLL_PDIVx(log2, 2), 0); 339 /* PLL: CTRL_SET: CLKMUX2_EN */ 340 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 341 FSL_XCVR_PLL_CTRL0_CM2_EN, 0); 342 } 343 break; 344 case PLL_MX95: 345 val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div; 346 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0); 347 val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT; 348 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0); 349 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR, 350 fsl_xcvr_pll_cfg[i].mfd, 0); 351 val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN; 352 fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0); 353 break; 354 default: 355 dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); 356 return -EINVAL; 357 } 358 359 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 360 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 361 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 362 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 363 FSL_XCVR_PHY_CTRL_PHY_EN, 1); 364 /* PHY: CTRL2_SET: EARC_TX_MODE */ 365 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, 366 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); 367 } else if (!tx) { /* SPDIF / ARC RX mode */ 368 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 369 /* PHY: CTRL_SET: SPDIF_EN */ 370 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 371 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); 372 else /* PHY: CTRL_SET: ARC RX setup */ 373 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 374 FSL_XCVR_PHY_CTRL_PHY_EN | 375 FSL_XCVR_PHY_CTRL_RX_CM_EN | 376 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1); 377 } 378 379 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", 380 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi, 381 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2); 382 return 0; 383 } 384 385 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) 386 { 387 struct device *dev = &xcvr->pdev->dev; 388 int ret; 389 390 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; 391 clk_disable_unprepare(xcvr->phy_clk); 392 fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk, 393 xcvr->pll8k_clk, xcvr->pll11k_clk, freq); 394 ret = clk_set_rate(xcvr->phy_clk, freq); 395 if (ret < 0) { 396 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret); 397 return ret; 398 } 399 ret = clk_prepare_enable(xcvr->phy_clk); 400 if (ret) { 401 dev_err(dev, "failed to start PHY clock: %d\n", ret); 402 return ret; 403 } 404 405 if (!xcvr->soc_data->use_phy) 406 return 0; 407 /* Release AI interface from reset */ 408 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 409 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 410 if (ret < 0) { 411 dev_err(dev, "Error while setting IER0: %d\n", ret); 412 return ret; 413 } 414 415 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 416 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 417 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 418 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 419 FSL_XCVR_PHY_CTRL_PHY_EN, 1); 420 /* PHY: CTRL2_SET: EARC_TX_MODE */ 421 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, 422 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); 423 } else { /* SPDIF mode */ 424 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ 425 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 426 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | 427 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); 428 } 429 430 dev_dbg(dev, "PLL Fexp: %u\n", freq); 431 432 return 0; 433 } 434 435 #define FSL_XCVR_SPDIF_RX_FREQ 175000000 436 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, 437 struct snd_soc_dai *dai) 438 { 439 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 440 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 441 u32 m_ctl = 0, v_ctl = 0; 442 u32 r = substream->runtime->rate, ch = substream->runtime->channels; 443 u32 fout = 32 * r * ch * 10; 444 int ret = 0; 445 446 switch (xcvr->mode) { 447 case FSL_XCVR_MODE_SPDIF: 448 if (xcvr->soc_data->spdif_only && tx) { 449 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, 450 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, 451 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); 452 if (ret < 0) { 453 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); 454 return ret; 455 } 456 } 457 fallthrough; 458 case FSL_XCVR_MODE_ARC: 459 if (tx) { 460 ret = fsl_xcvr_en_aud_pll(xcvr, fout); 461 if (ret < 0) { 462 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", 463 fout, ret); 464 return ret; 465 } 466 467 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, 468 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); 469 if (ret < 0) { 470 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); 471 return ret; 472 } 473 474 /** 475 * set SPDIF MODE - this flag is used to gate 476 * SPDIF output, useless for SPDIF RX 477 */ 478 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 479 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 480 } else { 481 /** 482 * Clear RX FIFO, flip RX FIFO bits, 483 * disable eARC related HW mode detects 484 */ 485 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, 486 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 487 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | 488 FSL_XCVR_RX_DPTH_CTRL_COMP | 489 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 490 if (ret < 0) { 491 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 492 return ret; 493 } 494 495 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); 496 if (ret < 0) { 497 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", 498 FSL_XCVR_SPDIF_RX_FREQ, ret); 499 return ret; 500 } 501 } 502 break; 503 case FSL_XCVR_MODE_EARC: 504 if (!tx) { 505 /** Clear RX FIFO, flip RX FIFO bits */ 506 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, 507 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 508 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); 509 if (ret < 0) { 510 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 511 return ret; 512 } 513 514 /** Enable eARC related HW mode detects */ 515 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR, 516 FSL_XCVR_RX_DPTH_CTRL_COMP | 517 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 518 if (ret < 0) { 519 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); 520 return ret; 521 } 522 } 523 524 /* clear CMDC RESET */ 525 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 526 /* set TX_RX_MODE */ 527 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE; 528 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0); 529 break; 530 } 531 532 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 533 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL); 534 if (ret < 0) { 535 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); 536 return ret; 537 } 538 539 /* set DPATH RESET */ 540 m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx); 541 v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx); 542 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); 543 if (ret < 0) { 544 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); 545 return ret; 546 } 547 548 return 0; 549 } 550 551 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream, 552 const struct snd_pcm_hw_constraint_list *channels, 553 const struct snd_pcm_hw_constraint_list *rates) 554 { 555 struct snd_pcm_runtime *rt = substream->runtime; 556 int ret; 557 558 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 559 channels); 560 if (ret < 0) 561 return ret; 562 563 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE, 564 rates); 565 if (ret < 0) 566 return ret; 567 568 return 0; 569 } 570 571 static int fsl_xcvr_startup(struct snd_pcm_substream *substream, 572 struct snd_soc_dai *dai) 573 { 574 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 575 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 576 int ret = 0; 577 578 if (xcvr->streams & BIT(substream->stream)) { 579 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); 580 return -EBUSY; 581 } 582 583 /* 584 * EDMA controller needs period size to be a multiple of 585 * tx/rx maxburst 586 */ 587 if (xcvr->soc_data->use_edma) 588 snd_pcm_hw_constraint_step(substream->runtime, 0, 589 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 590 tx ? xcvr->dma_prms_tx.maxburst : 591 xcvr->dma_prms_rx.maxburst); 592 593 switch (xcvr->mode) { 594 case FSL_XCVR_MODE_SPDIF: 595 case FSL_XCVR_MODE_ARC: 596 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 597 &fsl_xcvr_spdif_rates_constr); 598 break; 599 case FSL_XCVR_MODE_EARC: 600 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr, 601 &fsl_xcvr_earc_rates_constr); 602 break; 603 } 604 if (ret < 0) 605 return ret; 606 607 xcvr->streams |= BIT(substream->stream); 608 609 if (!xcvr->soc_data->spdif_only) { 610 struct snd_soc_card *card = dai->component->card; 611 612 /* Disable XCVR controls if there is stream started */ 613 down_read(&card->snd_card->controls_rwsem); 614 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false); 615 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false); 616 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false); 617 up_read(&card->snd_card->controls_rwsem); 618 } 619 620 return 0; 621 } 622 623 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream, 624 struct snd_soc_dai *dai) 625 { 626 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 627 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 628 u32 mask = 0, val = 0; 629 int ret; 630 631 xcvr->streams &= ~BIT(substream->stream); 632 633 /* Enable XCVR controls if there is no stream started */ 634 if (!xcvr->streams) { 635 if (!xcvr->soc_data->spdif_only) { 636 struct snd_soc_card *card = dai->component->card; 637 638 down_read(&card->snd_card->controls_rwsem); 639 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true); 640 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 641 (xcvr->mode == FSL_XCVR_MODE_ARC)); 642 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 643 (xcvr->mode == FSL_XCVR_MODE_EARC)); 644 up_read(&card->snd_card->controls_rwsem); 645 } 646 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 647 FSL_XCVR_IRQ_EARC_ALL, 0); 648 if (ret < 0) { 649 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); 650 return; 651 } 652 653 /* clear SPDIF MODE */ 654 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 655 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 656 } 657 658 if (xcvr->mode == FSL_XCVR_MODE_EARC) { 659 /* set CMDC RESET */ 660 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 661 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 662 } 663 664 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 665 if (ret < 0) { 666 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); 667 return; 668 } 669 } 670 671 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, 672 struct snd_soc_dai *dai) 673 { 674 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 675 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 676 int ret; 677 678 switch (cmd) { 679 case SNDRV_PCM_TRIGGER_START: 680 case SNDRV_PCM_TRIGGER_RESUME: 681 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 682 if (tx) { 683 switch (xcvr->mode) { 684 case FSL_XCVR_MODE_EARC: 685 /* set isr_cmdc_tx_en, w1c */ 686 ret = regmap_write(xcvr->regmap, 687 FSL_XCVR_ISR_SET, 688 FSL_XCVR_ISR_CMDC_TX_EN); 689 if (ret < 0) { 690 dev_err(dai->dev, "err updating isr %d\n", ret); 691 return ret; 692 } 693 fallthrough; 694 case FSL_XCVR_MODE_SPDIF: 695 ret = regmap_write(xcvr->regmap, 696 FSL_XCVR_TX_DPTH_CTRL_SET, 697 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 698 if (ret < 0) { 699 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); 700 return ret; 701 } 702 break; 703 } 704 } 705 706 /* enable DMA RD/WR */ 707 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 708 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0); 709 if (ret < 0) { 710 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); 711 return ret; 712 } 713 714 /* clear DPATH RESET */ 715 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 716 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 717 0); 718 if (ret < 0) { 719 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); 720 return ret; 721 } 722 723 break; 724 case SNDRV_PCM_TRIGGER_STOP: 725 case SNDRV_PCM_TRIGGER_SUSPEND: 726 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 727 /* disable DMA RD/WR */ 728 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 729 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 730 FSL_XCVR_EXT_CTRL_DMA_DIS(tx)); 731 if (ret < 0) { 732 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); 733 return ret; 734 } 735 736 if (tx) { 737 switch (xcvr->mode) { 738 case FSL_XCVR_MODE_SPDIF: 739 ret = regmap_write(xcvr->regmap, 740 FSL_XCVR_TX_DPTH_CTRL_CLR, 741 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 742 if (ret < 0) { 743 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); 744 return ret; 745 } 746 if (xcvr->soc_data->spdif_only) 747 break; 748 else 749 fallthrough; 750 case FSL_XCVR_MODE_EARC: 751 /* clear ISR_CMDC_TX_EN, W1C */ 752 ret = regmap_write(xcvr->regmap, 753 FSL_XCVR_ISR_CLR, 754 FSL_XCVR_ISR_CMDC_TX_EN); 755 if (ret < 0) { 756 dev_err(dai->dev, 757 "Err updating ISR %d\n", ret); 758 return ret; 759 } 760 break; 761 } 762 } 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 return 0; 769 } 770 771 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) 772 { 773 struct device *dev = &xcvr->pdev->dev; 774 const struct firmware *fw; 775 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET; 776 u32 mask, val; 777 778 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); 779 if (ret) { 780 dev_err(dev, "failed to request firmware.\n"); 781 return ret; 782 } 783 784 rem = fw->size; 785 786 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */ 787 if (rem > 16384) { 788 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem); 789 release_firmware(fw); 790 return -ENOMEM; 791 } 792 793 for (page = 0; page < 10; page++) { 794 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 795 FSL_XCVR_EXT_CTRL_PAGE_MASK, 796 FSL_XCVR_EXT_CTRL_PAGE(page)); 797 if (ret < 0) { 798 dev_err(dev, "FW: failed to set page %d, err=%d\n", 799 page, ret); 800 goto err_firmware; 801 } 802 803 off = page * size; 804 out = min(rem, size); 805 /* IPG clock is assumed to be running, otherwise it will hang */ 806 if (out > 0) { 807 /* write firmware into code memory */ 808 memcpy_toio(xcvr->ram_addr, fw->data + off, out); 809 rem -= out; 810 if (rem == 0) { 811 /* last part of firmware written */ 812 /* clean remaining part of code memory page */ 813 memset_io(xcvr->ram_addr + out, 0, size - out); 814 } 815 } else { 816 /* clean current page, including data memory */ 817 memset_io(xcvr->ram_addr, 0, size); 818 } 819 } 820 821 err_firmware: 822 release_firmware(fw); 823 if (ret < 0) 824 return ret; 825 826 /* configure watermarks */ 827 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK; 828 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX); 829 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX); 830 /* disable DMA RD/WR */ 831 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 832 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 833 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 834 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK; 835 val |= FSL_XCVR_EXT_CTRL_PAGE(8); 836 837 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 838 if (ret < 0) { 839 dev_err(dev, "Failed to set watermarks: %d\n", ret); 840 return ret; 841 } 842 843 /* Store Capabilities Data Structure into Data RAM */ 844 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, 845 FSL_XCVR_CAPDS_SIZE); 846 return 0; 847 } 848 849 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol, 850 struct snd_ctl_elem_info *uinfo) 851 { 852 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 853 uinfo->count = 1; 854 855 return 0; 856 } 857 858 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol, 859 struct snd_ctl_elem_info *uinfo) 860 { 861 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 862 uinfo->count = sizeof_field(struct snd_aes_iec958, status); 863 864 return 0; 865 } 866 867 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol, 868 struct snd_ctl_elem_value *ucontrol) 869 { 870 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 871 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 872 873 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); 874 875 return 0; 876 } 877 878 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol, 879 struct snd_ctl_elem_value *ucontrol) 880 { 881 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 882 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 883 884 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); 885 886 return 0; 887 } 888 889 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol, 890 struct snd_ctl_elem_value *ucontrol) 891 { 892 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 893 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 894 895 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); 896 897 return 0; 898 } 899 900 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = { 901 /* Channel status controller */ 902 { 903 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 904 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 905 .access = SNDRV_CTL_ELEM_ACCESS_READ, 906 .info = fsl_xcvr_type_iec958_info, 907 .get = fsl_xcvr_rx_cs_get, 908 }, 909 /* Capture channel status, bytes */ 910 { 911 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 912 .name = "Capture Channel Status", 913 .access = SNDRV_CTL_ELEM_ACCESS_READ, 914 .info = fsl_xcvr_type_iec958_bytes_info, 915 .get = fsl_xcvr_rx_cs_get, 916 }, 917 }; 918 919 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = { 920 /* Channel status controller */ 921 { 922 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 923 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 924 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 925 .info = fsl_xcvr_type_iec958_info, 926 .get = fsl_xcvr_tx_cs_get, 927 .put = fsl_xcvr_tx_cs_put, 928 }, 929 /* Playback channel status, bytes */ 930 { 931 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 932 .name = "Playback Channel Status", 933 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 934 .info = fsl_xcvr_type_iec958_bytes_info, 935 .get = fsl_xcvr_tx_cs_get, 936 .put = fsl_xcvr_tx_cs_put, 937 }, 938 }; 939 940 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai) 941 { 942 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 943 944 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); 945 946 if (xcvr->soc_data->spdif_only) 947 xcvr->mode = FSL_XCVR_MODE_SPDIF; 948 else { 949 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1); 950 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1); 951 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1); 952 } 953 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls, 954 ARRAY_SIZE(fsl_xcvr_tx_ctls)); 955 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls, 956 ARRAY_SIZE(fsl_xcvr_rx_ctls)); 957 return 0; 958 } 959 960 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = { 961 .probe = fsl_xcvr_dai_probe, 962 .prepare = fsl_xcvr_prepare, 963 .startup = fsl_xcvr_startup, 964 .shutdown = fsl_xcvr_shutdown, 965 .trigger = fsl_xcvr_trigger, 966 }; 967 968 static struct snd_soc_dai_driver fsl_xcvr_dai = { 969 .ops = &fsl_xcvr_dai_ops, 970 .playback = { 971 .stream_name = "CPU-Playback", 972 .channels_min = 1, 973 .channels_max = 32, 974 .rate_min = 32000, 975 .rate_max = 1536000, 976 .rates = SNDRV_PCM_RATE_KNOT, 977 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 978 }, 979 .capture = { 980 .stream_name = "CPU-Capture", 981 .channels_min = 1, 982 .channels_max = 32, 983 .rate_min = 32000, 984 .rate_max = 1536000, 985 .rates = SNDRV_PCM_RATE_KNOT, 986 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 987 }, 988 }; 989 990 static const struct snd_soc_component_driver fsl_xcvr_comp = { 991 .name = "fsl-xcvr-dai", 992 .legacy_dai_naming = 1, 993 }; 994 995 static const struct reg_default fsl_xcvr_reg_defaults[] = { 996 { FSL_XCVR_VERSION, 0x00000000 }, 997 { FSL_XCVR_EXT_CTRL, 0xF8204040 }, 998 { FSL_XCVR_EXT_STATUS, 0x00000000 }, 999 { FSL_XCVR_EXT_IER0, 0x00000000 }, 1000 { FSL_XCVR_EXT_IER1, 0x00000000 }, 1001 { FSL_XCVR_EXT_ISR, 0x00000000 }, 1002 { FSL_XCVR_EXT_ISR_SET, 0x00000000 }, 1003 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 }, 1004 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 }, 1005 { FSL_XCVR_IER, 0x00000000 }, 1006 { FSL_XCVR_ISR, 0x00000000 }, 1007 { FSL_XCVR_ISR_SET, 0x00000000 }, 1008 { FSL_XCVR_ISR_CLR, 0x00000000 }, 1009 { FSL_XCVR_ISR_TOG, 0x00000000 }, 1010 { FSL_XCVR_CLK_CTRL, 0x0000018F }, 1011 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 }, 1012 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 }, 1013 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 }, 1014 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 }, 1015 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 }, 1016 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1017 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1018 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1019 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 }, 1020 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 }, 1021 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 }, 1022 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 }, 1023 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 }, 1024 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 }, 1025 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 }, 1026 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 }, 1027 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 }, 1028 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 }, 1029 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 }, 1030 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 }, 1031 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 }, 1032 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 }, 1033 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 }, 1034 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 1035 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 1036 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 1037 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 }, 1038 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 }, 1039 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 }, 1040 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 }, 1041 { FSL_XCVR_DEBUG_REG_0, 0x00000000 }, 1042 { FSL_XCVR_DEBUG_REG_1, 0x00000000 }, 1043 }; 1044 1045 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) 1046 { 1047 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1048 1049 if (!xcvr->soc_data->use_phy) 1050 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) || 1051 reg > FSL_XCVR_TX_DPTH_BCRR) 1052 return false; 1053 switch (reg) { 1054 case FSL_XCVR_VERSION: 1055 case FSL_XCVR_EXT_CTRL: 1056 case FSL_XCVR_EXT_STATUS: 1057 case FSL_XCVR_EXT_IER0: 1058 case FSL_XCVR_EXT_IER1: 1059 case FSL_XCVR_EXT_ISR: 1060 case FSL_XCVR_EXT_ISR_SET: 1061 case FSL_XCVR_EXT_ISR_CLR: 1062 case FSL_XCVR_EXT_ISR_TOG: 1063 case FSL_XCVR_IER: 1064 case FSL_XCVR_ISR: 1065 case FSL_XCVR_ISR_SET: 1066 case FSL_XCVR_ISR_CLR: 1067 case FSL_XCVR_ISR_TOG: 1068 case FSL_XCVR_PHY_AI_CTRL: 1069 case FSL_XCVR_PHY_AI_CTRL_SET: 1070 case FSL_XCVR_PHY_AI_CTRL_CLR: 1071 case FSL_XCVR_PHY_AI_CTRL_TOG: 1072 case FSL_XCVR_PHY_AI_RDATA: 1073 case FSL_XCVR_CLK_CTRL: 1074 case FSL_XCVR_RX_DPTH_CTRL: 1075 case FSL_XCVR_RX_DPTH_CTRL_SET: 1076 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1077 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1078 case FSL_XCVR_RX_CS_DATA_0: 1079 case FSL_XCVR_RX_CS_DATA_1: 1080 case FSL_XCVR_RX_CS_DATA_2: 1081 case FSL_XCVR_RX_CS_DATA_3: 1082 case FSL_XCVR_RX_CS_DATA_4: 1083 case FSL_XCVR_RX_CS_DATA_5: 1084 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1085 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1086 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1087 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1088 case FSL_XCVR_RX_DPTH_TSCR: 1089 case FSL_XCVR_RX_DPTH_BCR: 1090 case FSL_XCVR_RX_DPTH_BCTR: 1091 case FSL_XCVR_RX_DPTH_BCRR: 1092 case FSL_XCVR_TX_DPTH_CTRL: 1093 case FSL_XCVR_TX_DPTH_CTRL_SET: 1094 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1095 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1096 case FSL_XCVR_TX_CS_DATA_0: 1097 case FSL_XCVR_TX_CS_DATA_1: 1098 case FSL_XCVR_TX_CS_DATA_2: 1099 case FSL_XCVR_TX_CS_DATA_3: 1100 case FSL_XCVR_TX_CS_DATA_4: 1101 case FSL_XCVR_TX_CS_DATA_5: 1102 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1103 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1104 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1105 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1106 case FSL_XCVR_TX_DPTH_TSCR: 1107 case FSL_XCVR_TX_DPTH_BCR: 1108 case FSL_XCVR_TX_DPTH_BCTR: 1109 case FSL_XCVR_TX_DPTH_BCRR: 1110 case FSL_XCVR_DEBUG_REG_0: 1111 case FSL_XCVR_DEBUG_REG_1: 1112 return true; 1113 default: 1114 return false; 1115 } 1116 } 1117 1118 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) 1119 { 1120 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1121 1122 if (!xcvr->soc_data->use_phy) 1123 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) 1124 return false; 1125 switch (reg) { 1126 case FSL_XCVR_EXT_CTRL: 1127 case FSL_XCVR_EXT_IER0: 1128 case FSL_XCVR_EXT_IER1: 1129 case FSL_XCVR_EXT_ISR: 1130 case FSL_XCVR_EXT_ISR_SET: 1131 case FSL_XCVR_EXT_ISR_CLR: 1132 case FSL_XCVR_EXT_ISR_TOG: 1133 case FSL_XCVR_IER: 1134 case FSL_XCVR_ISR_SET: 1135 case FSL_XCVR_ISR_CLR: 1136 case FSL_XCVR_ISR_TOG: 1137 case FSL_XCVR_PHY_AI_CTRL: 1138 case FSL_XCVR_PHY_AI_CTRL_SET: 1139 case FSL_XCVR_PHY_AI_CTRL_CLR: 1140 case FSL_XCVR_PHY_AI_CTRL_TOG: 1141 case FSL_XCVR_PHY_AI_WDATA: 1142 case FSL_XCVR_CLK_CTRL: 1143 case FSL_XCVR_RX_DPTH_CTRL: 1144 case FSL_XCVR_RX_DPTH_CTRL_SET: 1145 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1146 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1147 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1148 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1149 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1150 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1151 case FSL_XCVR_TX_DPTH_CTRL_SET: 1152 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1153 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1154 case FSL_XCVR_TX_CS_DATA_0: 1155 case FSL_XCVR_TX_CS_DATA_1: 1156 case FSL_XCVR_TX_CS_DATA_2: 1157 case FSL_XCVR_TX_CS_DATA_3: 1158 case FSL_XCVR_TX_CS_DATA_4: 1159 case FSL_XCVR_TX_CS_DATA_5: 1160 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1161 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1162 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1163 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1164 return true; 1165 default: 1166 return false; 1167 } 1168 } 1169 1170 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) 1171 { 1172 return fsl_xcvr_readable_reg(dev, reg); 1173 } 1174 1175 static const struct regmap_config fsl_xcvr_regmap_cfg = { 1176 .reg_bits = 32, 1177 .reg_stride = 4, 1178 .val_bits = 32, 1179 .max_register = FSL_XCVR_MAX_REG, 1180 .reg_defaults = fsl_xcvr_reg_defaults, 1181 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults), 1182 .readable_reg = fsl_xcvr_readable_reg, 1183 .volatile_reg = fsl_xcvr_volatile_reg, 1184 .writeable_reg = fsl_xcvr_writeable_reg, 1185 .cache_type = REGCACHE_FLAT, 1186 }; 1187 1188 static irqreturn_t irq0_isr(int irq, void *devid) 1189 { 1190 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; 1191 struct device *dev = &xcvr->pdev->dev; 1192 struct regmap *regmap = xcvr->regmap; 1193 void __iomem *reg_ctrl, *reg_buff; 1194 u32 isr, isr_clr = 0, val, i; 1195 1196 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr); 1197 1198 if (isr & FSL_XCVR_IRQ_NEW_CS) { 1199 dev_dbg(dev, "Received new CS block\n"); 1200 isr_clr |= FSL_XCVR_IRQ_NEW_CS; 1201 if (!xcvr->soc_data->spdif_only) { 1202 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 1203 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1204 FSL_XCVR_EXT_CTRL_PAGE_MASK, 1205 FSL_XCVR_EXT_CTRL_PAGE(8)); 1206 1207 /* Find updated CS buffer */ 1208 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; 1209 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; 1210 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1211 if (!val) { 1212 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; 1213 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; 1214 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1215 } 1216 1217 if (val) { 1218 /* copy CS buffer */ 1219 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, 1220 sizeof(xcvr->rx_iec958.status)); 1221 for (i = 0; i < 6; i++) { 1222 val = *(u32 *)(xcvr->rx_iec958.status + i*4); 1223 *(u32 *)(xcvr->rx_iec958.status + i*4) = 1224 bitrev32(val); 1225 } 1226 /* clear CS control register */ 1227 memset_io(reg_ctrl, 0, sizeof(val)); 1228 } 1229 } 1230 } 1231 if (isr & FSL_XCVR_IRQ_NEW_UD) { 1232 dev_dbg(dev, "Received new UD block\n"); 1233 isr_clr |= FSL_XCVR_IRQ_NEW_UD; 1234 } 1235 if (isr & FSL_XCVR_IRQ_MUTE) { 1236 dev_dbg(dev, "HW mute bit detected\n"); 1237 isr_clr |= FSL_XCVR_IRQ_MUTE; 1238 } 1239 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) { 1240 dev_dbg(dev, "RX/TX FIFO full/empty\n"); 1241 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR; 1242 } 1243 if (isr & FSL_XCVR_IRQ_ARC_MODE) { 1244 dev_dbg(dev, "CMDC SM falls out of eARC mode\n"); 1245 isr_clr |= FSL_XCVR_IRQ_ARC_MODE; 1246 } 1247 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) { 1248 dev_dbg(dev, "DMA read request\n"); 1249 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ; 1250 } 1251 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) { 1252 dev_dbg(dev, "DMA write request\n"); 1253 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ; 1254 } 1255 1256 if (isr_clr) { 1257 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr); 1258 return IRQ_HANDLED; 1259 } 1260 1261 return IRQ_NONE; 1262 } 1263 1264 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = { 1265 .fw_name = "imx/xcvr/xcvr-imx8mp.bin", 1266 .use_phy = true, 1267 .pll_ver = PLL_MX8MP, 1268 }; 1269 1270 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = { 1271 .spdif_only = true, 1272 .use_edma = true, 1273 }; 1274 1275 static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = { 1276 .spdif_only = true, 1277 .use_phy = true, 1278 .use_edma = true, 1279 .pll_ver = PLL_MX95, 1280 }; 1281 1282 static const struct of_device_id fsl_xcvr_dt_ids[] = { 1283 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data }, 1284 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data}, 1285 { .compatible = "fsl,imx95-xcvr", .data = &fsl_xcvr_imx95_data}, 1286 { /* sentinel */ } 1287 }; 1288 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids); 1289 1290 static int fsl_xcvr_probe(struct platform_device *pdev) 1291 { 1292 struct device *dev = &pdev->dev; 1293 struct fsl_xcvr *xcvr; 1294 struct resource *rx_res, *tx_res; 1295 void __iomem *regs; 1296 int ret, irq; 1297 1298 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); 1299 if (!xcvr) 1300 return -ENOMEM; 1301 1302 xcvr->pdev = pdev; 1303 xcvr->soc_data = of_device_get_match_data(&pdev->dev); 1304 1305 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); 1306 if (IS_ERR(xcvr->ipg_clk)) { 1307 dev_err(dev, "failed to get ipg clock\n"); 1308 return PTR_ERR(xcvr->ipg_clk); 1309 } 1310 1311 xcvr->phy_clk = devm_clk_get(dev, "phy"); 1312 if (IS_ERR(xcvr->phy_clk)) { 1313 dev_err(dev, "failed to get phy clock\n"); 1314 return PTR_ERR(xcvr->phy_clk); 1315 } 1316 1317 xcvr->spba_clk = devm_clk_get(dev, "spba"); 1318 if (IS_ERR(xcvr->spba_clk)) { 1319 dev_err(dev, "failed to get spba clock\n"); 1320 return PTR_ERR(xcvr->spba_clk); 1321 } 1322 1323 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); 1324 if (IS_ERR(xcvr->pll_ipg_clk)) { 1325 dev_err(dev, "failed to get pll_ipg clock\n"); 1326 return PTR_ERR(xcvr->pll_ipg_clk); 1327 } 1328 1329 fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, 1330 &xcvr->pll11k_clk); 1331 1332 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); 1333 if (IS_ERR(xcvr->ram_addr)) 1334 return PTR_ERR(xcvr->ram_addr); 1335 1336 regs = devm_platform_ioremap_resource_byname(pdev, "regs"); 1337 if (IS_ERR(regs)) 1338 return PTR_ERR(regs); 1339 1340 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, 1341 &fsl_xcvr_regmap_cfg); 1342 if (IS_ERR(xcvr->regmap)) { 1343 dev_err(dev, "failed to init XCVR regmap: %ld\n", 1344 PTR_ERR(xcvr->regmap)); 1345 return PTR_ERR(xcvr->regmap); 1346 } 1347 1348 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 1349 if (IS_ERR(xcvr->reset)) { 1350 dev_err(dev, "failed to get XCVR reset control\n"); 1351 return PTR_ERR(xcvr->reset); 1352 } 1353 1354 /* get IRQs */ 1355 irq = platform_get_irq(pdev, 0); 1356 if (irq < 0) 1357 return irq; 1358 1359 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); 1360 if (ret) { 1361 dev_err(dev, "failed to claim IRQ0: %i\n", ret); 1362 return ret; 1363 } 1364 1365 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo"); 1366 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo"); 1367 if (!rx_res || !tx_res) { 1368 dev_err(dev, "could not find rxfifo or txfifo resource\n"); 1369 return -EINVAL; 1370 } 1371 xcvr->dma_prms_rx.chan_name = "rx"; 1372 xcvr->dma_prms_tx.chan_name = "tx"; 1373 xcvr->dma_prms_rx.addr = rx_res->start; 1374 xcvr->dma_prms_tx.addr = tx_res->start; 1375 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; 1376 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; 1377 1378 platform_set_drvdata(pdev, xcvr); 1379 pm_runtime_enable(dev); 1380 regcache_cache_only(xcvr->regmap, true); 1381 1382 /* 1383 * Register platform component before registering cpu dai for there 1384 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1385 */ 1386 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1387 if (ret) { 1388 pm_runtime_disable(dev); 1389 dev_err(dev, "failed to pcm register\n"); 1390 return ret; 1391 } 1392 1393 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp, 1394 &fsl_xcvr_dai, 1); 1395 if (ret) { 1396 pm_runtime_disable(dev); 1397 dev_err(dev, "failed to register component %s\n", 1398 fsl_xcvr_comp.name); 1399 } 1400 1401 return ret; 1402 } 1403 1404 static void fsl_xcvr_remove(struct platform_device *pdev) 1405 { 1406 pm_runtime_disable(&pdev->dev); 1407 } 1408 1409 static int fsl_xcvr_runtime_suspend(struct device *dev) 1410 { 1411 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1412 int ret; 1413 1414 /* 1415 * Clear interrupts, when streams starts or resumes after 1416 * suspend, interrupts are enabled in prepare(), so no need 1417 * to enable interrupts in resume(). 1418 */ 1419 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 1420 FSL_XCVR_IRQ_EARC_ALL, 0); 1421 if (ret < 0) 1422 dev_err(dev, "Failed to clear IER0: %d\n", ret); 1423 1424 if (!xcvr->soc_data->spdif_only) { 1425 /* Assert M0+ reset */ 1426 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1427 FSL_XCVR_EXT_CTRL_CORE_RESET, 1428 FSL_XCVR_EXT_CTRL_CORE_RESET); 1429 if (ret < 0) 1430 dev_err(dev, "Failed to assert M0+ core: %d\n", ret); 1431 } 1432 1433 regcache_cache_only(xcvr->regmap, true); 1434 1435 clk_disable_unprepare(xcvr->spba_clk); 1436 clk_disable_unprepare(xcvr->phy_clk); 1437 clk_disable_unprepare(xcvr->pll_ipg_clk); 1438 clk_disable_unprepare(xcvr->ipg_clk); 1439 1440 return 0; 1441 } 1442 1443 static int fsl_xcvr_runtime_resume(struct device *dev) 1444 { 1445 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1446 int ret; 1447 1448 ret = reset_control_assert(xcvr->reset); 1449 if (ret < 0) { 1450 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); 1451 return ret; 1452 } 1453 1454 ret = clk_prepare_enable(xcvr->ipg_clk); 1455 if (ret) { 1456 dev_err(dev, "failed to start IPG clock.\n"); 1457 return ret; 1458 } 1459 1460 ret = clk_prepare_enable(xcvr->pll_ipg_clk); 1461 if (ret) { 1462 dev_err(dev, "failed to start PLL IPG clock.\n"); 1463 goto stop_ipg_clk; 1464 } 1465 1466 ret = clk_prepare_enable(xcvr->phy_clk); 1467 if (ret) { 1468 dev_err(dev, "failed to start PHY clock: %d\n", ret); 1469 goto stop_pll_ipg_clk; 1470 } 1471 1472 ret = clk_prepare_enable(xcvr->spba_clk); 1473 if (ret) { 1474 dev_err(dev, "failed to start SPBA clock.\n"); 1475 goto stop_phy_clk; 1476 } 1477 1478 regcache_cache_only(xcvr->regmap, false); 1479 regcache_mark_dirty(xcvr->regmap); 1480 ret = regcache_sync(xcvr->regmap); 1481 1482 if (ret) { 1483 dev_err(dev, "failed to sync regcache.\n"); 1484 goto stop_spba_clk; 1485 } 1486 1487 if (xcvr->soc_data->spdif_only) 1488 return 0; 1489 1490 ret = reset_control_deassert(xcvr->reset); 1491 if (ret) { 1492 dev_err(dev, "failed to deassert M0+ reset.\n"); 1493 goto stop_spba_clk; 1494 } 1495 1496 ret = fsl_xcvr_load_firmware(xcvr); 1497 if (ret) { 1498 dev_err(dev, "failed to load firmware.\n"); 1499 goto stop_spba_clk; 1500 } 1501 1502 /* Release M0+ reset */ 1503 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1504 FSL_XCVR_EXT_CTRL_CORE_RESET, 0); 1505 if (ret < 0) { 1506 dev_err(dev, "M0+ core release failed: %d\n", ret); 1507 goto stop_spba_clk; 1508 } 1509 1510 /* Let M0+ core complete firmware initialization */ 1511 msleep(50); 1512 1513 return 0; 1514 1515 stop_spba_clk: 1516 clk_disable_unprepare(xcvr->spba_clk); 1517 stop_phy_clk: 1518 clk_disable_unprepare(xcvr->phy_clk); 1519 stop_pll_ipg_clk: 1520 clk_disable_unprepare(xcvr->pll_ipg_clk); 1521 stop_ipg_clk: 1522 clk_disable_unprepare(xcvr->ipg_clk); 1523 1524 return ret; 1525 } 1526 1527 static const struct dev_pm_ops fsl_xcvr_pm_ops = { 1528 RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, fsl_xcvr_runtime_resume, NULL) 1529 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1530 pm_runtime_force_resume) 1531 }; 1532 1533 static struct platform_driver fsl_xcvr_driver = { 1534 .probe = fsl_xcvr_probe, 1535 .driver = { 1536 .name = "fsl,imx8mp-audio-xcvr", 1537 .pm = pm_ptr(&fsl_xcvr_pm_ops), 1538 .of_match_table = fsl_xcvr_dt_ids, 1539 }, 1540 .remove_new = fsl_xcvr_remove, 1541 }; 1542 module_platform_driver(fsl_xcvr_driver); 1543 1544 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>"); 1545 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver"); 1546 MODULE_LICENSE("GPL v2"); 1547