1 /* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * 13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards: 14 * 15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most 16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only 17 * one FIFO which combines all valid receive slots. We cannot even select 18 * which slots we want to receive. The WM9712 with which this driver 19 * was developed with always sends GPIO status data in slot 12 which 20 * we receive in our (PCM-) data stream. The only chance we have is to 21 * manually skip this data in the FIQ handler. With sampling rates different 22 * from 48000Hz not every frame has valid receive data, so the ratio 23 * between pcm data and GPIO status data changes. Our FIQ handler is not 24 * able to handle this, hence this driver only works with 48000Hz sampling 25 * rate. 26 * Reading and writing AC97 registers is another challenge. The core 27 * provides us status bits when the read register is updated with *another* 28 * value. When we read the same register two times (and the register still 29 * contains the same value) these status bits are not set. We work 30 * around this by not polling these bits but only wait a fixed delay. 31 */ 32 33 #include <linux/init.h> 34 #include <linux/io.h> 35 #include <linux/module.h> 36 #include <linux/interrupt.h> 37 #include <linux/clk.h> 38 #include <linux/device.h> 39 #include <linux/delay.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/of.h> 43 #include <linux/of_address.h> 44 #include <linux/of_irq.h> 45 #include <linux/of_platform.h> 46 47 #include <sound/core.h> 48 #include <sound/pcm.h> 49 #include <sound/pcm_params.h> 50 #include <sound/initval.h> 51 #include <sound/soc.h> 52 #include <sound/dmaengine_pcm.h> 53 54 #include "fsl_ssi.h" 55 #include "imx-pcm.h" 56 57 #ifdef PPC 58 #define read_ssi(addr) in_be32(addr) 59 #define write_ssi(val, addr) out_be32(addr, val) 60 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set) 61 #else 62 #define read_ssi(addr) readl(addr) 63 #define write_ssi(val, addr) writel(val, addr) 64 /* 65 * FIXME: Proper locking should be added at write_ssi_mask caller level 66 * to ensure this register read/modify/write sequence is race free. 67 */ 68 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set) 69 { 70 u32 val = readl(addr); 71 val = (val & ~clear) | set; 72 writel(val, addr); 73 } 74 #endif 75 76 /** 77 * FSLSSI_I2S_RATES: sample rates supported by the I2S 78 * 79 * This driver currently only supports the SSI running in I2S slave mode, 80 * which means the codec determines the sample rate. Therefore, we tell 81 * ALSA that we support all rates and let the codec driver decide what rates 82 * are really supported. 83 */ 84 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS 85 86 /** 87 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 88 * 89 * This driver currently only supports the SSI running in I2S slave mode. 90 * 91 * The SSI has a limitation in that the samples must be in the same byte 92 * order as the host CPU. This is because when multiple bytes are written 93 * to the STX register, the bytes and bits must be written in the same 94 * order. The STX is a shift register, so all the bits need to be aligned 95 * (bit-endianness must match byte-endianness). Processors typically write 96 * the bits within a byte in the same order that the bytes of a word are 97 * written in. So if the host CPU is big-endian, then only big-endian 98 * samples will be written to STX properly. 99 */ 100 #ifdef __BIG_ENDIAN 101 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ 102 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ 103 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) 104 #else 105 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ 106 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 107 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 108 #endif 109 110 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ 111 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ 112 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) 113 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ 114 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ 115 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) 116 117 enum fsl_ssi_type { 118 FSL_SSI_MCP8610, 119 FSL_SSI_MX21, 120 FSL_SSI_MX35, 121 FSL_SSI_MX51, 122 }; 123 124 struct fsl_ssi_reg_val { 125 u32 sier; 126 u32 srcr; 127 u32 stcr; 128 u32 scr; 129 }; 130 131 struct fsl_ssi_rxtx_reg_val { 132 struct fsl_ssi_reg_val rx; 133 struct fsl_ssi_reg_val tx; 134 }; 135 136 /** 137 * fsl_ssi_private: per-SSI private data 138 * 139 * @ssi: pointer to the SSI's registers 140 * @ssi_phys: physical address of the SSI registers 141 * @irq: IRQ of this SSI 142 * @playback: the number of playback streams opened 143 * @capture: the number of capture streams opened 144 * @cpu_dai: the CPU DAI for this device 145 * @dev_attr: the sysfs device attribute structure 146 * @stats: SSI statistics 147 */ 148 struct fsl_ssi_private { 149 struct ccsr_ssi __iomem *ssi; 150 dma_addr_t ssi_phys; 151 unsigned int irq; 152 unsigned int fifo_depth; 153 struct snd_soc_dai_driver cpu_dai_drv; 154 struct platform_device *pdev; 155 unsigned int dai_fmt; 156 157 enum fsl_ssi_type hw_type; 158 bool use_dma; 159 bool baudclk_locked; 160 bool use_dual_fifo; 161 u8 i2s_mode; 162 spinlock_t baudclk_lock; 163 struct clk *baudclk; 164 struct clk *clk; 165 struct snd_dmaengine_dai_dma_data dma_params_tx; 166 struct snd_dmaengine_dai_dma_data dma_params_rx; 167 struct imx_pcm_fiq_params fiq_params; 168 /* Register values for rx/tx configuration */ 169 struct fsl_ssi_rxtx_reg_val rxtx_reg_val; 170 171 struct fsl_ssi_dbg dbg_stats; 172 }; 173 174 static const struct of_device_id fsl_ssi_ids[] = { 175 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610}, 176 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51}, 177 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35}, 178 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21}, 179 {} 180 }; 181 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 182 183 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) 184 { 185 return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97); 186 } 187 188 static bool fsl_ssi_on_imx(struct fsl_ssi_private *ssi_private) 189 { 190 switch (ssi_private->hw_type) { 191 case FSL_SSI_MX21: 192 case FSL_SSI_MX35: 193 case FSL_SSI_MX51: 194 return true; 195 case FSL_SSI_MCP8610: 196 return false; 197 } 198 199 return false; 200 } 201 202 /* 203 * imx51 and later SoCs have a slightly different IP that allows the 204 * SSI configuration while the SSI unit is running. 205 * 206 * More important, it is necessary on those SoCs to configure the 207 * sperate TX/RX DMA bits just before starting the stream 208 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi 209 * sends any DMA requests to the SDMA unit, otherwise it is not defined 210 * how the SDMA unit handles the DMA request. 211 * 212 * SDMA units are present on devices starting at imx35 but the imx35 213 * reference manual states that the DMA bits should not be changed 214 * while the SSI unit is running (SSIEN). So we support the necessary 215 * online configuration of fsl-ssi starting at imx51. 216 */ 217 static bool fsl_ssi_offline_config(struct fsl_ssi_private *ssi_private) 218 { 219 switch (ssi_private->hw_type) { 220 case FSL_SSI_MCP8610: 221 case FSL_SSI_MX21: 222 case FSL_SSI_MX35: 223 return true; 224 case FSL_SSI_MX51: 225 return false; 226 } 227 228 return true; 229 } 230 231 /** 232 * fsl_ssi_isr: SSI interrupt handler 233 * 234 * Although it's possible to use the interrupt handler to send and receive 235 * data to/from the SSI, we use the DMA instead. Programming is more 236 * complicated, but the performance is much better. 237 * 238 * This interrupt handler is used only to gather statistics. 239 * 240 * @irq: IRQ of the SSI device 241 * @dev_id: pointer to the ssi_private structure for this SSI device 242 */ 243 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 244 { 245 struct fsl_ssi_private *ssi_private = dev_id; 246 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 247 __be32 sisr; 248 __be32 sisr2; 249 __be32 sisr_write_mask = 0; 250 251 switch (ssi_private->hw_type) { 252 case FSL_SSI_MX21: 253 sisr_write_mask = 0; 254 break; 255 256 case FSL_SSI_MCP8610: 257 case FSL_SSI_MX35: 258 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 259 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 260 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; 261 break; 262 263 case FSL_SSI_MX51: 264 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 265 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1; 266 break; 267 } 268 269 /* We got an interrupt, so read the status register to see what we 270 were interrupted for. We mask it with the Interrupt Enable register 271 so that we only check for events that we're interested in. 272 */ 273 sisr = read_ssi(&ssi->sisr); 274 275 sisr2 = sisr & sisr_write_mask; 276 /* Clear the bits that we set */ 277 if (sisr2) 278 write_ssi(sisr2, &ssi->sisr); 279 280 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); 281 282 return IRQ_HANDLED; 283 } 284 285 /* 286 * Enable/Disable all rx/tx config flags at once. 287 */ 288 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, 289 bool enable) 290 { 291 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 292 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; 293 294 if (enable) { 295 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier); 296 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr); 297 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr); 298 } else { 299 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0); 300 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0); 301 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0); 302 } 303 } 304 305 /* 306 * Calculate the bits that have to be disabled for the current stream that is 307 * getting disabled. This keeps the bits enabled that are necessary for the 308 * second stream to work if 'stream_active' is true. 309 * 310 * Detailed calculation: 311 * These are the values that need to be active after disabling. For non-active 312 * second stream, this is 0: 313 * vals_stream * !!stream_active 314 * 315 * The following computes the overall differences between the setup for the 316 * to-disable stream and the active stream, a simple XOR: 317 * vals_disable ^ (vals_stream * !!(stream_active)) 318 * 319 * The full expression adds a mask on all values we care about 320 */ 321 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ 322 ((vals_disable) & \ 323 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) 324 325 /* 326 * Enable/Disable a ssi configuration. You have to pass either 327 * ssi_private->rxtx_reg_val.rx or tx as vals parameter. 328 */ 329 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, 330 struct fsl_ssi_reg_val *vals) 331 { 332 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 333 struct fsl_ssi_reg_val *avals; 334 u32 scr_val = read_ssi(&ssi->scr); 335 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 336 !!(scr_val & CCSR_SSI_SCR_RE); 337 int keep_active; 338 339 if (nr_active_streams - 1 > 0) 340 keep_active = 1; 341 else 342 keep_active = 0; 343 344 /* Find the other direction values rx or tx which we do not want to 345 * modify */ 346 if (&ssi_private->rxtx_reg_val.rx == vals) 347 avals = &ssi_private->rxtx_reg_val.tx; 348 else 349 avals = &ssi_private->rxtx_reg_val.rx; 350 351 /* If vals should be disabled, start with disabling the unit */ 352 if (!enable) { 353 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 354 keep_active); 355 write_ssi_mask(&ssi->scr, scr, 0); 356 } 357 358 /* 359 * We are running on a SoC which does not support online SSI 360 * reconfiguration, so we have to enable all necessary flags at once 361 * even if we do not use them later (capture and playback configuration) 362 */ 363 if (fsl_ssi_offline_config(ssi_private)) { 364 if ((enable && !nr_active_streams) || 365 (!enable && !keep_active)) 366 fsl_ssi_rxtx_config(ssi_private, enable); 367 368 goto config_done; 369 } 370 371 /* 372 * Configure single direction units while the SSI unit is running 373 * (online configuration) 374 */ 375 if (enable) { 376 write_ssi_mask(&ssi->sier, 0, vals->sier); 377 write_ssi_mask(&ssi->srcr, 0, vals->srcr); 378 write_ssi_mask(&ssi->stcr, 0, vals->stcr); 379 } else { 380 u32 sier; 381 u32 srcr; 382 u32 stcr; 383 384 /* 385 * Disabling the necessary flags for one of rx/tx while the 386 * other stream is active is a little bit more difficult. We 387 * have to disable only those flags that differ between both 388 * streams (rx XOR tx) and that are set in the stream that is 389 * disabled now. Otherwise we could alter flags of the other 390 * stream 391 */ 392 393 /* These assignments are simply vals without bits set in avals*/ 394 sier = fsl_ssi_disable_val(vals->sier, avals->sier, 395 keep_active); 396 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, 397 keep_active); 398 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 399 keep_active); 400 401 write_ssi_mask(&ssi->srcr, srcr, 0); 402 write_ssi_mask(&ssi->stcr, stcr, 0); 403 write_ssi_mask(&ssi->sier, sier, 0); 404 } 405 406 config_done: 407 /* Enabling of subunits is done after configuration */ 408 if (enable) 409 write_ssi_mask(&ssi->scr, 0, vals->scr); 410 } 411 412 413 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) 414 { 415 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); 416 } 417 418 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) 419 { 420 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); 421 } 422 423 /* 424 * Setup rx/tx register values used to enable/disable the streams. These will 425 * be used later in fsl_ssi_config to setup the streams without the need to 426 * check for all different SSI modes. 427 */ 428 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) 429 { 430 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; 431 432 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; 433 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; 434 reg->rx.scr = 0; 435 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; 436 reg->tx.stcr = CCSR_SSI_STCR_TFEN0; 437 reg->tx.scr = 0; 438 439 if (!fsl_ssi_is_ac97(ssi_private)) { 440 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; 441 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; 442 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; 443 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; 444 } 445 446 if (ssi_private->use_dma) { 447 reg->rx.sier |= CCSR_SSI_SIER_RDMAE; 448 reg->tx.sier |= CCSR_SSI_SIER_TDMAE; 449 } else { 450 reg->rx.sier |= CCSR_SSI_SIER_RIE; 451 reg->tx.sier |= CCSR_SSI_SIER_TIE; 452 } 453 454 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; 455 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; 456 } 457 458 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 459 { 460 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 461 462 /* 463 * Setup the clock control register 464 */ 465 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), 466 &ssi->stccr); 467 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), 468 &ssi->srccr); 469 470 /* 471 * Enable AC97 mode and startup the SSI 472 */ 473 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, 474 &ssi->sacnt); 475 write_ssi(0xff, &ssi->saccdis); 476 write_ssi(0x300, &ssi->saccen); 477 478 /* 479 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 480 * codec before a stream is started. 481 */ 482 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | 483 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 484 485 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); 486 } 487 488 /** 489 * fsl_ssi_startup: create a new substream 490 * 491 * This is the first function called when a stream is opened. 492 * 493 * If this is the first stream open, then grab the IRQ and program most of 494 * the SSI registers. 495 */ 496 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 497 struct snd_soc_dai *dai) 498 { 499 struct snd_soc_pcm_runtime *rtd = substream->private_data; 500 struct fsl_ssi_private *ssi_private = 501 snd_soc_dai_get_drvdata(rtd->cpu_dai); 502 unsigned long flags; 503 504 if (!dai->active && !fsl_ssi_is_ac97(ssi_private)) { 505 spin_lock_irqsave(&ssi_private->baudclk_lock, flags); 506 ssi_private->baudclk_locked = false; 507 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); 508 } 509 510 /* When using dual fifo mode, it is safer to ensure an even period 511 * size. If appearing to an odd number while DMA always starts its 512 * task from fifo0, fifo1 would be neglected at the end of each 513 * period. But SSI would still access fifo1 with an invalid data. 514 */ 515 if (ssi_private->use_dual_fifo) 516 snd_pcm_hw_constraint_step(substream->runtime, 0, 517 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 518 519 return 0; 520 } 521 522 /** 523 * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock 524 * 525 * Note: This function can be only called when using SSI as DAI master 526 * 527 * Quick instruction for parameters: 528 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels 529 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. 530 */ 531 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 532 int clk_id, unsigned int freq, int dir) 533 { 534 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 535 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 536 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; 537 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 538 unsigned long flags, clkrate, baudrate, tmprate; 539 u64 sub, savesub = 100000; 540 541 /* Don't apply it to any non-baudclk circumstance */ 542 if (IS_ERR(ssi_private->baudclk)) 543 return -EINVAL; 544 545 /* It should be already enough to divide clock by setting pm alone */ 546 psr = 0; 547 div2 = 0; 548 549 factor = (div2 + 1) * (7 * psr + 1) * 2; 550 551 for (i = 0; i < 255; i++) { 552 /* The bclk rate must be smaller than 1/5 sysclk rate */ 553 if (factor * (i + 1) < 5) 554 continue; 555 556 tmprate = freq * factor * (i + 2); 557 clkrate = clk_round_rate(ssi_private->baudclk, tmprate); 558 559 do_div(clkrate, factor); 560 afreq = (u32)clkrate / (i + 1); 561 562 if (freq == afreq) 563 sub = 0; 564 else if (freq / afreq == 1) 565 sub = freq - afreq; 566 else if (afreq / freq == 1) 567 sub = afreq - freq; 568 else 569 continue; 570 571 /* Calculate the fraction */ 572 sub *= 100000; 573 do_div(sub, freq); 574 575 if (sub < savesub) { 576 baudrate = tmprate; 577 savesub = sub; 578 pm = i; 579 } 580 581 /* We are lucky */ 582 if (savesub == 0) 583 break; 584 } 585 586 /* No proper pm found if it is still remaining the initial value */ 587 if (pm == 999) { 588 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); 589 return -EINVAL; 590 } 591 592 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | 593 (psr ? CCSR_SSI_SxCCR_PSR : 0); 594 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | 595 CCSR_SSI_SxCCR_PSR; 596 597 if (dir == SND_SOC_CLOCK_OUT || synchronous) 598 write_ssi_mask(&ssi->stccr, mask, stccr); 599 else 600 write_ssi_mask(&ssi->srccr, mask, stccr); 601 602 spin_lock_irqsave(&ssi_private->baudclk_lock, flags); 603 if (!ssi_private->baudclk_locked) { 604 ret = clk_set_rate(ssi_private->baudclk, baudrate); 605 if (ret) { 606 spin_unlock_irqrestore(&ssi_private->baudclk_lock, 607 flags); 608 dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); 609 return -EINVAL; 610 } 611 ssi_private->baudclk_locked = true; 612 } 613 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); 614 615 return 0; 616 } 617 618 /** 619 * fsl_ssi_hw_params - program the sample size 620 * 621 * Most of the SSI registers have been programmed in the startup function, 622 * but the word length must be programmed here. Unfortunately, programming 623 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can 624 * cause a problem with supporting simultaneous playback and capture. If 625 * the SSI is already playing a stream, then that stream may be temporarily 626 * stopped when you start capture. 627 * 628 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the 629 * clock master. 630 */ 631 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 632 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 633 { 634 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 635 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 636 unsigned int channels = params_channels(hw_params); 637 unsigned int sample_size = 638 snd_pcm_format_width(params_format(hw_params)); 639 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 640 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; 641 642 /* 643 * If we're in synchronous mode, and the SSI is already enabled, 644 * then STCCR is already set properly. 645 */ 646 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) 647 return 0; 648 649 /* 650 * FIXME: The documentation says that SxCCR[WL] should not be 651 * modified while the SSI is enabled. The only time this can 652 * happen is if we're trying to do simultaneous playback and 653 * capture in asynchronous mode. Unfortunately, I have been enable 654 * to get that to work at all on the P1022DS. Therefore, we don't 655 * bother to disable/enable the SSI when setting SxCCR[WL], because 656 * the SSI will stop anyway. Maybe one day, this will get fixed. 657 */ 658 659 /* In synchronous mode, the SSI uses STCCR for capture */ 660 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 661 ssi_private->cpu_dai_drv.symmetric_rates) 662 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl); 663 else 664 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl); 665 666 if (!fsl_ssi_is_ac97(ssi_private)) 667 write_ssi_mask(&ssi->scr, 668 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 669 channels == 1 ? 0 : ssi_private->i2s_mode); 670 671 return 0; 672 } 673 674 /** 675 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. 676 */ 677 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 678 { 679 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 680 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 681 u32 strcr = 0, stcr, srcr, scr, mask; 682 u8 wm; 683 684 ssi_private->dai_fmt = fmt; 685 686 fsl_ssi_setup_reg_vals(ssi_private); 687 688 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 689 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 690 691 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 692 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 693 CCSR_SSI_STCR_TEFS; 694 stcr = read_ssi(&ssi->stcr) & ~mask; 695 srcr = read_ssi(&ssi->srcr) & ~mask; 696 697 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 698 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 699 case SND_SOC_DAIFMT_I2S: 700 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 701 case SND_SOC_DAIFMT_CBS_CFS: 702 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 703 break; 704 case SND_SOC_DAIFMT_CBM_CFM: 705 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 706 break; 707 default: 708 return -EINVAL; 709 } 710 711 /* Data on rising edge of bclk, frame low, 1clk before data */ 712 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | 713 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 714 break; 715 case SND_SOC_DAIFMT_LEFT_J: 716 /* Data on rising edge of bclk, frame high */ 717 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; 718 break; 719 case SND_SOC_DAIFMT_DSP_A: 720 /* Data on rising edge of bclk, frame high, 1clk before data */ 721 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 722 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 723 break; 724 case SND_SOC_DAIFMT_DSP_B: 725 /* Data on rising edge of bclk, frame high */ 726 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 727 CCSR_SSI_STCR_TXBIT0; 728 break; 729 case SND_SOC_DAIFMT_AC97: 730 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; 731 break; 732 default: 733 return -EINVAL; 734 } 735 scr |= ssi_private->i2s_mode; 736 737 /* DAI clock inversion */ 738 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 739 case SND_SOC_DAIFMT_NB_NF: 740 /* Nothing to do for both normal cases */ 741 break; 742 case SND_SOC_DAIFMT_IB_NF: 743 /* Invert bit clock */ 744 strcr ^= CCSR_SSI_STCR_TSCKP; 745 break; 746 case SND_SOC_DAIFMT_NB_IF: 747 /* Invert frame clock */ 748 strcr ^= CCSR_SSI_STCR_TFSI; 749 break; 750 case SND_SOC_DAIFMT_IB_IF: 751 /* Invert both clocks */ 752 strcr ^= CCSR_SSI_STCR_TSCKP; 753 strcr ^= CCSR_SSI_STCR_TFSI; 754 break; 755 default: 756 return -EINVAL; 757 } 758 759 /* DAI clock master masks */ 760 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 761 case SND_SOC_DAIFMT_CBS_CFS: 762 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; 763 scr |= CCSR_SSI_SCR_SYS_CLK_EN; 764 break; 765 case SND_SOC_DAIFMT_CBM_CFM: 766 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 767 break; 768 default: 769 return -EINVAL; 770 } 771 772 stcr |= strcr; 773 srcr |= strcr; 774 775 if (ssi_private->cpu_dai_drv.symmetric_rates) { 776 /* Need to clear RXDIR when using SYNC mode */ 777 srcr &= ~CCSR_SSI_SRCR_RXDIR; 778 scr |= CCSR_SSI_SCR_SYN; 779 } 780 781 write_ssi(stcr, &ssi->stcr); 782 write_ssi(srcr, &ssi->srcr); 783 write_ssi(scr, &ssi->scr); 784 785 /* 786 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't 787 * use FIFO 1. We program the transmit water to signal a DMA transfer 788 * if there are only two (or fewer) elements left in the FIFO. Two 789 * elements equals one frame (left channel, right channel). This value, 790 * however, depends on the depth of the transmit buffer. 791 * 792 * We set the watermark on the same level as the DMA burstsize. For 793 * fiq it is probably better to use the biggest possible watermark 794 * size. 795 */ 796 if (ssi_private->use_dma) 797 wm = ssi_private->fifo_depth - 2; 798 else 799 wm = ssi_private->fifo_depth; 800 801 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 802 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm), 803 &ssi->sfcsr); 804 805 if (ssi_private->use_dual_fifo) { 806 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, 807 CCSR_SSI_SRCR_RFEN1); 808 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, 809 CCSR_SSI_STCR_TFEN1); 810 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, 811 CCSR_SSI_SCR_TCH_EN); 812 } 813 814 if (fmt & SND_SOC_DAIFMT_AC97) 815 fsl_ssi_setup_ac97(ssi_private); 816 817 return 0; 818 } 819 820 /** 821 * fsl_ssi_set_dai_tdm_slot - set TDM slot number 822 * 823 * Note: This function can be only called when using SSI as DAI master 824 */ 825 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 826 u32 rx_mask, int slots, int slot_width) 827 { 828 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 829 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 830 u32 val; 831 832 /* The slot number should be >= 2 if using Network mode or I2S mode */ 833 val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET); 834 if (val && slots < 2) { 835 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 836 return -EINVAL; 837 } 838 839 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK, 840 CCSR_SSI_SxCCR_DC(slots)); 841 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK, 842 CCSR_SSI_SxCCR_DC(slots)); 843 844 /* The register SxMSKs needs SSI to provide essential clock due to 845 * hardware design. So we here temporarily enable SSI to set them. 846 */ 847 val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN; 848 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN); 849 850 write_ssi(tx_mask, &ssi->stmsk); 851 write_ssi(rx_mask, &ssi->srmsk); 852 853 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val); 854 855 return 0; 856 } 857 858 /** 859 * fsl_ssi_trigger: start and stop the DMA transfer. 860 * 861 * This function is called by ALSA to start, stop, pause, and resume the DMA 862 * transfer of data. 863 * 864 * The DMA channel is in external master start and pause mode, which 865 * means the SSI completely controls the flow of data. 866 */ 867 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 868 struct snd_soc_dai *dai) 869 { 870 struct snd_soc_pcm_runtime *rtd = substream->private_data; 871 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 872 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 873 unsigned long flags; 874 875 switch (cmd) { 876 case SNDRV_PCM_TRIGGER_START: 877 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 878 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 879 fsl_ssi_tx_config(ssi_private, true); 880 else 881 fsl_ssi_rx_config(ssi_private, true); 882 break; 883 884 case SNDRV_PCM_TRIGGER_STOP: 885 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 886 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 887 fsl_ssi_tx_config(ssi_private, false); 888 else 889 fsl_ssi_rx_config(ssi_private, false); 890 891 if (!fsl_ssi_is_ac97(ssi_private) && (read_ssi(&ssi->scr) & 892 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) { 893 spin_lock_irqsave(&ssi_private->baudclk_lock, flags); 894 ssi_private->baudclk_locked = false; 895 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); 896 } 897 break; 898 899 default: 900 return -EINVAL; 901 } 902 903 if (fsl_ssi_is_ac97(ssi_private)) { 904 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 905 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor); 906 else 907 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor); 908 } 909 910 return 0; 911 } 912 913 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 914 { 915 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); 916 917 if (fsl_ssi_on_imx(ssi_private) && ssi_private->use_dma) { 918 dai->playback_dma_data = &ssi_private->dma_params_tx; 919 dai->capture_dma_data = &ssi_private->dma_params_rx; 920 } 921 922 return 0; 923 } 924 925 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 926 .startup = fsl_ssi_startup, 927 .hw_params = fsl_ssi_hw_params, 928 .set_fmt = fsl_ssi_set_dai_fmt, 929 .set_sysclk = fsl_ssi_set_dai_sysclk, 930 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 931 .trigger = fsl_ssi_trigger, 932 }; 933 934 /* Template for the CPU dai driver structure */ 935 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 936 .probe = fsl_ssi_dai_probe, 937 .playback = { 938 .channels_min = 1, 939 .channels_max = 2, 940 .rates = FSLSSI_I2S_RATES, 941 .formats = FSLSSI_I2S_FORMATS, 942 }, 943 .capture = { 944 .channels_min = 1, 945 .channels_max = 2, 946 .rates = FSLSSI_I2S_RATES, 947 .formats = FSLSSI_I2S_FORMATS, 948 }, 949 .ops = &fsl_ssi_dai_ops, 950 }; 951 952 static const struct snd_soc_component_driver fsl_ssi_component = { 953 .name = "fsl-ssi", 954 }; 955 956 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 957 .ac97_control = 1, 958 .playback = { 959 .stream_name = "AC97 Playback", 960 .channels_min = 2, 961 .channels_max = 2, 962 .rates = SNDRV_PCM_RATE_8000_48000, 963 .formats = SNDRV_PCM_FMTBIT_S16_LE, 964 }, 965 .capture = { 966 .stream_name = "AC97 Capture", 967 .channels_min = 2, 968 .channels_max = 2, 969 .rates = SNDRV_PCM_RATE_48000, 970 .formats = SNDRV_PCM_FMTBIT_S16_LE, 971 }, 972 .ops = &fsl_ssi_dai_ops, 973 }; 974 975 976 static struct fsl_ssi_private *fsl_ac97_data; 977 978 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 979 unsigned short val) 980 { 981 struct ccsr_ssi *ssi = fsl_ac97_data->ssi; 982 unsigned int lreg; 983 unsigned int lval; 984 985 if (reg > 0x7f) 986 return; 987 988 989 lreg = reg << 12; 990 write_ssi(lreg, &ssi->sacadd); 991 992 lval = val << 4; 993 write_ssi(lval , &ssi->sacdat); 994 995 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, 996 CCSR_SSI_SACNT_WR); 997 udelay(100); 998 } 999 1000 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1001 unsigned short reg) 1002 { 1003 struct ccsr_ssi *ssi = fsl_ac97_data->ssi; 1004 1005 unsigned short val = -1; 1006 unsigned int lreg; 1007 1008 lreg = (reg & 0x7f) << 12; 1009 write_ssi(lreg, &ssi->sacadd); 1010 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK, 1011 CCSR_SSI_SACNT_RD); 1012 1013 udelay(100); 1014 1015 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff; 1016 1017 return val; 1018 } 1019 1020 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1021 .read = fsl_ssi_ac97_read, 1022 .write = fsl_ssi_ac97_write, 1023 }; 1024 1025 /** 1026 * Make every character in a string lower-case 1027 */ 1028 static void make_lowercase(char *s) 1029 { 1030 char *p = s; 1031 char c; 1032 1033 while ((c = *p)) { 1034 if ((c >= 'A') && (c <= 'Z')) 1035 *p = c + ('a' - 'A'); 1036 p++; 1037 } 1038 } 1039 1040 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1041 struct fsl_ssi_private *ssi_private, void __iomem *iomem) 1042 { 1043 struct device_node *np = pdev->dev.of_node; 1044 u32 dmas[4]; 1045 int ret; 1046 1047 ssi_private->clk = devm_clk_get(&pdev->dev, NULL); 1048 if (IS_ERR(ssi_private->clk)) { 1049 ret = PTR_ERR(ssi_private->clk); 1050 dev_err(&pdev->dev, "could not get clock: %d\n", ret); 1051 return ret; 1052 } 1053 1054 ret = clk_prepare_enable(ssi_private->clk); 1055 if (ret) { 1056 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1057 return ret; 1058 } 1059 1060 /* For those SLAVE implementations, we ingore non-baudclk cases 1061 * and, instead, abandon MASTER mode that needs baud clock. 1062 */ 1063 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); 1064 if (IS_ERR(ssi_private->baudclk)) 1065 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", 1066 PTR_ERR(ssi_private->baudclk)); 1067 else 1068 clk_prepare_enable(ssi_private->baudclk); 1069 1070 /* 1071 * We have burstsize be "fifo_depth - 2" to match the SSI 1072 * watermark setting in fsl_ssi_startup(). 1073 */ 1074 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; 1075 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; 1076 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + 1077 offsetof(struct ccsr_ssi, stx0); 1078 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + 1079 offsetof(struct ccsr_ssi, srx0); 1080 1081 ret = !of_property_read_u32_array(np, "dmas", dmas, 4); 1082 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1083 ssi_private->use_dual_fifo = true; 1084 /* When using dual fifo mode, we need to keep watermark 1085 * as even numbers due to dma script limitation. 1086 */ 1087 ssi_private->dma_params_tx.maxburst &= ~0x1; 1088 ssi_private->dma_params_rx.maxburst &= ~0x1; 1089 } 1090 1091 if (!ssi_private->use_dma) { 1092 1093 /* 1094 * Some boards use an incompatible codec. To get it 1095 * working, we are using imx-fiq-pcm-audio, that 1096 * can handle those codecs. DMA is not possible in this 1097 * situation. 1098 */ 1099 1100 ssi_private->fiq_params.irq = ssi_private->irq; 1101 ssi_private->fiq_params.base = iomem; 1102 ssi_private->fiq_params.dma_params_rx = 1103 &ssi_private->dma_params_rx; 1104 ssi_private->fiq_params.dma_params_tx = 1105 &ssi_private->dma_params_tx; 1106 1107 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); 1108 if (ret) 1109 goto error_pcm; 1110 } else { 1111 ret = imx_pcm_dma_init(pdev); 1112 if (ret) 1113 goto error_pcm; 1114 } 1115 1116 return 0; 1117 1118 error_pcm: 1119 if (!IS_ERR(ssi_private->baudclk)) 1120 clk_disable_unprepare(ssi_private->baudclk); 1121 1122 clk_disable_unprepare(ssi_private->clk); 1123 1124 return ret; 1125 } 1126 1127 static void fsl_ssi_imx_clean(struct platform_device *pdev, 1128 struct fsl_ssi_private *ssi_private) 1129 { 1130 if (!ssi_private->use_dma) 1131 imx_pcm_fiq_exit(pdev); 1132 if (!IS_ERR(ssi_private->baudclk)) 1133 clk_disable_unprepare(ssi_private->baudclk); 1134 clk_disable_unprepare(ssi_private->clk); 1135 } 1136 1137 static int fsl_ssi_probe(struct platform_device *pdev) 1138 { 1139 struct fsl_ssi_private *ssi_private; 1140 int ret = 0; 1141 struct device_node *np = pdev->dev.of_node; 1142 const struct of_device_id *of_id; 1143 enum fsl_ssi_type hw_type; 1144 const char *p, *sprop; 1145 const uint32_t *iprop; 1146 struct resource res; 1147 char name[64]; 1148 bool ac97 = false; 1149 1150 /* SSIs that are not connected on the board should have a 1151 * status = "disabled" 1152 * property in their device tree nodes. 1153 */ 1154 if (!of_device_is_available(np)) 1155 return -ENODEV; 1156 1157 of_id = of_match_device(fsl_ssi_ids, &pdev->dev); 1158 if (!of_id) 1159 return -EINVAL; 1160 hw_type = (enum fsl_ssi_type) of_id->data; 1161 1162 sprop = of_get_property(np, "fsl,mode", NULL); 1163 if (!sprop) { 1164 dev_err(&pdev->dev, "fsl,mode property is necessary\n"); 1165 return -EINVAL; 1166 } 1167 if (!strcmp(sprop, "ac97-slave")) 1168 ac97 = true; 1169 1170 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), 1171 GFP_KERNEL); 1172 if (!ssi_private) { 1173 dev_err(&pdev->dev, "could not allocate DAI object\n"); 1174 return -ENOMEM; 1175 } 1176 1177 ssi_private->use_dma = !of_property_read_bool(np, 1178 "fsl,fiq-stream-filter"); 1179 ssi_private->hw_type = hw_type; 1180 1181 if (ac97) { 1182 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, 1183 sizeof(fsl_ssi_ac97_dai)); 1184 1185 fsl_ac97_data = ssi_private; 1186 1187 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1188 } else { 1189 /* Initialize this copy of the CPU DAI driver structure */ 1190 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, 1191 sizeof(fsl_ssi_dai_template)); 1192 } 1193 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); 1194 1195 /* Get the addresses and IRQ */ 1196 ret = of_address_to_resource(np, 0, &res); 1197 if (ret) { 1198 dev_err(&pdev->dev, "could not determine device resources\n"); 1199 return ret; 1200 } 1201 ssi_private->ssi = of_iomap(np, 0); 1202 if (!ssi_private->ssi) { 1203 dev_err(&pdev->dev, "could not map device resources\n"); 1204 return -ENOMEM; 1205 } 1206 ssi_private->ssi_phys = res.start; 1207 1208 ssi_private->irq = irq_of_parse_and_map(np, 0); 1209 if (!ssi_private->irq) { 1210 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); 1211 return -ENXIO; 1212 } 1213 1214 /* Are the RX and the TX clocks locked? */ 1215 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1216 ssi_private->cpu_dai_drv.symmetric_rates = 1; 1217 ssi_private->cpu_dai_drv.symmetric_channels = 1; 1218 ssi_private->cpu_dai_drv.symmetric_samplebits = 1; 1219 } 1220 1221 /* Determine the FIFO depth. */ 1222 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1223 if (iprop) 1224 ssi_private->fifo_depth = be32_to_cpup(iprop); 1225 else 1226 /* Older 8610 DTs didn't have the fifo-depth property */ 1227 ssi_private->fifo_depth = 8; 1228 1229 ssi_private->baudclk_locked = false; 1230 spin_lock_init(&ssi_private->baudclk_lock); 1231 1232 dev_set_drvdata(&pdev->dev, ssi_private); 1233 1234 if (fsl_ssi_on_imx(ssi_private)) { 1235 ret = fsl_ssi_imx_probe(pdev, ssi_private, ssi_private->ssi); 1236 if (ret) 1237 goto error_irqmap; 1238 } 1239 1240 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component, 1241 &ssi_private->cpu_dai_drv, 1); 1242 if (ret) { 1243 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1244 goto error_asoc_register; 1245 } 1246 1247 if (ssi_private->use_dma) { 1248 ret = devm_request_irq(&pdev->dev, ssi_private->irq, 1249 fsl_ssi_isr, 0, dev_name(&pdev->dev), 1250 ssi_private); 1251 if (ret < 0) { 1252 dev_err(&pdev->dev, "could not claim irq %u\n", 1253 ssi_private->irq); 1254 goto error_irq; 1255 } 1256 } 1257 1258 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); 1259 if (ret) 1260 goto error_asoc_register; 1261 1262 /* 1263 * If codec-handle property is missing from SSI node, we assume 1264 * that the machine driver uses new binding which does not require 1265 * SSI driver to trigger machine driver's probe. 1266 */ 1267 if (!of_get_property(np, "codec-handle", NULL)) 1268 goto done; 1269 1270 /* Trigger the machine driver's probe function. The platform driver 1271 * name of the machine driver is taken from /compatible property of the 1272 * device tree. We also pass the address of the CPU DAI driver 1273 * structure. 1274 */ 1275 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); 1276 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ 1277 p = strrchr(sprop, ','); 1278 if (p) 1279 sprop = p + 1; 1280 snprintf(name, sizeof(name), "snd-soc-%s", sprop); 1281 make_lowercase(name); 1282 1283 ssi_private->pdev = 1284 platform_device_register_data(&pdev->dev, name, 0, NULL, 0); 1285 if (IS_ERR(ssi_private->pdev)) { 1286 ret = PTR_ERR(ssi_private->pdev); 1287 dev_err(&pdev->dev, "failed to register platform: %d\n", ret); 1288 goto error_sound_card; 1289 } 1290 1291 done: 1292 return 0; 1293 1294 error_sound_card: 1295 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1296 1297 error_irq: 1298 snd_soc_unregister_component(&pdev->dev); 1299 1300 error_asoc_register: 1301 if (fsl_ssi_on_imx(ssi_private)) 1302 fsl_ssi_imx_clean(pdev, ssi_private); 1303 1304 error_irqmap: 1305 if (ssi_private->use_dma) 1306 irq_dispose_mapping(ssi_private->irq); 1307 1308 return ret; 1309 } 1310 1311 static int fsl_ssi_remove(struct platform_device *pdev) 1312 { 1313 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); 1314 1315 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1316 1317 if (ssi_private->pdev) 1318 platform_device_unregister(ssi_private->pdev); 1319 snd_soc_unregister_component(&pdev->dev); 1320 1321 if (fsl_ssi_on_imx(ssi_private)) 1322 fsl_ssi_imx_clean(pdev, ssi_private); 1323 1324 if (ssi_private->use_dma) 1325 irq_dispose_mapping(ssi_private->irq); 1326 1327 return 0; 1328 } 1329 1330 static struct platform_driver fsl_ssi_driver = { 1331 .driver = { 1332 .name = "fsl-ssi-dai", 1333 .owner = THIS_MODULE, 1334 .of_match_table = fsl_ssi_ids, 1335 }, 1336 .probe = fsl_ssi_probe, 1337 .remove = fsl_ssi_remove, 1338 }; 1339 1340 module_platform_driver(fsl_ssi_driver); 1341 1342 MODULE_ALIAS("platform:fsl-ssi-dai"); 1343 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1344 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1345 MODULE_LICENSE("GPL v2"); 1346