1 /* 2 * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Copyright (C) 2013 Freescale Semiconductor, Inc. 5 * 6 * Based on stmp3xxx_spdif_dai.c 7 * Vladimir Barinov <vbarinov@embeddedalley.com> 8 * Copyright 2008 SigmaTel, Inc 9 * Copyright 2008 Embedded Alley Solutions, Inc 10 * 11 * This file is licensed under the terms of the GNU General Public License 12 * version 2. This program is licensed "as is" without any warranty of any 13 * kind, whether express or implied. 14 */ 15 16 #include <linux/bitrev.h> 17 #include <linux/clk.h> 18 #include <linux/module.h> 19 #include <linux/of_address.h> 20 #include <linux/of_device.h> 21 #include <linux/of_irq.h> 22 #include <linux/regmap.h> 23 24 #include <sound/asoundef.h> 25 #include <sound/dmaengine_pcm.h> 26 #include <sound/soc.h> 27 28 #include "fsl_spdif.h" 29 #include "imx-pcm.h" 30 31 #define FSL_SPDIF_TXFIFO_WML 0x8 32 #define FSL_SPDIF_RXFIFO_WML 0x8 33 34 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 35 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 36 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 37 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 38 INT_LOSS_LOCK | INT_DPLL_LOCKED) 39 40 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 41 42 /* Index list for the values that has if (DPLL Locked) condition */ 43 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 44 #define SRPC_NODPLL_START1 0x5 45 #define SRPC_NODPLL_START2 0xc 46 47 #define DEFAULT_RXCLK_SRC 1 48 49 /* 50 * SPDIF control structure 51 * Defines channel status, subcode and Q sub 52 */ 53 struct spdif_mixer_control { 54 /* spinlock to access control data */ 55 spinlock_t ctl_lock; 56 57 /* IEC958 channel tx status bit */ 58 unsigned char ch_status[4]; 59 60 /* User bits */ 61 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 62 63 /* Q subcode part of user bits */ 64 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 65 66 /* Buffer offset for U/Q */ 67 u32 upos; 68 u32 qpos; 69 70 /* Ready buffer index of the two buffers */ 71 u32 ready_buf; 72 }; 73 74 /** 75 * fsl_spdif_priv: Freescale SPDIF private data 76 * 77 * @fsl_spdif_control: SPDIF control data 78 * @cpu_dai_drv: cpu dai driver 79 * @pdev: platform device pointer 80 * @regmap: regmap handler 81 * @dpll_locked: dpll lock flag 82 * @txrate: the best rates for playback 83 * @txclk_df: STC_TXCLK_DF dividers value for playback 84 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 85 * @txclk_src: STC_TXCLK_SRC values for playback 86 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 87 * @txclk: tx clock sources for playback 88 * @rxclk: rx clock sources for capture 89 * @coreclk: core clock for register access via DMA 90 * @sysclk: system clock for rx clock rate measurement 91 * @dma_params_tx: DMA parameters for transmit channel 92 * @dma_params_rx: DMA parameters for receive channel 93 */ 94 struct fsl_spdif_priv { 95 struct spdif_mixer_control fsl_spdif_control; 96 struct snd_soc_dai_driver cpu_dai_drv; 97 struct platform_device *pdev; 98 struct regmap *regmap; 99 bool dpll_locked; 100 u32 txrate[SPDIF_TXRATE_MAX]; 101 u8 txclk_df[SPDIF_TXRATE_MAX]; 102 u8 sysclk_df[SPDIF_TXRATE_MAX]; 103 u8 txclk_src[SPDIF_TXRATE_MAX]; 104 u8 rxclk_src; 105 struct clk *txclk[SPDIF_TXRATE_MAX]; 106 struct clk *rxclk; 107 struct clk *coreclk; 108 struct clk *sysclk; 109 struct snd_dmaengine_dai_dma_data dma_params_tx; 110 struct snd_dmaengine_dai_dma_data dma_params_rx; 111 }; 112 113 /* DPLL locked and lock loss interrupt handler */ 114 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 115 { 116 struct regmap *regmap = spdif_priv->regmap; 117 struct platform_device *pdev = spdif_priv->pdev; 118 u32 locked; 119 120 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 121 locked &= SRPC_DPLL_LOCKED; 122 123 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 124 locked ? "locked" : "loss lock"); 125 126 spdif_priv->dpll_locked = locked ? true : false; 127 } 128 129 /* Receiver found illegal symbol interrupt handler */ 130 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 131 { 132 struct regmap *regmap = spdif_priv->regmap; 133 struct platform_device *pdev = spdif_priv->pdev; 134 135 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 136 137 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 138 if (!spdif_priv->dpll_locked) 139 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 140 } 141 142 /* U/Q Channel receive register full */ 143 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 144 { 145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 146 struct regmap *regmap = spdif_priv->regmap; 147 struct platform_device *pdev = spdif_priv->pdev; 148 u32 *pos, size, val, reg; 149 150 switch (name) { 151 case 'U': 152 pos = &ctrl->upos; 153 size = SPDIF_UBITS_SIZE; 154 reg = REG_SPDIF_SRU; 155 break; 156 case 'Q': 157 pos = &ctrl->qpos; 158 size = SPDIF_QSUB_SIZE; 159 reg = REG_SPDIF_SRQ; 160 break; 161 default: 162 dev_err(&pdev->dev, "unsupported channel name\n"); 163 return; 164 } 165 166 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 167 168 if (*pos >= size * 2) { 169 *pos = 0; 170 } else if (unlikely((*pos % size) + 3 > size)) { 171 dev_err(&pdev->dev, "User bit receivce buffer overflow\n"); 172 return; 173 } 174 175 regmap_read(regmap, reg, &val); 176 ctrl->subcode[*pos++] = val >> 16; 177 ctrl->subcode[*pos++] = val >> 8; 178 ctrl->subcode[*pos++] = val; 179 } 180 181 /* U/Q Channel sync found */ 182 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 183 { 184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 185 struct platform_device *pdev = spdif_priv->pdev; 186 187 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 188 189 /* U/Q buffer reset */ 190 if (ctrl->qpos == 0) 191 return; 192 193 /* Set ready to this buffer */ 194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 195 } 196 197 /* U/Q Channel framing error */ 198 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 199 { 200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 201 struct regmap *regmap = spdif_priv->regmap; 202 struct platform_device *pdev = spdif_priv->pdev; 203 u32 val; 204 205 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 206 207 /* Read U/Q data to clear the irq and do buffer reset */ 208 regmap_read(regmap, REG_SPDIF_SRU, &val); 209 regmap_read(regmap, REG_SPDIF_SRQ, &val); 210 211 /* Drop this U/Q buffer */ 212 ctrl->ready_buf = 0; 213 ctrl->upos = 0; 214 ctrl->qpos = 0; 215 } 216 217 /* Get spdif interrupt status and clear the interrupt */ 218 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 219 { 220 struct regmap *regmap = spdif_priv->regmap; 221 u32 val, val2; 222 223 regmap_read(regmap, REG_SPDIF_SIS, &val); 224 regmap_read(regmap, REG_SPDIF_SIE, &val2); 225 226 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 227 228 return val; 229 } 230 231 static irqreturn_t spdif_isr(int irq, void *devid) 232 { 233 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 234 struct platform_device *pdev = spdif_priv->pdev; 235 u32 sis; 236 237 sis = spdif_intr_status_clear(spdif_priv); 238 239 if (sis & INT_DPLL_LOCKED) 240 spdif_irq_dpll_lock(spdif_priv); 241 242 if (sis & INT_TXFIFO_UNOV) 243 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 244 245 if (sis & INT_TXFIFO_RESYNC) 246 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 247 248 if (sis & INT_CNEW) 249 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 250 251 if (sis & INT_VAL_NOGOOD) 252 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 253 254 if (sis & INT_SYM_ERR) 255 spdif_irq_sym_error(spdif_priv); 256 257 if (sis & INT_BIT_ERR) 258 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 259 260 if (sis & INT_URX_FUL) 261 spdif_irq_uqrx_full(spdif_priv, 'U'); 262 263 if (sis & INT_URX_OV) 264 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 265 266 if (sis & INT_QRX_FUL) 267 spdif_irq_uqrx_full(spdif_priv, 'Q'); 268 269 if (sis & INT_QRX_OV) 270 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 271 272 if (sis & INT_UQ_SYNC) 273 spdif_irq_uq_sync(spdif_priv); 274 275 if (sis & INT_UQ_ERR) 276 spdif_irq_uq_err(spdif_priv); 277 278 if (sis & INT_RXFIFO_UNOV) 279 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 280 281 if (sis & INT_RXFIFO_RESYNC) 282 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 283 284 if (sis & INT_LOSS_LOCK) 285 spdif_irq_dpll_lock(spdif_priv); 286 287 /* FIXME: Write Tx FIFO to clear TxEm */ 288 if (sis & INT_TX_EM) 289 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 290 291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 292 if (sis & INT_RXFIFO_FUL) 293 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 294 295 return IRQ_HANDLED; 296 } 297 298 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 299 { 300 struct regmap *regmap = spdif_priv->regmap; 301 u32 val, cycle = 1000; 302 303 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 304 305 /* 306 * RESET bit would be cleared after finishing its reset procedure, 307 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 308 */ 309 do { 310 regmap_read(regmap, REG_SPDIF_SCR, &val); 311 } while ((val & SCR_SOFT_RESET) && cycle--); 312 313 if (cycle) 314 return 0; 315 else 316 return -EBUSY; 317 } 318 319 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 320 u8 mask, u8 cstatus) 321 { 322 ctrl->ch_status[3] &= ~mask; 323 ctrl->ch_status[3] |= cstatus & mask; 324 } 325 326 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 327 { 328 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 329 struct regmap *regmap = spdif_priv->regmap; 330 struct platform_device *pdev = spdif_priv->pdev; 331 u32 ch_status; 332 333 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 334 (bitrev8(ctrl->ch_status[1]) << 8) | 335 bitrev8(ctrl->ch_status[2]); 336 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 337 338 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 339 340 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 341 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 342 343 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 344 } 345 346 /* Set SPDIF PhaseConfig register for rx clock */ 347 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 348 enum spdif_gainsel gainsel, int dpll_locked) 349 { 350 struct regmap *regmap = spdif_priv->regmap; 351 u8 clksrc = spdif_priv->rxclk_src; 352 353 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 354 return -EINVAL; 355 356 regmap_update_bits(regmap, REG_SPDIF_SRPC, 357 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 358 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 359 360 return 0; 361 } 362 363 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 364 int sample_rate) 365 { 366 struct snd_soc_pcm_runtime *rtd = substream->private_data; 367 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 368 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 369 struct regmap *regmap = spdif_priv->regmap; 370 struct platform_device *pdev = spdif_priv->pdev; 371 unsigned long csfs = 0; 372 u32 stc, mask, rate; 373 u8 clk, txclk_df, sysclk_df; 374 int ret; 375 376 switch (sample_rate) { 377 case 32000: 378 rate = SPDIF_TXRATE_32000; 379 csfs = IEC958_AES3_CON_FS_32000; 380 break; 381 case 44100: 382 rate = SPDIF_TXRATE_44100; 383 csfs = IEC958_AES3_CON_FS_44100; 384 break; 385 case 48000: 386 rate = SPDIF_TXRATE_48000; 387 csfs = IEC958_AES3_CON_FS_48000; 388 break; 389 case 96000: 390 rate = SPDIF_TXRATE_96000; 391 csfs = IEC958_AES3_CON_FS_96000; 392 break; 393 case 192000: 394 rate = SPDIF_TXRATE_192000; 395 csfs = IEC958_AES3_CON_FS_192000; 396 break; 397 default: 398 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 399 return -EINVAL; 400 } 401 402 clk = spdif_priv->txclk_src[rate]; 403 if (clk >= STC_TXCLK_SRC_MAX) { 404 dev_err(&pdev->dev, "tx clock source is out of range\n"); 405 return -EINVAL; 406 } 407 408 txclk_df = spdif_priv->txclk_df[rate]; 409 if (txclk_df == 0) { 410 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 411 return -EINVAL; 412 } 413 414 sysclk_df = spdif_priv->sysclk_df[rate]; 415 416 /* Don't mess up the clocks from other modules */ 417 if (clk != STC_TXCLK_SPDIF_ROOT) 418 goto clk_set_bypass; 419 420 /* 421 * The S/PDIF block needs a clock of 64 * fs * txclk_df. 422 * So request 64 * fs * (txclk_df + 1) to get rounded. 423 */ 424 ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1)); 425 if (ret) { 426 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 427 return ret; 428 } 429 430 clk_set_bypass: 431 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 432 (64 * sample_rate * txclk_df * sysclk_df)); 433 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 434 clk_get_rate(spdif_priv->txclk[rate])); 435 436 /* set fs field in consumer channel status */ 437 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 438 439 /* select clock source and divisor */ 440 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 441 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 442 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 443 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 444 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 445 446 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 447 spdif_priv->txrate[rate], sample_rate); 448 449 return 0; 450 } 451 452 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 453 struct snd_soc_dai *cpu_dai) 454 { 455 struct snd_soc_pcm_runtime *rtd = substream->private_data; 456 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 457 struct platform_device *pdev = spdif_priv->pdev; 458 struct regmap *regmap = spdif_priv->regmap; 459 u32 scr, mask, i; 460 int ret; 461 462 /* Reset module and interrupts only for first initialization */ 463 if (!cpu_dai->active) { 464 ret = clk_prepare_enable(spdif_priv->coreclk); 465 if (ret) { 466 dev_err(&pdev->dev, "failed to enable core clock\n"); 467 return ret; 468 } 469 470 ret = spdif_softreset(spdif_priv); 471 if (ret) { 472 dev_err(&pdev->dev, "failed to soft reset\n"); 473 goto err; 474 } 475 476 /* Disable all the interrupts */ 477 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 478 } 479 480 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 481 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 482 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 483 SCR_TXFIFO_FSEL_IF8; 484 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 485 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 486 SCR_TXFIFO_FSEL_MASK; 487 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 488 clk_prepare_enable(spdif_priv->txclk[i]); 489 } else { 490 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 491 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 492 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 493 clk_prepare_enable(spdif_priv->rxclk); 494 } 495 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 496 497 /* Power up SPDIF module */ 498 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 499 500 return 0; 501 502 err: 503 clk_disable_unprepare(spdif_priv->coreclk); 504 505 return ret; 506 } 507 508 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 509 struct snd_soc_dai *cpu_dai) 510 { 511 struct snd_soc_pcm_runtime *rtd = substream->private_data; 512 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 513 struct regmap *regmap = spdif_priv->regmap; 514 u32 scr, mask, i; 515 516 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 517 scr = 0; 518 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 519 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 520 SCR_TXFIFO_FSEL_MASK; 521 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 522 clk_disable_unprepare(spdif_priv->txclk[i]); 523 } else { 524 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 525 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 526 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 527 clk_disable_unprepare(spdif_priv->rxclk); 528 } 529 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 530 531 /* Power down SPDIF module only if tx&rx are both inactive */ 532 if (!cpu_dai->active) { 533 spdif_intr_status_clear(spdif_priv); 534 regmap_update_bits(regmap, REG_SPDIF_SCR, 535 SCR_LOW_POWER, SCR_LOW_POWER); 536 clk_disable_unprepare(spdif_priv->coreclk); 537 } 538 } 539 540 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 541 struct snd_pcm_hw_params *params, 542 struct snd_soc_dai *dai) 543 { 544 struct snd_soc_pcm_runtime *rtd = substream->private_data; 545 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 546 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 547 struct platform_device *pdev = spdif_priv->pdev; 548 u32 sample_rate = params_rate(params); 549 int ret = 0; 550 551 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 552 ret = spdif_set_sample_rate(substream, sample_rate); 553 if (ret) { 554 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 555 __func__, sample_rate); 556 return ret; 557 } 558 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 559 IEC958_AES3_CON_CLOCK_1000PPM); 560 spdif_write_channel_status(spdif_priv); 561 } else { 562 /* Setup rx clock source */ 563 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 564 } 565 566 return ret; 567 } 568 569 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 570 int cmd, struct snd_soc_dai *dai) 571 { 572 struct snd_soc_pcm_runtime *rtd = substream->private_data; 573 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 574 struct regmap *regmap = spdif_priv->regmap; 575 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 576 u32 intr = SIE_INTR_FOR(tx); 577 u32 dmaen = SCR_DMA_xX_EN(tx); 578 579 switch (cmd) { 580 case SNDRV_PCM_TRIGGER_START: 581 case SNDRV_PCM_TRIGGER_RESUME: 582 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 583 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 584 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 585 break; 586 case SNDRV_PCM_TRIGGER_STOP: 587 case SNDRV_PCM_TRIGGER_SUSPEND: 588 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 589 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 590 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 591 break; 592 default: 593 return -EINVAL; 594 } 595 596 return 0; 597 } 598 599 static struct snd_soc_dai_ops fsl_spdif_dai_ops = { 600 .startup = fsl_spdif_startup, 601 .hw_params = fsl_spdif_hw_params, 602 .trigger = fsl_spdif_trigger, 603 .shutdown = fsl_spdif_shutdown, 604 }; 605 606 607 /* 608 * FSL SPDIF IEC958 controller(mixer) functions 609 * 610 * Channel status get/put control 611 * User bit value get/put control 612 * Valid bit value get control 613 * DPLL lock status get control 614 * User bit sync mode selection control 615 */ 616 617 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 618 struct snd_ctl_elem_info *uinfo) 619 { 620 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 621 uinfo->count = 1; 622 623 return 0; 624 } 625 626 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 627 struct snd_ctl_elem_value *uvalue) 628 { 629 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 630 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 631 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 632 633 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 634 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 635 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 636 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 637 638 return 0; 639 } 640 641 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 642 struct snd_ctl_elem_value *uvalue) 643 { 644 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 645 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 646 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 647 648 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 649 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 650 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 651 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 652 653 spdif_write_channel_status(spdif_priv); 654 655 return 0; 656 } 657 658 /* Get channel status from SPDIF_RX_CCHAN register */ 659 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 660 struct snd_ctl_elem_value *ucontrol) 661 { 662 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 663 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 664 struct regmap *regmap = spdif_priv->regmap; 665 u32 cstatus, val; 666 667 regmap_read(regmap, REG_SPDIF_SIS, &val); 668 if (!(val & INT_CNEW)) 669 return -EAGAIN; 670 671 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 672 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 673 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 674 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 675 676 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 677 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 678 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 679 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 680 681 /* Clear intr */ 682 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 683 684 return 0; 685 } 686 687 /* 688 * Get User bits (subcode) from chip value which readed out 689 * in UChannel register. 690 */ 691 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 692 struct snd_ctl_elem_value *ucontrol) 693 { 694 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 695 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 696 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 697 unsigned long flags; 698 int ret = -EAGAIN; 699 700 spin_lock_irqsave(&ctrl->ctl_lock, flags); 701 if (ctrl->ready_buf) { 702 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 703 memcpy(&ucontrol->value.iec958.subcode[0], 704 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 705 ret = 0; 706 } 707 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 708 709 return ret; 710 } 711 712 /* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */ 713 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 714 struct snd_ctl_elem_info *uinfo) 715 { 716 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 717 uinfo->count = SPDIF_QSUB_SIZE; 718 719 return 0; 720 } 721 722 /* Get Q subcode from chip value which readed out in QChannel register */ 723 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 724 struct snd_ctl_elem_value *ucontrol) 725 { 726 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 727 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 728 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 729 unsigned long flags; 730 int ret = -EAGAIN; 731 732 spin_lock_irqsave(&ctrl->ctl_lock, flags); 733 if (ctrl->ready_buf) { 734 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 735 memcpy(&ucontrol->value.bytes.data[0], 736 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 737 ret = 0; 738 } 739 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 740 741 return ret; 742 } 743 744 /* Valid bit infomation */ 745 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, 746 struct snd_ctl_elem_info *uinfo) 747 { 748 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 749 uinfo->count = 1; 750 uinfo->value.integer.min = 0; 751 uinfo->value.integer.max = 1; 752 753 return 0; 754 } 755 756 /* Get valid good bit from interrupt status register */ 757 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol, 758 struct snd_ctl_elem_value *ucontrol) 759 { 760 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 761 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 762 struct regmap *regmap = spdif_priv->regmap; 763 u32 val; 764 765 regmap_read(regmap, REG_SPDIF_SIS, &val); 766 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 767 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 768 769 return 0; 770 } 771 772 /* DPLL lock infomation */ 773 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 774 struct snd_ctl_elem_info *uinfo) 775 { 776 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 777 uinfo->count = 1; 778 uinfo->value.integer.min = 16000; 779 uinfo->value.integer.max = 96000; 780 781 return 0; 782 } 783 784 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 785 24, 16, 12, 8, 6, 4, 3, 786 }; 787 788 /* Get RX data clock rate given the SPDIF bus_clk */ 789 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 790 enum spdif_gainsel gainsel) 791 { 792 struct regmap *regmap = spdif_priv->regmap; 793 struct platform_device *pdev = spdif_priv->pdev; 794 u64 tmpval64, busclk_freq = 0; 795 u32 freqmeas, phaseconf; 796 u8 clksrc; 797 798 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 799 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 800 801 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 802 803 /* Get bus clock from system */ 804 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 805 busclk_freq = clk_get_rate(spdif_priv->sysclk); 806 807 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 808 tmpval64 = (u64) busclk_freq * freqmeas; 809 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 810 do_div(tmpval64, 128 * 1024); 811 812 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 813 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 814 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 815 816 return (int)tmpval64; 817 } 818 819 /* 820 * Get DPLL lock or not info from stable interrupt status register. 821 * User application must use this control to get locked, 822 * then can do next PCM operation 823 */ 824 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 825 struct snd_ctl_elem_value *ucontrol) 826 { 827 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 828 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 829 int rate = 0; 830 831 if (spdif_priv->dpll_locked) 832 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 833 834 ucontrol->value.integer.value[0] = rate; 835 836 return 0; 837 } 838 839 /* User bit sync mode info */ 840 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol, 841 struct snd_ctl_elem_info *uinfo) 842 { 843 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 844 uinfo->count = 1; 845 uinfo->value.integer.min = 0; 846 uinfo->value.integer.max = 1; 847 848 return 0; 849 } 850 851 /* 852 * User bit sync mode: 853 * 1 CD User channel subcode 854 * 0 Non-CD data 855 */ 856 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 857 struct snd_ctl_elem_value *ucontrol) 858 { 859 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 860 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 861 struct regmap *regmap = spdif_priv->regmap; 862 u32 val; 863 864 regmap_read(regmap, REG_SPDIF_SRCD, &val); 865 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 866 867 return 0; 868 } 869 870 /* 871 * User bit sync mode: 872 * 1 CD User channel subcode 873 * 0 Non-CD data 874 */ 875 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 876 struct snd_ctl_elem_value *ucontrol) 877 { 878 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 879 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 880 struct regmap *regmap = spdif_priv->regmap; 881 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 882 883 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 884 885 return 0; 886 } 887 888 /* FSL SPDIF IEC958 controller defines */ 889 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 890 /* Status cchanel controller */ 891 { 892 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 893 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 894 .access = SNDRV_CTL_ELEM_ACCESS_READ | 895 SNDRV_CTL_ELEM_ACCESS_WRITE | 896 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 897 .info = fsl_spdif_info, 898 .get = fsl_spdif_pb_get, 899 .put = fsl_spdif_pb_put, 900 }, 901 { 902 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 903 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 904 .access = SNDRV_CTL_ELEM_ACCESS_READ | 905 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 906 .info = fsl_spdif_info, 907 .get = fsl_spdif_capture_get, 908 }, 909 /* User bits controller */ 910 { 911 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 912 .name = "IEC958 Subcode Capture Default", 913 .access = SNDRV_CTL_ELEM_ACCESS_READ | 914 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 915 .info = fsl_spdif_info, 916 .get = fsl_spdif_subcode_get, 917 }, 918 { 919 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 920 .name = "IEC958 Q-subcode Capture Default", 921 .access = SNDRV_CTL_ELEM_ACCESS_READ | 922 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 923 .info = fsl_spdif_qinfo, 924 .get = fsl_spdif_qget, 925 }, 926 /* Valid bit error controller */ 927 { 928 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 929 .name = "IEC958 V-Bit Errors", 930 .access = SNDRV_CTL_ELEM_ACCESS_READ | 931 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 932 .info = fsl_spdif_vbit_info, 933 .get = fsl_spdif_vbit_get, 934 }, 935 /* DPLL lock info get controller */ 936 { 937 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 938 .name = "RX Sample Rate", 939 .access = SNDRV_CTL_ELEM_ACCESS_READ | 940 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 941 .info = fsl_spdif_rxrate_info, 942 .get = fsl_spdif_rxrate_get, 943 }, 944 /* User bit sync mode set/get controller */ 945 { 946 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 947 .name = "IEC958 USyncMode CDText", 948 .access = SNDRV_CTL_ELEM_ACCESS_READ | 949 SNDRV_CTL_ELEM_ACCESS_WRITE | 950 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 951 .info = fsl_spdif_usync_info, 952 .get = fsl_spdif_usync_get, 953 .put = fsl_spdif_usync_put, 954 }, 955 }; 956 957 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 958 { 959 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 960 961 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 962 &spdif_private->dma_params_rx); 963 964 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 965 966 return 0; 967 } 968 969 static struct snd_soc_dai_driver fsl_spdif_dai = { 970 .probe = &fsl_spdif_dai_probe, 971 .playback = { 972 .stream_name = "CPU-Playback", 973 .channels_min = 2, 974 .channels_max = 2, 975 .rates = FSL_SPDIF_RATES_PLAYBACK, 976 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 977 }, 978 .capture = { 979 .stream_name = "CPU-Capture", 980 .channels_min = 2, 981 .channels_max = 2, 982 .rates = FSL_SPDIF_RATES_CAPTURE, 983 .formats = FSL_SPDIF_FORMATS_CAPTURE, 984 }, 985 .ops = &fsl_spdif_dai_ops, 986 }; 987 988 static const struct snd_soc_component_driver fsl_spdif_component = { 989 .name = "fsl-spdif", 990 }; 991 992 /* FSL SPDIF REGMAP */ 993 994 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 995 { 996 switch (reg) { 997 case REG_SPDIF_SCR: 998 case REG_SPDIF_SRCD: 999 case REG_SPDIF_SRPC: 1000 case REG_SPDIF_SIE: 1001 case REG_SPDIF_SIS: 1002 case REG_SPDIF_SRL: 1003 case REG_SPDIF_SRR: 1004 case REG_SPDIF_SRCSH: 1005 case REG_SPDIF_SRCSL: 1006 case REG_SPDIF_SRU: 1007 case REG_SPDIF_SRQ: 1008 case REG_SPDIF_STCSCH: 1009 case REG_SPDIF_STCSCL: 1010 case REG_SPDIF_SRFM: 1011 case REG_SPDIF_STC: 1012 return true; 1013 default: 1014 return false; 1015 } 1016 } 1017 1018 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1019 { 1020 switch (reg) { 1021 case REG_SPDIF_SCR: 1022 case REG_SPDIF_SRCD: 1023 case REG_SPDIF_SRPC: 1024 case REG_SPDIF_SIE: 1025 case REG_SPDIF_SIC: 1026 case REG_SPDIF_STL: 1027 case REG_SPDIF_STR: 1028 case REG_SPDIF_STCSCH: 1029 case REG_SPDIF_STCSCL: 1030 case REG_SPDIF_STC: 1031 return true; 1032 default: 1033 return false; 1034 } 1035 } 1036 1037 static const struct regmap_config fsl_spdif_regmap_config = { 1038 .reg_bits = 32, 1039 .reg_stride = 4, 1040 .val_bits = 32, 1041 1042 .max_register = REG_SPDIF_STC, 1043 .readable_reg = fsl_spdif_readable_reg, 1044 .writeable_reg = fsl_spdif_writeable_reg, 1045 }; 1046 1047 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1048 struct clk *clk, u64 savesub, 1049 enum spdif_txrate index, bool round) 1050 { 1051 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1052 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1053 u64 rate_ideal, rate_actual, sub; 1054 u32 sysclk_dfmin, sysclk_dfmax; 1055 u32 txclk_df, sysclk_df, arate; 1056 1057 /* The sysclk has an extra divisor [2, 512] */ 1058 sysclk_dfmin = is_sysclk ? 2 : 1; 1059 sysclk_dfmax = is_sysclk ? 512 : 1; 1060 1061 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1062 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1063 rate_ideal = rate[index] * (txclk_df + 1) * 64; 1064 if (round) 1065 rate_actual = clk_round_rate(clk, rate_ideal); 1066 else 1067 rate_actual = clk_get_rate(clk); 1068 1069 arate = rate_actual / 64; 1070 arate /= txclk_df * sysclk_df; 1071 1072 if (arate == rate[index]) { 1073 /* We are lucky */ 1074 savesub = 0; 1075 spdif_priv->txclk_df[index] = txclk_df; 1076 spdif_priv->sysclk_df[index] = sysclk_df; 1077 spdif_priv->txrate[index] = arate; 1078 goto out; 1079 } else if (arate / rate[index] == 1) { 1080 /* A little bigger than expect */ 1081 sub = (u64)(arate - rate[index]) * 100000; 1082 do_div(sub, rate[index]); 1083 if (sub >= savesub) 1084 continue; 1085 savesub = sub; 1086 spdif_priv->txclk_df[index] = txclk_df; 1087 spdif_priv->sysclk_df[index] = sysclk_df; 1088 spdif_priv->txrate[index] = arate; 1089 } else if (rate[index] / arate == 1) { 1090 /* A little smaller than expect */ 1091 sub = (u64)(rate[index] - arate) * 100000; 1092 do_div(sub, rate[index]); 1093 if (sub >= savesub) 1094 continue; 1095 savesub = sub; 1096 spdif_priv->txclk_df[index] = txclk_df; 1097 spdif_priv->sysclk_df[index] = sysclk_df; 1098 spdif_priv->txrate[index] = arate; 1099 } 1100 } 1101 } 1102 1103 out: 1104 return savesub; 1105 } 1106 1107 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1108 enum spdif_txrate index) 1109 { 1110 const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1111 struct platform_device *pdev = spdif_priv->pdev; 1112 struct device *dev = &pdev->dev; 1113 u64 savesub = 100000, ret; 1114 struct clk *clk; 1115 char tmp[16]; 1116 int i; 1117 1118 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1119 sprintf(tmp, "rxtx%d", i); 1120 clk = devm_clk_get(&pdev->dev, tmp); 1121 if (IS_ERR(clk)) { 1122 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1123 return PTR_ERR(clk); 1124 } 1125 if (!clk_get_rate(clk)) 1126 continue; 1127 1128 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1129 i == STC_TXCLK_SPDIF_ROOT); 1130 if (savesub == ret) 1131 continue; 1132 1133 savesub = ret; 1134 spdif_priv->txclk[index] = clk; 1135 spdif_priv->txclk_src[index] = i; 1136 1137 /* To quick catch a divisor, we allow a 0.1% deviation */ 1138 if (savesub < 100) 1139 break; 1140 } 1141 1142 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1143 spdif_priv->txclk_src[index], rate[index]); 1144 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", 1145 spdif_priv->txclk_df[index], rate[index]); 1146 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) 1147 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", 1148 spdif_priv->sysclk_df[index], rate[index]); 1149 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", 1150 rate[index], spdif_priv->txrate[index]); 1151 1152 return 0; 1153 } 1154 1155 static int fsl_spdif_probe(struct platform_device *pdev) 1156 { 1157 struct device_node *np = pdev->dev.of_node; 1158 struct fsl_spdif_priv *spdif_priv; 1159 struct spdif_mixer_control *ctrl; 1160 struct resource *res; 1161 void __iomem *regs; 1162 int irq, ret, i; 1163 1164 if (!np) 1165 return -ENODEV; 1166 1167 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1168 if (!spdif_priv) 1169 return -ENOMEM; 1170 1171 spdif_priv->pdev = pdev; 1172 1173 /* Initialize this copy of the CPU DAI driver structure */ 1174 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1175 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1176 1177 /* Get the addresses and IRQ */ 1178 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1179 regs = devm_ioremap_resource(&pdev->dev, res); 1180 if (IS_ERR(regs)) 1181 return PTR_ERR(regs); 1182 1183 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1184 "core", regs, &fsl_spdif_regmap_config); 1185 if (IS_ERR(spdif_priv->regmap)) { 1186 dev_err(&pdev->dev, "regmap init failed\n"); 1187 return PTR_ERR(spdif_priv->regmap); 1188 } 1189 1190 irq = platform_get_irq(pdev, 0); 1191 if (irq < 0) { 1192 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1193 return irq; 1194 } 1195 1196 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1197 dev_name(&pdev->dev), spdif_priv); 1198 if (ret) { 1199 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1200 return ret; 1201 } 1202 1203 /* Get system clock for rx clock rate calculation */ 1204 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); 1205 if (IS_ERR(spdif_priv->sysclk)) { 1206 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1207 return PTR_ERR(spdif_priv->sysclk); 1208 } 1209 1210 /* Get core clock for data register access via DMA */ 1211 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1212 if (IS_ERR(spdif_priv->coreclk)) { 1213 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1214 return PTR_ERR(spdif_priv->coreclk); 1215 } 1216 1217 /* Select clock source for rx/tx clock */ 1218 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); 1219 if (IS_ERR(spdif_priv->rxclk)) { 1220 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1221 return PTR_ERR(spdif_priv->rxclk); 1222 } 1223 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1224 1225 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1226 ret = fsl_spdif_probe_txclk(spdif_priv, i); 1227 if (ret) 1228 return ret; 1229 } 1230 1231 /* Initial spinlock for control data */ 1232 ctrl = &spdif_priv->fsl_spdif_control; 1233 spin_lock_init(&ctrl->ctl_lock); 1234 1235 /* Init tx channel status default value */ 1236 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1237 IEC958_AES0_CON_EMPHASIS_5015; 1238 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1239 ctrl->ch_status[2] = 0x00; 1240 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1241 IEC958_AES3_CON_CLOCK_1000PPM; 1242 1243 spdif_priv->dpll_locked = false; 1244 1245 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML; 1246 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML; 1247 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1248 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1249 1250 /* Register with ASoC */ 1251 dev_set_drvdata(&pdev->dev, spdif_priv); 1252 1253 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1254 &spdif_priv->cpu_dai_drv, 1); 1255 if (ret) { 1256 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1257 return ret; 1258 } 1259 1260 ret = imx_pcm_dma_init(pdev); 1261 if (ret) 1262 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret); 1263 1264 return ret; 1265 } 1266 1267 static const struct of_device_id fsl_spdif_dt_ids[] = { 1268 { .compatible = "fsl,imx35-spdif", }, 1269 { .compatible = "fsl,vf610-spdif", }, 1270 {} 1271 }; 1272 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1273 1274 static struct platform_driver fsl_spdif_driver = { 1275 .driver = { 1276 .name = "fsl-spdif-dai", 1277 .of_match_table = fsl_spdif_dt_ids, 1278 }, 1279 .probe = fsl_spdif_probe, 1280 }; 1281 1282 module_platform_driver(fsl_spdif_driver); 1283 1284 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1285 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1286 MODULE_LICENSE("GPL v2"); 1287 MODULE_ALIAS("platform:fsl-spdif-dai"); 1288