1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 #include <linux/pm_runtime.h> 20 21 #include <sound/asoundef.h> 22 #include <sound/dmaengine_pcm.h> 23 #include <sound/soc.h> 24 25 #include "fsl_spdif.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SPDIF_TXFIFO_WML 0x8 30 #define FSL_SPDIF_RXFIFO_WML 0x8 31 32 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 33 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 34 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 35 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 36 INT_LOSS_LOCK | INT_DPLL_LOCKED) 37 38 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 39 40 /* Index list for the values that has if (DPLL Locked) condition */ 41 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 42 #define SRPC_NODPLL_START1 0x5 43 #define SRPC_NODPLL_START2 0xc 44 45 #define DEFAULT_RXCLK_SRC 1 46 47 /** 48 * struct fsl_spdif_soc_data: soc specific data 49 * 50 * @imx: for imx platform 51 * @shared_root_clock: flag of sharing a clock source with others; 52 * so the driver shouldn't set root clock rate 53 * @raw_capture_mode: if raw capture mode support 54 * @cchannel_192b: if there are registers for 192bits C channel data 55 * @interrupts: interrupt number 56 * @tx_burst: tx maxburst size 57 * @rx_burst: rx maxburst size 58 * @tx_formats: tx supported data format 59 */ 60 struct fsl_spdif_soc_data { 61 bool imx; 62 bool shared_root_clock; 63 bool raw_capture_mode; 64 bool cchannel_192b; 65 u32 interrupts; 66 u32 tx_burst; 67 u32 rx_burst; 68 u64 tx_formats; 69 }; 70 71 /* 72 * SPDIF control structure 73 * Defines channel status, subcode and Q sub 74 */ 75 struct spdif_mixer_control { 76 /* spinlock to access control data */ 77 spinlock_t ctl_lock; 78 79 /* IEC958 channel tx status bit */ 80 unsigned char ch_status[4]; 81 82 /* User bits */ 83 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 84 85 /* Q subcode part of user bits */ 86 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 87 88 /* Buffer offset for U/Q */ 89 u32 upos; 90 u32 qpos; 91 92 /* Ready buffer index of the two buffers */ 93 u32 ready_buf; 94 }; 95 96 /** 97 * struct fsl_spdif_priv - Freescale SPDIF private data 98 * @soc: SPDIF soc data 99 * @fsl_spdif_control: SPDIF control data 100 * @cpu_dai_drv: cpu dai driver 101 * @pdev: platform device pointer 102 * @regmap: regmap handler 103 * @dpll_locked: dpll lock flag 104 * @txrate: the best rates for playback 105 * @txclk_df: STC_TXCLK_DF dividers value for playback 106 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 107 * @txclk_src: STC_TXCLK_SRC values for playback 108 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 109 * @txclk: tx clock sources for playback 110 * @rxclk: rx clock sources for capture 111 * @coreclk: core clock for register access via DMA 112 * @sysclk: system clock for rx clock rate measurement 113 * @spbaclk: SPBA clock (optional, depending on SoC design) 114 * @dma_params_tx: DMA parameters for transmit channel 115 * @dma_params_rx: DMA parameters for receive channel 116 * @regcache_srpc: regcache for SRPC 117 * @bypass: status of bypass input to output 118 * @pll8k_clk: PLL clock for the rate of multiply of 8kHz 119 * @pll11k_clk: PLL clock for the rate of multiply of 11kHz 120 */ 121 struct fsl_spdif_priv { 122 const struct fsl_spdif_soc_data *soc; 123 struct spdif_mixer_control fsl_spdif_control; 124 struct snd_soc_dai_driver cpu_dai_drv; 125 struct platform_device *pdev; 126 struct regmap *regmap; 127 bool dpll_locked; 128 u32 txrate[SPDIF_TXRATE_MAX]; 129 u8 txclk_df[SPDIF_TXRATE_MAX]; 130 u16 sysclk_df[SPDIF_TXRATE_MAX]; 131 u8 txclk_src[SPDIF_TXRATE_MAX]; 132 u8 rxclk_src; 133 struct clk *txclk[STC_TXCLK_SRC_MAX]; 134 struct clk *rxclk; 135 struct clk *coreclk; 136 struct clk *sysclk; 137 struct clk *spbaclk; 138 struct snd_dmaengine_dai_dma_data dma_params_tx; 139 struct snd_dmaengine_dai_dma_data dma_params_rx; 140 /* regcache for SRPC */ 141 u32 regcache_srpc; 142 bool bypass; 143 struct clk *pll8k_clk; 144 struct clk *pll11k_clk; 145 }; 146 147 static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 148 .imx = false, 149 .shared_root_clock = false, 150 .raw_capture_mode = false, 151 .interrupts = 1, 152 .tx_burst = FSL_SPDIF_TXFIFO_WML, 153 .rx_burst = FSL_SPDIF_RXFIFO_WML, 154 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 155 }; 156 157 static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 158 .imx = true, 159 .shared_root_clock = false, 160 .raw_capture_mode = false, 161 .interrupts = 1, 162 .tx_burst = FSL_SPDIF_TXFIFO_WML, 163 .rx_burst = FSL_SPDIF_RXFIFO_WML, 164 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 165 }; 166 167 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 168 .imx = true, 169 .shared_root_clock = true, 170 .raw_capture_mode = false, 171 .interrupts = 1, 172 .tx_burst = FSL_SPDIF_TXFIFO_WML, 173 .rx_burst = FSL_SPDIF_RXFIFO_WML, 174 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 175 176 }; 177 178 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = { 179 .imx = true, 180 .shared_root_clock = true, 181 .raw_capture_mode = false, 182 .interrupts = 2, 183 .tx_burst = 2, /* Applied for EDMA */ 184 .rx_burst = 2, /* Applied for EDMA */ 185 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 186 }; 187 188 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = { 189 .imx = true, 190 .shared_root_clock = false, 191 .raw_capture_mode = true, 192 .interrupts = 1, 193 .tx_burst = FSL_SPDIF_TXFIFO_WML, 194 .rx_burst = FSL_SPDIF_RXFIFO_WML, 195 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 196 }; 197 198 static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = { 199 .imx = true, 200 .shared_root_clock = true, 201 .raw_capture_mode = false, 202 .interrupts = 1, 203 .tx_burst = 2, /* Applied for EDMA */ 204 .rx_burst = 2, /* Applied for EDMA */ 205 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 206 .cchannel_192b = true, 207 }; 208 209 /* Check if clk is a root clock that does not share clock source with others */ 210 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 211 { 212 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 213 } 214 215 /* DPLL locked and lock loss interrupt handler */ 216 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 217 { 218 struct regmap *regmap = spdif_priv->regmap; 219 struct platform_device *pdev = spdif_priv->pdev; 220 u32 locked; 221 222 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 223 locked &= SRPC_DPLL_LOCKED; 224 225 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 226 locked ? "locked" : "loss lock"); 227 228 spdif_priv->dpll_locked = locked ? true : false; 229 } 230 231 /* Receiver found illegal symbol interrupt handler */ 232 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 233 { 234 struct regmap *regmap = spdif_priv->regmap; 235 struct platform_device *pdev = spdif_priv->pdev; 236 237 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 238 239 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 240 if (!spdif_priv->dpll_locked) 241 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 242 } 243 244 /* U/Q Channel receive register full */ 245 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 246 { 247 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 248 struct regmap *regmap = spdif_priv->regmap; 249 struct platform_device *pdev = spdif_priv->pdev; 250 u32 *pos, size, val, reg; 251 252 switch (name) { 253 case 'U': 254 pos = &ctrl->upos; 255 size = SPDIF_UBITS_SIZE; 256 reg = REG_SPDIF_SRU; 257 break; 258 case 'Q': 259 pos = &ctrl->qpos; 260 size = SPDIF_QSUB_SIZE; 261 reg = REG_SPDIF_SRQ; 262 break; 263 default: 264 dev_err(&pdev->dev, "unsupported channel name\n"); 265 return; 266 } 267 268 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 269 270 if (*pos >= size * 2) { 271 *pos = 0; 272 } else if (unlikely((*pos % size) + 3 > size)) { 273 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 274 return; 275 } 276 277 regmap_read(regmap, reg, &val); 278 ctrl->subcode[*pos++] = val >> 16; 279 ctrl->subcode[*pos++] = val >> 8; 280 ctrl->subcode[*pos++] = val; 281 } 282 283 /* U/Q Channel sync found */ 284 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 285 { 286 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 287 struct platform_device *pdev = spdif_priv->pdev; 288 289 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 290 291 /* U/Q buffer reset */ 292 if (ctrl->qpos == 0) 293 return; 294 295 /* Set ready to this buffer */ 296 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 297 } 298 299 /* U/Q Channel framing error */ 300 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 301 { 302 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 303 struct regmap *regmap = spdif_priv->regmap; 304 struct platform_device *pdev = spdif_priv->pdev; 305 u32 val; 306 307 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 308 309 /* Read U/Q data to clear the irq and do buffer reset */ 310 regmap_read(regmap, REG_SPDIF_SRU, &val); 311 regmap_read(regmap, REG_SPDIF_SRQ, &val); 312 313 /* Drop this U/Q buffer */ 314 ctrl->ready_buf = 0; 315 ctrl->upos = 0; 316 ctrl->qpos = 0; 317 } 318 319 /* Get spdif interrupt status and clear the interrupt */ 320 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 321 { 322 struct regmap *regmap = spdif_priv->regmap; 323 u32 val, val2; 324 325 regmap_read(regmap, REG_SPDIF_SIS, &val); 326 regmap_read(regmap, REG_SPDIF_SIE, &val2); 327 328 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 329 330 return val; 331 } 332 333 static irqreturn_t spdif_isr(int irq, void *devid) 334 { 335 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 336 struct platform_device *pdev = spdif_priv->pdev; 337 u32 sis; 338 339 sis = spdif_intr_status_clear(spdif_priv); 340 341 if (sis & INT_DPLL_LOCKED) 342 spdif_irq_dpll_lock(spdif_priv); 343 344 if (sis & INT_TXFIFO_UNOV) 345 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 346 347 if (sis & INT_TXFIFO_RESYNC) 348 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 349 350 if (sis & INT_CNEW) 351 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 352 353 if (sis & INT_VAL_NOGOOD) 354 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 355 356 if (sis & INT_SYM_ERR) 357 spdif_irq_sym_error(spdif_priv); 358 359 if (sis & INT_BIT_ERR) 360 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 361 362 if (sis & INT_URX_FUL) 363 spdif_irq_uqrx_full(spdif_priv, 'U'); 364 365 if (sis & INT_URX_OV) 366 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 367 368 if (sis & INT_QRX_FUL) 369 spdif_irq_uqrx_full(spdif_priv, 'Q'); 370 371 if (sis & INT_QRX_OV) 372 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 373 374 if (sis & INT_UQ_SYNC) 375 spdif_irq_uq_sync(spdif_priv); 376 377 if (sis & INT_UQ_ERR) 378 spdif_irq_uq_err(spdif_priv); 379 380 if (sis & INT_RXFIFO_UNOV) 381 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 382 383 if (sis & INT_RXFIFO_RESYNC) 384 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 385 386 if (sis & INT_LOSS_LOCK) 387 spdif_irq_dpll_lock(spdif_priv); 388 389 /* FIXME: Write Tx FIFO to clear TxEm */ 390 if (sis & INT_TX_EM) 391 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 392 393 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 394 if (sis & INT_RXFIFO_FUL) 395 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 396 397 return IRQ_HANDLED; 398 } 399 400 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 401 { 402 struct regmap *regmap = spdif_priv->regmap; 403 u32 val, cycle = 1000; 404 405 regcache_cache_bypass(regmap, true); 406 407 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 408 409 /* 410 * RESET bit would be cleared after finishing its reset procedure, 411 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 412 */ 413 do { 414 regmap_read(regmap, REG_SPDIF_SCR, &val); 415 } while ((val & SCR_SOFT_RESET) && cycle--); 416 417 regcache_cache_bypass(regmap, false); 418 regcache_mark_dirty(regmap); 419 regcache_sync(regmap); 420 421 if (cycle) 422 return 0; 423 else 424 return -EBUSY; 425 } 426 427 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 428 u8 mask, u8 cstatus) 429 { 430 ctrl->ch_status[3] &= ~mask; 431 ctrl->ch_status[3] |= cstatus & mask; 432 } 433 434 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 435 { 436 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 437 struct regmap *regmap = spdif_priv->regmap; 438 struct platform_device *pdev = spdif_priv->pdev; 439 u32 ch_status; 440 441 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 442 (bitrev8(ctrl->ch_status[1]) << 8) | 443 bitrev8(ctrl->ch_status[2]); 444 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 445 446 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 447 448 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 449 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 450 451 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 452 453 if (spdif_priv->soc->cchannel_192b) { 454 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) | 455 (bitrev8(ctrl->ch_status[1]) << 16) | 456 (bitrev8(ctrl->ch_status[2]) << 8) | 457 bitrev8(ctrl->ch_status[3]); 458 459 regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000); 460 461 /* 462 * The first 32bit should be in REG_SPDIF_STCCA_31_0 register, 463 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP 464 * then can get correct result with HDMI analyzer capture. 465 * There is a hardware bug here. 466 */ 467 regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status); 468 } 469 } 470 471 /* Set SPDIF PhaseConfig register for rx clock */ 472 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 473 enum spdif_gainsel gainsel, int dpll_locked) 474 { 475 struct regmap *regmap = spdif_priv->regmap; 476 u8 clksrc = spdif_priv->rxclk_src; 477 478 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 479 return -EINVAL; 480 481 regmap_update_bits(regmap, REG_SPDIF_SRPC, 482 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 483 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 484 485 return 0; 486 } 487 488 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index); 489 490 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 491 int sample_rate) 492 { 493 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 494 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 495 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 496 struct regmap *regmap = spdif_priv->regmap; 497 struct platform_device *pdev = spdif_priv->pdev; 498 unsigned long csfs = 0; 499 u32 stc, mask, rate; 500 u16 sysclk_df; 501 u8 clk, txclk_df; 502 int ret; 503 504 switch (sample_rate) { 505 case 32000: 506 rate = SPDIF_TXRATE_32000; 507 csfs = IEC958_AES3_CON_FS_32000; 508 break; 509 case 44100: 510 rate = SPDIF_TXRATE_44100; 511 csfs = IEC958_AES3_CON_FS_44100; 512 break; 513 case 48000: 514 rate = SPDIF_TXRATE_48000; 515 csfs = IEC958_AES3_CON_FS_48000; 516 break; 517 case 88200: 518 rate = SPDIF_TXRATE_88200; 519 csfs = IEC958_AES3_CON_FS_88200; 520 break; 521 case 96000: 522 rate = SPDIF_TXRATE_96000; 523 csfs = IEC958_AES3_CON_FS_96000; 524 break; 525 case 176400: 526 rate = SPDIF_TXRATE_176400; 527 csfs = IEC958_AES3_CON_FS_176400; 528 break; 529 case 192000: 530 rate = SPDIF_TXRATE_192000; 531 csfs = IEC958_AES3_CON_FS_192000; 532 break; 533 default: 534 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 535 return -EINVAL; 536 } 537 538 ret = fsl_spdif_probe_txclk(spdif_priv, rate); 539 if (ret) 540 return ret; 541 542 clk = spdif_priv->txclk_src[rate]; 543 if (clk >= STC_TXCLK_SRC_MAX) { 544 dev_err(&pdev->dev, "tx clock source is out of range\n"); 545 return -EINVAL; 546 } 547 548 txclk_df = spdif_priv->txclk_df[rate]; 549 if (txclk_df == 0) { 550 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 551 return -EINVAL; 552 } 553 554 sysclk_df = spdif_priv->sysclk_df[rate]; 555 556 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 557 goto clk_set_bypass; 558 559 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 560 ret = clk_set_rate(spdif_priv->txclk[clk], 561 64 * sample_rate * txclk_df); 562 if (ret) { 563 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 564 return ret; 565 } 566 567 clk_set_bypass: 568 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 569 (64 * sample_rate * txclk_df * sysclk_df)); 570 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 571 clk_get_rate(spdif_priv->txclk[clk])); 572 573 /* set fs field in consumer channel status */ 574 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 575 576 /* select clock source and divisor */ 577 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 578 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 579 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 580 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 581 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 582 583 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 584 spdif_priv->txrate[rate], sample_rate); 585 586 return 0; 587 } 588 589 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 590 struct snd_soc_dai *cpu_dai) 591 { 592 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 593 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 594 struct platform_device *pdev = spdif_priv->pdev; 595 struct regmap *regmap = spdif_priv->regmap; 596 u32 scr, mask; 597 int ret; 598 599 /* Reset module and interrupts only for first initialization */ 600 if (!snd_soc_dai_active(cpu_dai)) { 601 ret = spdif_softreset(spdif_priv); 602 if (ret) { 603 dev_err(&pdev->dev, "failed to soft reset\n"); 604 return ret; 605 } 606 607 /* Disable all the interrupts */ 608 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 609 } 610 611 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 612 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 613 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 614 SCR_TXFIFO_FSEL_IF8; 615 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 616 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 617 SCR_TXFIFO_FSEL_MASK; 618 } else { 619 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 620 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 621 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 622 } 623 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 624 625 /* Power up SPDIF module */ 626 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 627 628 return 0; 629 } 630 631 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 632 struct snd_soc_dai *cpu_dai) 633 { 634 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 635 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 636 struct regmap *regmap = spdif_priv->regmap; 637 u32 scr, mask; 638 639 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 640 scr = 0; 641 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 642 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 643 SCR_TXFIFO_FSEL_MASK; 644 /* Disable TX clock */ 645 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0); 646 } else { 647 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 648 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 649 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 650 } 651 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 652 653 /* Power down SPDIF module only if tx&rx are both inactive */ 654 if (!snd_soc_dai_active(cpu_dai)) { 655 spdif_intr_status_clear(spdif_priv); 656 regmap_update_bits(regmap, REG_SPDIF_SCR, 657 SCR_LOW_POWER, SCR_LOW_POWER); 658 } 659 } 660 661 static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate) 662 { 663 struct platform_device *pdev = spdif_priv->pdev; 664 struct clk *clk; 665 int ret; 666 667 /* Reparent clock if required condition is true */ 668 if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT)) 669 return 0; 670 671 /* Get root clock */ 672 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT]; 673 674 /* Disable clock first, for it was enabled by pm_runtime */ 675 clk_disable_unprepare(clk); 676 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk, 677 spdif_priv->pll11k_clk, sample_rate); 678 ret = clk_prepare_enable(clk); 679 if (ret) 680 return ret; 681 682 return 0; 683 } 684 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 685 struct snd_pcm_hw_params *params, 686 struct snd_soc_dai *dai) 687 { 688 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 689 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 690 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 691 struct platform_device *pdev = spdif_priv->pdev; 692 u32 sample_rate = params_rate(params); 693 int ret = 0; 694 695 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 696 ret = spdif_reparent_rootclk(spdif_priv, sample_rate); 697 if (ret) { 698 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n", 699 __func__, sample_rate); 700 return ret; 701 } 702 703 ret = spdif_set_sample_rate(substream, sample_rate); 704 if (ret) { 705 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 706 __func__, sample_rate); 707 return ret; 708 } 709 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 710 IEC958_AES3_CON_CLOCK_1000PPM); 711 spdif_write_channel_status(spdif_priv); 712 } else { 713 /* Setup rx clock source */ 714 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 715 } 716 717 return ret; 718 } 719 720 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 721 int cmd, struct snd_soc_dai *dai) 722 { 723 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 724 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 725 struct regmap *regmap = spdif_priv->regmap; 726 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 727 u32 intr = SIE_INTR_FOR(tx); 728 u32 dmaen = SCR_DMA_xX_EN(tx); 729 730 switch (cmd) { 731 case SNDRV_PCM_TRIGGER_START: 732 case SNDRV_PCM_TRIGGER_RESUME: 733 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 734 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 735 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 736 break; 737 case SNDRV_PCM_TRIGGER_STOP: 738 case SNDRV_PCM_TRIGGER_SUSPEND: 739 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 740 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 741 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 742 break; 743 default: 744 return -EINVAL; 745 } 746 747 return 0; 748 } 749 750 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 751 .startup = fsl_spdif_startup, 752 .hw_params = fsl_spdif_hw_params, 753 .trigger = fsl_spdif_trigger, 754 .shutdown = fsl_spdif_shutdown, 755 }; 756 757 758 /* 759 * FSL SPDIF IEC958 controller(mixer) functions 760 * 761 * Channel status get/put control 762 * User bit value get/put control 763 * Valid bit value get control 764 * DPLL lock status get control 765 * User bit sync mode selection control 766 */ 767 768 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 769 struct snd_ctl_elem_info *uinfo) 770 { 771 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 772 uinfo->count = 1; 773 774 return 0; 775 } 776 777 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 778 struct snd_ctl_elem_value *uvalue) 779 { 780 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 781 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 782 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 783 784 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 785 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 786 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 787 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 788 789 return 0; 790 } 791 792 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 793 struct snd_ctl_elem_value *uvalue) 794 { 795 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 796 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 797 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 798 799 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 800 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 801 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 802 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 803 804 spdif_write_channel_status(spdif_priv); 805 806 return 0; 807 } 808 809 /* Get channel status from SPDIF_RX_CCHAN register */ 810 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 811 struct snd_ctl_elem_value *ucontrol) 812 { 813 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 814 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 815 struct regmap *regmap = spdif_priv->regmap; 816 u32 cstatus, val; 817 818 regmap_read(regmap, REG_SPDIF_SIS, &val); 819 if (!(val & INT_CNEW)) 820 return -EAGAIN; 821 822 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 823 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 824 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 825 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 826 827 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 828 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 829 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 830 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 831 832 /* Clear intr */ 833 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 834 835 return 0; 836 } 837 838 /* 839 * Get User bits (subcode) from chip value which readed out 840 * in UChannel register. 841 */ 842 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 843 struct snd_ctl_elem_value *ucontrol) 844 { 845 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 846 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 847 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 848 unsigned long flags; 849 int ret = -EAGAIN; 850 851 spin_lock_irqsave(&ctrl->ctl_lock, flags); 852 if (ctrl->ready_buf) { 853 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 854 memcpy(&ucontrol->value.iec958.subcode[0], 855 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 856 ret = 0; 857 } 858 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 859 860 return ret; 861 } 862 863 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 864 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 865 struct snd_ctl_elem_info *uinfo) 866 { 867 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 868 uinfo->count = SPDIF_QSUB_SIZE; 869 870 return 0; 871 } 872 873 /* Get Q subcode from chip value which readed out in QChannel register */ 874 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 875 struct snd_ctl_elem_value *ucontrol) 876 { 877 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 878 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 879 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 880 unsigned long flags; 881 int ret = -EAGAIN; 882 883 spin_lock_irqsave(&ctrl->ctl_lock, flags); 884 if (ctrl->ready_buf) { 885 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 886 memcpy(&ucontrol->value.bytes.data[0], 887 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 888 ret = 0; 889 } 890 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 891 892 return ret; 893 } 894 895 /* Get valid good bit from interrupt status register */ 896 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 897 struct snd_ctl_elem_value *ucontrol) 898 { 899 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 900 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 901 struct regmap *regmap = spdif_priv->regmap; 902 u32 val; 903 904 regmap_read(regmap, REG_SPDIF_SIS, &val); 905 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 906 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 907 908 return 0; 909 } 910 911 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 912 struct snd_ctl_elem_value *ucontrol) 913 { 914 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 915 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 916 struct regmap *regmap = spdif_priv->regmap; 917 u32 val; 918 919 regmap_read(regmap, REG_SPDIF_SCR, &val); 920 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 921 val = 1 - val; 922 ucontrol->value.integer.value[0] = val; 923 924 return 0; 925 } 926 927 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 928 struct snd_ctl_elem_value *ucontrol) 929 { 930 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 931 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 932 struct regmap *regmap = spdif_priv->regmap; 933 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 934 935 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 936 937 return 0; 938 } 939 940 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol, 941 struct snd_ctl_elem_value *ucontrol) 942 { 943 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 944 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 945 struct regmap *regmap = spdif_priv->regmap; 946 u32 val; 947 948 regmap_read(regmap, REG_SPDIF_SCR, &val); 949 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0; 950 ucontrol->value.integer.value[0] = val; 951 952 return 0; 953 } 954 955 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol, 956 struct snd_ctl_elem_value *ucontrol) 957 { 958 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 959 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 960 struct regmap *regmap = spdif_priv->regmap; 961 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); 962 963 if (val) 964 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; 965 else 966 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; 967 968 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val); 969 970 return 0; 971 } 972 973 static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol, 974 struct snd_ctl_elem_value *ucontrol) 975 { 976 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 977 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 978 979 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0; 980 981 return 0; 982 } 983 984 static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol, 985 struct snd_ctl_elem_value *ucontrol) 986 { 987 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 988 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 989 struct snd_soc_card *card = dai->component->card; 990 bool set = (ucontrol->value.integer.value[0] != 0); 991 struct regmap *regmap = priv->regmap; 992 struct snd_soc_pcm_runtime *rtd; 993 u32 scr, mask; 994 int stream; 995 996 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 997 998 if (priv->bypass == set) 999 return 0; /* nothing to do */ 1000 1001 if (snd_soc_dai_active(dai)) { 1002 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n"); 1003 return -EBUSY; 1004 } 1005 1006 pm_runtime_get_sync(dai->dev); 1007 1008 if (set) { 1009 /* Disable interrupts */ 1010 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 1011 1012 /* Configure BYPASS mode */ 1013 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF; 1014 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK | 1015 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK; 1016 /* Power up SPDIF module */ 1017 mask |= SCR_LOW_POWER; 1018 } else { 1019 /* Power down SPDIF module, disable TX */ 1020 scr = SCR_LOW_POWER | SCR_TXSEL_OFF; 1021 mask = SCR_LOW_POWER | SCR_TXSEL_MASK; 1022 } 1023 1024 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 1025 1026 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */ 1027 for_each_pcm_streams(stream) 1028 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1); 1029 1030 priv->bypass = set; 1031 pm_runtime_put_sync(dai->dev); 1032 1033 return 0; 1034 } 1035 1036 /* DPLL lock information */ 1037 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 1038 struct snd_ctl_elem_info *uinfo) 1039 { 1040 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1041 uinfo->count = 1; 1042 uinfo->value.integer.min = 16000; 1043 uinfo->value.integer.max = 192000; 1044 1045 return 0; 1046 } 1047 1048 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 1049 24, 16, 12, 8, 6, 4, 3, 1050 }; 1051 1052 /* Get RX data clock rate given the SPDIF bus_clk */ 1053 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 1054 enum spdif_gainsel gainsel) 1055 { 1056 struct regmap *regmap = spdif_priv->regmap; 1057 struct platform_device *pdev = spdif_priv->pdev; 1058 u64 tmpval64, busclk_freq = 0; 1059 u32 freqmeas, phaseconf; 1060 u8 clksrc; 1061 1062 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 1063 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 1064 1065 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 1066 1067 /* Get bus clock from system */ 1068 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 1069 busclk_freq = clk_get_rate(spdif_priv->sysclk); 1070 1071 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 1072 tmpval64 = (u64) busclk_freq * freqmeas; 1073 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 1074 do_div(tmpval64, 128 * 1024); 1075 1076 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 1077 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 1078 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 1079 1080 return (int)tmpval64; 1081 } 1082 1083 /* 1084 * Get DPLL lock or not info from stable interrupt status register. 1085 * User application must use this control to get locked, 1086 * then can do next PCM operation 1087 */ 1088 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 1089 struct snd_ctl_elem_value *ucontrol) 1090 { 1091 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1092 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1093 int rate = 0; 1094 1095 if (spdif_priv->dpll_locked) 1096 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 1097 1098 ucontrol->value.integer.value[0] = rate; 1099 1100 return 0; 1101 } 1102 1103 /* 1104 * User bit sync mode: 1105 * 1 CD User channel subcode 1106 * 0 Non-CD data 1107 */ 1108 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 1109 struct snd_ctl_elem_value *ucontrol) 1110 { 1111 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1112 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1113 struct regmap *regmap = spdif_priv->regmap; 1114 u32 val; 1115 1116 regmap_read(regmap, REG_SPDIF_SRCD, &val); 1117 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 1118 1119 return 0; 1120 } 1121 1122 /* 1123 * User bit sync mode: 1124 * 1 CD User channel subcode 1125 * 0 Non-CD data 1126 */ 1127 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 1128 struct snd_ctl_elem_value *ucontrol) 1129 { 1130 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1131 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1132 struct regmap *regmap = spdif_priv->regmap; 1133 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 1134 1135 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 1136 1137 return 0; 1138 } 1139 1140 /* FSL SPDIF IEC958 controller defines */ 1141 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 1142 /* Status cchanel controller */ 1143 { 1144 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1145 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1146 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1147 SNDRV_CTL_ELEM_ACCESS_WRITE | 1148 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1149 .info = fsl_spdif_info, 1150 .get = fsl_spdif_pb_get, 1151 .put = fsl_spdif_pb_put, 1152 }, 1153 { 1154 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1155 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1156 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1157 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1158 .info = fsl_spdif_info, 1159 .get = fsl_spdif_capture_get, 1160 }, 1161 /* User bits controller */ 1162 { 1163 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1164 .name = "IEC958 Subcode Capture Default", 1165 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1166 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1167 .info = fsl_spdif_info, 1168 .get = fsl_spdif_subcode_get, 1169 }, 1170 { 1171 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1172 .name = "IEC958 Q-subcode Capture Default", 1173 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1174 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1175 .info = fsl_spdif_qinfo, 1176 .get = fsl_spdif_qget, 1177 }, 1178 /* Valid bit error controller */ 1179 { 1180 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1181 .name = "IEC958 RX V-Bit Errors", 1182 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1183 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1184 .info = snd_ctl_boolean_mono_info, 1185 .get = fsl_spdif_rx_vbit_get, 1186 }, 1187 { 1188 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1189 .name = "IEC958 TX V-Bit", 1190 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1191 SNDRV_CTL_ELEM_ACCESS_WRITE | 1192 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1193 .info = snd_ctl_boolean_mono_info, 1194 .get = fsl_spdif_tx_vbit_get, 1195 .put = fsl_spdif_tx_vbit_put, 1196 }, 1197 /* DPLL lock info get controller */ 1198 { 1199 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1200 .name = "RX Sample Rate", 1201 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1202 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1203 .info = fsl_spdif_rxrate_info, 1204 .get = fsl_spdif_rxrate_get, 1205 }, 1206 /* RX bypass controller */ 1207 { 1208 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1209 .name = "Bypass Mode", 1210 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1211 .info = snd_ctl_boolean_mono_info, 1212 .get = fsl_spdif_bypass_get, 1213 .put = fsl_spdif_bypass_put, 1214 }, 1215 /* User bit sync mode set/get controller */ 1216 { 1217 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1218 .name = "IEC958 USyncMode CDText", 1219 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1220 SNDRV_CTL_ELEM_ACCESS_WRITE | 1221 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1222 .info = snd_ctl_boolean_mono_info, 1223 .get = fsl_spdif_usync_get, 1224 .put = fsl_spdif_usync_put, 1225 }, 1226 }; 1227 1228 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = { 1229 { 1230 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1231 .name = "IEC958 Raw Capture Mode", 1232 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1233 SNDRV_CTL_ELEM_ACCESS_WRITE | 1234 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1235 .info = snd_ctl_boolean_mono_info, 1236 .get = fsl_spdif_rx_rcm_get, 1237 .put = fsl_spdif_rx_rcm_put, 1238 }, 1239 }; 1240 1241 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1242 { 1243 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1244 1245 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1246 &spdif_private->dma_params_rx); 1247 1248 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1249 1250 if (spdif_private->soc->raw_capture_mode) 1251 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm, 1252 ARRAY_SIZE(fsl_spdif_ctrls_rcm)); 1253 1254 /*Clear the val bit for Tx*/ 1255 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1256 SCR_VAL_MASK, SCR_VAL_CLEAR); 1257 1258 return 0; 1259 } 1260 1261 static struct snd_soc_dai_driver fsl_spdif_dai = { 1262 .probe = &fsl_spdif_dai_probe, 1263 .playback = { 1264 .stream_name = "CPU-Playback", 1265 .channels_min = 2, 1266 .channels_max = 2, 1267 .rates = FSL_SPDIF_RATES_PLAYBACK, 1268 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1269 }, 1270 .capture = { 1271 .stream_name = "CPU-Capture", 1272 .channels_min = 2, 1273 .channels_max = 2, 1274 .rates = FSL_SPDIF_RATES_CAPTURE, 1275 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1276 }, 1277 .ops = &fsl_spdif_dai_ops, 1278 }; 1279 1280 static const struct snd_soc_component_driver fsl_spdif_component = { 1281 .name = "fsl-spdif", 1282 .legacy_dai_naming = 1, 1283 }; 1284 1285 /* FSL SPDIF REGMAP */ 1286 static const struct reg_default fsl_spdif_reg_defaults[] = { 1287 {REG_SPDIF_SCR, 0x00000400}, 1288 {REG_SPDIF_SRCD, 0x00000000}, 1289 {REG_SPDIF_SIE, 0x00000000}, 1290 {REG_SPDIF_STL, 0x00000000}, 1291 {REG_SPDIF_STR, 0x00000000}, 1292 {REG_SPDIF_STCSCH, 0x00000000}, 1293 {REG_SPDIF_STCSCL, 0x00000000}, 1294 {REG_SPDIF_STCSPH, 0x00000000}, 1295 {REG_SPDIF_STCSPL, 0x00000000}, 1296 {REG_SPDIF_STC, 0x00020f00}, 1297 }; 1298 1299 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1300 { 1301 switch (reg) { 1302 case REG_SPDIF_SCR: 1303 case REG_SPDIF_SRCD: 1304 case REG_SPDIF_SRPC: 1305 case REG_SPDIF_SIE: 1306 case REG_SPDIF_SIS: 1307 case REG_SPDIF_SRL: 1308 case REG_SPDIF_SRR: 1309 case REG_SPDIF_SRCSH: 1310 case REG_SPDIF_SRCSL: 1311 case REG_SPDIF_SRU: 1312 case REG_SPDIF_SRQ: 1313 case REG_SPDIF_STCSCH: 1314 case REG_SPDIF_STCSCL: 1315 case REG_SPDIF_STCSPH: 1316 case REG_SPDIF_STCSPL: 1317 case REG_SPDIF_SRFM: 1318 case REG_SPDIF_STC: 1319 case REG_SPDIF_SRCCA_31_0: 1320 case REG_SPDIF_SRCCA_63_32: 1321 case REG_SPDIF_SRCCA_95_64: 1322 case REG_SPDIF_SRCCA_127_96: 1323 case REG_SPDIF_SRCCA_159_128: 1324 case REG_SPDIF_SRCCA_191_160: 1325 case REG_SPDIF_STCCA_31_0: 1326 case REG_SPDIF_STCCA_63_32: 1327 case REG_SPDIF_STCCA_95_64: 1328 case REG_SPDIF_STCCA_127_96: 1329 case REG_SPDIF_STCCA_159_128: 1330 case REG_SPDIF_STCCA_191_160: 1331 return true; 1332 default: 1333 return false; 1334 } 1335 } 1336 1337 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1338 { 1339 switch (reg) { 1340 case REG_SPDIF_SRPC: 1341 case REG_SPDIF_SIS: 1342 case REG_SPDIF_SRL: 1343 case REG_SPDIF_SRR: 1344 case REG_SPDIF_SRCSH: 1345 case REG_SPDIF_SRCSL: 1346 case REG_SPDIF_SRU: 1347 case REG_SPDIF_SRQ: 1348 case REG_SPDIF_SRFM: 1349 case REG_SPDIF_SRCCA_31_0: 1350 case REG_SPDIF_SRCCA_63_32: 1351 case REG_SPDIF_SRCCA_95_64: 1352 case REG_SPDIF_SRCCA_127_96: 1353 case REG_SPDIF_SRCCA_159_128: 1354 case REG_SPDIF_SRCCA_191_160: 1355 return true; 1356 default: 1357 return false; 1358 } 1359 } 1360 1361 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1362 { 1363 switch (reg) { 1364 case REG_SPDIF_SCR: 1365 case REG_SPDIF_SRCD: 1366 case REG_SPDIF_SRPC: 1367 case REG_SPDIF_SIE: 1368 case REG_SPDIF_SIC: 1369 case REG_SPDIF_STL: 1370 case REG_SPDIF_STR: 1371 case REG_SPDIF_STCSCH: 1372 case REG_SPDIF_STCSCL: 1373 case REG_SPDIF_STCSPH: 1374 case REG_SPDIF_STCSPL: 1375 case REG_SPDIF_STC: 1376 case REG_SPDIF_STCCA_31_0: 1377 case REG_SPDIF_STCCA_63_32: 1378 case REG_SPDIF_STCCA_95_64: 1379 case REG_SPDIF_STCCA_127_96: 1380 case REG_SPDIF_STCCA_159_128: 1381 case REG_SPDIF_STCCA_191_160: 1382 return true; 1383 default: 1384 return false; 1385 } 1386 } 1387 1388 static const struct regmap_config fsl_spdif_regmap_config = { 1389 .reg_bits = 32, 1390 .reg_stride = 4, 1391 .val_bits = 32, 1392 1393 .max_register = REG_SPDIF_STCCA_191_160, 1394 .reg_defaults = fsl_spdif_reg_defaults, 1395 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1396 .readable_reg = fsl_spdif_readable_reg, 1397 .volatile_reg = fsl_spdif_volatile_reg, 1398 .writeable_reg = fsl_spdif_writeable_reg, 1399 .cache_type = REGCACHE_FLAT, 1400 }; 1401 1402 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1403 struct clk *clk, u64 savesub, 1404 enum spdif_txrate index, bool round) 1405 { 1406 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1407 192000, }; 1408 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1409 u64 rate_ideal, rate_actual, sub; 1410 u32 arate; 1411 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1412 u8 txclk_df; 1413 1414 /* The sysclk has an extra divisor [2, 512] */ 1415 sysclk_dfmin = is_sysclk ? 2 : 1; 1416 sysclk_dfmax = is_sysclk ? 512 : 1; 1417 1418 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1419 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1420 rate_ideal = rate[index] * txclk_df * 64ULL; 1421 if (round) 1422 rate_actual = clk_round_rate(clk, rate_ideal); 1423 else 1424 rate_actual = clk_get_rate(clk); 1425 1426 arate = rate_actual / 64; 1427 arate /= txclk_df * sysclk_df; 1428 1429 if (arate == rate[index]) { 1430 /* We are lucky */ 1431 savesub = 0; 1432 spdif_priv->txclk_df[index] = txclk_df; 1433 spdif_priv->sysclk_df[index] = sysclk_df; 1434 spdif_priv->txrate[index] = arate; 1435 goto out; 1436 } else if (arate / rate[index] == 1) { 1437 /* A little bigger than expect */ 1438 sub = (u64)(arate - rate[index]) * 100000; 1439 do_div(sub, rate[index]); 1440 if (sub >= savesub) 1441 continue; 1442 savesub = sub; 1443 spdif_priv->txclk_df[index] = txclk_df; 1444 spdif_priv->sysclk_df[index] = sysclk_df; 1445 spdif_priv->txrate[index] = arate; 1446 } else if (rate[index] / arate == 1) { 1447 /* A little smaller than expect */ 1448 sub = (u64)(rate[index] - arate) * 100000; 1449 do_div(sub, rate[index]); 1450 if (sub >= savesub) 1451 continue; 1452 savesub = sub; 1453 spdif_priv->txclk_df[index] = txclk_df; 1454 spdif_priv->sysclk_df[index] = sysclk_df; 1455 spdif_priv->txrate[index] = arate; 1456 } 1457 } 1458 } 1459 1460 out: 1461 return savesub; 1462 } 1463 1464 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1465 enum spdif_txrate index) 1466 { 1467 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1468 192000, }; 1469 struct platform_device *pdev = spdif_priv->pdev; 1470 struct device *dev = &pdev->dev; 1471 u64 savesub = 100000, ret; 1472 struct clk *clk; 1473 int i; 1474 1475 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1476 clk = spdif_priv->txclk[i]; 1477 if (IS_ERR(clk)) { 1478 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1479 return PTR_ERR(clk); 1480 } 1481 if (!clk_get_rate(clk)) 1482 continue; 1483 1484 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1485 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1486 if (savesub == ret) 1487 continue; 1488 1489 savesub = ret; 1490 spdif_priv->txclk_src[index] = i; 1491 1492 /* To quick catch a divisor, we allow a 0.1% deviation */ 1493 if (savesub < 100) 1494 break; 1495 } 1496 1497 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1498 spdif_priv->txclk_src[index], rate[index]); 1499 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n", 1500 spdif_priv->txclk_df[index], rate[index]); 1501 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk)) 1502 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n", 1503 spdif_priv->sysclk_df[index], rate[index]); 1504 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n", 1505 rate[index], spdif_priv->txrate[index]); 1506 1507 return 0; 1508 } 1509 1510 static int fsl_spdif_probe(struct platform_device *pdev) 1511 { 1512 struct fsl_spdif_priv *spdif_priv; 1513 struct spdif_mixer_control *ctrl; 1514 struct resource *res; 1515 void __iomem *regs; 1516 int irq, ret, i; 1517 char tmp[16]; 1518 1519 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1520 if (!spdif_priv) 1521 return -ENOMEM; 1522 1523 spdif_priv->pdev = pdev; 1524 1525 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1526 1527 /* Initialize this copy of the CPU DAI driver structure */ 1528 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1529 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1530 spdif_priv->cpu_dai_drv.playback.formats = 1531 spdif_priv->soc->tx_formats; 1532 1533 /* Get the addresses and IRQ */ 1534 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1535 if (IS_ERR(regs)) 1536 return PTR_ERR(regs); 1537 1538 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); 1539 if (IS_ERR(spdif_priv->regmap)) { 1540 dev_err(&pdev->dev, "regmap init failed\n"); 1541 return PTR_ERR(spdif_priv->regmap); 1542 } 1543 1544 for (i = 0; i < spdif_priv->soc->interrupts; i++) { 1545 irq = platform_get_irq(pdev, i); 1546 if (irq < 0) 1547 return irq; 1548 1549 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1550 dev_name(&pdev->dev), spdif_priv); 1551 if (ret) { 1552 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1553 return ret; 1554 } 1555 } 1556 1557 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1558 sprintf(tmp, "rxtx%d", i); 1559 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp); 1560 if (IS_ERR(spdif_priv->txclk[i])) { 1561 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i); 1562 return PTR_ERR(spdif_priv->txclk[i]); 1563 } 1564 } 1565 1566 /* Get system clock for rx clock rate calculation */ 1567 spdif_priv->sysclk = spdif_priv->txclk[5]; 1568 if (IS_ERR(spdif_priv->sysclk)) { 1569 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1570 return PTR_ERR(spdif_priv->sysclk); 1571 } 1572 1573 /* Get core clock for data register access via DMA */ 1574 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1575 if (IS_ERR(spdif_priv->coreclk)) { 1576 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1577 return PTR_ERR(spdif_priv->coreclk); 1578 } 1579 1580 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1581 if (IS_ERR(spdif_priv->spbaclk)) 1582 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1583 1584 /* Select clock source for rx/tx clock */ 1585 spdif_priv->rxclk = spdif_priv->txclk[1]; 1586 if (IS_ERR(spdif_priv->rxclk)) { 1587 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1588 return PTR_ERR(spdif_priv->rxclk); 1589 } 1590 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1591 1592 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk, 1593 &spdif_priv->pll11k_clk); 1594 1595 /* Initial spinlock for control data */ 1596 ctrl = &spdif_priv->fsl_spdif_control; 1597 spin_lock_init(&ctrl->ctl_lock); 1598 1599 /* Init tx channel status default value */ 1600 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1601 IEC958_AES0_CON_EMPHASIS_5015; 1602 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1603 ctrl->ch_status[2] = 0x00; 1604 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1605 IEC958_AES3_CON_CLOCK_1000PPM; 1606 1607 spdif_priv->dpll_locked = false; 1608 1609 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; 1610 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; 1611 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1612 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1613 1614 /* Register with ASoC */ 1615 dev_set_drvdata(&pdev->dev, spdif_priv); 1616 pm_runtime_enable(&pdev->dev); 1617 regcache_cache_only(spdif_priv->regmap, true); 1618 1619 /* 1620 * Register platform component before registering cpu dai for there 1621 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1622 */ 1623 ret = imx_pcm_dma_init(pdev); 1624 if (ret) { 1625 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); 1626 goto err_pm_disable; 1627 } 1628 1629 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1630 &spdif_priv->cpu_dai_drv, 1); 1631 if (ret) { 1632 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1633 goto err_pm_disable; 1634 } 1635 1636 return ret; 1637 1638 err_pm_disable: 1639 pm_runtime_disable(&pdev->dev); 1640 return ret; 1641 } 1642 1643 static int fsl_spdif_remove(struct platform_device *pdev) 1644 { 1645 pm_runtime_disable(&pdev->dev); 1646 1647 return 0; 1648 } 1649 1650 #ifdef CONFIG_PM 1651 static int fsl_spdif_runtime_suspend(struct device *dev) 1652 { 1653 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1654 int i; 1655 1656 /* Disable all the interrupts */ 1657 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); 1658 1659 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1660 &spdif_priv->regcache_srpc); 1661 regcache_cache_only(spdif_priv->regmap, true); 1662 1663 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) 1664 clk_disable_unprepare(spdif_priv->txclk[i]); 1665 1666 if (!IS_ERR(spdif_priv->spbaclk)) 1667 clk_disable_unprepare(spdif_priv->spbaclk); 1668 clk_disable_unprepare(spdif_priv->coreclk); 1669 1670 return 0; 1671 } 1672 1673 static int fsl_spdif_runtime_resume(struct device *dev) 1674 { 1675 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1676 int ret; 1677 int i; 1678 1679 ret = clk_prepare_enable(spdif_priv->coreclk); 1680 if (ret) { 1681 dev_err(dev, "failed to enable core clock\n"); 1682 return ret; 1683 } 1684 1685 if (!IS_ERR(spdif_priv->spbaclk)) { 1686 ret = clk_prepare_enable(spdif_priv->spbaclk); 1687 if (ret) { 1688 dev_err(dev, "failed to enable spba clock\n"); 1689 goto disable_core_clk; 1690 } 1691 } 1692 1693 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1694 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1695 if (ret) 1696 goto disable_tx_clk; 1697 } 1698 1699 regcache_cache_only(spdif_priv->regmap, false); 1700 regcache_mark_dirty(spdif_priv->regmap); 1701 1702 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1703 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1704 spdif_priv->regcache_srpc); 1705 1706 ret = regcache_sync(spdif_priv->regmap); 1707 if (ret) 1708 goto disable_tx_clk; 1709 1710 return 0; 1711 1712 disable_tx_clk: 1713 for (i--; i >= 0; i--) 1714 clk_disable_unprepare(spdif_priv->txclk[i]); 1715 if (!IS_ERR(spdif_priv->spbaclk)) 1716 clk_disable_unprepare(spdif_priv->spbaclk); 1717 disable_core_clk: 1718 clk_disable_unprepare(spdif_priv->coreclk); 1719 1720 return ret; 1721 } 1722 #endif /* CONFIG_PM */ 1723 1724 static const struct dev_pm_ops fsl_spdif_pm = { 1725 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1726 pm_runtime_force_resume) 1727 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1728 NULL) 1729 }; 1730 1731 static const struct of_device_id fsl_spdif_dt_ids[] = { 1732 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1733 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1734 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1735 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, }, 1736 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, }, 1737 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, }, 1738 {} 1739 }; 1740 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1741 1742 static struct platform_driver fsl_spdif_driver = { 1743 .driver = { 1744 .name = "fsl-spdif-dai", 1745 .of_match_table = fsl_spdif_dt_ids, 1746 .pm = &fsl_spdif_pm, 1747 }, 1748 .probe = fsl_spdif_probe, 1749 .remove = fsl_spdif_remove, 1750 }; 1751 1752 module_platform_driver(fsl_spdif_driver); 1753 1754 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1755 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1756 MODULE_LICENSE("GPL v2"); 1757 MODULE_ALIAS("platform:fsl-spdif-dai"); 1758