xref: /linux/sound/soc/fsl/fsl_sai.h (revision b68fc09be48edbc47de1a0f3d42ef8adf6c0ac55) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2012-2013 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __FSL_SAI_H
7 #define __FSL_SAI_H
8 
9 #include <sound/dmaengine_pcm.h>
10 
11 #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
12 			 SNDRV_PCM_FMTBIT_S20_3LE |\
13 			 SNDRV_PCM_FMTBIT_S24_LE |\
14 			 SNDRV_PCM_FMTBIT_S32_LE)
15 
16 /* SAI Register Map Register */
17 #define FSL_SAI_TCSR	0x00 /* SAI Transmit Control */
18 #define FSL_SAI_TCR1	0x04 /* SAI Transmit Configuration 1 */
19 #define FSL_SAI_TCR2	0x08 /* SAI Transmit Configuration 2 */
20 #define FSL_SAI_TCR3	0x0c /* SAI Transmit Configuration 3 */
21 #define FSL_SAI_TCR4	0x10 /* SAI Transmit Configuration 4 */
22 #define FSL_SAI_TCR5	0x14 /* SAI Transmit Configuration 5 */
23 #define FSL_SAI_TDR	0x20 /* SAI Transmit Data */
24 #define FSL_SAI_TFR	0x40 /* SAI Transmit FIFO */
25 #define FSL_SAI_TMR	0x60 /* SAI Transmit Mask */
26 #define FSL_SAI_RCSR	0x80 /* SAI Receive Control */
27 #define FSL_SAI_RCR1	0x84 /* SAI Receive Configuration 1 */
28 #define FSL_SAI_RCR2	0x88 /* SAI Receive Configuration 2 */
29 #define FSL_SAI_RCR3	0x8c /* SAI Receive Configuration 3 */
30 #define FSL_SAI_RCR4	0x90 /* SAI Receive Configuration 4 */
31 #define FSL_SAI_RCR5	0x94 /* SAI Receive Configuration 5 */
32 #define FSL_SAI_RDR	0xa0 /* SAI Receive Data */
33 #define FSL_SAI_RFR	0xc0 /* SAI Receive FIFO */
34 #define FSL_SAI_RMR	0xe0 /* SAI Receive Mask */
35 
36 #define FSL_SAI_xCSR(tx)	(tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
37 #define FSL_SAI_xCR1(tx)	(tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1)
38 #define FSL_SAI_xCR2(tx)	(tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2)
39 #define FSL_SAI_xCR3(tx)	(tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3)
40 #define FSL_SAI_xCR4(tx)	(tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4)
41 #define FSL_SAI_xCR5(tx)	(tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5)
42 #define FSL_SAI_xDR(tx)		(tx ? FSL_SAI_TDR : FSL_SAI_RDR)
43 #define FSL_SAI_xFR(tx)		(tx ? FSL_SAI_TFR : FSL_SAI_RFR)
44 #define FSL_SAI_xMR(tx)		(tx ? FSL_SAI_TMR : FSL_SAI_RMR)
45 
46 /* SAI Transmit/Receive Control Register */
47 #define FSL_SAI_CSR_TERE	BIT(31)
48 #define FSL_SAI_CSR_FR		BIT(25)
49 #define FSL_SAI_CSR_SR		BIT(24)
50 #define FSL_SAI_CSR_xF_SHIFT	16
51 #define FSL_SAI_CSR_xF_W_SHIFT	18
52 #define FSL_SAI_CSR_xF_MASK	(0x1f << FSL_SAI_CSR_xF_SHIFT)
53 #define FSL_SAI_CSR_xF_W_MASK	(0x7 << FSL_SAI_CSR_xF_W_SHIFT)
54 #define FSL_SAI_CSR_WSF		BIT(20)
55 #define FSL_SAI_CSR_SEF		BIT(19)
56 #define FSL_SAI_CSR_FEF		BIT(18)
57 #define FSL_SAI_CSR_FWF		BIT(17)
58 #define FSL_SAI_CSR_FRF		BIT(16)
59 #define FSL_SAI_CSR_xIE_SHIFT	8
60 #define FSL_SAI_CSR_xIE_MASK	(0x1f << FSL_SAI_CSR_xIE_SHIFT)
61 #define FSL_SAI_CSR_WSIE	BIT(12)
62 #define FSL_SAI_CSR_SEIE	BIT(11)
63 #define FSL_SAI_CSR_FEIE	BIT(10)
64 #define FSL_SAI_CSR_FWIE	BIT(9)
65 #define FSL_SAI_CSR_FRIE	BIT(8)
66 #define FSL_SAI_CSR_FRDE	BIT(0)
67 
68 /* SAI Transmit and Receive Configuration 1 Register */
69 #define FSL_SAI_CR1_RFW_MASK	0x1f
70 
71 /* SAI Transmit and Receive Configuration 2 Register */
72 #define FSL_SAI_CR2_SYNC	BIT(30)
73 #define FSL_SAI_CR2_MSEL_MASK	(0x3 << 26)
74 #define FSL_SAI_CR2_MSEL_BUS	0
75 #define FSL_SAI_CR2_MSEL_MCLK1	BIT(26)
76 #define FSL_SAI_CR2_MSEL_MCLK2	BIT(27)
77 #define FSL_SAI_CR2_MSEL_MCLK3	(BIT(26) | BIT(27))
78 #define FSL_SAI_CR2_MSEL(ID)	((ID) << 26)
79 #define FSL_SAI_CR2_BCP		BIT(25)
80 #define FSL_SAI_CR2_BCD_MSTR	BIT(24)
81 #define FSL_SAI_CR2_DIV_MASK	0xff
82 
83 /* SAI Transmit and Receive Configuration 3 Register */
84 #define FSL_SAI_CR3_TRCE	BIT(16)
85 #define FSL_SAI_CR3_WDFL(x)	(x)
86 #define FSL_SAI_CR3_WDFL_MASK	0x1f
87 
88 /* SAI Transmit and Receive Configuration 4 Register */
89 #define FSL_SAI_CR4_FRSZ(x)	(((x) - 1) << 16)
90 #define FSL_SAI_CR4_FRSZ_MASK	(0x1f << 16)
91 #define FSL_SAI_CR4_SYWD(x)	(((x) - 1) << 8)
92 #define FSL_SAI_CR4_SYWD_MASK	(0x1f << 8)
93 #define FSL_SAI_CR4_MF		BIT(4)
94 #define FSL_SAI_CR4_FSE		BIT(3)
95 #define FSL_SAI_CR4_FSP		BIT(1)
96 #define FSL_SAI_CR4_FSD_MSTR	BIT(0)
97 
98 /* SAI Transmit and Receive Configuration 5 Register */
99 #define FSL_SAI_CR5_WNW(x)	(((x) - 1) << 24)
100 #define FSL_SAI_CR5_WNW_MASK	(0x1f << 24)
101 #define FSL_SAI_CR5_W0W(x)	(((x) - 1) << 16)
102 #define FSL_SAI_CR5_W0W_MASK	(0x1f << 16)
103 #define FSL_SAI_CR5_FBT(x)	((x) << 8)
104 #define FSL_SAI_CR5_FBT_MASK	(0x1f << 8)
105 
106 /* SAI type */
107 #define FSL_SAI_DMA		BIT(0)
108 #define FSL_SAI_USE_AC97	BIT(1)
109 #define FSL_SAI_NET		BIT(2)
110 #define FSL_SAI_TRA_SYN		BIT(3)
111 #define FSL_SAI_REC_SYN		BIT(4)
112 #define FSL_SAI_USE_I2S_SLAVE	BIT(5)
113 
114 #define FSL_FMT_TRANSMITTER	0
115 #define FSL_FMT_RECEIVER	1
116 
117 /* SAI clock sources */
118 #define FSL_SAI_CLK_BUS		0
119 #define FSL_SAI_CLK_MAST1	1
120 #define FSL_SAI_CLK_MAST2	2
121 #define FSL_SAI_CLK_MAST3	3
122 
123 #define FSL_SAI_MCLK_MAX	4
124 
125 /* SAI data transfer numbers per DMA request */
126 #define FSL_SAI_MAXBURST_TX 6
127 #define FSL_SAI_MAXBURST_RX 6
128 
129 struct fsl_sai {
130 	struct platform_device *pdev;
131 	struct regmap *regmap;
132 	struct clk *bus_clk;
133 	struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
134 
135 	bool is_slave_mode;
136 	bool is_lsb_first;
137 	bool is_dsp_mode;
138 	bool sai_on_imx;
139 	bool synchronous[2];
140 
141 	unsigned int mclk_id[2];
142 	unsigned int mclk_streams;
143 	unsigned int slots;
144 	unsigned int slot_width;
145 
146 	struct snd_dmaengine_dai_dma_data dma_params_rx;
147 	struct snd_dmaengine_dai_dma_data dma_params_tx;
148 };
149 
150 #define TX 1
151 #define RX 0
152 
153 #endif /* __FSL_SAI_H */
154