1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2012-2013 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __FSL_SAI_H 7 #define __FSL_SAI_H 8 9 #include <sound/dmaengine_pcm.h> 10 11 #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 12 SNDRV_PCM_FMTBIT_S20_3LE |\ 13 SNDRV_PCM_FMTBIT_S24_LE |\ 14 SNDRV_PCM_FMTBIT_S32_LE |\ 15 SNDRV_PCM_FMTBIT_DSD_U8 |\ 16 SNDRV_PCM_FMTBIT_DSD_U16_LE |\ 17 SNDRV_PCM_FMTBIT_DSD_U32_LE) 18 19 /* SAI Register Map Register */ 20 #define FSL_SAI_VERID 0x00 /* SAI Version ID Register */ 21 #define FSL_SAI_PARAM 0x04 /* SAI Parameter Register */ 22 #define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */ 23 #define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */ 24 #define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */ 25 #define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */ 26 #define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */ 27 #define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */ 28 #define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */ 29 #define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */ 30 #define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */ 31 #define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */ 32 #define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */ 33 #define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */ 34 #define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */ 35 #define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */ 36 #define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */ 37 #define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */ 38 #define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */ 39 #define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */ 40 #define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */ 41 #define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */ 42 #define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */ 43 #define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */ 44 #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ 45 #define FSL_SAI_TTCTL 0x70 /* SAI Transmit Timestamp Control Register */ 46 #define FSL_SAI_TTCTN 0x74 /* SAI Transmit Timestamp Counter Register */ 47 #define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */ 48 #define FSL_SAI_TTCAP 0x7C /* SAI Transmit Timestamp Capture */ 49 #define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */ 50 #define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */ 51 #define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */ 52 #define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */ 53 #define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */ 54 #define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */ 55 #define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */ 56 #define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */ 57 #define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */ 58 #define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */ 59 #define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */ 60 #define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */ 61 #define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */ 62 #define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */ 63 #define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */ 64 #define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */ 65 #define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */ 66 #define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */ 67 #define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */ 68 #define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */ 69 #define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */ 70 #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */ 71 #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */ 72 #define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */ 73 #define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */ 74 #define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */ 75 #define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */ 76 77 #define FSL_SAI_MCTL 0x100 /* SAI MCLK Control Register */ 78 #define FSL_SAI_MDIV 0x104 /* SAI MCLK Divide Register */ 79 80 #define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs)) 81 #define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs)) 82 #define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs)) 83 #define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs)) 84 #define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs)) 85 #define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs)) 86 #define FSL_SAI_xDR0(tx) (tx ? FSL_SAI_TDR0 : FSL_SAI_RDR0) 87 #define FSL_SAI_xFR0(tx) (tx ? FSL_SAI_TFR0 : FSL_SAI_RFR0) 88 #define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR) 89 90 /* SAI Transmit/Receive Control Register */ 91 #define FSL_SAI_CSR_TERE BIT(31) 92 #define FSL_SAI_CSR_SE BIT(30) 93 #define FSL_SAI_CSR_FR BIT(25) 94 #define FSL_SAI_CSR_SR BIT(24) 95 #define FSL_SAI_CSR_xF_SHIFT 16 96 #define FSL_SAI_CSR_xF_W_SHIFT 18 97 #define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT) 98 #define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT) 99 #define FSL_SAI_CSR_WSF BIT(20) 100 #define FSL_SAI_CSR_SEF BIT(19) 101 #define FSL_SAI_CSR_FEF BIT(18) 102 #define FSL_SAI_CSR_FWF BIT(17) 103 #define FSL_SAI_CSR_FRF BIT(16) 104 #define FSL_SAI_CSR_xIE_SHIFT 8 105 #define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT) 106 #define FSL_SAI_CSR_WSIE BIT(12) 107 #define FSL_SAI_CSR_SEIE BIT(11) 108 #define FSL_SAI_CSR_FEIE BIT(10) 109 #define FSL_SAI_CSR_FWIE BIT(9) 110 #define FSL_SAI_CSR_FRIE BIT(8) 111 #define FSL_SAI_CSR_FRDE BIT(0) 112 113 /* SAI Transmit and Receive Configuration 1 Register */ 114 #define FSL_SAI_CR1_RFW_MASK(x) ((x) - 1) 115 116 /* SAI Transmit and Receive Configuration 2 Register */ 117 #define FSL_SAI_CR2_SYNC BIT(30) 118 #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) 119 #define FSL_SAI_CR2_MSEL_BUS 0 120 #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) 121 #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27) 122 #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27)) 123 #define FSL_SAI_CR2_MSEL(ID) ((ID) << 26) 124 #define FSL_SAI_CR2_BCP BIT(25) 125 #define FSL_SAI_CR2_BCD_MSTR BIT(24) 126 #define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */ 127 #define FSL_SAI_CR2_DIV_MASK 0xff 128 129 /* SAI Transmit and Receive Configuration 3 Register */ 130 #define FSL_SAI_CR3_TRCE(x) ((x) << 16) 131 #define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16) 132 #define FSL_SAI_CR3_WDFL(x) (x) 133 #define FSL_SAI_CR3_WDFL_MASK 0x1f 134 135 /* SAI Transmit and Receive Configuration 4 Register */ 136 137 #define FSL_SAI_CR4_FCONT BIT(28) 138 #define FSL_SAI_CR4_FCOMB_SHIFT BIT(26) 139 #define FSL_SAI_CR4_FCOMB_SOFT BIT(27) 140 #define FSL_SAI_CR4_FCOMB_MASK (0x3 << 26) 141 #define FSL_SAI_CR4_FPACK_8 (0x2 << 24) 142 #define FSL_SAI_CR4_FPACK_16 (0x3 << 24) 143 #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) 144 #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) 145 #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) 146 #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8) 147 #define FSL_SAI_CR4_CHMOD BIT(5) 148 #define FSL_SAI_CR4_CHMOD_MASK BIT(5) 149 #define FSL_SAI_CR4_MF BIT(4) 150 #define FSL_SAI_CR4_FSE BIT(3) 151 #define FSL_SAI_CR4_FSP BIT(1) 152 #define FSL_SAI_CR4_FSD_MSTR BIT(0) 153 154 /* SAI Transmit and Receive Configuration 5 Register */ 155 #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) 156 #define FSL_SAI_CR5_WNW_MASK (0x1f << 24) 157 #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) 158 #define FSL_SAI_CR5_W0W_MASK (0x1f << 16) 159 #define FSL_SAI_CR5_FBT(x) ((x) << 8) 160 #define FSL_SAI_CR5_FBT_MASK (0x1f << 8) 161 162 /* SAI MCLK Control Register */ 163 #define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */ 164 #define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24) 165 #define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24) 166 #define FSL_SAI_MCTL_MSEL_BUS 0 167 #define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24) 168 #define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25) 169 #define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25)) 170 #define FSL_SAI_MCTL_DIV_EN BIT(23) 171 #define FSL_SAI_MCTL_DIV_MASK 0xFF 172 173 /* SAI VERID Register */ 174 #define FSL_SAI_VERID_MAJOR_SHIFT 24 175 #define FSL_SAI_VERID_MAJOR_MASK GENMASK(31, 24) 176 #define FSL_SAI_VERID_MINOR_SHIFT 16 177 #define FSL_SAI_VERID_MINOR_MASK GENMASK(23, 16) 178 #define FSL_SAI_VERID_FEATURE_SHIFT 0 179 #define FSL_SAI_VERID_FEATURE_MASK GENMASK(15, 0) 180 #define FSL_SAI_VERID_EFIFO_EN BIT(0) 181 #define FSL_SAI_VERID_TSTMP_EN BIT(1) 182 183 /* SAI PARAM Register */ 184 #define FSL_SAI_PARAM_SPF_SHIFT 16 185 #define FSL_SAI_PARAM_SPF_MASK GENMASK(19, 16) 186 #define FSL_SAI_PARAM_WPF_SHIFT 8 187 #define FSL_SAI_PARAM_WPF_MASK GENMASK(11, 8) 188 #define FSL_SAI_PARAM_DLN_MASK GENMASK(3, 0) 189 190 /* SAI MCLK Divide Register */ 191 #define FSL_SAI_MDIV_MASK 0xFFFFF 192 193 /* SAI timestamp and bitcounter */ 194 #define FSL_SAI_xTCTL_TSEN BIT(0) 195 #define FSL_SAI_xTCTL_TSINC BIT(1) 196 #define FSL_SAI_xTCTL_RTSC BIT(8) 197 #define FSL_SAI_xTCTL_RBC BIT(9) 198 199 /* SAI type */ 200 #define FSL_SAI_DMA BIT(0) 201 #define FSL_SAI_USE_AC97 BIT(1) 202 #define FSL_SAI_NET BIT(2) 203 #define FSL_SAI_TRA_SYN BIT(3) 204 #define FSL_SAI_REC_SYN BIT(4) 205 #define FSL_SAI_USE_I2S_SLAVE BIT(5) 206 207 /* SAI clock sources */ 208 #define FSL_SAI_CLK_BUS 0 209 #define FSL_SAI_CLK_MAST1 1 210 #define FSL_SAI_CLK_MAST2 2 211 #define FSL_SAI_CLK_MAST3 3 212 213 #define FSL_SAI_MCLK_MAX 4 214 215 /* SAI data transfer numbers per DMA request */ 216 #define FSL_SAI_MAXBURST_TX 6 217 #define FSL_SAI_MAXBURST_RX 6 218 219 #define PMQOS_CPU_LATENCY BIT(0) 220 221 /* Max number of dataline */ 222 #define FSL_SAI_DL_NUM (8) 223 /* default dataline type is zero */ 224 #define FSL_SAI_DL_DEFAULT (0) 225 #define FSL_SAI_DL_I2S BIT(0) 226 #define FSL_SAI_DL_PDM BIT(1) 227 228 struct fsl_sai_soc_data { 229 bool use_imx_pcm; 230 bool use_edma; 231 bool mclk0_is_mclk1; 232 unsigned int fifo_depth; 233 unsigned int pins; 234 unsigned int reg_offset; 235 unsigned int flags; 236 unsigned int max_register; 237 }; 238 239 /** 240 * struct fsl_sai_verid - version id data 241 * @version: version number 242 * @feature: feature specification number 243 * 0000000000000000b - Standard feature set 244 * 0000000000000000b - Standard feature set 245 */ 246 struct fsl_sai_verid { 247 u32 version; 248 u32 feature; 249 }; 250 251 /** 252 * struct fsl_sai_param - parameter data 253 * @slot_num: The maximum number of slots per frame 254 * @fifo_depth: The number of words in each FIFO (depth) 255 * @dataline: The number of datalines implemented 256 */ 257 struct fsl_sai_param { 258 u32 slot_num; 259 u32 fifo_depth; 260 u32 dataline; 261 }; 262 263 struct fsl_sai_dl_cfg { 264 unsigned int type; 265 unsigned int pins[2]; 266 unsigned int mask[2]; 267 unsigned int start_off[2]; 268 unsigned int next_off[2]; 269 }; 270 271 struct fsl_sai { 272 struct platform_device *pdev; 273 struct regmap *regmap; 274 struct clk *bus_clk; 275 struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; 276 struct clk *pll8k_clk; 277 struct clk *pll11k_clk; 278 struct resource *res; 279 280 bool is_consumer_mode; 281 bool is_lsb_first; 282 bool is_dsp_mode; 283 bool is_pdm_mode; 284 bool synchronous[2]; 285 struct fsl_sai_dl_cfg *dl_cfg; 286 unsigned int dl_cfg_cnt; 287 288 unsigned int mclk_id[2]; 289 unsigned int mclk_streams; 290 unsigned int slots; 291 unsigned int slot_width; 292 unsigned int bclk_ratio; 293 294 const struct fsl_sai_soc_data *soc_data; 295 struct snd_soc_dai_driver cpu_dai_drv; 296 struct snd_dmaengine_dai_dma_data dma_params_rx; 297 struct snd_dmaengine_dai_dma_data dma_params_tx; 298 struct fsl_sai_verid verid; 299 struct fsl_sai_param param; 300 struct pm_qos_request pm_qos_req; 301 struct pinctrl *pinctrl; 302 struct pinctrl_state *pins_state; 303 }; 304 305 #define TX 1 306 #define RX 0 307 308 #endif /* __FSL_SAI_H */ 309