1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/pm_qos.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/time.h> 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 23 24 #include "fsl_sai.h" 25 #include "fsl_utils.h" 26 #include "imx-pcm.h" 27 28 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 29 FSL_SAI_CSR_FEIE) 30 31 static const unsigned int fsl_sai_rates[] = { 32 8000, 11025, 12000, 16000, 22050, 33 24000, 32000, 44100, 48000, 64000, 34 88200, 96000, 176400, 192000, 352800, 35 384000, 705600, 768000, 1411200, 2822400, 36 }; 37 38 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 39 .count = ARRAY_SIZE(fsl_sai_rates), 40 .list = fsl_sai_rates, 41 }; 42 43 /** 44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 45 * 46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 47 * or Receiver's for both streams. This function is used to check if clocks of 48 * the stream's are synced by the opposite stream. 49 * 50 * @sai: SAI context 51 * @dir: stream direction 52 */ 53 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 54 { 55 int adir = (dir == TX) ? RX : TX; 56 57 /* current dir in async mode while opposite dir in sync mode */ 58 return !sai->synchronous[dir] && sai->synchronous[adir]; 59 } 60 61 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 62 { 63 struct pinctrl_state *state = NULL; 64 65 if (sai->is_pdm_mode) { 66 /* DSD512@44.1kHz, DSD512@48kHz */ 67 if (bclk >= 22579200) 68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 69 70 /* Get default DSD state */ 71 if (IS_ERR_OR_NULL(state)) 72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 73 } else { 74 /* 706k32b2c, 768k32b2c, etc */ 75 if (bclk >= 45158400) 76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 77 } 78 79 /* Get default state */ 80 if (IS_ERR_OR_NULL(state)) 81 state = pinctrl_lookup_state(sai->pinctrl, "default"); 82 83 return state; 84 } 85 86 static irqreturn_t fsl_sai_isr(int irq, void *devid) 87 { 88 struct fsl_sai *sai = (struct fsl_sai *)devid; 89 unsigned int ofs = sai->soc_data->reg_offset; 90 struct device *dev = &sai->pdev->dev; 91 u32 flags, xcsr, mask; 92 irqreturn_t iret = IRQ_NONE; 93 94 /* 95 * Both IRQ status bits and IRQ mask bits are in the xCSR but 96 * different shifts. And we here create a mask only for those 97 * IRQs that we activated. 98 */ 99 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 100 101 /* Tx IRQ */ 102 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 103 flags = xcsr & mask; 104 105 if (flags) 106 iret = IRQ_HANDLED; 107 else 108 goto irq_rx; 109 110 if (flags & FSL_SAI_CSR_WSF) 111 dev_dbg(dev, "isr: Start of Tx word detected\n"); 112 113 if (flags & FSL_SAI_CSR_SEF) 114 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 115 116 if (flags & FSL_SAI_CSR_FEF) 117 dev_dbg(dev, "isr: Transmit underrun detected\n"); 118 119 if (flags & FSL_SAI_CSR_FWF) 120 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 121 122 if (flags & FSL_SAI_CSR_FRF) 123 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 124 125 flags &= FSL_SAI_CSR_xF_W_MASK; 126 xcsr &= ~FSL_SAI_CSR_xF_MASK; 127 128 if (flags) 129 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 130 131 irq_rx: 132 /* Rx IRQ */ 133 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 134 flags = xcsr & mask; 135 136 if (flags) 137 iret = IRQ_HANDLED; 138 else 139 goto out; 140 141 if (flags & FSL_SAI_CSR_WSF) 142 dev_dbg(dev, "isr: Start of Rx word detected\n"); 143 144 if (flags & FSL_SAI_CSR_SEF) 145 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 146 147 if (flags & FSL_SAI_CSR_FEF) 148 dev_dbg(dev, "isr: Receive overflow detected\n"); 149 150 if (flags & FSL_SAI_CSR_FWF) 151 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 152 153 if (flags & FSL_SAI_CSR_FRF) 154 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 155 156 flags &= FSL_SAI_CSR_xF_W_MASK; 157 xcsr &= ~FSL_SAI_CSR_xF_MASK; 158 159 if (flags) 160 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 161 162 out: 163 return iret; 164 } 165 166 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 167 u32 rx_mask, int slots, int slot_width) 168 { 169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 170 171 sai->slots = slots; 172 sai->slot_width = slot_width; 173 174 return 0; 175 } 176 177 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 178 unsigned int ratio) 179 { 180 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 181 182 sai->bclk_ratio = ratio; 183 184 return 0; 185 } 186 187 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 188 int clk_id, unsigned int freq, bool tx) 189 { 190 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 191 unsigned int ofs = sai->soc_data->reg_offset; 192 u32 val_cr2 = 0; 193 194 switch (clk_id) { 195 case FSL_SAI_CLK_BUS: 196 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 197 break; 198 case FSL_SAI_CLK_MAST1: 199 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 200 break; 201 case FSL_SAI_CLK_MAST2: 202 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 203 break; 204 case FSL_SAI_CLK_MAST3: 205 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 206 break; 207 default: 208 return -EINVAL; 209 } 210 211 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 212 FSL_SAI_CR2_MSEL_MASK, val_cr2); 213 214 return 0; 215 } 216 217 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 218 { 219 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 220 int ret; 221 222 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 223 sai->pll8k_clk, sai->pll11k_clk, freq); 224 225 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 226 if (ret < 0) 227 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 228 229 return ret; 230 } 231 232 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 233 int clk_id, unsigned int freq, int dir) 234 { 235 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 236 int ret; 237 238 if (dir == SND_SOC_CLOCK_IN) 239 return 0; 240 241 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 242 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 243 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 244 return -EINVAL; 245 } 246 247 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 248 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 249 return -EINVAL; 250 } 251 252 if (sai->mclk_streams == 0) { 253 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 254 if (ret < 0) 255 return ret; 256 } 257 } 258 259 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 260 if (ret) { 261 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 262 return ret; 263 } 264 265 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 266 if (ret) 267 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 268 269 return ret; 270 } 271 272 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 273 unsigned int fmt, bool tx) 274 { 275 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 276 unsigned int ofs = sai->soc_data->reg_offset; 277 u32 val_cr2 = 0, val_cr4 = 0; 278 279 if (!sai->is_lsb_first) 280 val_cr4 |= FSL_SAI_CR4_MF; 281 282 sai->is_pdm_mode = false; 283 sai->is_dsp_mode = false; 284 /* DAI mode */ 285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 286 case SND_SOC_DAIFMT_I2S: 287 /* 288 * Frame low, 1clk before data, one word length for frame sync, 289 * frame sync starts one serial clock cycle earlier, 290 * that is, together with the last bit of the previous 291 * data word. 292 */ 293 val_cr2 |= FSL_SAI_CR2_BCP; 294 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 295 break; 296 case SND_SOC_DAIFMT_LEFT_J: 297 /* 298 * Frame high, one word length for frame sync, 299 * frame sync asserts with the first bit of the frame. 300 */ 301 val_cr2 |= FSL_SAI_CR2_BCP; 302 break; 303 case SND_SOC_DAIFMT_DSP_A: 304 /* 305 * Frame high, 1clk before data, one bit for frame sync, 306 * frame sync starts one serial clock cycle earlier, 307 * that is, together with the last bit of the previous 308 * data word. 309 */ 310 val_cr2 |= FSL_SAI_CR2_BCP; 311 val_cr4 |= FSL_SAI_CR4_FSE; 312 sai->is_dsp_mode = true; 313 break; 314 case SND_SOC_DAIFMT_DSP_B: 315 /* 316 * Frame high, one bit for frame sync, 317 * frame sync asserts with the first bit of the frame. 318 */ 319 val_cr2 |= FSL_SAI_CR2_BCP; 320 sai->is_dsp_mode = true; 321 break; 322 case SND_SOC_DAIFMT_PDM: 323 val_cr2 |= FSL_SAI_CR2_BCP; 324 val_cr4 &= ~FSL_SAI_CR4_MF; 325 sai->is_pdm_mode = true; 326 break; 327 case SND_SOC_DAIFMT_RIGHT_J: 328 /* To be done */ 329 default: 330 return -EINVAL; 331 } 332 333 /* DAI clock inversion */ 334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 335 case SND_SOC_DAIFMT_IB_IF: 336 /* Invert both clocks */ 337 val_cr2 ^= FSL_SAI_CR2_BCP; 338 val_cr4 ^= FSL_SAI_CR4_FSP; 339 break; 340 case SND_SOC_DAIFMT_IB_NF: 341 /* Invert bit clock */ 342 val_cr2 ^= FSL_SAI_CR2_BCP; 343 break; 344 case SND_SOC_DAIFMT_NB_IF: 345 /* Invert frame clock */ 346 val_cr4 ^= FSL_SAI_CR4_FSP; 347 break; 348 case SND_SOC_DAIFMT_NB_NF: 349 /* Nothing to do for both normal cases */ 350 break; 351 default: 352 return -EINVAL; 353 } 354 355 /* DAI clock provider masks */ 356 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 357 case SND_SOC_DAIFMT_BP_FP: 358 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 359 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 360 sai->is_consumer_mode = false; 361 break; 362 case SND_SOC_DAIFMT_BC_FC: 363 sai->is_consumer_mode = true; 364 break; 365 case SND_SOC_DAIFMT_BP_FC: 366 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 367 sai->is_consumer_mode = false; 368 break; 369 case SND_SOC_DAIFMT_BC_FP: 370 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 371 sai->is_consumer_mode = true; 372 break; 373 default: 374 return -EINVAL; 375 } 376 377 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 378 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 379 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 380 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 381 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 382 383 return 0; 384 } 385 386 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 387 { 388 int ret; 389 390 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 391 if (ret) { 392 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 393 return ret; 394 } 395 396 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 397 if (ret) 398 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 399 400 return ret; 401 } 402 403 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 404 { 405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 406 unsigned int reg, ofs = sai->soc_data->reg_offset; 407 unsigned long clk_rate; 408 u32 savediv = 0, ratio, bestdiff = freq; 409 int adir = tx ? RX : TX; 410 int dir = tx ? TX : RX; 411 u32 id; 412 bool support_1_1_ratio = sai->verid.version >= 0x0301; 413 414 /* Don't apply to consumer mode */ 415 if (sai->is_consumer_mode) 416 return 0; 417 418 /* 419 * There is no point in polling MCLK0 if it is identical to MCLK1. 420 * And given that MQS use case has to use MCLK1 though two clocks 421 * are the same, we simply skip MCLK0 and start to find from MCLK1. 422 */ 423 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 424 425 for (; id < FSL_SAI_MCLK_MAX; id++) { 426 int diff; 427 428 clk_rate = clk_get_rate(sai->mclk_clk[id]); 429 if (!clk_rate) 430 continue; 431 432 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 433 if (!ratio || ratio > 512) 434 continue; 435 if (ratio == 1 && !support_1_1_ratio) 436 continue; 437 if ((ratio & 1) && ratio > 1) 438 continue; 439 440 diff = abs((long)clk_rate - ratio * freq); 441 442 /* 443 * Drop the source that can not be 444 * divided into the required rate. 445 */ 446 if (diff != 0 && clk_rate / diff < 1000) 447 continue; 448 449 dev_dbg(dai->dev, 450 "ratio %d for freq %dHz based on clock %ldHz\n", 451 ratio, freq, clk_rate); 452 453 454 if (diff < bestdiff) { 455 savediv = ratio; 456 sai->mclk_id[tx] = id; 457 bestdiff = diff; 458 } 459 460 if (diff == 0) 461 break; 462 } 463 464 if (savediv == 0) { 465 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 466 tx ? 'T' : 'R', freq); 467 return -EINVAL; 468 } 469 470 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 471 sai->mclk_id[tx], savediv, bestdiff); 472 473 /* 474 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 475 * set TCR2 register for playback. 476 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 477 * and capture. 478 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 479 * and capture. 480 * 4) For Tx and Rx are both Synchronous with another SAI, we just 481 * ignore it. 482 */ 483 if (fsl_sai_dir_is_synced(sai, adir)) 484 reg = FSL_SAI_xCR2(!tx, ofs); 485 else if (!sai->synchronous[dir]) 486 reg = FSL_SAI_xCR2(tx, ofs); 487 else 488 return 0; 489 490 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 491 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 492 493 if (savediv == 1) { 494 regmap_update_bits(sai->regmap, reg, 495 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 496 FSL_SAI_CR2_BYP); 497 if (fsl_sai_dir_is_synced(sai, adir)) 498 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 499 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 500 else 501 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 502 FSL_SAI_CR2_BCI, 0); 503 } else { 504 regmap_update_bits(sai->regmap, reg, 505 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 506 savediv / 2 - 1); 507 } 508 509 return 0; 510 } 511 512 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 513 struct snd_pcm_hw_params *params, 514 struct snd_soc_dai *cpu_dai) 515 { 516 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 517 unsigned int ofs = sai->soc_data->reg_offset; 518 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 519 unsigned int channels = params_channels(params); 520 struct snd_dmaengine_dai_dma_data *dma_params; 521 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 522 u32 word_width = params_width(params); 523 int trce_mask = 0, dl_cfg_idx = 0; 524 int dl_cfg_cnt = sai->dl_cfg_cnt; 525 u32 dl_type = FSL_SAI_DL_I2S; 526 u32 val_cr4 = 0, val_cr5 = 0; 527 u32 slots = (channels == 1) ? 2 : channels; 528 u32 slot_width = word_width; 529 int adir = tx ? RX : TX; 530 u32 pins, bclk; 531 u32 watermark; 532 int ret, i; 533 534 if (sai->slot_width) 535 slot_width = sai->slot_width; 536 537 if (sai->slots) 538 slots = sai->slots; 539 else if (sai->bclk_ratio) 540 slots = sai->bclk_ratio / slot_width; 541 542 pins = DIV_ROUND_UP(channels, slots); 543 544 /* 545 * PDM mode, channels are independent 546 * each channels are on one dataline/FIFO. 547 */ 548 if (sai->is_pdm_mode) { 549 pins = channels; 550 dl_type = FSL_SAI_DL_PDM; 551 } 552 553 for (i = 0; i < dl_cfg_cnt; i++) { 554 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 555 dl_cfg_idx = i; 556 break; 557 } 558 } 559 560 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 561 dev_err(cpu_dai->dev, "channel not supported\n"); 562 return -EINVAL; 563 } 564 565 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 566 567 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 568 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 569 if (!IS_ERR_OR_NULL(sai->pins_state)) { 570 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 571 if (ret) { 572 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 573 return ret; 574 } 575 } 576 } 577 578 if (!sai->is_consumer_mode) { 579 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 580 if (ret) 581 return ret; 582 583 /* Do not enable the clock if it is already enabled */ 584 if (!(sai->mclk_streams & BIT(substream->stream))) { 585 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 586 if (ret) 587 return ret; 588 589 sai->mclk_streams |= BIT(substream->stream); 590 } 591 } 592 593 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 594 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 595 596 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 597 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 598 599 if (sai->is_lsb_first || sai->is_pdm_mode) 600 val_cr5 |= FSL_SAI_CR5_FBT(0); 601 else 602 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 603 604 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 605 606 /* Set to output mode to avoid tri-stated data pins */ 607 if (tx) 608 val_cr4 |= FSL_SAI_CR4_CHMOD; 609 610 /* 611 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 612 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 613 * RCR5(TCR5) for playback(capture), or there will be sync error. 614 */ 615 616 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 617 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 618 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 619 FSL_SAI_CR4_CHMOD_MASK, 620 val_cr4); 621 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 622 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 623 FSL_SAI_CR5_FBT_MASK, val_cr5); 624 } 625 626 /* 627 * Combine mode has limation: 628 * - Can't used for singel dataline/FIFO case except the FIFO0 629 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 630 * are successive and start from FIFO0 631 * 632 * So for common usage, all multi fifo case disable the combine mode. 633 */ 634 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 635 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 636 FSL_SAI_CR4_FCOMB_MASK, 0); 637 else 638 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 639 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 640 641 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 642 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 643 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 644 645 if (sai->is_multi_fifo_dma) { 646 sai->audio_config[tx].words_per_fifo = min(slots, channels); 647 if (tx) { 648 sai->audio_config[tx].n_fifos_dst = pins; 649 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 650 } else { 651 sai->audio_config[tx].n_fifos_src = pins; 652 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 653 } 654 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 655 dma_params->peripheral_config = &sai->audio_config[tx]; 656 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 657 658 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 659 (dma_params->maxburst - 1); 660 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 661 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 662 watermark); 663 } 664 665 /* Find a proper tcre setting */ 666 for (i = 0; i < sai->soc_data->pins; i++) { 667 trce_mask = (1 << (i + 1)) - 1; 668 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 669 break; 670 } 671 672 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 673 FSL_SAI_CR3_TRCE_MASK, 674 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 675 676 /* 677 * When the TERE and FSD_MSTR enabled before configuring the word width 678 * There will be no frame sync clock issue, because word width impact 679 * the generation of frame sync clock. 680 * 681 * TERE enabled earlier only for i.MX8MP case for the hardware limitation, 682 * We need to disable FSD_MSTR before configuring word width, then enable 683 * FSD_MSTR bit for this specific case. 684 */ 685 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 686 !sai->is_consumer_mode) 687 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 688 FSL_SAI_CR4_FSD_MSTR, 0); 689 690 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 691 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 692 FSL_SAI_CR4_CHMOD_MASK, 693 val_cr4); 694 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 695 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 696 FSL_SAI_CR5_FBT_MASK, val_cr5); 697 698 /* Enable FSD_MSTR after configuring word width */ 699 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 700 !sai->is_consumer_mode) 701 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 702 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR); 703 704 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 705 ~0UL - ((1 << min(channels, slots)) - 1)); 706 707 return 0; 708 } 709 710 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 711 struct snd_soc_dai *cpu_dai) 712 { 713 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 714 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 715 unsigned int ofs = sai->soc_data->reg_offset; 716 717 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 718 FSL_SAI_CR3_TRCE_MASK, 0); 719 720 if (!sai->is_consumer_mode && 721 sai->mclk_streams & BIT(substream->stream)) { 722 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 723 sai->mclk_streams &= ~BIT(substream->stream); 724 } 725 726 return 0; 727 } 728 729 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 730 { 731 unsigned int ofs = sai->soc_data->reg_offset; 732 bool tx = dir == TX; 733 u32 xcsr, count = 100, mask; 734 735 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 736 mask = FSL_SAI_CSR_TERE; 737 else 738 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 739 740 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 741 mask, 0); 742 743 /* TERE will remain set till the end of current frame */ 744 do { 745 udelay(10); 746 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 747 } while (--count && xcsr & FSL_SAI_CSR_TERE); 748 749 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 750 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 751 752 /* 753 * For sai master mode, after several open/close sai, 754 * there will be no frame clock, and can't recover 755 * anymore. Add software reset to fix this issue. 756 * This is a hardware bug, and will be fix in the 757 * next sai version. 758 */ 759 if (!sai->is_consumer_mode) { 760 /* Software Reset */ 761 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 762 /* Clear SR bit to finish the reset */ 763 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 764 } 765 } 766 767 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 768 struct snd_soc_dai *cpu_dai) 769 { 770 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 771 unsigned int ofs = sai->soc_data->reg_offset; 772 773 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 774 int adir = tx ? RX : TX; 775 int dir = tx ? TX : RX; 776 u32 xcsr; 777 778 /* 779 * Asynchronous mode: Clear SYNC for both Tx and Rx. 780 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 781 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 782 */ 783 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 784 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 785 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 786 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 787 788 /* 789 * It is recommended that the transmitter is the last enabled 790 * and the first disabled. 791 */ 792 switch (cmd) { 793 case SNDRV_PCM_TRIGGER_START: 794 case SNDRV_PCM_TRIGGER_RESUME: 795 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 796 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 797 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 798 799 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 800 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 801 /* 802 * Enable the opposite direction for synchronous mode 803 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 804 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 805 * 806 * RM recommends to enable RE after TE for case 1 and to enable 807 * TE after RE for case 2, but we here may not always guarantee 808 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 809 * TE after RE, which is against what RM recommends but should 810 * be safe to do, judging by years of testing results. 811 */ 812 if (fsl_sai_dir_is_synced(sai, adir)) 813 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 814 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 815 816 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 817 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 818 break; 819 case SNDRV_PCM_TRIGGER_STOP: 820 case SNDRV_PCM_TRIGGER_SUSPEND: 821 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 822 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 823 FSL_SAI_CSR_FRDE, 0); 824 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 825 FSL_SAI_CSR_xIE_MASK, 0); 826 827 /* Check if the opposite FRDE is also disabled */ 828 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 829 830 /* 831 * If opposite stream provides clocks for synchronous mode and 832 * it is inactive, disable it before disabling the current one 833 */ 834 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 835 fsl_sai_config_disable(sai, adir); 836 837 /* 838 * Disable current stream if either of: 839 * 1. current stream doesn't provide clocks for synchronous mode 840 * 2. current stream provides clocks for synchronous mode but no 841 * more stream is active. 842 */ 843 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 844 fsl_sai_config_disable(sai, dir); 845 846 break; 847 default: 848 return -EINVAL; 849 } 850 851 return 0; 852 } 853 854 static int fsl_sai_startup(struct snd_pcm_substream *substream, 855 struct snd_soc_dai *cpu_dai) 856 { 857 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 858 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 859 int ret; 860 861 /* 862 * EDMA controller needs period size to be a multiple of 863 * tx/rx maxburst 864 */ 865 if (sai->soc_data->use_edma) 866 snd_pcm_hw_constraint_step(substream->runtime, 0, 867 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 868 tx ? sai->dma_params_tx.maxburst : 869 sai->dma_params_rx.maxburst); 870 871 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 872 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 873 874 return ret; 875 } 876 877 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 878 { 879 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 880 unsigned int ofs = sai->soc_data->reg_offset; 881 882 /* Software Reset for both Tx and Rx */ 883 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 884 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 885 /* Clear SR bit to finish the reset */ 886 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 887 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 888 889 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 890 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 891 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 892 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 893 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 894 sai->dma_params_rx.maxburst - 1); 895 896 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 897 &sai->dma_params_rx); 898 899 return 0; 900 } 901 902 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 903 .probe = fsl_sai_dai_probe, 904 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 905 .set_sysclk = fsl_sai_set_dai_sysclk, 906 .set_fmt = fsl_sai_set_dai_fmt, 907 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 908 .hw_params = fsl_sai_hw_params, 909 .hw_free = fsl_sai_hw_free, 910 .trigger = fsl_sai_trigger, 911 .startup = fsl_sai_startup, 912 }; 913 914 static int fsl_sai_dai_resume(struct snd_soc_component *component) 915 { 916 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 917 struct device *dev = &sai->pdev->dev; 918 int ret; 919 920 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 921 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 922 if (ret) { 923 dev_err(dev, "failed to set proper pins state: %d\n", ret); 924 return ret; 925 } 926 } 927 928 return 0; 929 } 930 931 static struct snd_soc_dai_driver fsl_sai_dai_template = { 932 .playback = { 933 .stream_name = "CPU-Playback", 934 .channels_min = 1, 935 .channels_max = 32, 936 .rate_min = 8000, 937 .rate_max = 2822400, 938 .rates = SNDRV_PCM_RATE_KNOT, 939 .formats = FSL_SAI_FORMATS, 940 }, 941 .capture = { 942 .stream_name = "CPU-Capture", 943 .channels_min = 1, 944 .channels_max = 32, 945 .rate_min = 8000, 946 .rate_max = 2822400, 947 .rates = SNDRV_PCM_RATE_KNOT, 948 .formats = FSL_SAI_FORMATS, 949 }, 950 .ops = &fsl_sai_pcm_dai_ops, 951 }; 952 953 static const struct snd_soc_component_driver fsl_component = { 954 .name = "fsl-sai", 955 .resume = fsl_sai_dai_resume, 956 .legacy_dai_naming = 1, 957 }; 958 959 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 960 {FSL_SAI_TCR1(0), 0}, 961 {FSL_SAI_TCR2(0), 0}, 962 {FSL_SAI_TCR3(0), 0}, 963 {FSL_SAI_TCR4(0), 0}, 964 {FSL_SAI_TCR5(0), 0}, 965 {FSL_SAI_TDR0, 0}, 966 {FSL_SAI_TDR1, 0}, 967 {FSL_SAI_TDR2, 0}, 968 {FSL_SAI_TDR3, 0}, 969 {FSL_SAI_TDR4, 0}, 970 {FSL_SAI_TDR5, 0}, 971 {FSL_SAI_TDR6, 0}, 972 {FSL_SAI_TDR7, 0}, 973 {FSL_SAI_TMR, 0}, 974 {FSL_SAI_RCR1(0), 0}, 975 {FSL_SAI_RCR2(0), 0}, 976 {FSL_SAI_RCR3(0), 0}, 977 {FSL_SAI_RCR4(0), 0}, 978 {FSL_SAI_RCR5(0), 0}, 979 {FSL_SAI_RMR, 0}, 980 }; 981 982 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 983 {FSL_SAI_TCR1(8), 0}, 984 {FSL_SAI_TCR2(8), 0}, 985 {FSL_SAI_TCR3(8), 0}, 986 {FSL_SAI_TCR4(8), 0}, 987 {FSL_SAI_TCR5(8), 0}, 988 {FSL_SAI_TDR0, 0}, 989 {FSL_SAI_TDR1, 0}, 990 {FSL_SAI_TDR2, 0}, 991 {FSL_SAI_TDR3, 0}, 992 {FSL_SAI_TDR4, 0}, 993 {FSL_SAI_TDR5, 0}, 994 {FSL_SAI_TDR6, 0}, 995 {FSL_SAI_TDR7, 0}, 996 {FSL_SAI_TMR, 0}, 997 {FSL_SAI_RCR1(8), 0}, 998 {FSL_SAI_RCR2(8), 0}, 999 {FSL_SAI_RCR3(8), 0}, 1000 {FSL_SAI_RCR4(8), 0}, 1001 {FSL_SAI_RCR5(8), 0}, 1002 {FSL_SAI_RMR, 0}, 1003 {FSL_SAI_MCTL, 0}, 1004 {FSL_SAI_MDIV, 0}, 1005 }; 1006 1007 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 1008 { 1009 struct fsl_sai *sai = dev_get_drvdata(dev); 1010 unsigned int ofs = sai->soc_data->reg_offset; 1011 1012 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1013 return true; 1014 1015 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1016 return true; 1017 1018 switch (reg) { 1019 case FSL_SAI_TFR0: 1020 case FSL_SAI_TFR1: 1021 case FSL_SAI_TFR2: 1022 case FSL_SAI_TFR3: 1023 case FSL_SAI_TFR4: 1024 case FSL_SAI_TFR5: 1025 case FSL_SAI_TFR6: 1026 case FSL_SAI_TFR7: 1027 case FSL_SAI_TMR: 1028 case FSL_SAI_RDR0: 1029 case FSL_SAI_RDR1: 1030 case FSL_SAI_RDR2: 1031 case FSL_SAI_RDR3: 1032 case FSL_SAI_RDR4: 1033 case FSL_SAI_RDR5: 1034 case FSL_SAI_RDR6: 1035 case FSL_SAI_RDR7: 1036 case FSL_SAI_RFR0: 1037 case FSL_SAI_RFR1: 1038 case FSL_SAI_RFR2: 1039 case FSL_SAI_RFR3: 1040 case FSL_SAI_RFR4: 1041 case FSL_SAI_RFR5: 1042 case FSL_SAI_RFR6: 1043 case FSL_SAI_RFR7: 1044 case FSL_SAI_RMR: 1045 case FSL_SAI_MCTL: 1046 case FSL_SAI_MDIV: 1047 case FSL_SAI_VERID: 1048 case FSL_SAI_PARAM: 1049 case FSL_SAI_TTCTN: 1050 case FSL_SAI_RTCTN: 1051 case FSL_SAI_TTCTL: 1052 case FSL_SAI_TBCTN: 1053 case FSL_SAI_TTCAP: 1054 case FSL_SAI_RTCTL: 1055 case FSL_SAI_RBCTN: 1056 case FSL_SAI_RTCAP: 1057 return true; 1058 default: 1059 return false; 1060 } 1061 } 1062 1063 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1064 { 1065 struct fsl_sai *sai = dev_get_drvdata(dev); 1066 unsigned int ofs = sai->soc_data->reg_offset; 1067 1068 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1069 return true; 1070 1071 /* Set VERID and PARAM be volatile for reading value in probe */ 1072 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1073 return true; 1074 1075 switch (reg) { 1076 case FSL_SAI_TFR0: 1077 case FSL_SAI_TFR1: 1078 case FSL_SAI_TFR2: 1079 case FSL_SAI_TFR3: 1080 case FSL_SAI_TFR4: 1081 case FSL_SAI_TFR5: 1082 case FSL_SAI_TFR6: 1083 case FSL_SAI_TFR7: 1084 case FSL_SAI_RFR0: 1085 case FSL_SAI_RFR1: 1086 case FSL_SAI_RFR2: 1087 case FSL_SAI_RFR3: 1088 case FSL_SAI_RFR4: 1089 case FSL_SAI_RFR5: 1090 case FSL_SAI_RFR6: 1091 case FSL_SAI_RFR7: 1092 case FSL_SAI_RDR0: 1093 case FSL_SAI_RDR1: 1094 case FSL_SAI_RDR2: 1095 case FSL_SAI_RDR3: 1096 case FSL_SAI_RDR4: 1097 case FSL_SAI_RDR5: 1098 case FSL_SAI_RDR6: 1099 case FSL_SAI_RDR7: 1100 return true; 1101 default: 1102 return false; 1103 } 1104 } 1105 1106 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1107 { 1108 struct fsl_sai *sai = dev_get_drvdata(dev); 1109 unsigned int ofs = sai->soc_data->reg_offset; 1110 1111 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1112 return true; 1113 1114 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1115 return true; 1116 1117 switch (reg) { 1118 case FSL_SAI_TDR0: 1119 case FSL_SAI_TDR1: 1120 case FSL_SAI_TDR2: 1121 case FSL_SAI_TDR3: 1122 case FSL_SAI_TDR4: 1123 case FSL_SAI_TDR5: 1124 case FSL_SAI_TDR6: 1125 case FSL_SAI_TDR7: 1126 case FSL_SAI_TMR: 1127 case FSL_SAI_RMR: 1128 case FSL_SAI_MCTL: 1129 case FSL_SAI_MDIV: 1130 case FSL_SAI_TTCTL: 1131 case FSL_SAI_RTCTL: 1132 return true; 1133 default: 1134 return false; 1135 } 1136 } 1137 1138 static struct regmap_config fsl_sai_regmap_config = { 1139 .reg_bits = 32, 1140 .reg_stride = 4, 1141 .val_bits = 32, 1142 .fast_io = true, 1143 1144 .max_register = FSL_SAI_RMR, 1145 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1146 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1147 .readable_reg = fsl_sai_readable_reg, 1148 .volatile_reg = fsl_sai_volatile_reg, 1149 .writeable_reg = fsl_sai_writeable_reg, 1150 .cache_type = REGCACHE_FLAT, 1151 }; 1152 1153 static int fsl_sai_check_version(struct device *dev) 1154 { 1155 struct fsl_sai *sai = dev_get_drvdata(dev); 1156 unsigned char ofs = sai->soc_data->reg_offset; 1157 unsigned int val; 1158 int ret; 1159 1160 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1161 return 0; 1162 1163 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1164 if (ret < 0) 1165 return ret; 1166 1167 dev_dbg(dev, "VERID: 0x%016X\n", val); 1168 1169 sai->verid.version = val & 1170 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1171 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1172 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1173 1174 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1175 if (ret < 0) 1176 return ret; 1177 1178 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1179 1180 /* Max slots per frame, power of 2 */ 1181 sai->param.slot_num = 1 << 1182 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1183 1184 /* Words per fifo, power of 2 */ 1185 sai->param.fifo_depth = 1 << 1186 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1187 1188 /* Number of datalines implemented */ 1189 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1190 1191 return 0; 1192 } 1193 1194 /* 1195 * Calculate the offset between first two datalines, don't 1196 * different offset in one case. 1197 */ 1198 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1199 { 1200 int fbidx, nbidx, offset; 1201 1202 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1203 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1204 offset = nbidx - fbidx - 1; 1205 1206 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1207 } 1208 1209 /* 1210 * read the fsl,dataline property from dts file. 1211 * It has 3 value for each configuration, first one means the type: 1212 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1213 * dataline mask for 'tx'. for example 1214 * 1215 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1216 * 1217 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1218 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1219 * 1220 */ 1221 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1222 { 1223 struct platform_device *pdev = sai->pdev; 1224 struct device_node *np = pdev->dev.of_node; 1225 struct device *dev = &pdev->dev; 1226 int ret, elems, i, index, num_cfg; 1227 char *propname = "fsl,dataline"; 1228 struct fsl_sai_dl_cfg *cfg; 1229 unsigned long dl_mask; 1230 unsigned int soc_dl; 1231 u32 rx, tx, type; 1232 1233 elems = of_property_count_u32_elems(np, propname); 1234 1235 if (elems <= 0) { 1236 elems = 0; 1237 } else if (elems % 3) { 1238 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1239 return -EINVAL; 1240 } 1241 1242 num_cfg = elems / 3; 1243 /* Add one more for default value */ 1244 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1245 if (!cfg) 1246 return -ENOMEM; 1247 1248 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1249 soc_dl = BIT(sai->soc_data->pins) - 1; 1250 cfg[0].type = FSL_SAI_DL_DEFAULT; 1251 cfg[0].pins[0] = sai->soc_data->pins; 1252 cfg[0].mask[0] = soc_dl; 1253 cfg[0].start_off[0] = 0; 1254 cfg[0].next_off[0] = 0; 1255 1256 cfg[0].pins[1] = sai->soc_data->pins; 1257 cfg[0].mask[1] = soc_dl; 1258 cfg[0].start_off[1] = 0; 1259 cfg[0].next_off[1] = 0; 1260 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1261 /* 1262 * type of dataline 1263 * 0 means default mode 1264 * 1 means I2S mode 1265 * 2 means PDM mode 1266 */ 1267 ret = of_property_read_u32_index(np, propname, index++, &type); 1268 if (ret) 1269 return -EINVAL; 1270 1271 ret = of_property_read_u32_index(np, propname, index++, &rx); 1272 if (ret) 1273 return -EINVAL; 1274 1275 ret = of_property_read_u32_index(np, propname, index++, &tx); 1276 if (ret) 1277 return -EINVAL; 1278 1279 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1280 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1281 return -EINVAL; 1282 } 1283 1284 rx = rx & soc_dl; 1285 tx = tx & soc_dl; 1286 1287 cfg[i].type = type; 1288 cfg[i].pins[0] = hweight8(rx); 1289 cfg[i].mask[0] = rx; 1290 dl_mask = rx; 1291 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1292 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1293 1294 cfg[i].pins[1] = hweight8(tx); 1295 cfg[i].mask[1] = tx; 1296 dl_mask = tx; 1297 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1298 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1299 } 1300 1301 sai->dl_cfg = cfg; 1302 sai->dl_cfg_cnt = num_cfg + 1; 1303 return 0; 1304 } 1305 1306 static int fsl_sai_runtime_suspend(struct device *dev); 1307 static int fsl_sai_runtime_resume(struct device *dev); 1308 1309 static int fsl_sai_probe(struct platform_device *pdev) 1310 { 1311 struct device_node *np = pdev->dev.of_node; 1312 struct device *dev = &pdev->dev; 1313 struct fsl_sai *sai; 1314 struct regmap *gpr; 1315 void __iomem *base; 1316 char tmp[8]; 1317 int irq, ret, i; 1318 int index; 1319 u32 dmas[4]; 1320 1321 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1322 if (!sai) 1323 return -ENOMEM; 1324 1325 sai->pdev = pdev; 1326 sai->soc_data = of_device_get_match_data(dev); 1327 1328 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1329 1330 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1331 if (IS_ERR(base)) 1332 return PTR_ERR(base); 1333 1334 if (sai->soc_data->reg_offset == 8) { 1335 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1336 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1337 fsl_sai_regmap_config.num_reg_defaults = 1338 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1339 } 1340 1341 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1342 if (IS_ERR(sai->regmap)) { 1343 dev_err(dev, "regmap init failed\n"); 1344 return PTR_ERR(sai->regmap); 1345 } 1346 1347 sai->bus_clk = devm_clk_get(dev, "bus"); 1348 /* Compatible with old DTB cases */ 1349 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1350 sai->bus_clk = devm_clk_get(dev, "sai"); 1351 if (IS_ERR(sai->bus_clk)) { 1352 dev_err(dev, "failed to get bus clock: %ld\n", 1353 PTR_ERR(sai->bus_clk)); 1354 /* -EPROBE_DEFER */ 1355 return PTR_ERR(sai->bus_clk); 1356 } 1357 1358 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1359 sprintf(tmp, "mclk%d", i); 1360 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1361 if (IS_ERR(sai->mclk_clk[i])) { 1362 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1363 i, PTR_ERR(sai->mclk_clk[i])); 1364 sai->mclk_clk[i] = NULL; 1365 } 1366 } 1367 1368 if (sai->soc_data->mclk0_is_mclk1) 1369 sai->mclk_clk[0] = sai->mclk_clk[1]; 1370 else 1371 sai->mclk_clk[0] = sai->bus_clk; 1372 1373 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1374 &sai->pll11k_clk); 1375 1376 /* Use Multi FIFO mode depending on the support from SDMA script */ 1377 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1378 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1379 sai->is_multi_fifo_dma = true; 1380 1381 /* read dataline mask for rx and tx*/ 1382 ret = fsl_sai_read_dlcfg(sai); 1383 if (ret < 0) { 1384 dev_err(dev, "failed to read dlcfg %d\n", ret); 1385 return ret; 1386 } 1387 1388 irq = platform_get_irq(pdev, 0); 1389 if (irq < 0) 1390 return irq; 1391 1392 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1393 np->name, sai); 1394 if (ret) { 1395 dev_err(dev, "failed to claim irq %u\n", irq); 1396 return ret; 1397 } 1398 1399 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1400 sizeof(fsl_sai_dai_template)); 1401 1402 /* Sync Tx with Rx as default by following old DT binding */ 1403 sai->synchronous[RX] = true; 1404 sai->synchronous[TX] = false; 1405 sai->cpu_dai_drv.symmetric_rate = 1; 1406 sai->cpu_dai_drv.symmetric_channels = 1; 1407 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1408 1409 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1410 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1411 /* error out if both synchronous and asynchronous are present */ 1412 dev_err(dev, "invalid binding for synchronous mode\n"); 1413 return -EINVAL; 1414 } 1415 1416 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1417 /* Sync Rx with Tx */ 1418 sai->synchronous[RX] = false; 1419 sai->synchronous[TX] = true; 1420 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1421 /* Discard all settings for asynchronous mode */ 1422 sai->synchronous[RX] = false; 1423 sai->synchronous[TX] = false; 1424 sai->cpu_dai_drv.symmetric_rate = 0; 1425 sai->cpu_dai_drv.symmetric_channels = 0; 1426 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1427 } 1428 1429 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1430 1431 if (sai->mclk_direction_output && 1432 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1433 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1434 if (IS_ERR(gpr)) { 1435 dev_err(dev, "cannot find iomuxc registers\n"); 1436 return PTR_ERR(gpr); 1437 } 1438 1439 index = of_alias_get_id(np, "sai"); 1440 if (index < 0) 1441 return index; 1442 1443 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1444 MCLK_DIR(index)); 1445 } 1446 1447 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1448 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1449 sai->dma_params_rx.maxburst = 1450 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1451 sai->dma_params_tx.maxburst = 1452 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1453 1454 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1455 1456 platform_set_drvdata(pdev, sai); 1457 pm_runtime_enable(dev); 1458 if (!pm_runtime_enabled(dev)) { 1459 ret = fsl_sai_runtime_resume(dev); 1460 if (ret) 1461 goto err_pm_disable; 1462 } 1463 1464 ret = pm_runtime_resume_and_get(dev); 1465 if (ret < 0) 1466 goto err_pm_get_sync; 1467 1468 /* Get sai version */ 1469 ret = fsl_sai_check_version(dev); 1470 if (ret < 0) 1471 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1472 1473 /* Select MCLK direction */ 1474 if (sai->mclk_direction_output && 1475 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1476 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1477 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1478 } 1479 1480 ret = pm_runtime_put_sync(dev); 1481 if (ret < 0 && ret != -ENOSYS) 1482 goto err_pm_get_sync; 1483 1484 /* 1485 * Register platform component before registering cpu dai for there 1486 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1487 */ 1488 if (sai->soc_data->use_imx_pcm) { 1489 ret = imx_pcm_dma_init(pdev); 1490 if (ret) { 1491 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1492 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1493 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1494 goto err_pm_get_sync; 1495 } 1496 } else { 1497 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1498 if (ret) { 1499 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1500 goto err_pm_get_sync; 1501 } 1502 } 1503 1504 ret = devm_snd_soc_register_component(dev, &fsl_component, 1505 &sai->cpu_dai_drv, 1); 1506 if (ret) 1507 goto err_pm_get_sync; 1508 1509 return ret; 1510 1511 err_pm_get_sync: 1512 if (!pm_runtime_status_suspended(dev)) 1513 fsl_sai_runtime_suspend(dev); 1514 err_pm_disable: 1515 pm_runtime_disable(dev); 1516 1517 return ret; 1518 } 1519 1520 static void fsl_sai_remove(struct platform_device *pdev) 1521 { 1522 pm_runtime_disable(&pdev->dev); 1523 if (!pm_runtime_status_suspended(&pdev->dev)) 1524 fsl_sai_runtime_suspend(&pdev->dev); 1525 } 1526 1527 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1528 .use_imx_pcm = false, 1529 .use_edma = false, 1530 .fifo_depth = 32, 1531 .pins = 1, 1532 .reg_offset = 0, 1533 .mclk0_is_mclk1 = false, 1534 .flags = 0, 1535 .max_register = FSL_SAI_RMR, 1536 }; 1537 1538 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1539 .use_imx_pcm = true, 1540 .use_edma = false, 1541 .fifo_depth = 32, 1542 .pins = 1, 1543 .reg_offset = 0, 1544 .mclk0_is_mclk1 = true, 1545 .flags = 0, 1546 .max_register = FSL_SAI_RMR, 1547 }; 1548 1549 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1550 .use_imx_pcm = true, 1551 .use_edma = false, 1552 .fifo_depth = 16, 1553 .pins = 2, 1554 .reg_offset = 8, 1555 .mclk0_is_mclk1 = false, 1556 .flags = PMQOS_CPU_LATENCY, 1557 .max_register = FSL_SAI_RMR, 1558 }; 1559 1560 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1561 .use_imx_pcm = true, 1562 .use_edma = false, 1563 .fifo_depth = 128, 1564 .pins = 8, 1565 .reg_offset = 8, 1566 .mclk0_is_mclk1 = false, 1567 .flags = 0, 1568 .max_register = FSL_SAI_RMR, 1569 }; 1570 1571 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1572 .use_imx_pcm = true, 1573 .use_edma = true, 1574 .fifo_depth = 64, 1575 .pins = 4, 1576 .reg_offset = 0, 1577 .mclk0_is_mclk1 = false, 1578 .flags = 0, 1579 .max_register = FSL_SAI_RMR, 1580 }; 1581 1582 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1583 .use_imx_pcm = true, 1584 .use_edma = false, 1585 .fifo_depth = 128, 1586 .reg_offset = 8, 1587 .mclk0_is_mclk1 = false, 1588 .pins = 8, 1589 .flags = 0, 1590 .max_register = FSL_SAI_MCTL, 1591 }; 1592 1593 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1594 .use_imx_pcm = true, 1595 .use_edma = false, 1596 .fifo_depth = 128, 1597 .reg_offset = 8, 1598 .mclk0_is_mclk1 = false, 1599 .pins = 8, 1600 .flags = 0, 1601 .max_register = FSL_SAI_MDIV, 1602 }; 1603 1604 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1605 .use_imx_pcm = true, 1606 .use_edma = false, 1607 .fifo_depth = 128, 1608 .reg_offset = 8, 1609 .mclk0_is_mclk1 = false, 1610 .pins = 8, 1611 .flags = 0, 1612 .max_register = FSL_SAI_MDIV, 1613 .mclk_with_tere = true, 1614 }; 1615 1616 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1617 .use_imx_pcm = true, 1618 .use_edma = true, 1619 .fifo_depth = 16, 1620 .reg_offset = 8, 1621 .mclk0_is_mclk1 = false, 1622 .pins = 4, 1623 .flags = PMQOS_CPU_LATENCY, 1624 .max_register = FSL_SAI_RTCAP, 1625 }; 1626 1627 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1628 .use_imx_pcm = true, 1629 .use_edma = true, 1630 .fifo_depth = 128, 1631 .reg_offset = 8, 1632 .mclk0_is_mclk1 = false, 1633 .pins = 4, 1634 .flags = 0, 1635 .max_register = FSL_SAI_MCTL, 1636 .max_burst = {8, 8}, 1637 }; 1638 1639 static const struct of_device_id fsl_sai_ids[] = { 1640 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1641 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1642 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1643 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1644 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1645 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1646 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1647 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1648 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1649 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1650 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1651 { /* sentinel */ } 1652 }; 1653 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1654 1655 static int fsl_sai_runtime_suspend(struct device *dev) 1656 { 1657 struct fsl_sai *sai = dev_get_drvdata(dev); 1658 1659 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1660 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1661 1662 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1663 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1664 1665 clk_disable_unprepare(sai->bus_clk); 1666 1667 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1668 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1669 1670 regcache_cache_only(sai->regmap, true); 1671 1672 return 0; 1673 } 1674 1675 static int fsl_sai_runtime_resume(struct device *dev) 1676 { 1677 struct fsl_sai *sai = dev_get_drvdata(dev); 1678 unsigned int ofs = sai->soc_data->reg_offset; 1679 int ret; 1680 1681 ret = clk_prepare_enable(sai->bus_clk); 1682 if (ret) { 1683 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1684 return ret; 1685 } 1686 1687 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1688 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1689 if (ret) 1690 goto disable_bus_clk; 1691 } 1692 1693 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1694 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1695 if (ret) 1696 goto disable_tx_clk; 1697 } 1698 1699 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1700 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1701 1702 regcache_cache_only(sai->regmap, false); 1703 regcache_mark_dirty(sai->regmap); 1704 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1705 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1706 usleep_range(1000, 2000); 1707 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1708 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1709 1710 ret = regcache_sync(sai->regmap); 1711 if (ret) 1712 goto disable_rx_clk; 1713 1714 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1715 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1716 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1717 1718 return 0; 1719 1720 disable_rx_clk: 1721 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1722 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1723 disable_tx_clk: 1724 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1725 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1726 disable_bus_clk: 1727 clk_disable_unprepare(sai->bus_clk); 1728 1729 return ret; 1730 } 1731 1732 static const struct dev_pm_ops fsl_sai_pm_ops = { 1733 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1734 fsl_sai_runtime_resume, NULL) 1735 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1736 pm_runtime_force_resume) 1737 }; 1738 1739 static struct platform_driver fsl_sai_driver = { 1740 .probe = fsl_sai_probe, 1741 .remove_new = fsl_sai_remove, 1742 .driver = { 1743 .name = "fsl-sai", 1744 .pm = &fsl_sai_pm_ops, 1745 .of_match_table = fsl_sai_ids, 1746 }, 1747 }; 1748 module_platform_driver(fsl_sai_driver); 1749 1750 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1751 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1752 MODULE_ALIAS("platform:fsl-sai"); 1753 MODULE_LICENSE("GPL"); 1754