1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/pm_qos.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/time.h> 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 23 24 #include "fsl_sai.h" 25 #include "fsl_utils.h" 26 #include "imx-pcm.h" 27 28 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 29 FSL_SAI_CSR_FEIE) 30 31 static const unsigned int fsl_sai_rates[] = { 32 8000, 11025, 12000, 16000, 22050, 33 24000, 32000, 44100, 48000, 64000, 34 88200, 96000, 176400, 192000, 352800, 35 384000, 705600, 768000, 1411200, 2822400, 36 }; 37 38 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 39 .count = ARRAY_SIZE(fsl_sai_rates), 40 .list = fsl_sai_rates, 41 }; 42 43 /** 44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 45 * 46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 47 * or Receiver's for both streams. This function is used to check if clocks of 48 * the stream's are synced by the opposite stream. 49 * 50 * @sai: SAI context 51 * @dir: stream direction 52 */ 53 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 54 { 55 int adir = (dir == TX) ? RX : TX; 56 57 /* current dir in async mode while opposite dir in sync mode */ 58 return !sai->synchronous[dir] && sai->synchronous[adir]; 59 } 60 61 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 62 { 63 struct pinctrl_state *state = NULL; 64 65 if (sai->is_pdm_mode) { 66 /* DSD512@44.1kHz, DSD512@48kHz */ 67 if (bclk >= 22579200) 68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 69 70 /* Get default DSD state */ 71 if (IS_ERR_OR_NULL(state)) 72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 73 } else { 74 /* 706k32b2c, 768k32b2c, etc */ 75 if (bclk >= 45158400) 76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 77 } 78 79 /* Get default state */ 80 if (IS_ERR_OR_NULL(state)) 81 state = pinctrl_lookup_state(sai->pinctrl, "default"); 82 83 return state; 84 } 85 86 static irqreturn_t fsl_sai_isr(int irq, void *devid) 87 { 88 struct fsl_sai *sai = (struct fsl_sai *)devid; 89 unsigned int ofs = sai->soc_data->reg_offset; 90 struct device *dev = &sai->pdev->dev; 91 u32 flags, xcsr, mask; 92 irqreturn_t iret = IRQ_NONE; 93 94 /* 95 * Both IRQ status bits and IRQ mask bits are in the xCSR but 96 * different shifts. And we here create a mask only for those 97 * IRQs that we activated. 98 */ 99 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 100 101 /* Tx IRQ */ 102 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 103 flags = xcsr & mask; 104 105 if (flags) 106 iret = IRQ_HANDLED; 107 else 108 goto irq_rx; 109 110 if (flags & FSL_SAI_CSR_WSF) 111 dev_dbg(dev, "isr: Start of Tx word detected\n"); 112 113 if (flags & FSL_SAI_CSR_SEF) 114 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 115 116 if (flags & FSL_SAI_CSR_FEF) 117 dev_dbg(dev, "isr: Transmit underrun detected\n"); 118 119 if (flags & FSL_SAI_CSR_FWF) 120 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 121 122 if (flags & FSL_SAI_CSR_FRF) 123 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 124 125 flags &= FSL_SAI_CSR_xF_W_MASK; 126 xcsr &= ~FSL_SAI_CSR_xF_MASK; 127 128 if (flags) 129 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 130 131 irq_rx: 132 /* Rx IRQ */ 133 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 134 flags = xcsr & mask; 135 136 if (flags) 137 iret = IRQ_HANDLED; 138 else 139 goto out; 140 141 if (flags & FSL_SAI_CSR_WSF) 142 dev_dbg(dev, "isr: Start of Rx word detected\n"); 143 144 if (flags & FSL_SAI_CSR_SEF) 145 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 146 147 if (flags & FSL_SAI_CSR_FEF) 148 dev_dbg(dev, "isr: Receive overflow detected\n"); 149 150 if (flags & FSL_SAI_CSR_FWF) 151 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 152 153 if (flags & FSL_SAI_CSR_FRF) 154 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 155 156 flags &= FSL_SAI_CSR_xF_W_MASK; 157 xcsr &= ~FSL_SAI_CSR_xF_MASK; 158 159 if (flags) 160 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 161 162 out: 163 return iret; 164 } 165 166 static int fsl_sai_set_dai_tdm_slot_tx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 167 u32 rx_mask, int slots, int slot_width) 168 { 169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 170 bool tx = true; 171 172 sai->slots[tx] = slots; 173 sai->slot_width[tx] = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_tdm_slot_rx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 179 u32 rx_mask, int slots, int slot_width) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 182 bool tx = false; 183 184 sai->slots[tx] = slots; 185 sai->slot_width[tx] = slot_width; 186 187 return 0; 188 } 189 190 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 191 u32 rx_mask, int slots, int slot_width) 192 { 193 int ret; 194 195 ret = fsl_sai_set_dai_tdm_slot_tx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 196 if (ret) 197 return ret; 198 199 return fsl_sai_set_dai_tdm_slot_rx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 200 } 201 202 static int fsl_sai_xlate_tdm_slot_mask(unsigned int slots, 203 unsigned int *tx_mask, unsigned int *rx_mask) 204 { 205 /* Leave it empty, don't change the value of tx_mask and rx_mask */ 206 return 0; 207 } 208 209 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 210 unsigned int ratio) 211 { 212 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 213 214 sai->bclk_ratio = ratio; 215 216 return 0; 217 } 218 219 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 220 int clk_id, unsigned int freq, bool tx) 221 { 222 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 223 unsigned int ofs = sai->soc_data->reg_offset; 224 u32 val_cr2 = 0; 225 226 switch (clk_id) { 227 case FSL_SAI_CLK_BUS: 228 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 229 break; 230 case FSL_SAI_CLK_MAST1: 231 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 232 break; 233 case FSL_SAI_CLK_MAST2: 234 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 235 break; 236 case FSL_SAI_CLK_MAST3: 237 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 238 break; 239 default: 240 return -EINVAL; 241 } 242 243 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 244 FSL_SAI_CR2_MSEL_MASK, val_cr2); 245 246 return 0; 247 } 248 249 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 250 { 251 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 252 int ret; 253 254 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 255 sai->pll8k_clk, sai->pll11k_clk, freq); 256 257 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 258 if (ret < 0) 259 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 260 261 return ret; 262 } 263 264 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 265 int clk_id, unsigned int freq, int dir) 266 { 267 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 268 int ret; 269 270 if (dir == SND_SOC_CLOCK_IN) 271 return 0; 272 273 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 274 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 275 return -EINVAL; 276 } 277 278 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 279 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 280 return -EINVAL; 281 } 282 283 if (sai->mclk_streams == 0 && freq > 0) { 284 ret = fsl_sai_set_mclk_rate(cpu_dai, 285 clk_id ? clk_id : FSL_SAI_CLK_MAST1, 286 freq); 287 if (ret < 0) 288 return ret; 289 } 290 291 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 292 if (ret) { 293 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 294 return ret; 295 } 296 297 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 298 if (ret) 299 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 300 301 return ret; 302 } 303 304 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 305 unsigned int fmt, bool tx) 306 { 307 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 308 unsigned int ofs = sai->soc_data->reg_offset; 309 u32 val_cr2 = 0, val_cr4 = 0; 310 311 if (!sai->is_lsb_first) 312 val_cr4 |= FSL_SAI_CR4_MF; 313 314 sai->is_pdm_mode = false; 315 sai->is_dsp_mode[tx] = false; 316 /* DAI mode */ 317 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 318 case SND_SOC_DAIFMT_I2S: 319 /* 320 * Frame low, 1clk before data, one word length for frame sync, 321 * frame sync starts one serial clock cycle earlier, 322 * that is, together with the last bit of the previous 323 * data word. 324 */ 325 val_cr2 |= FSL_SAI_CR2_BCP; 326 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 327 break; 328 case SND_SOC_DAIFMT_LEFT_J: 329 /* 330 * Frame high, one word length for frame sync, 331 * frame sync asserts with the first bit of the frame. 332 */ 333 val_cr2 |= FSL_SAI_CR2_BCP; 334 break; 335 case SND_SOC_DAIFMT_DSP_A: 336 /* 337 * Frame high, 1clk before data, one bit for frame sync, 338 * frame sync starts one serial clock cycle earlier, 339 * that is, together with the last bit of the previous 340 * data word. 341 */ 342 val_cr2 |= FSL_SAI_CR2_BCP; 343 val_cr4 |= FSL_SAI_CR4_FSE; 344 sai->is_dsp_mode[tx] = true; 345 break; 346 case SND_SOC_DAIFMT_DSP_B: 347 /* 348 * Frame high, one bit for frame sync, 349 * frame sync asserts with the first bit of the frame. 350 */ 351 val_cr2 |= FSL_SAI_CR2_BCP; 352 sai->is_dsp_mode[tx] = true; 353 break; 354 case SND_SOC_DAIFMT_PDM: 355 val_cr2 |= FSL_SAI_CR2_BCP; 356 val_cr4 &= ~FSL_SAI_CR4_MF; 357 sai->is_pdm_mode = true; 358 break; 359 case SND_SOC_DAIFMT_RIGHT_J: 360 /* To be done */ 361 default: 362 return -EINVAL; 363 } 364 365 /* DAI clock inversion */ 366 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 367 case SND_SOC_DAIFMT_IB_IF: 368 /* Invert both clocks */ 369 val_cr2 ^= FSL_SAI_CR2_BCP; 370 val_cr4 ^= FSL_SAI_CR4_FSP; 371 break; 372 case SND_SOC_DAIFMT_IB_NF: 373 /* Invert bit clock */ 374 val_cr2 ^= FSL_SAI_CR2_BCP; 375 break; 376 case SND_SOC_DAIFMT_NB_IF: 377 /* Invert frame clock */ 378 val_cr4 ^= FSL_SAI_CR4_FSP; 379 break; 380 case SND_SOC_DAIFMT_NB_NF: 381 /* Nothing to do for both normal cases */ 382 break; 383 default: 384 return -EINVAL; 385 } 386 387 /* DAI clock provider masks */ 388 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 389 case SND_SOC_DAIFMT_BP_FP: 390 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 391 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 392 sai->is_consumer_mode[tx] = false; 393 break; 394 case SND_SOC_DAIFMT_BC_FC: 395 sai->is_consumer_mode[tx] = true; 396 break; 397 case SND_SOC_DAIFMT_BP_FC: 398 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 399 sai->is_consumer_mode[tx] = false; 400 break; 401 case SND_SOC_DAIFMT_BC_FP: 402 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 403 sai->is_consumer_mode[tx] = true; 404 break; 405 default: 406 return -EINVAL; 407 } 408 409 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 410 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 411 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 412 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 413 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 414 415 return 0; 416 } 417 418 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 419 { 420 int ret; 421 422 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 423 if (ret) { 424 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 425 return ret; 426 } 427 428 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 429 if (ret) 430 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 431 432 return ret; 433 } 434 435 static int fsl_sai_set_dai_fmt_tx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 436 { 437 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 438 } 439 440 static int fsl_sai_set_dai_fmt_rx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 441 { 442 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 443 } 444 445 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 446 { 447 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 448 unsigned int reg, ofs = sai->soc_data->reg_offset; 449 unsigned long clk_rate; 450 u32 savediv = 0, ratio, bestdiff = freq; 451 int adir = tx ? RX : TX; 452 int dir = tx ? TX : RX; 453 u32 id; 454 bool support_1_1_ratio = sai->verid.version >= 0x0301; 455 456 /* Don't apply to consumer mode */ 457 if (sai->is_consumer_mode[tx]) 458 return 0; 459 460 /* 461 * There is no point in polling MCLK0 if it is identical to MCLK1. 462 * And given that MQS use case has to use MCLK1 though two clocks 463 * are the same, we simply skip MCLK0 and start to find from MCLK1. 464 */ 465 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 466 467 for (; id < FSL_SAI_MCLK_MAX; id++) { 468 int diff; 469 470 clk_rate = clk_get_rate(sai->mclk_clk[id]); 471 if (!clk_rate) 472 continue; 473 474 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 475 if (!ratio || ratio > 512) 476 continue; 477 if (ratio == 1 && !support_1_1_ratio) 478 continue; 479 if ((ratio & 1) && ratio > 1) 480 continue; 481 482 diff = abs((long)clk_rate - ratio * freq); 483 484 /* 485 * Drop the source that can not be 486 * divided into the required rate. 487 */ 488 if (diff != 0 && clk_rate / diff < 1000) 489 continue; 490 491 dev_dbg(dai->dev, 492 "ratio %d for freq %dHz based on clock %ldHz\n", 493 ratio, freq, clk_rate); 494 495 496 if (diff < bestdiff) { 497 savediv = ratio; 498 sai->mclk_id[tx] = id; 499 bestdiff = diff; 500 } 501 502 if (diff == 0) 503 break; 504 } 505 506 if (savediv == 0) { 507 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 508 tx ? 'T' : 'R', freq); 509 return -EINVAL; 510 } 511 512 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 513 sai->mclk_id[tx], savediv, bestdiff); 514 515 /* 516 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 517 * set TCR2 register for playback. 518 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 519 * and capture. 520 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 521 * and capture. 522 * 4) For Tx and Rx are both Synchronous with another SAI, we just 523 * ignore it. 524 */ 525 if (fsl_sai_dir_is_synced(sai, adir)) 526 reg = FSL_SAI_xCR2(!tx, ofs); 527 else if (!sai->synchronous[dir]) 528 reg = FSL_SAI_xCR2(tx, ofs); 529 else 530 return 0; 531 532 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 533 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 534 535 if (savediv == 1) { 536 regmap_update_bits(sai->regmap, reg, 537 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 538 FSL_SAI_CR2_BYP); 539 if (fsl_sai_dir_is_synced(sai, adir)) 540 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 541 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 542 else 543 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 544 FSL_SAI_CR2_BCI, 0); 545 } else { 546 regmap_update_bits(sai->regmap, reg, 547 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 548 savediv / 2 - 1); 549 } 550 551 return 0; 552 } 553 554 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 555 struct snd_pcm_hw_params *params, 556 struct snd_soc_dai *cpu_dai) 557 { 558 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 559 unsigned int ofs = sai->soc_data->reg_offset; 560 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 561 unsigned int channels = params_channels(params); 562 struct snd_dmaengine_dai_dma_data *dma_params; 563 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 564 u32 word_width = params_width(params); 565 int trce_mask = 0, dl_cfg_idx = 0; 566 int dl_cfg_cnt = sai->dl_cfg_cnt; 567 u32 dl_type = FSL_SAI_DL_I2S; 568 u32 val_cr4 = 0, val_cr5 = 0; 569 u32 slots = (channels == 1) ? 2 : channels; 570 u32 slot_width = word_width; 571 int adir = tx ? RX : TX; 572 u32 pins, bclk; 573 u32 watermark; 574 int ret, i; 575 576 if (sai->slot_width[tx]) 577 slot_width = sai->slot_width[tx]; 578 579 if (sai->slots[tx]) 580 slots = sai->slots[tx]; 581 else if (sai->bclk_ratio) 582 slots = sai->bclk_ratio / slot_width; 583 584 pins = DIV_ROUND_UP(channels, slots); 585 586 /* 587 * PDM mode, channels are independent 588 * each channels are on one dataline/FIFO. 589 */ 590 if (sai->is_pdm_mode) { 591 pins = channels; 592 dl_type = FSL_SAI_DL_PDM; 593 } 594 595 for (i = 0; i < dl_cfg_cnt; i++) { 596 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 597 dl_cfg_idx = i; 598 break; 599 } 600 } 601 602 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 603 dev_err(cpu_dai->dev, "channel not supported\n"); 604 return -EINVAL; 605 } 606 607 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 608 609 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 610 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 611 if (!IS_ERR_OR_NULL(sai->pins_state)) { 612 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 613 if (ret) { 614 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 615 return ret; 616 } 617 } 618 } 619 620 if (!sai->is_consumer_mode[tx]) { 621 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 622 if (ret) 623 return ret; 624 625 /* Do not enable the clock if it is already enabled */ 626 if (!(sai->mclk_streams & BIT(substream->stream))) { 627 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 628 if (ret) 629 return ret; 630 631 sai->mclk_streams |= BIT(substream->stream); 632 } 633 } 634 635 if (!sai->is_dsp_mode[tx] && !sai->is_pdm_mode) 636 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 637 638 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 639 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 640 641 if (sai->is_lsb_first || sai->is_pdm_mode) 642 val_cr5 |= FSL_SAI_CR5_FBT(0); 643 else 644 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 645 646 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 647 648 /* Set to avoid channel swap */ 649 val_cr4 |= FSL_SAI_CR4_FCONT; 650 651 /* Set to output mode to avoid tri-stated data pins */ 652 if (tx) 653 val_cr4 |= FSL_SAI_CR4_CHMOD; 654 655 /* 656 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 657 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 658 * RCR5(TCR5) for playback(capture), or there will be sync error. 659 */ 660 661 if (!sai->is_consumer_mode[tx] && fsl_sai_dir_is_synced(sai, adir)) { 662 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 663 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 664 FSL_SAI_CR4_CHMOD_MASK, 665 val_cr4); 666 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 667 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 668 FSL_SAI_CR5_FBT_MASK, val_cr5); 669 } 670 671 /* 672 * Combine mode has limation: 673 * - Can't used for singel dataline/FIFO case except the FIFO0 674 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 675 * are successive and start from FIFO0 676 * 677 * So for common usage, all multi fifo case disable the combine mode. 678 */ 679 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 680 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 681 FSL_SAI_CR4_FCOMB_MASK, 0); 682 else 683 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 684 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 685 686 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 687 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 688 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 689 690 if (sai->is_multi_fifo_dma) { 691 sai->audio_config[tx].words_per_fifo = min(slots, channels); 692 if (tx) { 693 sai->audio_config[tx].n_fifos_dst = pins; 694 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 695 } else { 696 sai->audio_config[tx].n_fifos_src = pins; 697 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 698 } 699 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 700 dma_params->peripheral_config = &sai->audio_config[tx]; 701 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 702 703 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 704 (dma_params->maxburst - 1); 705 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 706 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 707 watermark); 708 } 709 710 /* Find a proper tcre setting */ 711 for (i = 0; i < sai->soc_data->pins; i++) { 712 trce_mask = (1 << (i + 1)) - 1; 713 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 714 break; 715 } 716 717 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 718 FSL_SAI_CR3_TRCE_MASK, 719 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 720 721 /* 722 * When the TERE and FSD_MSTR enabled before configuring the word width 723 * There will be no frame sync clock issue, because word width impact 724 * the generation of frame sync clock. 725 * 726 * TERE enabled earlier only for i.MX8MP case for the hardware limitation, 727 * We need to disable FSD_MSTR before configuring word width, then enable 728 * FSD_MSTR bit for this specific case. 729 */ 730 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 731 !sai->is_consumer_mode[tx]) 732 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 733 FSL_SAI_CR4_FSD_MSTR, 0); 734 735 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 736 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 737 FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK, 738 val_cr4); 739 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 740 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 741 FSL_SAI_CR5_FBT_MASK, val_cr5); 742 743 /* Enable FSD_MSTR after configuring word width */ 744 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 745 !sai->is_consumer_mode[tx]) 746 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 747 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR); 748 749 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 750 ~0UL - ((1 << min(channels, slots)) - 1)); 751 752 return 0; 753 } 754 755 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 756 struct snd_soc_dai *cpu_dai) 757 { 758 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 759 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 760 unsigned int ofs = sai->soc_data->reg_offset; 761 762 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ 763 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0); 764 765 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 766 FSL_SAI_CR3_TRCE_MASK, 0); 767 768 if (!sai->is_consumer_mode[tx] && 769 sai->mclk_streams & BIT(substream->stream)) { 770 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 771 sai->mclk_streams &= ~BIT(substream->stream); 772 } 773 774 return 0; 775 } 776 777 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 778 { 779 unsigned int ofs = sai->soc_data->reg_offset; 780 bool tx = dir == TX; 781 u32 xcsr, count = 100, mask; 782 783 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 784 mask = FSL_SAI_CSR_TERE; 785 else 786 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 787 788 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 789 mask, 0); 790 791 /* TERE will remain set till the end of current frame */ 792 do { 793 udelay(10); 794 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 795 } while (--count && xcsr & FSL_SAI_CSR_TERE); 796 797 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 798 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 799 800 /* 801 * For sai master mode, after several open/close sai, 802 * there will be no frame clock, and can't recover 803 * anymore. Add software reset to fix this issue. 804 * This is a hardware bug, and will be fix in the 805 * next sai version. 806 * 807 * In consumer mode, this can happen even after a 808 * single open/close, especially if both tx and rx 809 * are running concurrently. 810 */ 811 /* Software Reset */ 812 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 813 /* Clear SR bit to finish the reset */ 814 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 815 } 816 817 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 818 struct snd_soc_dai *cpu_dai) 819 { 820 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 821 unsigned int ofs = sai->soc_data->reg_offset; 822 823 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 824 int adir = tx ? RX : TX; 825 int dir = tx ? TX : RX; 826 u32 xcsr; 827 828 /* 829 * Asynchronous mode: Clear SYNC for both Tx and Rx. 830 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 831 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 832 */ 833 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 834 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 835 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 836 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 837 838 /* 839 * It is recommended that the transmitter is the last enabled 840 * and the first disabled. 841 */ 842 switch (cmd) { 843 case SNDRV_PCM_TRIGGER_START: 844 case SNDRV_PCM_TRIGGER_RESUME: 845 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 846 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 847 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 848 849 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 850 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 851 /* 852 * Enable the opposite direction for synchronous mode 853 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 854 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 855 * 856 * RM recommends to enable RE after TE for case 1 and to enable 857 * TE after RE for case 2, but we here may not always guarantee 858 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 859 * TE after RE, which is against what RM recommends but should 860 * be safe to do, judging by years of testing results. 861 */ 862 if (fsl_sai_dir_is_synced(sai, adir)) 863 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 864 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 865 866 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 867 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 868 break; 869 case SNDRV_PCM_TRIGGER_STOP: 870 case SNDRV_PCM_TRIGGER_SUSPEND: 871 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 872 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 873 FSL_SAI_CSR_FRDE, 0); 874 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 875 FSL_SAI_CSR_xIE_MASK, 0); 876 877 /* Check if the opposite FRDE is also disabled */ 878 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 879 880 /* 881 * If opposite stream provides clocks for synchronous mode and 882 * it is inactive, disable it before disabling the current one 883 */ 884 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 885 fsl_sai_config_disable(sai, adir); 886 887 /* 888 * Disable current stream if either of: 889 * 1. current stream doesn't provide clocks for synchronous mode 890 * 2. current stream provides clocks for synchronous mode but no 891 * more stream is active. 892 */ 893 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 894 fsl_sai_config_disable(sai, dir); 895 896 break; 897 default: 898 return -EINVAL; 899 } 900 901 return 0; 902 } 903 904 static int fsl_sai_startup(struct snd_pcm_substream *substream, 905 struct snd_soc_dai *cpu_dai) 906 { 907 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 908 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 909 int ret; 910 911 /* 912 * EDMA controller needs period size to be a multiple of 913 * tx/rx maxburst 914 */ 915 if (sai->soc_data->use_edma) 916 snd_pcm_hw_constraint_step(substream->runtime, 0, 917 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 918 tx ? sai->dma_params_tx.maxburst : 919 sai->dma_params_rx.maxburst); 920 921 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 922 SNDRV_PCM_HW_PARAM_RATE, &sai->constraint_rates); 923 924 return ret; 925 } 926 927 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 928 { 929 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 930 unsigned int ofs = sai->soc_data->reg_offset; 931 932 /* Software Reset for both Tx and Rx */ 933 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 934 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 935 /* Clear SR bit to finish the reset */ 936 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 937 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 938 939 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 940 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 941 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 942 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 943 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 944 sai->dma_params_rx.maxburst - 1); 945 946 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 947 &sai->dma_params_rx); 948 949 return 0; 950 } 951 952 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 953 .probe = fsl_sai_dai_probe, 954 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 955 .set_sysclk = fsl_sai_set_dai_sysclk, 956 .set_fmt = fsl_sai_set_dai_fmt, 957 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 958 .hw_params = fsl_sai_hw_params, 959 .hw_free = fsl_sai_hw_free, 960 .trigger = fsl_sai_trigger, 961 .startup = fsl_sai_startup, 962 }; 963 964 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_tx_ops = { 965 .probe = fsl_sai_dai_probe, 966 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 967 .set_sysclk = fsl_sai_set_dai_sysclk, 968 .set_fmt = fsl_sai_set_dai_fmt_tx, 969 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_tx, 970 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 971 .hw_params = fsl_sai_hw_params, 972 .hw_free = fsl_sai_hw_free, 973 .trigger = fsl_sai_trigger, 974 .startup = fsl_sai_startup, 975 }; 976 977 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_rx_ops = { 978 .probe = fsl_sai_dai_probe, 979 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 980 .set_sysclk = fsl_sai_set_dai_sysclk, 981 .set_fmt = fsl_sai_set_dai_fmt_rx, 982 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_rx, 983 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 984 .hw_params = fsl_sai_hw_params, 985 .hw_free = fsl_sai_hw_free, 986 .trigger = fsl_sai_trigger, 987 .startup = fsl_sai_startup, 988 }; 989 990 static int fsl_sai_dai_resume(struct snd_soc_component *component) 991 { 992 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 993 struct device *dev = &sai->pdev->dev; 994 int ret; 995 996 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 997 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 998 if (ret) { 999 dev_err(dev, "failed to set proper pins state: %d\n", ret); 1000 return ret; 1001 } 1002 } 1003 1004 return 0; 1005 } 1006 1007 static struct snd_soc_dai_driver fsl_sai_dai_template[] = { 1008 { 1009 .name = "sai-tx-rx", 1010 .playback = { 1011 .stream_name = "CPU-Playback", 1012 .channels_min = 1, 1013 .channels_max = 32, 1014 .rate_min = 8000, 1015 .rate_max = 2822400, 1016 .rates = SNDRV_PCM_RATE_KNOT, 1017 .formats = FSL_SAI_FORMATS, 1018 }, 1019 .capture = { 1020 .stream_name = "CPU-Capture", 1021 .channels_min = 1, 1022 .channels_max = 32, 1023 .rate_min = 8000, 1024 .rate_max = 2822400, 1025 .rates = SNDRV_PCM_RATE_KNOT, 1026 .formats = FSL_SAI_FORMATS, 1027 }, 1028 .ops = &fsl_sai_pcm_dai_ops, 1029 }, 1030 { 1031 .name = "sai-tx", 1032 .playback = { 1033 .stream_name = "SAI-Playback", 1034 .channels_min = 1, 1035 .channels_max = 32, 1036 .rate_min = 8000, 1037 .rate_max = 2822400, 1038 .rates = SNDRV_PCM_RATE_KNOT, 1039 .formats = FSL_SAI_FORMATS, 1040 }, 1041 .ops = &fsl_sai_pcm_dai_tx_ops, 1042 }, 1043 { 1044 .name = "sai-rx", 1045 .capture = { 1046 .stream_name = "SAI-Capture", 1047 .channels_min = 1, 1048 .channels_max = 32, 1049 .rate_min = 8000, 1050 .rate_max = 2822400, 1051 .rates = SNDRV_PCM_RATE_KNOT, 1052 .formats = FSL_SAI_FORMATS, 1053 }, 1054 .ops = &fsl_sai_pcm_dai_rx_ops, 1055 }, 1056 }; 1057 1058 static const struct snd_soc_component_driver fsl_component = { 1059 .name = "fsl-sai", 1060 .resume = fsl_sai_dai_resume, 1061 .legacy_dai_naming = 1, 1062 }; 1063 1064 static const struct reg_default fsl_sai_reg_defaults_ofs0[] = { 1065 {FSL_SAI_TCR1(0), 0}, 1066 {FSL_SAI_TCR2(0), 0}, 1067 {FSL_SAI_TCR3(0), 0}, 1068 {FSL_SAI_TCR4(0), 0}, 1069 {FSL_SAI_TCR5(0), 0}, 1070 {FSL_SAI_TDR0, 0}, 1071 {FSL_SAI_TDR1, 0}, 1072 {FSL_SAI_TDR2, 0}, 1073 {FSL_SAI_TDR3, 0}, 1074 {FSL_SAI_TDR4, 0}, 1075 {FSL_SAI_TDR5, 0}, 1076 {FSL_SAI_TDR6, 0}, 1077 {FSL_SAI_TDR7, 0}, 1078 {FSL_SAI_TMR, 0}, 1079 {FSL_SAI_RCR1(0), 0}, 1080 {FSL_SAI_RCR2(0), 0}, 1081 {FSL_SAI_RCR3(0), 0}, 1082 {FSL_SAI_RCR4(0), 0}, 1083 {FSL_SAI_RCR5(0), 0}, 1084 {FSL_SAI_RMR, 0}, 1085 }; 1086 1087 static const struct reg_default fsl_sai_reg_defaults_ofs8[] = { 1088 {FSL_SAI_TCR1(8), 0}, 1089 {FSL_SAI_TCR2(8), 0}, 1090 {FSL_SAI_TCR3(8), 0}, 1091 {FSL_SAI_TCR4(8), 0}, 1092 {FSL_SAI_TCR5(8), 0}, 1093 {FSL_SAI_TDR0, 0}, 1094 {FSL_SAI_TDR1, 0}, 1095 {FSL_SAI_TDR2, 0}, 1096 {FSL_SAI_TDR3, 0}, 1097 {FSL_SAI_TDR4, 0}, 1098 {FSL_SAI_TDR5, 0}, 1099 {FSL_SAI_TDR6, 0}, 1100 {FSL_SAI_TDR7, 0}, 1101 {FSL_SAI_TMR, 0}, 1102 {FSL_SAI_RCR1(8), 0}, 1103 {FSL_SAI_RCR2(8), 0}, 1104 {FSL_SAI_RCR3(8), 0}, 1105 {FSL_SAI_RCR4(8), 0}, 1106 {FSL_SAI_RCR5(8), 0}, 1107 {FSL_SAI_RMR, 0}, 1108 {FSL_SAI_MCTL, 0}, 1109 {FSL_SAI_MDIV, 0}, 1110 }; 1111 1112 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 1113 { 1114 struct fsl_sai *sai = dev_get_drvdata(dev); 1115 unsigned int ofs = sai->soc_data->reg_offset; 1116 1117 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1118 return true; 1119 1120 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1121 return true; 1122 1123 switch (reg) { 1124 case FSL_SAI_TFR0: 1125 case FSL_SAI_TFR1: 1126 case FSL_SAI_TFR2: 1127 case FSL_SAI_TFR3: 1128 case FSL_SAI_TFR4: 1129 case FSL_SAI_TFR5: 1130 case FSL_SAI_TFR6: 1131 case FSL_SAI_TFR7: 1132 case FSL_SAI_TMR: 1133 case FSL_SAI_RDR0: 1134 case FSL_SAI_RDR1: 1135 case FSL_SAI_RDR2: 1136 case FSL_SAI_RDR3: 1137 case FSL_SAI_RDR4: 1138 case FSL_SAI_RDR5: 1139 case FSL_SAI_RDR6: 1140 case FSL_SAI_RDR7: 1141 case FSL_SAI_RFR0: 1142 case FSL_SAI_RFR1: 1143 case FSL_SAI_RFR2: 1144 case FSL_SAI_RFR3: 1145 case FSL_SAI_RFR4: 1146 case FSL_SAI_RFR5: 1147 case FSL_SAI_RFR6: 1148 case FSL_SAI_RFR7: 1149 case FSL_SAI_RMR: 1150 case FSL_SAI_MCTL: 1151 case FSL_SAI_MDIV: 1152 case FSL_SAI_VERID: 1153 case FSL_SAI_PARAM: 1154 case FSL_SAI_TTCTN: 1155 case FSL_SAI_RTCTN: 1156 case FSL_SAI_TTCTL: 1157 case FSL_SAI_TBCTN: 1158 case FSL_SAI_TTCAP: 1159 case FSL_SAI_RTCTL: 1160 case FSL_SAI_RBCTN: 1161 case FSL_SAI_RTCAP: 1162 return true; 1163 default: 1164 return false; 1165 } 1166 } 1167 1168 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1169 { 1170 struct fsl_sai *sai = dev_get_drvdata(dev); 1171 unsigned int ofs = sai->soc_data->reg_offset; 1172 1173 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1174 return true; 1175 1176 /* Set VERID and PARAM be volatile for reading value in probe */ 1177 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1178 return true; 1179 1180 switch (reg) { 1181 case FSL_SAI_TFR0: 1182 case FSL_SAI_TFR1: 1183 case FSL_SAI_TFR2: 1184 case FSL_SAI_TFR3: 1185 case FSL_SAI_TFR4: 1186 case FSL_SAI_TFR5: 1187 case FSL_SAI_TFR6: 1188 case FSL_SAI_TFR7: 1189 case FSL_SAI_RFR0: 1190 case FSL_SAI_RFR1: 1191 case FSL_SAI_RFR2: 1192 case FSL_SAI_RFR3: 1193 case FSL_SAI_RFR4: 1194 case FSL_SAI_RFR5: 1195 case FSL_SAI_RFR6: 1196 case FSL_SAI_RFR7: 1197 case FSL_SAI_RDR0: 1198 case FSL_SAI_RDR1: 1199 case FSL_SAI_RDR2: 1200 case FSL_SAI_RDR3: 1201 case FSL_SAI_RDR4: 1202 case FSL_SAI_RDR5: 1203 case FSL_SAI_RDR6: 1204 case FSL_SAI_RDR7: 1205 return true; 1206 default: 1207 return false; 1208 } 1209 } 1210 1211 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1212 { 1213 struct fsl_sai *sai = dev_get_drvdata(dev); 1214 unsigned int ofs = sai->soc_data->reg_offset; 1215 1216 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1217 return true; 1218 1219 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1220 return true; 1221 1222 switch (reg) { 1223 case FSL_SAI_TDR0: 1224 case FSL_SAI_TDR1: 1225 case FSL_SAI_TDR2: 1226 case FSL_SAI_TDR3: 1227 case FSL_SAI_TDR4: 1228 case FSL_SAI_TDR5: 1229 case FSL_SAI_TDR6: 1230 case FSL_SAI_TDR7: 1231 case FSL_SAI_TMR: 1232 case FSL_SAI_RMR: 1233 case FSL_SAI_MCTL: 1234 case FSL_SAI_MDIV: 1235 case FSL_SAI_TTCTL: 1236 case FSL_SAI_RTCTL: 1237 return true; 1238 default: 1239 return false; 1240 } 1241 } 1242 1243 static struct regmap_config fsl_sai_regmap_config = { 1244 .reg_bits = 32, 1245 .reg_stride = 4, 1246 .val_bits = 32, 1247 .fast_io = true, 1248 1249 .max_register = FSL_SAI_RMR, 1250 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1251 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1252 .readable_reg = fsl_sai_readable_reg, 1253 .volatile_reg = fsl_sai_volatile_reg, 1254 .writeable_reg = fsl_sai_writeable_reg, 1255 .cache_type = REGCACHE_FLAT, 1256 }; 1257 1258 static int fsl_sai_check_version(struct device *dev) 1259 { 1260 struct fsl_sai *sai = dev_get_drvdata(dev); 1261 unsigned char ofs = sai->soc_data->reg_offset; 1262 unsigned int val; 1263 int ret; 1264 1265 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1266 return 0; 1267 1268 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1269 if (ret < 0) 1270 return ret; 1271 1272 dev_dbg(dev, "VERID: 0x%016X\n", val); 1273 1274 sai->verid.version = val & 1275 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1276 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1277 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1278 1279 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1280 if (ret < 0) 1281 return ret; 1282 1283 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1284 1285 /* Max slots per frame, power of 2 */ 1286 sai->param.slot_num = 1 << 1287 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1288 1289 /* Words per fifo, power of 2 */ 1290 sai->param.fifo_depth = 1 << 1291 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1292 1293 /* Number of datalines implemented */ 1294 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1295 1296 return 0; 1297 } 1298 1299 /* 1300 * Calculate the offset between first two datalines, don't 1301 * different offset in one case. 1302 */ 1303 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1304 { 1305 int fbidx, nbidx, offset; 1306 1307 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1308 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1309 offset = nbidx - fbidx - 1; 1310 1311 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1312 } 1313 1314 /* 1315 * read the fsl,dataline property from dts file. 1316 * It has 3 value for each configuration, first one means the type: 1317 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1318 * dataline mask for 'tx'. for example 1319 * 1320 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1321 * 1322 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1323 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1324 * 1325 */ 1326 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1327 { 1328 struct platform_device *pdev = sai->pdev; 1329 struct device_node *np = pdev->dev.of_node; 1330 struct device *dev = &pdev->dev; 1331 int ret, elems, i, index, num_cfg; 1332 char *propname = "fsl,dataline"; 1333 struct fsl_sai_dl_cfg *cfg; 1334 unsigned long dl_mask; 1335 unsigned int soc_dl; 1336 u32 rx, tx, type; 1337 1338 elems = of_property_count_u32_elems(np, propname); 1339 1340 if (elems <= 0) { 1341 elems = 0; 1342 } else if (elems % 3) { 1343 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1344 return -EINVAL; 1345 } 1346 1347 num_cfg = elems / 3; 1348 /* Add one more for default value */ 1349 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1350 if (!cfg) 1351 return -ENOMEM; 1352 1353 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1354 soc_dl = BIT(sai->soc_data->pins) - 1; 1355 cfg[0].type = FSL_SAI_DL_DEFAULT; 1356 cfg[0].pins[0] = sai->soc_data->pins; 1357 cfg[0].mask[0] = soc_dl; 1358 cfg[0].start_off[0] = 0; 1359 cfg[0].next_off[0] = 0; 1360 1361 cfg[0].pins[1] = sai->soc_data->pins; 1362 cfg[0].mask[1] = soc_dl; 1363 cfg[0].start_off[1] = 0; 1364 cfg[0].next_off[1] = 0; 1365 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1366 /* 1367 * type of dataline 1368 * 0 means default mode 1369 * 1 means I2S mode 1370 * 2 means PDM mode 1371 */ 1372 ret = of_property_read_u32_index(np, propname, index++, &type); 1373 if (ret) 1374 return -EINVAL; 1375 1376 ret = of_property_read_u32_index(np, propname, index++, &rx); 1377 if (ret) 1378 return -EINVAL; 1379 1380 ret = of_property_read_u32_index(np, propname, index++, &tx); 1381 if (ret) 1382 return -EINVAL; 1383 1384 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1385 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1386 return -EINVAL; 1387 } 1388 1389 rx = rx & soc_dl; 1390 tx = tx & soc_dl; 1391 1392 cfg[i].type = type; 1393 cfg[i].pins[0] = hweight8(rx); 1394 cfg[i].mask[0] = rx; 1395 dl_mask = rx; 1396 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1397 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1398 1399 cfg[i].pins[1] = hweight8(tx); 1400 cfg[i].mask[1] = tx; 1401 dl_mask = tx; 1402 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1403 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1404 } 1405 1406 sai->dl_cfg = cfg; 1407 sai->dl_cfg_cnt = num_cfg + 1; 1408 return 0; 1409 } 1410 1411 static int fsl_sai_runtime_suspend(struct device *dev); 1412 static int fsl_sai_runtime_resume(struct device *dev); 1413 1414 static int fsl_sai_probe(struct platform_device *pdev) 1415 { 1416 struct device_node *np = pdev->dev.of_node; 1417 struct device *dev = &pdev->dev; 1418 struct fsl_sai *sai; 1419 struct regmap *gpr; 1420 void __iomem *base; 1421 char tmp[8]; 1422 int irq, ret, i; 1423 int index; 1424 u32 dmas[4]; 1425 1426 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1427 if (!sai) 1428 return -ENOMEM; 1429 1430 sai->pdev = pdev; 1431 sai->soc_data = of_device_get_match_data(dev); 1432 1433 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1434 1435 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1436 if (IS_ERR(base)) 1437 return PTR_ERR(base); 1438 1439 if (sai->soc_data->reg_offset == 8) { 1440 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1441 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1442 fsl_sai_regmap_config.num_reg_defaults = 1443 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1444 } 1445 1446 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1447 if (IS_ERR(sai->regmap)) { 1448 dev_err(dev, "regmap init failed\n"); 1449 return PTR_ERR(sai->regmap); 1450 } 1451 1452 sai->bus_clk = devm_clk_get(dev, "bus"); 1453 /* Compatible with old DTB cases */ 1454 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1455 sai->bus_clk = devm_clk_get(dev, "sai"); 1456 if (IS_ERR(sai->bus_clk)) { 1457 dev_err(dev, "failed to get bus clock: %ld\n", 1458 PTR_ERR(sai->bus_clk)); 1459 /* -EPROBE_DEFER */ 1460 return PTR_ERR(sai->bus_clk); 1461 } 1462 1463 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1464 sprintf(tmp, "mclk%d", i); 1465 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1466 if (IS_ERR(sai->mclk_clk[i])) { 1467 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1468 i, PTR_ERR(sai->mclk_clk[i])); 1469 sai->mclk_clk[i] = NULL; 1470 } 1471 } 1472 1473 if (sai->soc_data->mclk0_is_mclk1) 1474 sai->mclk_clk[0] = sai->mclk_clk[1]; 1475 else 1476 sai->mclk_clk[0] = sai->bus_clk; 1477 1478 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1479 &sai->pll11k_clk); 1480 1481 fsl_asoc_constrain_rates(&sai->constraint_rates, 1482 &fsl_sai_rate_constraints, 1483 sai->pll8k_clk, sai->pll11k_clk, NULL, 1484 sai->constraint_rates_list); 1485 1486 /* Use Multi FIFO mode depending on the support from SDMA script */ 1487 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1488 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1489 sai->is_multi_fifo_dma = true; 1490 1491 /* read dataline mask for rx and tx*/ 1492 ret = fsl_sai_read_dlcfg(sai); 1493 if (ret < 0) { 1494 dev_err(dev, "failed to read dlcfg %d\n", ret); 1495 return ret; 1496 } 1497 1498 irq = platform_get_irq(pdev, 0); 1499 if (irq < 0) 1500 return irq; 1501 1502 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1503 np->name, sai); 1504 if (ret) { 1505 dev_err(dev, "failed to claim irq %u\n", irq); 1506 return ret; 1507 } 1508 1509 memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template, 1510 sizeof(*fsl_sai_dai_template) * ARRAY_SIZE(fsl_sai_dai_template)); 1511 1512 /* Sync Tx with Rx as default by following old DT binding */ 1513 sai->synchronous[RX] = true; 1514 sai->synchronous[TX] = false; 1515 sai->cpu_dai_drv[0].symmetric_rate = 1; 1516 sai->cpu_dai_drv[0].symmetric_channels = 1; 1517 sai->cpu_dai_drv[0].symmetric_sample_bits = 1; 1518 1519 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1520 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1521 /* error out if both synchronous and asynchronous are present */ 1522 dev_err(dev, "invalid binding for synchronous mode\n"); 1523 return -EINVAL; 1524 } 1525 1526 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1527 /* Sync Rx with Tx */ 1528 sai->synchronous[RX] = false; 1529 sai->synchronous[TX] = true; 1530 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1531 /* Discard all settings for asynchronous mode */ 1532 sai->synchronous[RX] = false; 1533 sai->synchronous[TX] = false; 1534 sai->cpu_dai_drv[0].symmetric_rate = 0; 1535 sai->cpu_dai_drv[0].symmetric_channels = 0; 1536 sai->cpu_dai_drv[0].symmetric_sample_bits = 0; 1537 } 1538 1539 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1540 1541 if (sai->mclk_direction_output && 1542 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1543 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1544 if (IS_ERR(gpr)) { 1545 dev_err(dev, "cannot find iomuxc registers\n"); 1546 return PTR_ERR(gpr); 1547 } 1548 1549 index = of_alias_get_id(np, "sai"); 1550 if (index < 0) 1551 return index; 1552 1553 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1554 MCLK_DIR(index)); 1555 } 1556 1557 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1558 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1559 sai->dma_params_rx.maxburst = 1560 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1561 sai->dma_params_tx.maxburst = 1562 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1563 1564 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1565 1566 platform_set_drvdata(pdev, sai); 1567 pm_runtime_enable(dev); 1568 if (!pm_runtime_enabled(dev)) { 1569 ret = fsl_sai_runtime_resume(dev); 1570 if (ret) 1571 goto err_pm_disable; 1572 } 1573 1574 ret = pm_runtime_resume_and_get(dev); 1575 if (ret < 0) 1576 goto err_pm_get_sync; 1577 1578 /* Get sai version */ 1579 ret = fsl_sai_check_version(dev); 1580 if (ret < 0) 1581 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1582 1583 /* Select MCLK direction */ 1584 if (sai->mclk_direction_output && 1585 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1586 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1587 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1588 } 1589 1590 ret = pm_runtime_put_sync(dev); 1591 if (ret < 0 && ret != -ENOSYS) 1592 goto err_pm_get_sync; 1593 1594 /* 1595 * Register platform component before registering cpu dai for there 1596 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1597 */ 1598 if (sai->soc_data->use_imx_pcm) { 1599 ret = imx_pcm_dma_init(pdev); 1600 if (ret) { 1601 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1602 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1603 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1604 goto err_pm_get_sync; 1605 } 1606 } else { 1607 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1608 if (ret) { 1609 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1610 goto err_pm_get_sync; 1611 } 1612 } 1613 1614 ret = devm_snd_soc_register_component(dev, &fsl_component, 1615 sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template)); 1616 if (ret) 1617 goto err_pm_get_sync; 1618 1619 return ret; 1620 1621 err_pm_get_sync: 1622 if (!pm_runtime_status_suspended(dev)) 1623 fsl_sai_runtime_suspend(dev); 1624 err_pm_disable: 1625 pm_runtime_disable(dev); 1626 1627 return ret; 1628 } 1629 1630 static void fsl_sai_remove(struct platform_device *pdev) 1631 { 1632 pm_runtime_disable(&pdev->dev); 1633 if (!pm_runtime_status_suspended(&pdev->dev)) 1634 fsl_sai_runtime_suspend(&pdev->dev); 1635 } 1636 1637 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1638 .use_imx_pcm = false, 1639 .use_edma = false, 1640 .fifo_depth = 32, 1641 .pins = 1, 1642 .reg_offset = 0, 1643 .mclk0_is_mclk1 = false, 1644 .flags = 0, 1645 .max_register = FSL_SAI_RMR, 1646 }; 1647 1648 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1649 .use_imx_pcm = true, 1650 .use_edma = false, 1651 .fifo_depth = 32, 1652 .pins = 1, 1653 .reg_offset = 0, 1654 .mclk0_is_mclk1 = true, 1655 .flags = 0, 1656 .max_register = FSL_SAI_RMR, 1657 }; 1658 1659 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1660 .use_imx_pcm = true, 1661 .use_edma = false, 1662 .fifo_depth = 16, 1663 .pins = 2, 1664 .reg_offset = 8, 1665 .mclk0_is_mclk1 = false, 1666 .flags = PMQOS_CPU_LATENCY, 1667 .max_register = FSL_SAI_RMR, 1668 }; 1669 1670 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1671 .use_imx_pcm = true, 1672 .use_edma = false, 1673 .fifo_depth = 128, 1674 .pins = 8, 1675 .reg_offset = 8, 1676 .mclk0_is_mclk1 = false, 1677 .flags = 0, 1678 .max_register = FSL_SAI_RMR, 1679 }; 1680 1681 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1682 .use_imx_pcm = true, 1683 .use_edma = true, 1684 .fifo_depth = 64, 1685 .pins = 4, 1686 .reg_offset = 0, 1687 .mclk0_is_mclk1 = false, 1688 .flags = 0, 1689 .max_register = FSL_SAI_RMR, 1690 }; 1691 1692 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1693 .use_imx_pcm = true, 1694 .use_edma = false, 1695 .fifo_depth = 128, 1696 .reg_offset = 8, 1697 .mclk0_is_mclk1 = false, 1698 .pins = 8, 1699 .flags = 0, 1700 .max_register = FSL_SAI_MCTL, 1701 }; 1702 1703 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1704 .use_imx_pcm = true, 1705 .use_edma = false, 1706 .fifo_depth = 128, 1707 .reg_offset = 8, 1708 .mclk0_is_mclk1 = false, 1709 .pins = 8, 1710 .flags = 0, 1711 .max_register = FSL_SAI_MDIV, 1712 }; 1713 1714 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1715 .use_imx_pcm = true, 1716 .use_edma = false, 1717 .fifo_depth = 128, 1718 .reg_offset = 8, 1719 .mclk0_is_mclk1 = false, 1720 .pins = 8, 1721 .flags = 0, 1722 .max_register = FSL_SAI_MDIV, 1723 .mclk_with_tere = true, 1724 }; 1725 1726 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1727 .use_imx_pcm = true, 1728 .use_edma = true, 1729 .fifo_depth = 16, 1730 .reg_offset = 8, 1731 .mclk0_is_mclk1 = false, 1732 .pins = 4, 1733 .flags = PMQOS_CPU_LATENCY, 1734 .max_register = FSL_SAI_RTCAP, 1735 }; 1736 1737 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1738 .use_imx_pcm = true, 1739 .use_edma = true, 1740 .fifo_depth = 128, 1741 .reg_offset = 8, 1742 .mclk0_is_mclk1 = false, 1743 .pins = 4, 1744 .flags = 0, 1745 .max_register = FSL_SAI_MCTL, 1746 .max_burst = {8, 8}, 1747 }; 1748 1749 static const struct fsl_sai_soc_data fsl_sai_imx95_data = { 1750 .use_imx_pcm = true, 1751 .use_edma = true, 1752 .fifo_depth = 128, 1753 .reg_offset = 8, 1754 .mclk0_is_mclk1 = false, 1755 .pins = 8, 1756 .flags = 0, 1757 .max_register = FSL_SAI_MCTL, 1758 .max_burst = {8, 8}, 1759 }; 1760 1761 static const struct of_device_id fsl_sai_ids[] = { 1762 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1763 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1764 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1765 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1766 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1767 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1768 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1769 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1770 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1771 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1772 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1773 { .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data }, 1774 { /* sentinel */ } 1775 }; 1776 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1777 1778 static int fsl_sai_runtime_suspend(struct device *dev) 1779 { 1780 struct fsl_sai *sai = dev_get_drvdata(dev); 1781 1782 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1783 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1784 1785 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1786 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1787 1788 clk_disable_unprepare(sai->bus_clk); 1789 1790 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1791 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1792 1793 regcache_cache_only(sai->regmap, true); 1794 1795 return 0; 1796 } 1797 1798 static int fsl_sai_runtime_resume(struct device *dev) 1799 { 1800 struct fsl_sai *sai = dev_get_drvdata(dev); 1801 unsigned int ofs = sai->soc_data->reg_offset; 1802 int ret; 1803 1804 ret = clk_prepare_enable(sai->bus_clk); 1805 if (ret) { 1806 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1807 return ret; 1808 } 1809 1810 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1811 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1812 if (ret) 1813 goto disable_bus_clk; 1814 } 1815 1816 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1817 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1818 if (ret) 1819 goto disable_tx_clk; 1820 } 1821 1822 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1823 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1824 1825 regcache_cache_only(sai->regmap, false); 1826 regcache_mark_dirty(sai->regmap); 1827 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1828 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1829 usleep_range(1000, 2000); 1830 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1831 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1832 1833 ret = regcache_sync(sai->regmap); 1834 if (ret) 1835 goto disable_rx_clk; 1836 1837 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1838 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1839 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1840 1841 return 0; 1842 1843 disable_rx_clk: 1844 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1845 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1846 disable_tx_clk: 1847 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1848 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1849 disable_bus_clk: 1850 clk_disable_unprepare(sai->bus_clk); 1851 1852 return ret; 1853 } 1854 1855 static const struct dev_pm_ops fsl_sai_pm_ops = { 1856 RUNTIME_PM_OPS(fsl_sai_runtime_suspend, fsl_sai_runtime_resume, NULL) 1857 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1858 }; 1859 1860 static struct platform_driver fsl_sai_driver = { 1861 .probe = fsl_sai_probe, 1862 .remove = fsl_sai_remove, 1863 .driver = { 1864 .name = "fsl-sai", 1865 .pm = pm_ptr(&fsl_sai_pm_ops), 1866 .of_match_table = fsl_sai_ids, 1867 }, 1868 }; 1869 module_platform_driver(fsl_sai_driver); 1870 1871 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1872 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1873 MODULE_ALIAS("platform:fsl-sai"); 1874 MODULE_LICENSE("GPL"); 1875