1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 /** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55 { 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60 } 61 62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63 { 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85 } 86 87 static irqreturn_t fsl_sai_isr(int irq, void *devid) 88 { 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) { 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 /* FIFO reset for safety */ 120 xcsr |= FSL_SAI_CSR_FR; 121 } 122 123 if (flags & FSL_SAI_CSR_FWF) 124 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 125 126 if (flags & FSL_SAI_CSR_FRF) 127 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 128 129 flags &= FSL_SAI_CSR_xF_W_MASK; 130 xcsr &= ~FSL_SAI_CSR_xF_MASK; 131 132 if (flags) 133 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 134 135 irq_rx: 136 /* Rx IRQ */ 137 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 138 flags = xcsr & mask; 139 140 if (flags) 141 iret = IRQ_HANDLED; 142 else 143 goto out; 144 145 if (flags & FSL_SAI_CSR_WSF) 146 dev_dbg(dev, "isr: Start of Rx word detected\n"); 147 148 if (flags & FSL_SAI_CSR_SEF) 149 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 150 151 if (flags & FSL_SAI_CSR_FEF) { 152 dev_dbg(dev, "isr: Receive overflow detected\n"); 153 /* FIFO reset for safety */ 154 xcsr |= FSL_SAI_CSR_FR; 155 } 156 157 if (flags & FSL_SAI_CSR_FWF) 158 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 159 160 if (flags & FSL_SAI_CSR_FRF) 161 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 162 163 flags &= FSL_SAI_CSR_xF_W_MASK; 164 xcsr &= ~FSL_SAI_CSR_xF_MASK; 165 166 if (flags) 167 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 168 169 out: 170 return iret; 171 } 172 173 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 174 u32 rx_mask, int slots, int slot_width) 175 { 176 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 177 178 sai->slots = slots; 179 sai->slot_width = slot_width; 180 181 return 0; 182 } 183 184 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 185 unsigned int ratio) 186 { 187 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 188 189 sai->bclk_ratio = ratio; 190 191 return 0; 192 } 193 194 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 195 int clk_id, unsigned int freq, bool tx) 196 { 197 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 198 unsigned int ofs = sai->soc_data->reg_offset; 199 u32 val_cr2 = 0; 200 201 switch (clk_id) { 202 case FSL_SAI_CLK_BUS: 203 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 204 break; 205 case FSL_SAI_CLK_MAST1: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 207 break; 208 case FSL_SAI_CLK_MAST2: 209 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 210 break; 211 case FSL_SAI_CLK_MAST3: 212 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 213 break; 214 default: 215 return -EINVAL; 216 } 217 218 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 219 FSL_SAI_CR2_MSEL_MASK, val_cr2); 220 221 return 0; 222 } 223 224 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 225 { 226 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 227 int ret; 228 229 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 230 sai->pll8k_clk, sai->pll11k_clk, freq); 231 232 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 233 if (ret < 0) 234 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 235 236 return ret; 237 } 238 239 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 240 int clk_id, unsigned int freq, int dir) 241 { 242 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 243 int ret; 244 245 if (dir == SND_SOC_CLOCK_IN) 246 return 0; 247 248 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 249 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 250 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 251 return -EINVAL; 252 } 253 254 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 255 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 256 return -EINVAL; 257 } 258 259 if (sai->mclk_streams == 0) { 260 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 261 if (ret < 0) 262 return ret; 263 } 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 267 if (ret) { 268 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 269 return ret; 270 } 271 272 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 273 if (ret) 274 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 275 276 return ret; 277 } 278 279 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 280 unsigned int fmt, bool tx) 281 { 282 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 283 unsigned int ofs = sai->soc_data->reg_offset; 284 u32 val_cr2 = 0, val_cr4 = 0; 285 286 if (!sai->is_lsb_first) 287 val_cr4 |= FSL_SAI_CR4_MF; 288 289 sai->is_pdm_mode = false; 290 /* DAI mode */ 291 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 292 case SND_SOC_DAIFMT_I2S: 293 /* 294 * Frame low, 1clk before data, one word length for frame sync, 295 * frame sync starts one serial clock cycle earlier, 296 * that is, together with the last bit of the previous 297 * data word. 298 */ 299 val_cr2 |= FSL_SAI_CR2_BCP; 300 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 301 break; 302 case SND_SOC_DAIFMT_LEFT_J: 303 /* 304 * Frame high, one word length for frame sync, 305 * frame sync asserts with the first bit of the frame. 306 */ 307 val_cr2 |= FSL_SAI_CR2_BCP; 308 break; 309 case SND_SOC_DAIFMT_DSP_A: 310 /* 311 * Frame high, 1clk before data, one bit for frame sync, 312 * frame sync starts one serial clock cycle earlier, 313 * that is, together with the last bit of the previous 314 * data word. 315 */ 316 val_cr2 |= FSL_SAI_CR2_BCP; 317 val_cr4 |= FSL_SAI_CR4_FSE; 318 sai->is_dsp_mode = true; 319 break; 320 case SND_SOC_DAIFMT_DSP_B: 321 /* 322 * Frame high, one bit for frame sync, 323 * frame sync asserts with the first bit of the frame. 324 */ 325 val_cr2 |= FSL_SAI_CR2_BCP; 326 sai->is_dsp_mode = true; 327 break; 328 case SND_SOC_DAIFMT_PDM: 329 val_cr2 |= FSL_SAI_CR2_BCP; 330 val_cr4 &= ~FSL_SAI_CR4_MF; 331 sai->is_pdm_mode = true; 332 break; 333 case SND_SOC_DAIFMT_RIGHT_J: 334 /* To be done */ 335 default: 336 return -EINVAL; 337 } 338 339 /* DAI clock inversion */ 340 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 341 case SND_SOC_DAIFMT_IB_IF: 342 /* Invert both clocks */ 343 val_cr2 ^= FSL_SAI_CR2_BCP; 344 val_cr4 ^= FSL_SAI_CR4_FSP; 345 break; 346 case SND_SOC_DAIFMT_IB_NF: 347 /* Invert bit clock */ 348 val_cr2 ^= FSL_SAI_CR2_BCP; 349 break; 350 case SND_SOC_DAIFMT_NB_IF: 351 /* Invert frame clock */ 352 val_cr4 ^= FSL_SAI_CR4_FSP; 353 break; 354 case SND_SOC_DAIFMT_NB_NF: 355 /* Nothing to do for both normal cases */ 356 break; 357 default: 358 return -EINVAL; 359 } 360 361 /* DAI clock provider masks */ 362 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 363 case SND_SOC_DAIFMT_BP_FP: 364 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 365 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 366 sai->is_consumer_mode = false; 367 break; 368 case SND_SOC_DAIFMT_BC_FC: 369 sai->is_consumer_mode = true; 370 break; 371 case SND_SOC_DAIFMT_BP_FC: 372 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 373 sai->is_consumer_mode = false; 374 break; 375 case SND_SOC_DAIFMT_BC_FP: 376 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 377 sai->is_consumer_mode = true; 378 break; 379 default: 380 return -EINVAL; 381 } 382 383 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 384 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 385 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 386 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 387 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 388 389 return 0; 390 } 391 392 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 393 { 394 int ret; 395 396 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 397 if (ret) { 398 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 399 return ret; 400 } 401 402 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 403 if (ret) 404 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 405 406 return ret; 407 } 408 409 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 410 { 411 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 412 unsigned int reg, ofs = sai->soc_data->reg_offset; 413 unsigned long clk_rate; 414 u32 savediv = 0, ratio, bestdiff = freq; 415 int adir = tx ? RX : TX; 416 int dir = tx ? TX : RX; 417 u32 id; 418 bool support_1_1_ratio = sai->verid.version >= 0x0301; 419 420 /* Don't apply to consumer mode */ 421 if (sai->is_consumer_mode) 422 return 0; 423 424 /* 425 * There is no point in polling MCLK0 if it is identical to MCLK1. 426 * And given that MQS use case has to use MCLK1 though two clocks 427 * are the same, we simply skip MCLK0 and start to find from MCLK1. 428 */ 429 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 430 431 for (; id < FSL_SAI_MCLK_MAX; id++) { 432 int diff; 433 434 clk_rate = clk_get_rate(sai->mclk_clk[id]); 435 if (!clk_rate) 436 continue; 437 438 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 439 if (!ratio || ratio > 512) 440 continue; 441 if (ratio == 1 && !support_1_1_ratio) 442 continue; 443 if ((ratio & 1) && ratio > 1) 444 continue; 445 446 diff = abs((long)clk_rate - ratio * freq); 447 448 /* 449 * Drop the source that can not be 450 * divided into the required rate. 451 */ 452 if (diff != 0 && clk_rate / diff < 1000) 453 continue; 454 455 dev_dbg(dai->dev, 456 "ratio %d for freq %dHz based on clock %ldHz\n", 457 ratio, freq, clk_rate); 458 459 460 if (diff < bestdiff) { 461 savediv = ratio; 462 sai->mclk_id[tx] = id; 463 bestdiff = diff; 464 } 465 466 if (diff == 0) 467 break; 468 } 469 470 if (savediv == 0) { 471 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 472 tx ? 'T' : 'R', freq); 473 return -EINVAL; 474 } 475 476 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 477 sai->mclk_id[tx], savediv, bestdiff); 478 479 /* 480 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 481 * set TCR2 register for playback. 482 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 483 * and capture. 484 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 485 * and capture. 486 * 4) For Tx and Rx are both Synchronous with another SAI, we just 487 * ignore it. 488 */ 489 if (fsl_sai_dir_is_synced(sai, adir)) 490 reg = FSL_SAI_xCR2(!tx, ofs); 491 else if (!sai->synchronous[dir]) 492 reg = FSL_SAI_xCR2(tx, ofs); 493 else 494 return 0; 495 496 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 497 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 498 499 if (savediv == 1) 500 regmap_update_bits(sai->regmap, reg, 501 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 502 FSL_SAI_CR2_BYP); 503 else 504 regmap_update_bits(sai->regmap, reg, 505 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 506 savediv / 2 - 1); 507 508 if (sai->soc_data->max_register >= FSL_SAI_MCTL) { 509 /* SAI is in master mode at this point, so enable MCLK */ 510 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 511 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 512 } 513 514 return 0; 515 } 516 517 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 518 struct snd_pcm_hw_params *params, 519 struct snd_soc_dai *cpu_dai) 520 { 521 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 522 unsigned int ofs = sai->soc_data->reg_offset; 523 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 524 unsigned int channels = params_channels(params); 525 struct snd_dmaengine_dai_dma_data *dma_params; 526 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 527 u32 word_width = params_width(params); 528 int trce_mask = 0, dl_cfg_idx = 0; 529 int dl_cfg_cnt = sai->dl_cfg_cnt; 530 u32 dl_type = FSL_SAI_DL_I2S; 531 u32 val_cr4 = 0, val_cr5 = 0; 532 u32 slots = (channels == 1) ? 2 : channels; 533 u32 slot_width = word_width; 534 int adir = tx ? RX : TX; 535 u32 pins, bclk; 536 int ret, i; 537 538 if (sai->slots) 539 slots = sai->slots; 540 541 if (sai->slot_width) 542 slot_width = sai->slot_width; 543 544 pins = DIV_ROUND_UP(channels, slots); 545 546 /* 547 * PDM mode, channels are independent 548 * each channels are on one dataline/FIFO. 549 */ 550 if (sai->is_pdm_mode) { 551 pins = channels; 552 dl_type = FSL_SAI_DL_PDM; 553 } 554 555 for (i = 0; i < dl_cfg_cnt; i++) { 556 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 557 dl_cfg_idx = i; 558 break; 559 } 560 } 561 562 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 563 dev_err(cpu_dai->dev, "channel not supported\n"); 564 return -EINVAL; 565 } 566 567 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 568 569 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 570 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 571 if (!IS_ERR_OR_NULL(sai->pins_state)) { 572 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 573 if (ret) { 574 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 575 return ret; 576 } 577 } 578 } 579 580 if (!sai->is_consumer_mode) { 581 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 582 if (ret) 583 return ret; 584 585 /* Do not enable the clock if it is already enabled */ 586 if (!(sai->mclk_streams & BIT(substream->stream))) { 587 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 588 if (ret) 589 return ret; 590 591 sai->mclk_streams |= BIT(substream->stream); 592 } 593 } 594 595 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 596 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 597 598 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 599 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 600 601 if (sai->is_lsb_first || sai->is_pdm_mode) 602 val_cr5 |= FSL_SAI_CR5_FBT(0); 603 else 604 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 605 606 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 607 608 /* Set to output mode to avoid tri-stated data pins */ 609 if (tx) 610 val_cr4 |= FSL_SAI_CR4_CHMOD; 611 612 /* 613 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 614 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 615 * RCR5(TCR5) for playback(capture), or there will be sync error. 616 */ 617 618 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 619 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 620 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 621 FSL_SAI_CR4_CHMOD_MASK, 622 val_cr4); 623 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 624 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 625 FSL_SAI_CR5_FBT_MASK, val_cr5); 626 } 627 628 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1) 629 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 630 FSL_SAI_CR4_FCOMB_MASK, 0); 631 else 632 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 633 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 634 635 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 636 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 637 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 638 639 /* Find a proper tcre setting */ 640 for (i = 0; i < sai->soc_data->pins; i++) { 641 trce_mask = (1 << (i + 1)) - 1; 642 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 643 break; 644 } 645 646 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 647 FSL_SAI_CR3_TRCE_MASK, 648 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 649 650 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 651 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 652 FSL_SAI_CR4_CHMOD_MASK, 653 val_cr4); 654 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 655 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 656 FSL_SAI_CR5_FBT_MASK, val_cr5); 657 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 658 ~0UL - ((1 << min(channels, slots)) - 1)); 659 660 return 0; 661 } 662 663 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 664 struct snd_soc_dai *cpu_dai) 665 { 666 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 667 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 668 unsigned int ofs = sai->soc_data->reg_offset; 669 670 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 671 FSL_SAI_CR3_TRCE_MASK, 0); 672 673 if (!sai->is_consumer_mode && 674 sai->mclk_streams & BIT(substream->stream)) { 675 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 676 sai->mclk_streams &= ~BIT(substream->stream); 677 } 678 679 return 0; 680 } 681 682 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 683 { 684 unsigned int ofs = sai->soc_data->reg_offset; 685 bool tx = dir == TX; 686 u32 xcsr, count = 100; 687 688 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 689 FSL_SAI_CSR_TERE, 0); 690 691 /* TERE will remain set till the end of current frame */ 692 do { 693 udelay(10); 694 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 695 } while (--count && xcsr & FSL_SAI_CSR_TERE); 696 697 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 698 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 699 700 /* 701 * For sai master mode, after several open/close sai, 702 * there will be no frame clock, and can't recover 703 * anymore. Add software reset to fix this issue. 704 * This is a hardware bug, and will be fix in the 705 * next sai version. 706 */ 707 if (!sai->is_consumer_mode) { 708 /* Software Reset */ 709 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 710 /* Clear SR bit to finish the reset */ 711 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 712 } 713 } 714 715 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 716 struct snd_soc_dai *cpu_dai) 717 { 718 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 719 unsigned int ofs = sai->soc_data->reg_offset; 720 721 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 722 int adir = tx ? RX : TX; 723 int dir = tx ? TX : RX; 724 u32 xcsr; 725 726 /* 727 * Asynchronous mode: Clear SYNC for both Tx and Rx. 728 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 729 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 730 */ 731 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 732 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 733 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 734 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 735 736 /* 737 * It is recommended that the transmitter is the last enabled 738 * and the first disabled. 739 */ 740 switch (cmd) { 741 case SNDRV_PCM_TRIGGER_START: 742 case SNDRV_PCM_TRIGGER_RESUME: 743 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 744 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 745 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 746 747 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 748 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 749 /* 750 * Enable the opposite direction for synchronous mode 751 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 752 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 753 * 754 * RM recommends to enable RE after TE for case 1 and to enable 755 * TE after RE for case 2, but we here may not always guarantee 756 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 757 * TE after RE, which is against what RM recommends but should 758 * be safe to do, judging by years of testing results. 759 */ 760 if (fsl_sai_dir_is_synced(sai, adir)) 761 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 762 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 763 764 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 765 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 766 break; 767 case SNDRV_PCM_TRIGGER_STOP: 768 case SNDRV_PCM_TRIGGER_SUSPEND: 769 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 770 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 771 FSL_SAI_CSR_FRDE, 0); 772 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 773 FSL_SAI_CSR_xIE_MASK, 0); 774 775 /* Check if the opposite FRDE is also disabled */ 776 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 777 778 /* 779 * If opposite stream provides clocks for synchronous mode and 780 * it is inactive, disable it before disabling the current one 781 */ 782 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 783 fsl_sai_config_disable(sai, adir); 784 785 /* 786 * Disable current stream if either of: 787 * 1. current stream doesn't provide clocks for synchronous mode 788 * 2. current stream provides clocks for synchronous mode but no 789 * more stream is active. 790 */ 791 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 792 fsl_sai_config_disable(sai, dir); 793 794 break; 795 default: 796 return -EINVAL; 797 } 798 799 return 0; 800 } 801 802 static int fsl_sai_startup(struct snd_pcm_substream *substream, 803 struct snd_soc_dai *cpu_dai) 804 { 805 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 806 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 807 int ret; 808 809 /* 810 * EDMA controller needs period size to be a multiple of 811 * tx/rx maxburst 812 */ 813 if (sai->soc_data->use_edma) 814 snd_pcm_hw_constraint_step(substream->runtime, 0, 815 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 816 tx ? sai->dma_params_tx.maxburst : 817 sai->dma_params_rx.maxburst); 818 819 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 820 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 821 822 return ret; 823 } 824 825 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 826 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 827 .set_sysclk = fsl_sai_set_dai_sysclk, 828 .set_fmt = fsl_sai_set_dai_fmt, 829 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 830 .hw_params = fsl_sai_hw_params, 831 .hw_free = fsl_sai_hw_free, 832 .trigger = fsl_sai_trigger, 833 .startup = fsl_sai_startup, 834 }; 835 836 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 837 { 838 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 839 unsigned int ofs = sai->soc_data->reg_offset; 840 841 /* Software Reset for both Tx and Rx */ 842 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 843 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 844 /* Clear SR bit to finish the reset */ 845 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 846 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 847 848 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 849 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 850 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 851 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 852 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 853 FSL_SAI_MAXBURST_RX - 1); 854 855 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 856 &sai->dma_params_rx); 857 858 return 0; 859 } 860 861 static int fsl_sai_dai_resume(struct snd_soc_component *component) 862 { 863 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 864 struct device *dev = &sai->pdev->dev; 865 int ret; 866 867 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 868 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 869 if (ret) { 870 dev_err(dev, "failed to set proper pins state: %d\n", ret); 871 return ret; 872 } 873 } 874 875 return 0; 876 } 877 878 static struct snd_soc_dai_driver fsl_sai_dai_template = { 879 .probe = fsl_sai_dai_probe, 880 .playback = { 881 .stream_name = "CPU-Playback", 882 .channels_min = 1, 883 .channels_max = 32, 884 .rate_min = 8000, 885 .rate_max = 2822400, 886 .rates = SNDRV_PCM_RATE_KNOT, 887 .formats = FSL_SAI_FORMATS, 888 }, 889 .capture = { 890 .stream_name = "CPU-Capture", 891 .channels_min = 1, 892 .channels_max = 32, 893 .rate_min = 8000, 894 .rate_max = 2822400, 895 .rates = SNDRV_PCM_RATE_KNOT, 896 .formats = FSL_SAI_FORMATS, 897 }, 898 .ops = &fsl_sai_pcm_dai_ops, 899 }; 900 901 static const struct snd_soc_component_driver fsl_component = { 902 .name = "fsl-sai", 903 .resume = fsl_sai_dai_resume, 904 .legacy_dai_naming = 1, 905 }; 906 907 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 908 {FSL_SAI_TCR1(0), 0}, 909 {FSL_SAI_TCR2(0), 0}, 910 {FSL_SAI_TCR3(0), 0}, 911 {FSL_SAI_TCR4(0), 0}, 912 {FSL_SAI_TCR5(0), 0}, 913 {FSL_SAI_TDR0, 0}, 914 {FSL_SAI_TDR1, 0}, 915 {FSL_SAI_TDR2, 0}, 916 {FSL_SAI_TDR3, 0}, 917 {FSL_SAI_TDR4, 0}, 918 {FSL_SAI_TDR5, 0}, 919 {FSL_SAI_TDR6, 0}, 920 {FSL_SAI_TDR7, 0}, 921 {FSL_SAI_TMR, 0}, 922 {FSL_SAI_RCR1(0), 0}, 923 {FSL_SAI_RCR2(0), 0}, 924 {FSL_SAI_RCR3(0), 0}, 925 {FSL_SAI_RCR4(0), 0}, 926 {FSL_SAI_RCR5(0), 0}, 927 {FSL_SAI_RMR, 0}, 928 }; 929 930 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 931 {FSL_SAI_TCR1(8), 0}, 932 {FSL_SAI_TCR2(8), 0}, 933 {FSL_SAI_TCR3(8), 0}, 934 {FSL_SAI_TCR4(8), 0}, 935 {FSL_SAI_TCR5(8), 0}, 936 {FSL_SAI_TDR0, 0}, 937 {FSL_SAI_TDR1, 0}, 938 {FSL_SAI_TDR2, 0}, 939 {FSL_SAI_TDR3, 0}, 940 {FSL_SAI_TDR4, 0}, 941 {FSL_SAI_TDR5, 0}, 942 {FSL_SAI_TDR6, 0}, 943 {FSL_SAI_TDR7, 0}, 944 {FSL_SAI_TMR, 0}, 945 {FSL_SAI_RCR1(8), 0}, 946 {FSL_SAI_RCR2(8), 0}, 947 {FSL_SAI_RCR3(8), 0}, 948 {FSL_SAI_RCR4(8), 0}, 949 {FSL_SAI_RCR5(8), 0}, 950 {FSL_SAI_RMR, 0}, 951 {FSL_SAI_MCTL, 0}, 952 {FSL_SAI_MDIV, 0}, 953 }; 954 955 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 956 { 957 struct fsl_sai *sai = dev_get_drvdata(dev); 958 unsigned int ofs = sai->soc_data->reg_offset; 959 960 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 961 return true; 962 963 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 964 return true; 965 966 switch (reg) { 967 case FSL_SAI_TFR0: 968 case FSL_SAI_TFR1: 969 case FSL_SAI_TFR2: 970 case FSL_SAI_TFR3: 971 case FSL_SAI_TFR4: 972 case FSL_SAI_TFR5: 973 case FSL_SAI_TFR6: 974 case FSL_SAI_TFR7: 975 case FSL_SAI_TMR: 976 case FSL_SAI_RDR0: 977 case FSL_SAI_RDR1: 978 case FSL_SAI_RDR2: 979 case FSL_SAI_RDR3: 980 case FSL_SAI_RDR4: 981 case FSL_SAI_RDR5: 982 case FSL_SAI_RDR6: 983 case FSL_SAI_RDR7: 984 case FSL_SAI_RFR0: 985 case FSL_SAI_RFR1: 986 case FSL_SAI_RFR2: 987 case FSL_SAI_RFR3: 988 case FSL_SAI_RFR4: 989 case FSL_SAI_RFR5: 990 case FSL_SAI_RFR6: 991 case FSL_SAI_RFR7: 992 case FSL_SAI_RMR: 993 case FSL_SAI_MCTL: 994 case FSL_SAI_MDIV: 995 case FSL_SAI_VERID: 996 case FSL_SAI_PARAM: 997 case FSL_SAI_TTCTN: 998 case FSL_SAI_RTCTN: 999 case FSL_SAI_TTCTL: 1000 case FSL_SAI_TBCTN: 1001 case FSL_SAI_TTCAP: 1002 case FSL_SAI_RTCTL: 1003 case FSL_SAI_RBCTN: 1004 case FSL_SAI_RTCAP: 1005 return true; 1006 default: 1007 return false; 1008 } 1009 } 1010 1011 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1012 { 1013 struct fsl_sai *sai = dev_get_drvdata(dev); 1014 unsigned int ofs = sai->soc_data->reg_offset; 1015 1016 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1017 return true; 1018 1019 /* Set VERID and PARAM be volatile for reading value in probe */ 1020 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1021 return true; 1022 1023 switch (reg) { 1024 case FSL_SAI_TFR0: 1025 case FSL_SAI_TFR1: 1026 case FSL_SAI_TFR2: 1027 case FSL_SAI_TFR3: 1028 case FSL_SAI_TFR4: 1029 case FSL_SAI_TFR5: 1030 case FSL_SAI_TFR6: 1031 case FSL_SAI_TFR7: 1032 case FSL_SAI_RFR0: 1033 case FSL_SAI_RFR1: 1034 case FSL_SAI_RFR2: 1035 case FSL_SAI_RFR3: 1036 case FSL_SAI_RFR4: 1037 case FSL_SAI_RFR5: 1038 case FSL_SAI_RFR6: 1039 case FSL_SAI_RFR7: 1040 case FSL_SAI_RDR0: 1041 case FSL_SAI_RDR1: 1042 case FSL_SAI_RDR2: 1043 case FSL_SAI_RDR3: 1044 case FSL_SAI_RDR4: 1045 case FSL_SAI_RDR5: 1046 case FSL_SAI_RDR6: 1047 case FSL_SAI_RDR7: 1048 return true; 1049 default: 1050 return false; 1051 } 1052 } 1053 1054 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1055 { 1056 struct fsl_sai *sai = dev_get_drvdata(dev); 1057 unsigned int ofs = sai->soc_data->reg_offset; 1058 1059 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1060 return true; 1061 1062 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1063 return true; 1064 1065 switch (reg) { 1066 case FSL_SAI_TDR0: 1067 case FSL_SAI_TDR1: 1068 case FSL_SAI_TDR2: 1069 case FSL_SAI_TDR3: 1070 case FSL_SAI_TDR4: 1071 case FSL_SAI_TDR5: 1072 case FSL_SAI_TDR6: 1073 case FSL_SAI_TDR7: 1074 case FSL_SAI_TMR: 1075 case FSL_SAI_RMR: 1076 case FSL_SAI_MCTL: 1077 case FSL_SAI_MDIV: 1078 case FSL_SAI_TTCTL: 1079 case FSL_SAI_RTCTL: 1080 return true; 1081 default: 1082 return false; 1083 } 1084 } 1085 1086 static struct regmap_config fsl_sai_regmap_config = { 1087 .reg_bits = 32, 1088 .reg_stride = 4, 1089 .val_bits = 32, 1090 .fast_io = true, 1091 1092 .max_register = FSL_SAI_RMR, 1093 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1094 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1095 .readable_reg = fsl_sai_readable_reg, 1096 .volatile_reg = fsl_sai_volatile_reg, 1097 .writeable_reg = fsl_sai_writeable_reg, 1098 .cache_type = REGCACHE_FLAT, 1099 }; 1100 1101 static int fsl_sai_check_version(struct device *dev) 1102 { 1103 struct fsl_sai *sai = dev_get_drvdata(dev); 1104 unsigned char ofs = sai->soc_data->reg_offset; 1105 unsigned int val; 1106 int ret; 1107 1108 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1109 return 0; 1110 1111 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1112 if (ret < 0) 1113 return ret; 1114 1115 dev_dbg(dev, "VERID: 0x%016X\n", val); 1116 1117 sai->verid.version = val & 1118 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1119 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1120 1121 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1122 if (ret < 0) 1123 return ret; 1124 1125 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1126 1127 /* Max slots per frame, power of 2 */ 1128 sai->param.slot_num = 1 << 1129 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1130 1131 /* Words per fifo, power of 2 */ 1132 sai->param.fifo_depth = 1 << 1133 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1134 1135 /* Number of datalines implemented */ 1136 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1137 1138 return 0; 1139 } 1140 1141 /* 1142 * Calculate the offset between first two datalines, don't 1143 * different offset in one case. 1144 */ 1145 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1146 { 1147 int fbidx, nbidx, offset; 1148 1149 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1150 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1151 offset = nbidx - fbidx - 1; 1152 1153 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1154 } 1155 1156 /* 1157 * read the fsl,dataline property from dts file. 1158 * It has 3 value for each configuration, first one means the type: 1159 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1160 * dataline mask for 'tx'. for example 1161 * 1162 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1163 * 1164 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1165 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1166 * 1167 */ 1168 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1169 { 1170 struct platform_device *pdev = sai->pdev; 1171 struct device_node *np = pdev->dev.of_node; 1172 struct device *dev = &pdev->dev; 1173 int ret, elems, i, index, num_cfg; 1174 char *propname = "fsl,dataline"; 1175 struct fsl_sai_dl_cfg *cfg; 1176 unsigned long dl_mask; 1177 unsigned int soc_dl; 1178 u32 rx, tx, type; 1179 1180 elems = of_property_count_u32_elems(np, propname); 1181 1182 if (elems <= 0) { 1183 elems = 0; 1184 } else if (elems % 3) { 1185 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1186 return -EINVAL; 1187 } 1188 1189 num_cfg = elems / 3; 1190 /* Add one more for default value */ 1191 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1192 if (!cfg) 1193 return -ENOMEM; 1194 1195 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1196 soc_dl = BIT(sai->soc_data->pins) - 1; 1197 cfg[0].type = FSL_SAI_DL_DEFAULT; 1198 cfg[0].pins[0] = sai->soc_data->pins; 1199 cfg[0].mask[0] = soc_dl; 1200 cfg[0].start_off[0] = 0; 1201 cfg[0].next_off[0] = 0; 1202 1203 cfg[0].pins[1] = sai->soc_data->pins; 1204 cfg[0].mask[1] = soc_dl; 1205 cfg[0].start_off[1] = 0; 1206 cfg[0].next_off[1] = 0; 1207 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1208 /* 1209 * type of dataline 1210 * 0 means default mode 1211 * 1 means I2S mode 1212 * 2 means PDM mode 1213 */ 1214 ret = of_property_read_u32_index(np, propname, index++, &type); 1215 if (ret) 1216 return -EINVAL; 1217 1218 ret = of_property_read_u32_index(np, propname, index++, &rx); 1219 if (ret) 1220 return -EINVAL; 1221 1222 ret = of_property_read_u32_index(np, propname, index++, &tx); 1223 if (ret) 1224 return -EINVAL; 1225 1226 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1227 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1228 return -EINVAL; 1229 } 1230 1231 rx = rx & soc_dl; 1232 tx = tx & soc_dl; 1233 1234 cfg[i].type = type; 1235 cfg[i].pins[0] = hweight8(rx); 1236 cfg[i].mask[0] = rx; 1237 dl_mask = rx; 1238 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1239 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1240 1241 cfg[i].pins[1] = hweight8(tx); 1242 cfg[i].mask[1] = tx; 1243 dl_mask = tx; 1244 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1245 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1246 } 1247 1248 sai->dl_cfg = cfg; 1249 sai->dl_cfg_cnt = num_cfg + 1; 1250 return 0; 1251 } 1252 1253 static int fsl_sai_runtime_suspend(struct device *dev); 1254 static int fsl_sai_runtime_resume(struct device *dev); 1255 1256 static int fsl_sai_probe(struct platform_device *pdev) 1257 { 1258 struct device_node *np = pdev->dev.of_node; 1259 struct device *dev = &pdev->dev; 1260 struct fsl_sai *sai; 1261 struct regmap *gpr; 1262 void __iomem *base; 1263 char tmp[8]; 1264 int irq, ret, i; 1265 int index; 1266 1267 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1268 if (!sai) 1269 return -ENOMEM; 1270 1271 sai->pdev = pdev; 1272 sai->soc_data = of_device_get_match_data(dev); 1273 1274 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1275 1276 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1277 if (IS_ERR(base)) 1278 return PTR_ERR(base); 1279 1280 if (sai->soc_data->reg_offset == 8) { 1281 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1282 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1283 fsl_sai_regmap_config.num_reg_defaults = 1284 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1285 } 1286 1287 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1288 if (IS_ERR(sai->regmap)) { 1289 dev_err(dev, "regmap init failed\n"); 1290 return PTR_ERR(sai->regmap); 1291 } 1292 1293 sai->bus_clk = devm_clk_get(dev, "bus"); 1294 /* Compatible with old DTB cases */ 1295 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1296 sai->bus_clk = devm_clk_get(dev, "sai"); 1297 if (IS_ERR(sai->bus_clk)) { 1298 dev_err(dev, "failed to get bus clock: %ld\n", 1299 PTR_ERR(sai->bus_clk)); 1300 /* -EPROBE_DEFER */ 1301 return PTR_ERR(sai->bus_clk); 1302 } 1303 1304 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1305 sprintf(tmp, "mclk%d", i); 1306 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1307 if (IS_ERR(sai->mclk_clk[i])) { 1308 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1309 i + 1, PTR_ERR(sai->mclk_clk[i])); 1310 sai->mclk_clk[i] = NULL; 1311 } 1312 } 1313 1314 if (sai->soc_data->mclk0_is_mclk1) 1315 sai->mclk_clk[0] = sai->mclk_clk[1]; 1316 else 1317 sai->mclk_clk[0] = sai->bus_clk; 1318 1319 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1320 &sai->pll11k_clk); 1321 1322 /* read dataline mask for rx and tx*/ 1323 ret = fsl_sai_read_dlcfg(sai); 1324 if (ret < 0) { 1325 dev_err(dev, "failed to read dlcfg %d\n", ret); 1326 return ret; 1327 } 1328 1329 irq = platform_get_irq(pdev, 0); 1330 if (irq < 0) 1331 return irq; 1332 1333 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1334 np->name, sai); 1335 if (ret) { 1336 dev_err(dev, "failed to claim irq %u\n", irq); 1337 return ret; 1338 } 1339 1340 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1341 sizeof(fsl_sai_dai_template)); 1342 1343 /* Sync Tx with Rx as default by following old DT binding */ 1344 sai->synchronous[RX] = true; 1345 sai->synchronous[TX] = false; 1346 sai->cpu_dai_drv.symmetric_rate = 1; 1347 sai->cpu_dai_drv.symmetric_channels = 1; 1348 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1349 1350 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1351 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1352 /* error out if both synchronous and asynchronous are present */ 1353 dev_err(dev, "invalid binding for synchronous mode\n"); 1354 return -EINVAL; 1355 } 1356 1357 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1358 /* Sync Rx with Tx */ 1359 sai->synchronous[RX] = false; 1360 sai->synchronous[TX] = true; 1361 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1362 /* Discard all settings for asynchronous mode */ 1363 sai->synchronous[RX] = false; 1364 sai->synchronous[TX] = false; 1365 sai->cpu_dai_drv.symmetric_rate = 0; 1366 sai->cpu_dai_drv.symmetric_channels = 0; 1367 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1368 } 1369 1370 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1371 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1372 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1373 if (IS_ERR(gpr)) { 1374 dev_err(dev, "cannot find iomuxc registers\n"); 1375 return PTR_ERR(gpr); 1376 } 1377 1378 index = of_alias_get_id(np, "sai"); 1379 if (index < 0) 1380 return index; 1381 1382 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1383 MCLK_DIR(index)); 1384 } 1385 1386 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1387 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1388 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; 1389 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; 1390 1391 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1392 1393 platform_set_drvdata(pdev, sai); 1394 pm_runtime_enable(dev); 1395 if (!pm_runtime_enabled(dev)) { 1396 ret = fsl_sai_runtime_resume(dev); 1397 if (ret) 1398 goto err_pm_disable; 1399 } 1400 1401 ret = pm_runtime_resume_and_get(dev); 1402 if (ret < 0) 1403 goto err_pm_get_sync; 1404 1405 /* Get sai version */ 1406 ret = fsl_sai_check_version(dev); 1407 if (ret < 0) 1408 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1409 1410 /* Select MCLK direction */ 1411 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1412 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1413 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1414 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1415 } 1416 1417 ret = pm_runtime_put_sync(dev); 1418 if (ret < 0) 1419 goto err_pm_get_sync; 1420 1421 /* 1422 * Register platform component before registering cpu dai for there 1423 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1424 */ 1425 if (sai->soc_data->use_imx_pcm) { 1426 ret = imx_pcm_dma_init(pdev); 1427 if (ret) { 1428 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1429 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1430 goto err_pm_get_sync; 1431 } 1432 } else { 1433 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1434 if (ret) 1435 goto err_pm_get_sync; 1436 } 1437 1438 ret = devm_snd_soc_register_component(dev, &fsl_component, 1439 &sai->cpu_dai_drv, 1); 1440 if (ret) 1441 goto err_pm_get_sync; 1442 1443 return ret; 1444 1445 err_pm_get_sync: 1446 if (!pm_runtime_status_suspended(dev)) 1447 fsl_sai_runtime_suspend(dev); 1448 err_pm_disable: 1449 pm_runtime_disable(dev); 1450 1451 return ret; 1452 } 1453 1454 static int fsl_sai_remove(struct platform_device *pdev) 1455 { 1456 pm_runtime_disable(&pdev->dev); 1457 if (!pm_runtime_status_suspended(&pdev->dev)) 1458 fsl_sai_runtime_suspend(&pdev->dev); 1459 1460 return 0; 1461 } 1462 1463 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1464 .use_imx_pcm = false, 1465 .use_edma = false, 1466 .fifo_depth = 32, 1467 .pins = 1, 1468 .reg_offset = 0, 1469 .mclk0_is_mclk1 = false, 1470 .flags = 0, 1471 .max_register = FSL_SAI_RMR, 1472 }; 1473 1474 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1475 .use_imx_pcm = true, 1476 .use_edma = false, 1477 .fifo_depth = 32, 1478 .pins = 1, 1479 .reg_offset = 0, 1480 .mclk0_is_mclk1 = true, 1481 .flags = 0, 1482 .max_register = FSL_SAI_RMR, 1483 }; 1484 1485 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1486 .use_imx_pcm = true, 1487 .use_edma = false, 1488 .fifo_depth = 16, 1489 .pins = 2, 1490 .reg_offset = 8, 1491 .mclk0_is_mclk1 = false, 1492 .flags = PMQOS_CPU_LATENCY, 1493 .max_register = FSL_SAI_RMR, 1494 }; 1495 1496 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1497 .use_imx_pcm = true, 1498 .use_edma = false, 1499 .fifo_depth = 128, 1500 .pins = 8, 1501 .reg_offset = 8, 1502 .mclk0_is_mclk1 = false, 1503 .flags = 0, 1504 .max_register = FSL_SAI_RMR, 1505 }; 1506 1507 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1508 .use_imx_pcm = true, 1509 .use_edma = true, 1510 .fifo_depth = 64, 1511 .pins = 1, 1512 .reg_offset = 0, 1513 .mclk0_is_mclk1 = false, 1514 .flags = 0, 1515 .max_register = FSL_SAI_RMR, 1516 }; 1517 1518 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1519 .use_imx_pcm = true, 1520 .use_edma = false, 1521 .fifo_depth = 128, 1522 .reg_offset = 8, 1523 .mclk0_is_mclk1 = false, 1524 .pins = 8, 1525 .flags = 0, 1526 .max_register = FSL_SAI_MCTL, 1527 }; 1528 1529 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1530 .use_imx_pcm = true, 1531 .use_edma = false, 1532 .fifo_depth = 128, 1533 .reg_offset = 8, 1534 .mclk0_is_mclk1 = false, 1535 .pins = 8, 1536 .flags = 0, 1537 .max_register = FSL_SAI_MDIV, 1538 }; 1539 1540 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1541 .use_imx_pcm = true, 1542 .use_edma = true, 1543 .fifo_depth = 16, 1544 .reg_offset = 8, 1545 .mclk0_is_mclk1 = false, 1546 .pins = 4, 1547 .flags = PMQOS_CPU_LATENCY, 1548 .max_register = FSL_SAI_RTCAP, 1549 }; 1550 1551 static const struct of_device_id fsl_sai_ids[] = { 1552 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1553 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1554 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1555 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1556 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1557 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1558 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1559 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1560 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1561 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mp_data }, 1562 { /* sentinel */ } 1563 }; 1564 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1565 1566 static int fsl_sai_runtime_suspend(struct device *dev) 1567 { 1568 struct fsl_sai *sai = dev_get_drvdata(dev); 1569 1570 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1571 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1572 1573 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1574 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1575 1576 clk_disable_unprepare(sai->bus_clk); 1577 1578 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1579 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1580 1581 regcache_cache_only(sai->regmap, true); 1582 1583 return 0; 1584 } 1585 1586 static int fsl_sai_runtime_resume(struct device *dev) 1587 { 1588 struct fsl_sai *sai = dev_get_drvdata(dev); 1589 unsigned int ofs = sai->soc_data->reg_offset; 1590 int ret; 1591 1592 ret = clk_prepare_enable(sai->bus_clk); 1593 if (ret) { 1594 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1595 return ret; 1596 } 1597 1598 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1599 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1600 if (ret) 1601 goto disable_bus_clk; 1602 } 1603 1604 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1605 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1606 if (ret) 1607 goto disable_tx_clk; 1608 } 1609 1610 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1611 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1612 1613 regcache_cache_only(sai->regmap, false); 1614 regcache_mark_dirty(sai->regmap); 1615 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1616 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1617 usleep_range(1000, 2000); 1618 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1619 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1620 1621 ret = regcache_sync(sai->regmap); 1622 if (ret) 1623 goto disable_rx_clk; 1624 1625 return 0; 1626 1627 disable_rx_clk: 1628 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1629 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1630 disable_tx_clk: 1631 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1632 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1633 disable_bus_clk: 1634 clk_disable_unprepare(sai->bus_clk); 1635 1636 return ret; 1637 } 1638 1639 static const struct dev_pm_ops fsl_sai_pm_ops = { 1640 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1641 fsl_sai_runtime_resume, NULL) 1642 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1643 pm_runtime_force_resume) 1644 }; 1645 1646 static struct platform_driver fsl_sai_driver = { 1647 .probe = fsl_sai_probe, 1648 .remove = fsl_sai_remove, 1649 .driver = { 1650 .name = "fsl-sai", 1651 .pm = &fsl_sai_pm_ops, 1652 .of_match_table = fsl_sai_ids, 1653 }, 1654 }; 1655 module_platform_driver(fsl_sai_driver); 1656 1657 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1658 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1659 MODULE_ALIAS("platform:fsl-sai"); 1660 MODULE_LICENSE("GPL"); 1661