1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/pm_qos.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/time.h> 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 23 24 #include "fsl_sai.h" 25 #include "fsl_utils.h" 26 #include "imx-pcm.h" 27 28 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 29 FSL_SAI_CSR_FEIE) 30 31 static const unsigned int fsl_sai_rates[] = { 32 8000, 11025, 12000, 16000, 22050, 33 24000, 32000, 44100, 48000, 64000, 34 88200, 96000, 176400, 192000, 352800, 35 384000, 705600, 768000, 1411200, 2822400, 36 }; 37 38 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 39 .count = ARRAY_SIZE(fsl_sai_rates), 40 .list = fsl_sai_rates, 41 }; 42 43 /** 44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 45 * 46 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 47 * or Receiver's for both streams. This function is used to check if clocks of 48 * the stream's are synced by the opposite stream. 49 * 50 * @sai: SAI context 51 * @dir: stream direction 52 */ 53 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 54 { 55 int adir = (dir == TX) ? RX : TX; 56 57 /* current dir in async mode while opposite dir in sync mode */ 58 return !sai->synchronous[dir] && sai->synchronous[adir]; 59 } 60 61 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 62 { 63 struct pinctrl_state *state = NULL; 64 65 if (sai->is_pdm_mode) { 66 /* DSD512@44.1kHz, DSD512@48kHz */ 67 if (bclk >= 22579200) 68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 69 70 /* Get default DSD state */ 71 if (IS_ERR_OR_NULL(state)) 72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 73 } else { 74 /* 706k32b2c, 768k32b2c, etc */ 75 if (bclk >= 45158400) 76 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 77 } 78 79 /* Get default state */ 80 if (IS_ERR_OR_NULL(state)) 81 state = pinctrl_lookup_state(sai->pinctrl, "default"); 82 83 return state; 84 } 85 86 static irqreturn_t fsl_sai_isr(int irq, void *devid) 87 { 88 struct fsl_sai *sai = (struct fsl_sai *)devid; 89 unsigned int ofs = sai->soc_data->reg_offset; 90 struct device *dev = &sai->pdev->dev; 91 u32 flags, xcsr, mask; 92 irqreturn_t iret = IRQ_NONE; 93 94 /* 95 * Both IRQ status bits and IRQ mask bits are in the xCSR but 96 * different shifts. And we here create a mask only for those 97 * IRQs that we activated. 98 */ 99 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 100 101 /* Tx IRQ */ 102 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 103 flags = xcsr & mask; 104 105 if (flags) 106 iret = IRQ_HANDLED; 107 else 108 goto irq_rx; 109 110 if (flags & FSL_SAI_CSR_WSF) 111 dev_dbg(dev, "isr: Start of Tx word detected\n"); 112 113 if (flags & FSL_SAI_CSR_SEF) 114 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 115 116 if (flags & FSL_SAI_CSR_FEF) 117 dev_dbg(dev, "isr: Transmit underrun detected\n"); 118 119 if (flags & FSL_SAI_CSR_FWF) 120 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 121 122 if (flags & FSL_SAI_CSR_FRF) 123 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 124 125 flags &= FSL_SAI_CSR_xF_W_MASK; 126 xcsr &= ~FSL_SAI_CSR_xF_MASK; 127 128 if (flags) 129 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 130 131 irq_rx: 132 /* Rx IRQ */ 133 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 134 flags = xcsr & mask; 135 136 if (flags) 137 iret = IRQ_HANDLED; 138 else 139 goto out; 140 141 if (flags & FSL_SAI_CSR_WSF) 142 dev_dbg(dev, "isr: Start of Rx word detected\n"); 143 144 if (flags & FSL_SAI_CSR_SEF) 145 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 146 147 if (flags & FSL_SAI_CSR_FEF) 148 dev_dbg(dev, "isr: Receive overflow detected\n"); 149 150 if (flags & FSL_SAI_CSR_FWF) 151 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 152 153 if (flags & FSL_SAI_CSR_FRF) 154 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 155 156 flags &= FSL_SAI_CSR_xF_W_MASK; 157 xcsr &= ~FSL_SAI_CSR_xF_MASK; 158 159 if (flags) 160 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 161 162 out: 163 return iret; 164 } 165 166 static int fsl_sai_set_dai_tdm_slot_tx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 167 u32 rx_mask, int slots, int slot_width) 168 { 169 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 170 bool tx = true; 171 172 sai->slots[tx] = slots; 173 sai->slot_width[tx] = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_tdm_slot_rx(struct snd_soc_dai *cpu_dai, u32 tx_mask, 179 u32 rx_mask, int slots, int slot_width) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 182 bool tx = false; 183 184 sai->slots[tx] = slots; 185 sai->slot_width[tx] = slot_width; 186 187 return 0; 188 } 189 190 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 191 u32 rx_mask, int slots, int slot_width) 192 { 193 int ret; 194 195 ret = fsl_sai_set_dai_tdm_slot_tx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 196 if (ret) 197 return ret; 198 199 return fsl_sai_set_dai_tdm_slot_rx(cpu_dai, tx_mask, rx_mask, slots, slot_width); 200 } 201 202 static int fsl_sai_xlate_tdm_slot_mask(unsigned int slots, 203 unsigned int *tx_mask, unsigned int *rx_mask) 204 { 205 /* Leave it empty, don't change the value of tx_mask and rx_mask */ 206 return 0; 207 } 208 209 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 210 unsigned int ratio) 211 { 212 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 213 214 sai->bclk_ratio = ratio; 215 216 return 0; 217 } 218 219 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 220 int clk_id, unsigned int freq, bool tx) 221 { 222 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 223 unsigned int ofs = sai->soc_data->reg_offset; 224 u32 val_cr2 = 0; 225 226 switch (clk_id) { 227 case FSL_SAI_CLK_BUS: 228 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 229 break; 230 case FSL_SAI_CLK_MAST1: 231 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 232 break; 233 case FSL_SAI_CLK_MAST2: 234 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 235 break; 236 case FSL_SAI_CLK_MAST3: 237 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 238 break; 239 default: 240 return -EINVAL; 241 } 242 243 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 244 FSL_SAI_CR2_MSEL_MASK, val_cr2); 245 246 return 0; 247 } 248 249 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 250 { 251 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 252 int ret; 253 254 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 255 sai->pll8k_clk, sai->pll11k_clk, freq); 256 257 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 258 if (ret < 0) 259 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 260 261 return ret; 262 } 263 264 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 265 int clk_id, unsigned int freq, int dir) 266 { 267 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 268 int ret; 269 270 if (dir == SND_SOC_CLOCK_IN) 271 return 0; 272 273 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 274 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 275 return -EINVAL; 276 } 277 278 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 279 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 280 return -EINVAL; 281 } 282 283 if (sai->mclk_streams == 0 && freq > 0) { 284 ret = fsl_sai_set_mclk_rate(cpu_dai, 285 clk_id ? clk_id : FSL_SAI_CLK_MAST1, 286 freq); 287 if (ret < 0) 288 return ret; 289 } 290 291 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 292 if (ret) { 293 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 294 return ret; 295 } 296 297 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 298 if (ret) 299 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 300 301 return ret; 302 } 303 304 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 305 unsigned int fmt, bool tx) 306 { 307 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 308 unsigned int ofs = sai->soc_data->reg_offset; 309 u32 val_cr2 = 0, val_cr4 = 0; 310 311 if (!sai->is_lsb_first) 312 val_cr4 |= FSL_SAI_CR4_MF; 313 314 sai->is_pdm_mode = false; 315 sai->is_dsp_mode[tx] = false; 316 /* DAI mode */ 317 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 318 case SND_SOC_DAIFMT_I2S: 319 /* 320 * Frame low, 1clk before data, one word length for frame sync, 321 * frame sync starts one serial clock cycle earlier, 322 * that is, together with the last bit of the previous 323 * data word. 324 */ 325 val_cr2 |= FSL_SAI_CR2_BCP; 326 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 327 break; 328 case SND_SOC_DAIFMT_LEFT_J: 329 /* 330 * Frame high, one word length for frame sync, 331 * frame sync asserts with the first bit of the frame. 332 */ 333 val_cr2 |= FSL_SAI_CR2_BCP; 334 break; 335 case SND_SOC_DAIFMT_DSP_A: 336 /* 337 * Frame high, 1clk before data, one bit for frame sync, 338 * frame sync starts one serial clock cycle earlier, 339 * that is, together with the last bit of the previous 340 * data word. 341 */ 342 val_cr2 |= FSL_SAI_CR2_BCP; 343 val_cr4 |= FSL_SAI_CR4_FSE; 344 sai->is_dsp_mode[tx] = true; 345 break; 346 case SND_SOC_DAIFMT_DSP_B: 347 /* 348 * Frame high, one bit for frame sync, 349 * frame sync asserts with the first bit of the frame. 350 */ 351 val_cr2 |= FSL_SAI_CR2_BCP; 352 sai->is_dsp_mode[tx] = true; 353 break; 354 case SND_SOC_DAIFMT_PDM: 355 val_cr2 |= FSL_SAI_CR2_BCP; 356 sai->is_pdm_mode = true; 357 break; 358 case SND_SOC_DAIFMT_RIGHT_J: 359 /* To be done */ 360 default: 361 return -EINVAL; 362 } 363 364 /* DAI clock inversion */ 365 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 366 case SND_SOC_DAIFMT_IB_IF: 367 /* Invert both clocks */ 368 val_cr2 ^= FSL_SAI_CR2_BCP; 369 val_cr4 ^= FSL_SAI_CR4_FSP; 370 break; 371 case SND_SOC_DAIFMT_IB_NF: 372 /* Invert bit clock */ 373 val_cr2 ^= FSL_SAI_CR2_BCP; 374 break; 375 case SND_SOC_DAIFMT_NB_IF: 376 /* Invert frame clock */ 377 val_cr4 ^= FSL_SAI_CR4_FSP; 378 break; 379 case SND_SOC_DAIFMT_NB_NF: 380 /* Nothing to do for both normal cases */ 381 break; 382 default: 383 return -EINVAL; 384 } 385 386 /* DAI clock provider masks */ 387 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 388 case SND_SOC_DAIFMT_BP_FP: 389 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 390 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 391 sai->is_consumer_mode[tx] = false; 392 break; 393 case SND_SOC_DAIFMT_BC_FC: 394 sai->is_consumer_mode[tx] = true; 395 break; 396 case SND_SOC_DAIFMT_BP_FC: 397 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 398 sai->is_consumer_mode[tx] = false; 399 break; 400 case SND_SOC_DAIFMT_BC_FP: 401 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 402 sai->is_consumer_mode[tx] = true; 403 break; 404 default: 405 return -EINVAL; 406 } 407 408 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 409 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 410 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 411 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 412 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 413 414 return 0; 415 } 416 417 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 418 { 419 int ret; 420 421 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 422 if (ret) { 423 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 424 return ret; 425 } 426 427 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 428 if (ret) 429 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 430 431 return ret; 432 } 433 434 static int fsl_sai_set_dai_fmt_tx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 435 { 436 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 437 } 438 439 static int fsl_sai_set_dai_fmt_rx(struct snd_soc_dai *cpu_dai, unsigned int fmt) 440 { 441 return fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 442 } 443 444 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 445 { 446 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 447 unsigned int reg, ofs = sai->soc_data->reg_offset; 448 unsigned long clk_rate; 449 u32 savediv = 0, ratio, bestdiff = freq; 450 int adir = tx ? RX : TX; 451 int dir = tx ? TX : RX; 452 u32 id; 453 bool support_1_1_ratio = sai->verid.version >= 0x0301; 454 455 /* Don't apply to consumer mode */ 456 if (sai->is_consumer_mode[tx]) 457 return 0; 458 459 /* 460 * There is no point in polling MCLK0 if it is identical to MCLK1. 461 * And given that MQS use case has to use MCLK1 though two clocks 462 * are the same, we simply skip MCLK0 and start to find from MCLK1. 463 */ 464 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 465 466 for (; id < FSL_SAI_MCLK_MAX; id++) { 467 int diff; 468 469 clk_rate = clk_get_rate(sai->mclk_clk[id]); 470 if (!clk_rate) 471 continue; 472 473 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 474 if (!ratio || ratio > 512) 475 continue; 476 if (ratio == 1 && !support_1_1_ratio) 477 continue; 478 if ((ratio & 1) && ratio > 1) 479 continue; 480 481 diff = abs((long)clk_rate - ratio * freq); 482 483 /* 484 * Drop the source that can not be 485 * divided into the required rate. 486 */ 487 if (diff != 0 && clk_rate / diff < 1000) 488 continue; 489 490 dev_dbg(dai->dev, 491 "ratio %d for freq %dHz based on clock %ldHz\n", 492 ratio, freq, clk_rate); 493 494 495 if (diff < bestdiff) { 496 savediv = ratio; 497 sai->mclk_id[tx] = id; 498 bestdiff = diff; 499 } 500 501 if (diff == 0) 502 break; 503 } 504 505 if (savediv == 0) { 506 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 507 tx ? 'T' : 'R', freq); 508 return -EINVAL; 509 } 510 511 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 512 sai->mclk_id[tx], savediv, bestdiff); 513 514 /* 515 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 516 * set TCR2 register for playback. 517 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 518 * and capture. 519 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 520 * and capture. 521 * 4) For Tx and Rx are both Synchronous with another SAI, we just 522 * ignore it. 523 */ 524 if (fsl_sai_dir_is_synced(sai, adir)) 525 reg = FSL_SAI_xCR2(!tx, ofs); 526 else if (!sai->synchronous[dir]) 527 reg = FSL_SAI_xCR2(tx, ofs); 528 else 529 return 0; 530 531 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 532 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 533 534 if (savediv == 1) { 535 regmap_update_bits(sai->regmap, reg, 536 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 537 FSL_SAI_CR2_BYP); 538 if (fsl_sai_dir_is_synced(sai, adir)) 539 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 540 FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); 541 else 542 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 543 FSL_SAI_CR2_BCI, 0); 544 } else { 545 regmap_update_bits(sai->regmap, reg, 546 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 547 savediv / 2 - 1); 548 } 549 550 return 0; 551 } 552 553 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 554 struct snd_pcm_hw_params *params, 555 struct snd_soc_dai *cpu_dai) 556 { 557 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 558 unsigned int ofs = sai->soc_data->reg_offset; 559 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 560 unsigned int channels = params_channels(params); 561 struct snd_dmaengine_dai_dma_data *dma_params; 562 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 563 u32 word_width = params_width(params); 564 int trce_mask = 0, dl_cfg_idx = 0; 565 int dl_cfg_cnt = sai->dl_cfg_cnt; 566 u32 dl_type = FSL_SAI_DL_I2S; 567 u32 val_cr4 = 0, val_cr5 = 0; 568 u32 slots = (channels == 1) ? 2 : channels; 569 u32 slot_width = word_width; 570 int adir = tx ? RX : TX; 571 u32 pins, bclk; 572 u32 watermark; 573 int ret, i; 574 575 if (sai->slot_width[tx]) 576 slot_width = sai->slot_width[tx]; 577 578 if (sai->slots[tx]) 579 slots = sai->slots[tx]; 580 else if (sai->bclk_ratio) 581 slots = sai->bclk_ratio / slot_width; 582 583 pins = DIV_ROUND_UP(channels, slots); 584 585 /* 586 * PDM mode, channels are independent 587 * each channels are on one dataline/FIFO. 588 */ 589 if (sai->is_pdm_mode) { 590 pins = channels; 591 dl_type = FSL_SAI_DL_PDM; 592 } 593 594 for (i = 0; i < dl_cfg_cnt; i++) { 595 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 596 dl_cfg_idx = i; 597 break; 598 } 599 } 600 601 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 602 dev_err(cpu_dai->dev, "channel not supported\n"); 603 return -EINVAL; 604 } 605 606 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 607 608 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 609 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 610 if (!IS_ERR_OR_NULL(sai->pins_state)) { 611 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 612 if (ret) { 613 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 614 return ret; 615 } 616 } 617 } 618 619 if (!sai->is_consumer_mode[tx]) { 620 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 621 if (ret) 622 return ret; 623 624 /* Do not enable the clock if it is already enabled */ 625 if (!(sai->mclk_streams & BIT(substream->stream))) { 626 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 627 if (ret) 628 return ret; 629 630 sai->mclk_streams |= BIT(substream->stream); 631 } 632 } 633 634 if (!sai->is_dsp_mode[tx] && !sai->is_pdm_mode) 635 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 636 637 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 638 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 639 640 if (sai->is_lsb_first) 641 val_cr5 |= FSL_SAI_CR5_FBT(0); 642 else 643 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 644 645 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 646 647 /* Set to avoid channel swap */ 648 val_cr4 |= FSL_SAI_CR4_FCONT; 649 650 /* Set to output mode to avoid tri-stated data pins */ 651 if (tx) 652 val_cr4 |= FSL_SAI_CR4_CHMOD; 653 654 /* 655 * When Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will provide bclk and 656 * frame clock for Tx(Rx). We should set RCR4(TCR4), RCR5(TCR5) 657 * for playback(capture), or there will be sync error. 658 */ 659 660 if (fsl_sai_dir_is_synced(sai, adir)) { 661 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 662 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 663 FSL_SAI_CR4_CHMOD_MASK, 664 val_cr4); 665 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 666 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 667 FSL_SAI_CR5_FBT_MASK, val_cr5); 668 } 669 670 /* 671 * Combine mode has limation: 672 * - Can't used for singel dataline/FIFO case except the FIFO0 673 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 674 * are successive and start from FIFO0 675 * 676 * So for common usage, all multi fifo case disable the combine mode. 677 */ 678 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 679 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 680 FSL_SAI_CR4_FCOMB_MASK, 0); 681 else 682 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 683 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 684 685 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 686 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 687 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 688 689 if (sai->is_multi_fifo_dma) { 690 sai->audio_config[tx].words_per_fifo = min(slots, channels); 691 if (tx) { 692 sai->audio_config[tx].n_fifos_dst = pins; 693 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 694 } else { 695 sai->audio_config[tx].n_fifos_src = pins; 696 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 697 } 698 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 699 dma_params->peripheral_config = &sai->audio_config[tx]; 700 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 701 702 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 703 (dma_params->maxburst - 1); 704 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 705 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 706 watermark); 707 } 708 709 /* Find a proper tcre setting */ 710 for (i = 0; i < sai->soc_data->pins; i++) { 711 trce_mask = (1 << (i + 1)) - 1; 712 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 713 break; 714 } 715 716 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 717 FSL_SAI_CR3_TRCE_MASK, 718 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 719 720 /* 721 * When the TERE and FSD_MSTR enabled before configuring the word width 722 * There will be no frame sync clock issue, because word width impact 723 * the generation of frame sync clock. 724 * 725 * TERE enabled earlier only for i.MX8MP case for the hardware limitation, 726 * We need to disable FSD_MSTR before configuring word width, then enable 727 * FSD_MSTR bit for this specific case. 728 */ 729 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 730 !sai->is_consumer_mode[tx]) 731 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 732 FSL_SAI_CR4_FSD_MSTR, 0); 733 734 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 735 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 736 FSL_SAI_CR4_CHMOD_MASK | FSL_SAI_CR4_FCONT_MASK, 737 val_cr4); 738 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 739 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 740 FSL_SAI_CR5_FBT_MASK, val_cr5); 741 742 /* Enable FSD_MSTR after configuring word width */ 743 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output && 744 !sai->is_consumer_mode[tx]) 745 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 746 FSL_SAI_CR4_FSD_MSTR, FSL_SAI_CR4_FSD_MSTR); 747 748 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 749 ~0UL - ((1 << min(channels, slots)) - 1)); 750 751 return 0; 752 } 753 754 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 755 struct snd_soc_dai *cpu_dai) 756 { 757 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 758 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 759 unsigned int ofs = sai->soc_data->reg_offset; 760 761 /* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ 762 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 0); 763 764 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 765 FSL_SAI_CR3_TRCE_MASK, 0); 766 767 if (!sai->is_consumer_mode[tx] && 768 sai->mclk_streams & BIT(substream->stream)) { 769 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 770 sai->mclk_streams &= ~BIT(substream->stream); 771 } 772 773 return 0; 774 } 775 776 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 777 { 778 unsigned int ofs = sai->soc_data->reg_offset; 779 bool tx = dir == TX; 780 u32 xcsr, count = 100, mask; 781 782 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 783 mask = FSL_SAI_CSR_TERE; 784 else 785 mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE; 786 787 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 788 mask, 0); 789 790 /* TERE will remain set till the end of current frame */ 791 do { 792 udelay(10); 793 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 794 } while (--count && xcsr & FSL_SAI_CSR_TERE); 795 796 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 797 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 798 799 /* 800 * For sai master mode, after several open/close sai, 801 * there will be no frame clock, and can't recover 802 * anymore. Add software reset to fix this issue. 803 * This is a hardware bug, and will be fix in the 804 * next sai version. 805 * 806 * In consumer mode, this can happen even after a 807 * single open/close, especially if both tx and rx 808 * are running concurrently. 809 */ 810 /* Software Reset */ 811 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 812 /* Clear SR bit to finish the reset */ 813 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR, 0); 814 } 815 816 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 817 struct snd_soc_dai *cpu_dai) 818 { 819 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 820 unsigned int ofs = sai->soc_data->reg_offset; 821 822 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 823 int adir = tx ? RX : TX; 824 int dir = tx ? TX : RX; 825 u32 xcsr; 826 827 /* 828 * Asynchronous mode: Clear SYNC for both Tx and Rx. 829 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 830 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 831 */ 832 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 833 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 834 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 835 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 836 837 /* 838 * It is recommended that the transmitter is the last enabled 839 * and the first disabled. 840 */ 841 switch (cmd) { 842 case SNDRV_PCM_TRIGGER_START: 843 case SNDRV_PCM_TRIGGER_RESUME: 844 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 845 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 846 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 847 848 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 849 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 850 /* 851 * Enable the opposite direction for synchronous mode 852 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 853 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 854 * 855 * RM recommends to enable RE after TE for case 1 and to enable 856 * TE after RE for case 2, but we here may not always guarantee 857 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 858 * TE after RE, which is against what RM recommends but should 859 * be safe to do, judging by years of testing results. 860 */ 861 if (fsl_sai_dir_is_synced(sai, adir)) 862 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 863 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 864 865 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 866 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 867 break; 868 case SNDRV_PCM_TRIGGER_STOP: 869 case SNDRV_PCM_TRIGGER_SUSPEND: 870 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 871 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 872 FSL_SAI_CSR_FRDE, 0); 873 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 874 FSL_SAI_CSR_xIE_MASK, 0); 875 876 /* Check if the opposite FRDE is also disabled */ 877 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 878 879 /* 880 * If opposite stream provides clocks for synchronous mode and 881 * it is inactive, disable it before disabling the current one 882 */ 883 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 884 fsl_sai_config_disable(sai, adir); 885 886 /* 887 * Disable current stream if either of: 888 * 1. current stream doesn't provide clocks for synchronous mode 889 * 2. current stream provides clocks for synchronous mode but no 890 * more stream is active. 891 */ 892 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 893 fsl_sai_config_disable(sai, dir); 894 895 break; 896 default: 897 return -EINVAL; 898 } 899 900 return 0; 901 } 902 903 static int fsl_sai_startup(struct snd_pcm_substream *substream, 904 struct snd_soc_dai *cpu_dai) 905 { 906 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 907 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 908 int ret; 909 910 /* 911 * EDMA controller needs period size to be a multiple of 912 * tx/rx maxburst 913 */ 914 if (sai->soc_data->use_edma) 915 snd_pcm_hw_constraint_step(substream->runtime, 0, 916 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 917 tx ? sai->dma_params_tx.maxburst : 918 sai->dma_params_rx.maxburst); 919 920 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 921 SNDRV_PCM_HW_PARAM_RATE, &sai->constraint_rates); 922 923 return ret; 924 } 925 926 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 927 { 928 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 929 unsigned int ofs = sai->soc_data->reg_offset; 930 931 /* Software Reset for both Tx and Rx */ 932 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 933 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 934 /* Clear SR bit to finish the reset */ 935 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0); 936 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0); 937 938 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 939 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 940 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 941 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 942 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 943 sai->dma_params_rx.maxburst - 1); 944 945 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 946 &sai->dma_params_rx); 947 948 return 0; 949 } 950 951 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 952 .probe = fsl_sai_dai_probe, 953 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 954 .set_sysclk = fsl_sai_set_dai_sysclk, 955 .set_fmt = fsl_sai_set_dai_fmt, 956 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 957 .hw_params = fsl_sai_hw_params, 958 .hw_free = fsl_sai_hw_free, 959 .trigger = fsl_sai_trigger, 960 .startup = fsl_sai_startup, 961 }; 962 963 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_tx_ops = { 964 .probe = fsl_sai_dai_probe, 965 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 966 .set_sysclk = fsl_sai_set_dai_sysclk, 967 .set_fmt = fsl_sai_set_dai_fmt_tx, 968 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_tx, 969 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 970 .hw_params = fsl_sai_hw_params, 971 .hw_free = fsl_sai_hw_free, 972 .trigger = fsl_sai_trigger, 973 .startup = fsl_sai_startup, 974 }; 975 976 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_rx_ops = { 977 .probe = fsl_sai_dai_probe, 978 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 979 .set_sysclk = fsl_sai_set_dai_sysclk, 980 .set_fmt = fsl_sai_set_dai_fmt_rx, 981 .set_tdm_slot = fsl_sai_set_dai_tdm_slot_rx, 982 .xlate_tdm_slot_mask = fsl_sai_xlate_tdm_slot_mask, 983 .hw_params = fsl_sai_hw_params, 984 .hw_free = fsl_sai_hw_free, 985 .trigger = fsl_sai_trigger, 986 .startup = fsl_sai_startup, 987 }; 988 989 static int fsl_sai_dai_resume(struct snd_soc_component *component) 990 { 991 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 992 struct device *dev = &sai->pdev->dev; 993 int ret; 994 995 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 996 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 997 if (ret) { 998 dev_err(dev, "failed to set proper pins state: %d\n", ret); 999 return ret; 1000 } 1001 } 1002 1003 return 0; 1004 } 1005 1006 static struct snd_soc_dai_driver fsl_sai_dai_template[] = { 1007 { 1008 .name = "sai-tx-rx", 1009 .playback = { 1010 .stream_name = "CPU-Playback", 1011 .channels_min = 1, 1012 .channels_max = 32, 1013 .rate_min = 8000, 1014 .rate_max = 2822400, 1015 .rates = SNDRV_PCM_RATE_KNOT, 1016 .formats = FSL_SAI_FORMATS, 1017 }, 1018 .capture = { 1019 .stream_name = "CPU-Capture", 1020 .channels_min = 1, 1021 .channels_max = 32, 1022 .rate_min = 8000, 1023 .rate_max = 2822400, 1024 .rates = SNDRV_PCM_RATE_KNOT, 1025 .formats = FSL_SAI_FORMATS, 1026 }, 1027 .ops = &fsl_sai_pcm_dai_ops, 1028 }, 1029 { 1030 .name = "sai-tx", 1031 .playback = { 1032 .stream_name = "SAI-Playback", 1033 .channels_min = 1, 1034 .channels_max = 32, 1035 .rate_min = 8000, 1036 .rate_max = 2822400, 1037 .rates = SNDRV_PCM_RATE_KNOT, 1038 .formats = FSL_SAI_FORMATS, 1039 }, 1040 .ops = &fsl_sai_pcm_dai_tx_ops, 1041 }, 1042 { 1043 .name = "sai-rx", 1044 .capture = { 1045 .stream_name = "SAI-Capture", 1046 .channels_min = 1, 1047 .channels_max = 32, 1048 .rate_min = 8000, 1049 .rate_max = 2822400, 1050 .rates = SNDRV_PCM_RATE_KNOT, 1051 .formats = FSL_SAI_FORMATS, 1052 }, 1053 .ops = &fsl_sai_pcm_dai_rx_ops, 1054 }, 1055 }; 1056 1057 static const struct snd_soc_component_driver fsl_component = { 1058 .name = "fsl-sai", 1059 .resume = fsl_sai_dai_resume, 1060 .legacy_dai_naming = 1, 1061 }; 1062 1063 static const struct reg_default fsl_sai_reg_defaults_ofs0[] = { 1064 {FSL_SAI_TCR1(0), 0}, 1065 {FSL_SAI_TCR2(0), 0}, 1066 {FSL_SAI_TCR3(0), 0}, 1067 {FSL_SAI_TCR4(0), 0}, 1068 {FSL_SAI_TCR5(0), 0}, 1069 {FSL_SAI_TDR0, 0}, 1070 {FSL_SAI_TDR1, 0}, 1071 {FSL_SAI_TDR2, 0}, 1072 {FSL_SAI_TDR3, 0}, 1073 {FSL_SAI_TDR4, 0}, 1074 {FSL_SAI_TDR5, 0}, 1075 {FSL_SAI_TDR6, 0}, 1076 {FSL_SAI_TDR7, 0}, 1077 {FSL_SAI_TMR, 0}, 1078 {FSL_SAI_RCR1(0), 0}, 1079 {FSL_SAI_RCR2(0), 0}, 1080 {FSL_SAI_RCR3(0), 0}, 1081 {FSL_SAI_RCR4(0), 0}, 1082 {FSL_SAI_RCR5(0), 0}, 1083 {FSL_SAI_RMR, 0}, 1084 }; 1085 1086 static const struct reg_default fsl_sai_reg_defaults_ofs8[] = { 1087 {FSL_SAI_TCR1(8), 0}, 1088 {FSL_SAI_TCR2(8), 0}, 1089 {FSL_SAI_TCR3(8), 0}, 1090 {FSL_SAI_TCR4(8), 0}, 1091 {FSL_SAI_TCR5(8), 0}, 1092 {FSL_SAI_TDR0, 0}, 1093 {FSL_SAI_TDR1, 0}, 1094 {FSL_SAI_TDR2, 0}, 1095 {FSL_SAI_TDR3, 0}, 1096 {FSL_SAI_TDR4, 0}, 1097 {FSL_SAI_TDR5, 0}, 1098 {FSL_SAI_TDR6, 0}, 1099 {FSL_SAI_TDR7, 0}, 1100 {FSL_SAI_TMR, 0}, 1101 {FSL_SAI_RCR1(8), 0}, 1102 {FSL_SAI_RCR2(8), 0}, 1103 {FSL_SAI_RCR3(8), 0}, 1104 {FSL_SAI_RCR4(8), 0}, 1105 {FSL_SAI_RCR5(8), 0}, 1106 {FSL_SAI_RMR, 0}, 1107 {FSL_SAI_MCTL, 0}, 1108 {FSL_SAI_MDIV, 0}, 1109 }; 1110 1111 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 1112 { 1113 struct fsl_sai *sai = dev_get_drvdata(dev); 1114 unsigned int ofs = sai->soc_data->reg_offset; 1115 1116 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1117 return true; 1118 1119 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1120 return true; 1121 1122 switch (reg) { 1123 case FSL_SAI_TFR0: 1124 case FSL_SAI_TFR1: 1125 case FSL_SAI_TFR2: 1126 case FSL_SAI_TFR3: 1127 case FSL_SAI_TFR4: 1128 case FSL_SAI_TFR5: 1129 case FSL_SAI_TFR6: 1130 case FSL_SAI_TFR7: 1131 case FSL_SAI_TMR: 1132 case FSL_SAI_RDR0: 1133 case FSL_SAI_RDR1: 1134 case FSL_SAI_RDR2: 1135 case FSL_SAI_RDR3: 1136 case FSL_SAI_RDR4: 1137 case FSL_SAI_RDR5: 1138 case FSL_SAI_RDR6: 1139 case FSL_SAI_RDR7: 1140 case FSL_SAI_RFR0: 1141 case FSL_SAI_RFR1: 1142 case FSL_SAI_RFR2: 1143 case FSL_SAI_RFR3: 1144 case FSL_SAI_RFR4: 1145 case FSL_SAI_RFR5: 1146 case FSL_SAI_RFR6: 1147 case FSL_SAI_RFR7: 1148 case FSL_SAI_RMR: 1149 case FSL_SAI_MCTL: 1150 case FSL_SAI_MDIV: 1151 case FSL_SAI_VERID: 1152 case FSL_SAI_PARAM: 1153 case FSL_SAI_TTCTN: 1154 case FSL_SAI_RTCTN: 1155 case FSL_SAI_TTCTL: 1156 case FSL_SAI_TBCTN: 1157 case FSL_SAI_TTCAP: 1158 case FSL_SAI_RTCTL: 1159 case FSL_SAI_RBCTN: 1160 case FSL_SAI_RTCAP: 1161 return true; 1162 default: 1163 return false; 1164 } 1165 } 1166 1167 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1168 { 1169 struct fsl_sai *sai = dev_get_drvdata(dev); 1170 unsigned int ofs = sai->soc_data->reg_offset; 1171 1172 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1173 return true; 1174 1175 /* Set VERID and PARAM be volatile for reading value in probe */ 1176 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1177 return true; 1178 1179 switch (reg) { 1180 case FSL_SAI_TFR0: 1181 case FSL_SAI_TFR1: 1182 case FSL_SAI_TFR2: 1183 case FSL_SAI_TFR3: 1184 case FSL_SAI_TFR4: 1185 case FSL_SAI_TFR5: 1186 case FSL_SAI_TFR6: 1187 case FSL_SAI_TFR7: 1188 case FSL_SAI_RFR0: 1189 case FSL_SAI_RFR1: 1190 case FSL_SAI_RFR2: 1191 case FSL_SAI_RFR3: 1192 case FSL_SAI_RFR4: 1193 case FSL_SAI_RFR5: 1194 case FSL_SAI_RFR6: 1195 case FSL_SAI_RFR7: 1196 case FSL_SAI_RDR0: 1197 case FSL_SAI_RDR1: 1198 case FSL_SAI_RDR2: 1199 case FSL_SAI_RDR3: 1200 case FSL_SAI_RDR4: 1201 case FSL_SAI_RDR5: 1202 case FSL_SAI_RDR6: 1203 case FSL_SAI_RDR7: 1204 return true; 1205 default: 1206 return false; 1207 } 1208 } 1209 1210 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1211 { 1212 struct fsl_sai *sai = dev_get_drvdata(dev); 1213 unsigned int ofs = sai->soc_data->reg_offset; 1214 1215 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1216 return true; 1217 1218 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1219 return true; 1220 1221 switch (reg) { 1222 case FSL_SAI_TDR0: 1223 case FSL_SAI_TDR1: 1224 case FSL_SAI_TDR2: 1225 case FSL_SAI_TDR3: 1226 case FSL_SAI_TDR4: 1227 case FSL_SAI_TDR5: 1228 case FSL_SAI_TDR6: 1229 case FSL_SAI_TDR7: 1230 case FSL_SAI_TMR: 1231 case FSL_SAI_RMR: 1232 case FSL_SAI_MCTL: 1233 case FSL_SAI_MDIV: 1234 case FSL_SAI_TTCTL: 1235 case FSL_SAI_RTCTL: 1236 return true; 1237 default: 1238 return false; 1239 } 1240 } 1241 1242 static struct regmap_config fsl_sai_regmap_config = { 1243 .reg_bits = 32, 1244 .reg_stride = 4, 1245 .val_bits = 32, 1246 1247 .max_register = FSL_SAI_RMR, 1248 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1249 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1250 .readable_reg = fsl_sai_readable_reg, 1251 .volatile_reg = fsl_sai_volatile_reg, 1252 .writeable_reg = fsl_sai_writeable_reg, 1253 .cache_type = REGCACHE_FLAT, 1254 }; 1255 1256 static int fsl_sai_check_version(struct device *dev) 1257 { 1258 struct fsl_sai *sai = dev_get_drvdata(dev); 1259 unsigned char ofs = sai->soc_data->reg_offset; 1260 unsigned int val; 1261 int ret; 1262 1263 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1264 return 0; 1265 1266 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1267 if (ret < 0) 1268 return ret; 1269 1270 dev_dbg(dev, "VERID: 0x%016X\n", val); 1271 1272 sai->verid.version = val & 1273 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1274 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1275 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1276 1277 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1278 if (ret < 0) 1279 return ret; 1280 1281 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1282 1283 /* Max slots per frame, power of 2 */ 1284 sai->param.slot_num = 1 << 1285 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1286 1287 /* Words per fifo, power of 2 */ 1288 sai->param.fifo_depth = 1 << 1289 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1290 1291 /* Number of datalines implemented */ 1292 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1293 1294 return 0; 1295 } 1296 1297 /* 1298 * Calculate the offset between first two datalines, don't 1299 * different offset in one case. 1300 */ 1301 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1302 { 1303 int fbidx, nbidx, offset; 1304 1305 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1306 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1307 offset = nbidx - fbidx - 1; 1308 1309 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1310 } 1311 1312 /* 1313 * read the fsl,dataline property from dts file. 1314 * It has 3 value for each configuration, first one means the type: 1315 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1316 * dataline mask for 'tx'. for example 1317 * 1318 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1319 * 1320 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1321 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1322 * 1323 */ 1324 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1325 { 1326 struct platform_device *pdev = sai->pdev; 1327 struct device_node *np = pdev->dev.of_node; 1328 struct device *dev = &pdev->dev; 1329 int ret, elems, i, index, num_cfg; 1330 char *propname = "fsl,dataline"; 1331 struct fsl_sai_dl_cfg *cfg; 1332 unsigned long dl_mask; 1333 unsigned int soc_dl; 1334 u32 rx, tx, type; 1335 1336 elems = of_property_count_u32_elems(np, propname); 1337 1338 if (elems <= 0) { 1339 elems = 0; 1340 } else if (elems % 3) { 1341 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1342 return -EINVAL; 1343 } 1344 1345 num_cfg = elems / 3; 1346 /* Add one more for default value */ 1347 cfg = devm_kcalloc(&pdev->dev, num_cfg + 1, sizeof(*cfg), GFP_KERNEL); 1348 if (!cfg) 1349 return -ENOMEM; 1350 1351 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1352 soc_dl = BIT(sai->soc_data->pins) - 1; 1353 cfg[0].type = FSL_SAI_DL_DEFAULT; 1354 cfg[0].pins[0] = sai->soc_data->pins; 1355 cfg[0].mask[0] = soc_dl; 1356 cfg[0].start_off[0] = 0; 1357 cfg[0].next_off[0] = 0; 1358 1359 cfg[0].pins[1] = sai->soc_data->pins; 1360 cfg[0].mask[1] = soc_dl; 1361 cfg[0].start_off[1] = 0; 1362 cfg[0].next_off[1] = 0; 1363 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1364 /* 1365 * type of dataline 1366 * 0 means default mode 1367 * 1 means I2S mode 1368 * 2 means PDM mode 1369 */ 1370 ret = of_property_read_u32_index(np, propname, index++, &type); 1371 if (ret) 1372 return -EINVAL; 1373 1374 ret = of_property_read_u32_index(np, propname, index++, &rx); 1375 if (ret) 1376 return -EINVAL; 1377 1378 ret = of_property_read_u32_index(np, propname, index++, &tx); 1379 if (ret) 1380 return -EINVAL; 1381 1382 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1383 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1384 return -EINVAL; 1385 } 1386 1387 rx = rx & soc_dl; 1388 tx = tx & soc_dl; 1389 1390 cfg[i].type = type; 1391 cfg[i].pins[0] = hweight8(rx); 1392 cfg[i].mask[0] = rx; 1393 dl_mask = rx; 1394 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1395 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1396 1397 cfg[i].pins[1] = hweight8(tx); 1398 cfg[i].mask[1] = tx; 1399 dl_mask = tx; 1400 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1401 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1402 } 1403 1404 sai->dl_cfg = cfg; 1405 sai->dl_cfg_cnt = num_cfg + 1; 1406 return 0; 1407 } 1408 1409 static int fsl_sai_runtime_suspend(struct device *dev); 1410 static int fsl_sai_runtime_resume(struct device *dev); 1411 1412 static int fsl_sai_probe(struct platform_device *pdev) 1413 { 1414 struct device_node *np = pdev->dev.of_node; 1415 struct device *dev = &pdev->dev; 1416 struct fsl_sai *sai; 1417 struct regmap *gpr; 1418 void __iomem *base; 1419 char tmp[8]; 1420 int irq, ret, i; 1421 int index; 1422 u32 dmas[4]; 1423 1424 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1425 if (!sai) 1426 return -ENOMEM; 1427 1428 sai->pdev = pdev; 1429 sai->soc_data = of_device_get_match_data(dev); 1430 1431 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1432 1433 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1434 if (IS_ERR(base)) 1435 return PTR_ERR(base); 1436 1437 if (sai->soc_data->reg_offset == 8) { 1438 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1439 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1440 fsl_sai_regmap_config.num_reg_defaults = 1441 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1442 } 1443 1444 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1445 if (IS_ERR(sai->regmap)) { 1446 dev_err(dev, "regmap init failed\n"); 1447 return PTR_ERR(sai->regmap); 1448 } 1449 1450 sai->bus_clk = devm_clk_get(dev, "bus"); 1451 /* Compatible with old DTB cases */ 1452 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1453 sai->bus_clk = devm_clk_get(dev, "sai"); 1454 if (IS_ERR(sai->bus_clk)) { 1455 dev_err(dev, "failed to get bus clock: %ld\n", 1456 PTR_ERR(sai->bus_clk)); 1457 /* -EPROBE_DEFER */ 1458 return PTR_ERR(sai->bus_clk); 1459 } 1460 1461 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1462 sprintf(tmp, "mclk%d", i); 1463 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1464 if (IS_ERR(sai->mclk_clk[i])) { 1465 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1466 i, PTR_ERR(sai->mclk_clk[i])); 1467 sai->mclk_clk[i] = NULL; 1468 } 1469 } 1470 1471 if (sai->soc_data->mclk0_is_mclk1) 1472 sai->mclk_clk[0] = sai->mclk_clk[1]; 1473 else 1474 sai->mclk_clk[0] = sai->bus_clk; 1475 1476 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1477 &sai->pll11k_clk); 1478 1479 fsl_asoc_constrain_rates(&sai->constraint_rates, 1480 &fsl_sai_rate_constraints, 1481 sai->pll8k_clk, sai->pll11k_clk, NULL, 1482 sai->constraint_rates_list); 1483 1484 /* Use Multi FIFO mode depending on the support from SDMA script */ 1485 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1486 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1487 sai->is_multi_fifo_dma = true; 1488 1489 /* read dataline mask for rx and tx*/ 1490 ret = fsl_sai_read_dlcfg(sai); 1491 if (ret < 0) { 1492 dev_err(dev, "failed to read dlcfg %d\n", ret); 1493 return ret; 1494 } 1495 1496 irq = platform_get_irq(pdev, 0); 1497 if (irq < 0) 1498 return irq; 1499 1500 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1501 np->name, sai); 1502 if (ret) { 1503 dev_err(dev, "failed to claim irq %u\n", irq); 1504 return ret; 1505 } 1506 1507 memcpy(&sai->cpu_dai_drv, fsl_sai_dai_template, 1508 sizeof(*fsl_sai_dai_template) * ARRAY_SIZE(fsl_sai_dai_template)); 1509 1510 /* Sync Tx with Rx as default by following old DT binding */ 1511 sai->synchronous[RX] = true; 1512 sai->synchronous[TX] = false; 1513 sai->cpu_dai_drv[0].symmetric_rate = 1; 1514 sai->cpu_dai_drv[0].symmetric_channels = 1; 1515 sai->cpu_dai_drv[0].symmetric_sample_bits = 1; 1516 1517 if (of_property_read_bool(np, "fsl,sai-synchronous-rx") && 1518 of_property_read_bool(np, "fsl,sai-asynchronous")) { 1519 /* error out if both synchronous and asynchronous are present */ 1520 dev_err(dev, "invalid binding for synchronous mode\n"); 1521 return -EINVAL; 1522 } 1523 1524 if (of_property_read_bool(np, "fsl,sai-synchronous-rx")) { 1525 /* Sync Rx with Tx */ 1526 sai->synchronous[RX] = false; 1527 sai->synchronous[TX] = true; 1528 } else if (of_property_read_bool(np, "fsl,sai-asynchronous")) { 1529 /* Discard all settings for asynchronous mode */ 1530 sai->synchronous[RX] = false; 1531 sai->synchronous[TX] = false; 1532 sai->cpu_dai_drv[0].symmetric_rate = 0; 1533 sai->cpu_dai_drv[0].symmetric_channels = 0; 1534 sai->cpu_dai_drv[0].symmetric_sample_bits = 0; 1535 } 1536 1537 sai->mclk_direction_output = of_property_read_bool(np, "fsl,sai-mclk-direction-output"); 1538 1539 if (sai->mclk_direction_output && 1540 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1541 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1542 if (IS_ERR(gpr)) { 1543 dev_err(dev, "cannot find iomuxc registers\n"); 1544 return PTR_ERR(gpr); 1545 } 1546 1547 index = of_alias_get_id(np, "sai"); 1548 if (index < 0) 1549 return index; 1550 1551 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1552 MCLK_DIR(index)); 1553 } 1554 1555 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1556 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1557 sai->dma_params_rx.maxburst = 1558 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1559 sai->dma_params_tx.maxburst = 1560 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1561 1562 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1563 1564 platform_set_drvdata(pdev, sai); 1565 pm_runtime_enable(dev); 1566 if (!pm_runtime_enabled(dev)) { 1567 ret = fsl_sai_runtime_resume(dev); 1568 if (ret) 1569 goto err_pm_disable; 1570 } 1571 1572 ret = pm_runtime_resume_and_get(dev); 1573 if (ret < 0) 1574 goto err_pm_get_sync; 1575 1576 /* Get sai version */ 1577 ret = fsl_sai_check_version(dev); 1578 if (ret < 0) 1579 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1580 1581 /* Select MCLK direction */ 1582 if (sai->mclk_direction_output && 1583 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1584 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1585 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1586 } 1587 1588 ret = pm_runtime_put_sync(dev); 1589 if (ret < 0 && ret != -ENOSYS) 1590 goto err_pm_get_sync; 1591 1592 /* 1593 * Register platform component before registering cpu dai for there 1594 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1595 */ 1596 if (sai->soc_data->use_imx_pcm) { 1597 ret = imx_pcm_dma_init(pdev); 1598 if (ret) { 1599 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1600 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1601 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1602 goto err_pm_get_sync; 1603 } 1604 } else { 1605 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1606 if (ret) { 1607 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1608 goto err_pm_get_sync; 1609 } 1610 } 1611 1612 ret = devm_snd_soc_register_component(dev, &fsl_component, 1613 sai->cpu_dai_drv, ARRAY_SIZE(fsl_sai_dai_template)); 1614 if (ret) 1615 goto err_pm_get_sync; 1616 1617 return ret; 1618 1619 err_pm_get_sync: 1620 if (!pm_runtime_status_suspended(dev)) 1621 fsl_sai_runtime_suspend(dev); 1622 err_pm_disable: 1623 pm_runtime_disable(dev); 1624 1625 return ret; 1626 } 1627 1628 static void fsl_sai_remove(struct platform_device *pdev) 1629 { 1630 pm_runtime_disable(&pdev->dev); 1631 if (!pm_runtime_status_suspended(&pdev->dev)) 1632 fsl_sai_runtime_suspend(&pdev->dev); 1633 } 1634 1635 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1636 .use_imx_pcm = false, 1637 .use_edma = false, 1638 .fifo_depth = 32, 1639 .pins = 1, 1640 .reg_offset = 0, 1641 .mclk0_is_mclk1 = false, 1642 .flags = 0, 1643 .max_register = FSL_SAI_RMR, 1644 }; 1645 1646 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1647 .use_imx_pcm = true, 1648 .use_edma = false, 1649 .fifo_depth = 32, 1650 .pins = 1, 1651 .reg_offset = 0, 1652 .mclk0_is_mclk1 = true, 1653 .flags = 0, 1654 .max_register = FSL_SAI_RMR, 1655 }; 1656 1657 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1658 .use_imx_pcm = true, 1659 .use_edma = false, 1660 .fifo_depth = 16, 1661 .pins = 2, 1662 .reg_offset = 8, 1663 .mclk0_is_mclk1 = false, 1664 .flags = PMQOS_CPU_LATENCY, 1665 .max_register = FSL_SAI_RMR, 1666 }; 1667 1668 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1669 .use_imx_pcm = true, 1670 .use_edma = false, 1671 .fifo_depth = 128, 1672 .pins = 8, 1673 .reg_offset = 8, 1674 .mclk0_is_mclk1 = false, 1675 .flags = 0, 1676 .max_register = FSL_SAI_RMR, 1677 }; 1678 1679 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1680 .use_imx_pcm = true, 1681 .use_edma = true, 1682 .fifo_depth = 64, 1683 .pins = 4, 1684 .reg_offset = 0, 1685 .mclk0_is_mclk1 = false, 1686 .flags = 0, 1687 .max_register = FSL_SAI_RMR, 1688 }; 1689 1690 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1691 .use_imx_pcm = true, 1692 .use_edma = false, 1693 .fifo_depth = 128, 1694 .reg_offset = 8, 1695 .mclk0_is_mclk1 = false, 1696 .pins = 8, 1697 .flags = 0, 1698 .max_register = FSL_SAI_MCTL, 1699 }; 1700 1701 static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = { 1702 .use_imx_pcm = true, 1703 .use_edma = false, 1704 .fifo_depth = 128, 1705 .reg_offset = 8, 1706 .mclk0_is_mclk1 = false, 1707 .pins = 8, 1708 .flags = 0, 1709 .max_register = FSL_SAI_MDIV, 1710 }; 1711 1712 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1713 .use_imx_pcm = true, 1714 .use_edma = false, 1715 .fifo_depth = 128, 1716 .reg_offset = 8, 1717 .mclk0_is_mclk1 = false, 1718 .pins = 8, 1719 .flags = 0, 1720 .max_register = FSL_SAI_MDIV, 1721 .mclk_with_tere = true, 1722 }; 1723 1724 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1725 .use_imx_pcm = true, 1726 .use_edma = true, 1727 .fifo_depth = 16, 1728 .reg_offset = 8, 1729 .mclk0_is_mclk1 = false, 1730 .pins = 4, 1731 .flags = PMQOS_CPU_LATENCY, 1732 .max_register = FSL_SAI_RTCAP, 1733 }; 1734 1735 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1736 .use_imx_pcm = true, 1737 .use_edma = true, 1738 .fifo_depth = 128, 1739 .reg_offset = 8, 1740 .mclk0_is_mclk1 = false, 1741 .pins = 4, 1742 .flags = 0, 1743 .max_register = FSL_SAI_MCTL, 1744 .max_burst = {8, 8}, 1745 }; 1746 1747 static const struct fsl_sai_soc_data fsl_sai_imx95_data = { 1748 .use_imx_pcm = true, 1749 .use_edma = true, 1750 .fifo_depth = 128, 1751 .reg_offset = 8, 1752 .mclk0_is_mclk1 = false, 1753 .pins = 8, 1754 .flags = 0, 1755 .max_register = FSL_SAI_MCTL, 1756 .max_burst = {8, 8}, 1757 }; 1758 1759 static const struct of_device_id fsl_sai_ids[] = { 1760 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1761 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1762 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1763 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1764 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1765 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1766 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1767 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1768 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1769 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mn_data }, 1770 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1771 { .compatible = "fsl,imx95-sai", .data = &fsl_sai_imx95_data }, 1772 { /* sentinel */ } 1773 }; 1774 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1775 1776 static int fsl_sai_runtime_suspend(struct device *dev) 1777 { 1778 struct fsl_sai *sai = dev_get_drvdata(dev); 1779 1780 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1781 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1782 1783 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1784 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1785 1786 clk_disable_unprepare(sai->bus_clk); 1787 1788 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1789 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1790 1791 regcache_cache_only(sai->regmap, true); 1792 1793 return 0; 1794 } 1795 1796 static int fsl_sai_runtime_resume(struct device *dev) 1797 { 1798 struct fsl_sai *sai = dev_get_drvdata(dev); 1799 unsigned int ofs = sai->soc_data->reg_offset; 1800 int ret; 1801 1802 ret = clk_prepare_enable(sai->bus_clk); 1803 if (ret) { 1804 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1805 return ret; 1806 } 1807 1808 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1809 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1810 if (ret) 1811 goto disable_bus_clk; 1812 } 1813 1814 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1815 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1816 if (ret) 1817 goto disable_tx_clk; 1818 } 1819 1820 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1821 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1822 1823 regcache_cache_only(sai->regmap, false); 1824 regcache_mark_dirty(sai->regmap); 1825 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 1826 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, FSL_SAI_CSR_SR); 1827 usleep_range(1000, 2000); 1828 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR, 0); 1829 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR, 0); 1830 1831 ret = regcache_sync(sai->regmap); 1832 if (ret) 1833 goto disable_rx_clk; 1834 1835 if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output) 1836 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs), 1837 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 1838 1839 return 0; 1840 1841 disable_rx_clk: 1842 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1843 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1844 disable_tx_clk: 1845 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1846 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1847 disable_bus_clk: 1848 clk_disable_unprepare(sai->bus_clk); 1849 1850 return ret; 1851 } 1852 1853 static const struct dev_pm_ops fsl_sai_pm_ops = { 1854 RUNTIME_PM_OPS(fsl_sai_runtime_suspend, fsl_sai_runtime_resume, NULL) 1855 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1856 }; 1857 1858 static struct platform_driver fsl_sai_driver = { 1859 .probe = fsl_sai_probe, 1860 .remove = fsl_sai_remove, 1861 .driver = { 1862 .name = "fsl-sai", 1863 .pm = pm_ptr(&fsl_sai_pm_ops), 1864 .of_match_table = fsl_sai_ids, 1865 }, 1866 }; 1867 module_platform_driver(fsl_sai_driver); 1868 1869 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1870 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1871 MODULE_ALIAS("platform:fsl-sai"); 1872 MODULE_LICENSE("GPL"); 1873