1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // ALSA SoC IMX MQS driver 4 // 5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 6 // Copyright 2019 NXP 7 8 #include <linux/clk.h> 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/of.h> 16 #include <linux/pm.h> 17 #include <linux/slab.h> 18 #include <sound/soc.h> 19 #include <sound/pcm.h> 20 #include <sound/initval.h> 21 22 #define REG_MQS_CTRL 0x00 23 24 #define MQS_EN_MASK (0x1 << 28) 25 #define MQS_EN_SHIFT (28) 26 #define MQS_SW_RST_MASK (0x1 << 24) 27 #define MQS_SW_RST_SHIFT (24) 28 #define MQS_OVERSAMPLE_MASK (0x1 << 20) 29 #define MQS_OVERSAMPLE_SHIFT (20) 30 #define MQS_CLK_DIV_MASK (0xFF << 0) 31 #define MQS_CLK_DIV_SHIFT (0) 32 33 /** 34 * struct fsl_mqs_soc_data - soc specific data 35 * 36 * @use_gpr: control register is in General Purpose Register group 37 * @ctrl_off: control register offset 38 * @en_mask: enable bit mask 39 * @en_shift: enable bit shift 40 * @rst_mask: reset bit mask 41 * @rst_shift: reset bit shift 42 * @osr_mask: oversample bit mask 43 * @osr_shift: oversample bit shift 44 * @div_mask: clock divider mask 45 * @div_shift: clock divider bit shift 46 */ 47 struct fsl_mqs_soc_data { 48 bool use_gpr; 49 int ctrl_off; 50 int en_mask; 51 int en_shift; 52 int rst_mask; 53 int rst_shift; 54 int osr_mask; 55 int osr_shift; 56 int div_mask; 57 int div_shift; 58 }; 59 60 /* codec private data */ 61 struct fsl_mqs { 62 struct regmap *regmap; 63 struct clk *mclk; 64 struct clk *ipg; 65 const struct fsl_mqs_soc_data *soc; 66 67 unsigned int reg_mqs_ctrl; 68 }; 69 70 #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 71 #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE 72 73 static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, 74 struct snd_pcm_hw_params *params, 75 struct snd_soc_dai *dai) 76 { 77 struct snd_soc_component *component = dai->component; 78 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 79 unsigned long mclk_rate; 80 int div, res; 81 int lrclk; 82 83 mclk_rate = clk_get_rate(mqs_priv->mclk); 84 lrclk = params_rate(params); 85 86 /* 87 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; 88 * if repeat_rate is 8, mqs can achieve better quality. 89 * oversample rate is fix to 32 currently. 90 */ 91 div = mclk_rate / (32 * lrclk * 2 * 8); 92 res = mclk_rate % (32 * lrclk * 2 * 8); 93 94 if (res == 0 && div > 0 && div <= 256) { 95 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 96 mqs_priv->soc->div_mask, 97 (div - 1) << mqs_priv->soc->div_shift); 98 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 99 mqs_priv->soc->osr_mask, 0); 100 } else { 101 dev_err(component->dev, "can't get proper divider\n"); 102 } 103 104 return 0; 105 } 106 107 static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 108 { 109 /* Only LEFT_J & SLAVE mode is supported. */ 110 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 111 case SND_SOC_DAIFMT_LEFT_J: 112 break; 113 default: 114 return -EINVAL; 115 } 116 117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 118 case SND_SOC_DAIFMT_NB_NF: 119 break; 120 default: 121 return -EINVAL; 122 } 123 124 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 125 case SND_SOC_DAIFMT_BP_FP: 126 break; 127 default: 128 return -EINVAL; 129 } 130 131 return 0; 132 } 133 134 static int fsl_mqs_startup(struct snd_pcm_substream *substream, 135 struct snd_soc_dai *dai) 136 { 137 struct snd_soc_component *component = dai->component; 138 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 139 140 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 141 mqs_priv->soc->en_mask, 142 1 << mqs_priv->soc->en_shift); 143 return 0; 144 } 145 146 static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, 147 struct snd_soc_dai *dai) 148 { 149 struct snd_soc_component *component = dai->component; 150 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 151 152 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 153 mqs_priv->soc->en_mask, 0); 154 } 155 156 static const struct snd_soc_component_driver soc_codec_fsl_mqs = { 157 .idle_bias_on = 1, 158 .non_legacy_dai_naming = 1, 159 }; 160 161 static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { 162 .startup = fsl_mqs_startup, 163 .shutdown = fsl_mqs_shutdown, 164 .hw_params = fsl_mqs_hw_params, 165 .set_fmt = fsl_mqs_set_dai_fmt, 166 }; 167 168 static struct snd_soc_dai_driver fsl_mqs_dai = { 169 .name = "fsl-mqs-dai", 170 .playback = { 171 .stream_name = "Playback", 172 .channels_min = 2, 173 .channels_max = 2, 174 .rates = FSL_MQS_RATES, 175 .formats = FSL_MQS_FORMATS, 176 }, 177 .ops = &fsl_mqs_dai_ops, 178 }; 179 180 static const struct regmap_config fsl_mqs_regmap_config = { 181 .reg_bits = 32, 182 .reg_stride = 4, 183 .val_bits = 32, 184 .max_register = REG_MQS_CTRL, 185 .cache_type = REGCACHE_NONE, 186 }; 187 188 static int fsl_mqs_probe(struct platform_device *pdev) 189 { 190 struct device_node *np = pdev->dev.of_node; 191 struct device_node *gpr_np = NULL; 192 struct fsl_mqs *mqs_priv; 193 void __iomem *regs; 194 int ret; 195 196 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); 197 if (!mqs_priv) 198 return -ENOMEM; 199 200 /* On i.MX6sx the MQS control register is in GPR domain 201 * But in i.MX8QM/i.MX8QXP the control register is moved 202 * to its own domain. 203 */ 204 mqs_priv->soc = of_device_get_match_data(&pdev->dev); 205 206 if (mqs_priv->soc->use_gpr) { 207 gpr_np = of_parse_phandle(np, "gpr", 0); 208 if (!gpr_np) { 209 dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); 210 return -EINVAL; 211 } 212 213 mqs_priv->regmap = syscon_node_to_regmap(gpr_np); 214 if (IS_ERR(mqs_priv->regmap)) { 215 dev_err(&pdev->dev, "failed to get gpr regmap\n"); 216 ret = PTR_ERR(mqs_priv->regmap); 217 goto err_free_gpr_np; 218 } 219 } else { 220 regs = devm_platform_ioremap_resource(pdev, 0); 221 if (IS_ERR(regs)) 222 return PTR_ERR(regs); 223 224 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 225 "core", 226 regs, 227 &fsl_mqs_regmap_config); 228 if (IS_ERR(mqs_priv->regmap)) { 229 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 230 PTR_ERR(mqs_priv->regmap)); 231 return PTR_ERR(mqs_priv->regmap); 232 } 233 234 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); 235 if (IS_ERR(mqs_priv->ipg)) { 236 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 237 PTR_ERR(mqs_priv->ipg)); 238 return PTR_ERR(mqs_priv->ipg); 239 } 240 } 241 242 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); 243 if (IS_ERR(mqs_priv->mclk)) { 244 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 245 PTR_ERR(mqs_priv->mclk)); 246 ret = PTR_ERR(mqs_priv->mclk); 247 goto err_free_gpr_np; 248 } 249 250 dev_set_drvdata(&pdev->dev, mqs_priv); 251 pm_runtime_enable(&pdev->dev); 252 253 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, 254 &fsl_mqs_dai, 1); 255 if (ret) 256 goto err_free_gpr_np; 257 return 0; 258 259 err_free_gpr_np: 260 of_node_put(gpr_np); 261 262 return ret; 263 } 264 265 static int fsl_mqs_remove(struct platform_device *pdev) 266 { 267 pm_runtime_disable(&pdev->dev); 268 return 0; 269 } 270 271 #ifdef CONFIG_PM 272 static int fsl_mqs_runtime_resume(struct device *dev) 273 { 274 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 275 int ret; 276 277 ret = clk_prepare_enable(mqs_priv->ipg); 278 if (ret) { 279 dev_err(dev, "failed to enable ipg clock\n"); 280 return ret; 281 } 282 283 ret = clk_prepare_enable(mqs_priv->mclk); 284 if (ret) { 285 dev_err(dev, "failed to enable mclk clock\n"); 286 clk_disable_unprepare(mqs_priv->ipg); 287 return ret; 288 } 289 290 regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl); 291 return 0; 292 } 293 294 static int fsl_mqs_runtime_suspend(struct device *dev) 295 { 296 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 297 298 regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl); 299 300 clk_disable_unprepare(mqs_priv->mclk); 301 clk_disable_unprepare(mqs_priv->ipg); 302 303 return 0; 304 } 305 #endif 306 307 static const struct dev_pm_ops fsl_mqs_pm_ops = { 308 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, 309 fsl_mqs_runtime_resume, 310 NULL) 311 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 312 pm_runtime_force_resume) 313 }; 314 315 static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = { 316 .use_gpr = false, 317 .ctrl_off = REG_MQS_CTRL, 318 .en_mask = MQS_EN_MASK, 319 .en_shift = MQS_EN_SHIFT, 320 .rst_mask = MQS_SW_RST_MASK, 321 .rst_shift = MQS_SW_RST_SHIFT, 322 .osr_mask = MQS_OVERSAMPLE_MASK, 323 .osr_shift = MQS_OVERSAMPLE_SHIFT, 324 .div_mask = MQS_CLK_DIV_MASK, 325 .div_shift = MQS_CLK_DIV_SHIFT, 326 }; 327 328 static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = { 329 .use_gpr = true, 330 .ctrl_off = IOMUXC_GPR2, 331 .en_mask = IMX6SX_GPR2_MQS_EN_MASK, 332 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT, 333 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK, 334 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT, 335 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 336 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT, 337 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK, 338 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT, 339 }; 340 341 static const struct of_device_id fsl_mqs_dt_ids[] = { 342 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data }, 343 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data }, 344 {} 345 }; 346 MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); 347 348 static struct platform_driver fsl_mqs_driver = { 349 .probe = fsl_mqs_probe, 350 .remove = fsl_mqs_remove, 351 .driver = { 352 .name = "fsl-mqs", 353 .of_match_table = fsl_mqs_dt_ids, 354 .pm = &fsl_mqs_pm_ops, 355 }, 356 }; 357 358 module_platform_driver(fsl_mqs_driver); 359 360 MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>"); 361 MODULE_DESCRIPTION("MQS codec driver"); 362 MODULE_LICENSE("GPL v2"); 363 MODULE_ALIAS("platform:fsl-mqs"); 364