1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // ALSA SoC IMX MQS driver 4 // 5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 6 // Copyright 2019 NXP 7 8 #include <linux/clk.h> 9 #include <linux/firmware/imx/sm.h> 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/pm.h> 16 #include <linux/slab.h> 17 #include <sound/soc.h> 18 #include <sound/pcm.h> 19 #include <sound/initval.h> 20 21 #define REG_MQS_CTRL 0x00 22 23 #define MQS_EN_MASK (0x1 << 28) 24 #define MQS_EN_SHIFT (28) 25 #define MQS_SW_RST_MASK (0x1 << 24) 26 #define MQS_SW_RST_SHIFT (24) 27 #define MQS_OVERSAMPLE_MASK (0x1 << 20) 28 #define MQS_OVERSAMPLE_SHIFT (20) 29 #define MQS_CLK_DIV_MASK (0xFF << 0) 30 #define MQS_CLK_DIV_SHIFT (0) 31 32 enum reg_type { 33 TYPE_REG_OWN, /* module own register space */ 34 TYPE_REG_GPR, /* register in GPR space */ 35 TYPE_REG_SM, /* System Manager controls the register */ 36 }; 37 38 /** 39 * struct fsl_mqs_soc_data - soc specific data 40 * 41 * @type: control register space type 42 * @ctrl_off: control register offset 43 * @en_mask: enable bit mask 44 * @en_shift: enable bit shift 45 * @rst_mask: reset bit mask 46 * @rst_shift: reset bit shift 47 * @osr_mask: oversample bit mask 48 * @osr_shift: oversample bit shift 49 * @div_mask: clock divider mask 50 * @div_shift: clock divider bit shift 51 */ 52 struct fsl_mqs_soc_data { 53 enum reg_type type; 54 int ctrl_off; 55 int en_mask; 56 int en_shift; 57 int rst_mask; 58 int rst_shift; 59 int osr_mask; 60 int osr_shift; 61 int div_mask; 62 int div_shift; 63 }; 64 65 /* codec private data */ 66 struct fsl_mqs { 67 struct regmap *regmap; 68 struct clk *mclk; 69 struct clk *ipg; 70 const struct fsl_mqs_soc_data *soc; 71 72 unsigned int reg_mqs_ctrl; 73 }; 74 75 #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 76 #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE 77 78 static int fsl_mqs_sm_read(void *context, unsigned int reg, unsigned int *val) 79 { 80 struct fsl_mqs *mqs_priv = context; 81 int num = 1; 82 83 if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) && 84 mqs_priv->soc->ctrl_off == reg) 85 return scmi_imx_misc_ctrl_get(SCMI_IMX_CTRL_MQS1_SETTINGS, &num, val); 86 87 return -EINVAL; 88 }; 89 90 static int fsl_mqs_sm_write(void *context, unsigned int reg, unsigned int val) 91 { 92 struct fsl_mqs *mqs_priv = context; 93 94 if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) && 95 mqs_priv->soc->ctrl_off == reg) 96 return scmi_imx_misc_ctrl_set(SCMI_IMX_CTRL_MQS1_SETTINGS, val); 97 98 return -EINVAL; 99 }; 100 101 static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, 102 struct snd_pcm_hw_params *params, 103 struct snd_soc_dai *dai) 104 { 105 struct snd_soc_component *component = dai->component; 106 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 107 unsigned long mclk_rate; 108 int div, res; 109 int lrclk; 110 111 mclk_rate = clk_get_rate(mqs_priv->mclk); 112 lrclk = params_rate(params); 113 114 /* 115 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; 116 * if repeat_rate is 8, mqs can achieve better quality. 117 * oversample rate is fix to 32 currently. 118 */ 119 div = mclk_rate / (32 * lrclk * 2 * 8); 120 res = mclk_rate % (32 * lrclk * 2 * 8); 121 122 if (res == 0 && div > 0 && div <= 256) { 123 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 124 mqs_priv->soc->div_mask, 125 (div - 1) << mqs_priv->soc->div_shift); 126 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 127 mqs_priv->soc->osr_mask, 0); 128 } else { 129 dev_err(component->dev, "can't get proper divider\n"); 130 } 131 132 return 0; 133 } 134 135 static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 136 { 137 /* Only LEFT_J & SLAVE mode is supported. */ 138 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 139 case SND_SOC_DAIFMT_LEFT_J: 140 break; 141 default: 142 return -EINVAL; 143 } 144 145 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 146 case SND_SOC_DAIFMT_NB_NF: 147 break; 148 default: 149 return -EINVAL; 150 } 151 152 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 153 case SND_SOC_DAIFMT_CBC_CFC: 154 break; 155 default: 156 return -EINVAL; 157 } 158 159 return 0; 160 } 161 162 static int fsl_mqs_startup(struct snd_pcm_substream *substream, 163 struct snd_soc_dai *dai) 164 { 165 struct snd_soc_component *component = dai->component; 166 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 167 168 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 169 mqs_priv->soc->en_mask, 170 1 << mqs_priv->soc->en_shift); 171 return 0; 172 } 173 174 static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, 175 struct snd_soc_dai *dai) 176 { 177 struct snd_soc_component *component = dai->component; 178 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 179 180 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off, 181 mqs_priv->soc->en_mask, 0); 182 } 183 184 static const struct snd_soc_component_driver soc_codec_fsl_mqs = { 185 .idle_bias_on = 1, 186 }; 187 188 static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { 189 .startup = fsl_mqs_startup, 190 .shutdown = fsl_mqs_shutdown, 191 .hw_params = fsl_mqs_hw_params, 192 .set_fmt = fsl_mqs_set_dai_fmt, 193 }; 194 195 static struct snd_soc_dai_driver fsl_mqs_dai = { 196 .name = "fsl-mqs-dai", 197 .playback = { 198 .stream_name = "Playback", 199 .channels_min = 2, 200 .channels_max = 2, 201 .rates = FSL_MQS_RATES, 202 .formats = FSL_MQS_FORMATS, 203 }, 204 .ops = &fsl_mqs_dai_ops, 205 }; 206 207 static const struct regmap_config fsl_mqs_regmap_config = { 208 .reg_bits = 32, 209 .reg_stride = 4, 210 .val_bits = 32, 211 .max_register = REG_MQS_CTRL, 212 .cache_type = REGCACHE_NONE, 213 }; 214 215 static const struct regmap_config fsl_mqs_sm_regmap = { 216 .reg_bits = 32, 217 .val_bits = 32, 218 .reg_read = fsl_mqs_sm_read, 219 .reg_write = fsl_mqs_sm_write, 220 }; 221 222 static int fsl_mqs_probe(struct platform_device *pdev) 223 { 224 struct device_node *np = pdev->dev.of_node; 225 struct device_node *gpr_np = NULL; 226 struct fsl_mqs *mqs_priv; 227 void __iomem *regs; 228 int ret; 229 230 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); 231 if (!mqs_priv) 232 return -ENOMEM; 233 234 /* On i.MX6sx the MQS control register is in GPR domain 235 * But in i.MX8QM/i.MX8QXP the control register is moved 236 * to its own domain. 237 */ 238 mqs_priv->soc = of_device_get_match_data(&pdev->dev); 239 240 if (mqs_priv->soc->type == TYPE_REG_GPR) { 241 gpr_np = of_parse_phandle(np, "gpr", 0); 242 if (!gpr_np) { 243 dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); 244 return -EINVAL; 245 } 246 247 mqs_priv->regmap = syscon_node_to_regmap(gpr_np); 248 of_node_put(gpr_np); 249 if (IS_ERR(mqs_priv->regmap)) { 250 dev_err(&pdev->dev, "failed to get gpr regmap\n"); 251 return PTR_ERR(mqs_priv->regmap); 252 } 253 } else if (mqs_priv->soc->type == TYPE_REG_SM) { 254 mqs_priv->regmap = devm_regmap_init(&pdev->dev, 255 NULL, 256 mqs_priv, 257 &fsl_mqs_sm_regmap); 258 if (IS_ERR(mqs_priv->regmap)) { 259 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 260 PTR_ERR(mqs_priv->regmap)); 261 return PTR_ERR(mqs_priv->regmap); 262 } 263 } else { 264 regs = devm_platform_ioremap_resource(pdev, 0); 265 if (IS_ERR(regs)) 266 return PTR_ERR(regs); 267 268 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 269 "core", 270 regs, 271 &fsl_mqs_regmap_config); 272 if (IS_ERR(mqs_priv->regmap)) { 273 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 274 PTR_ERR(mqs_priv->regmap)); 275 return PTR_ERR(mqs_priv->regmap); 276 } 277 278 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); 279 if (IS_ERR(mqs_priv->ipg)) { 280 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 281 PTR_ERR(mqs_priv->ipg)); 282 return PTR_ERR(mqs_priv->ipg); 283 } 284 } 285 286 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); 287 if (IS_ERR(mqs_priv->mclk)) { 288 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 289 PTR_ERR(mqs_priv->mclk)); 290 return PTR_ERR(mqs_priv->mclk); 291 } 292 293 dev_set_drvdata(&pdev->dev, mqs_priv); 294 pm_runtime_enable(&pdev->dev); 295 296 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, 297 &fsl_mqs_dai, 1); 298 if (ret) 299 return ret; 300 301 return 0; 302 } 303 304 static void fsl_mqs_remove(struct platform_device *pdev) 305 { 306 pm_runtime_disable(&pdev->dev); 307 } 308 309 static int fsl_mqs_runtime_resume(struct device *dev) 310 { 311 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 312 int ret; 313 314 ret = clk_prepare_enable(mqs_priv->ipg); 315 if (ret) { 316 dev_err(dev, "failed to enable ipg clock\n"); 317 return ret; 318 } 319 320 ret = clk_prepare_enable(mqs_priv->mclk); 321 if (ret) { 322 dev_err(dev, "failed to enable mclk clock\n"); 323 clk_disable_unprepare(mqs_priv->ipg); 324 return ret; 325 } 326 327 regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl); 328 return 0; 329 } 330 331 static int fsl_mqs_runtime_suspend(struct device *dev) 332 { 333 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 334 335 regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl); 336 337 clk_disable_unprepare(mqs_priv->mclk); 338 clk_disable_unprepare(mqs_priv->ipg); 339 340 return 0; 341 } 342 343 static const struct dev_pm_ops fsl_mqs_pm_ops = { 344 RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, fsl_mqs_runtime_resume, NULL) 345 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 346 }; 347 348 static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = { 349 .type = TYPE_REG_OWN, 350 .ctrl_off = REG_MQS_CTRL, 351 .en_mask = MQS_EN_MASK, 352 .en_shift = MQS_EN_SHIFT, 353 .rst_mask = MQS_SW_RST_MASK, 354 .rst_shift = MQS_SW_RST_SHIFT, 355 .osr_mask = MQS_OVERSAMPLE_MASK, 356 .osr_shift = MQS_OVERSAMPLE_SHIFT, 357 .div_mask = MQS_CLK_DIV_MASK, 358 .div_shift = MQS_CLK_DIV_SHIFT, 359 }; 360 361 static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = { 362 .type = TYPE_REG_GPR, 363 .ctrl_off = IOMUXC_GPR2, 364 .en_mask = IMX6SX_GPR2_MQS_EN_MASK, 365 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT, 366 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK, 367 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT, 368 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 369 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT, 370 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK, 371 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT, 372 }; 373 374 static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = { 375 .type = TYPE_REG_GPR, 376 .ctrl_off = 0x20, 377 .en_mask = BIT(1), 378 .en_shift = 1, 379 .rst_mask = BIT(2), 380 .rst_shift = 2, 381 .osr_mask = BIT(3), 382 .osr_shift = 3, 383 .div_mask = GENMASK(15, 8), 384 .div_shift = 8, 385 }; 386 387 static const struct fsl_mqs_soc_data fsl_mqs_imx95_aon_data = { 388 .type = TYPE_REG_SM, 389 .ctrl_off = 0x88, 390 .en_mask = BIT(1), 391 .en_shift = 1, 392 .rst_mask = BIT(2), 393 .rst_shift = 2, 394 .osr_mask = BIT(3), 395 .osr_shift = 3, 396 .div_mask = GENMASK(15, 8), 397 .div_shift = 8, 398 }; 399 400 static const struct fsl_mqs_soc_data fsl_mqs_imx95_netc_data = { 401 .type = TYPE_REG_GPR, 402 .ctrl_off = 0x0, 403 .en_mask = BIT(2), 404 .en_shift = 2, 405 .rst_mask = BIT(3), 406 .rst_shift = 3, 407 .osr_mask = BIT(4), 408 .osr_shift = 4, 409 .div_mask = GENMASK(16, 9), 410 .div_shift = 9, 411 }; 412 413 static const struct of_device_id fsl_mqs_dt_ids[] = { 414 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data }, 415 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data }, 416 { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data }, 417 { .compatible = "fsl,imx95-aonmix-mqs", .data = &fsl_mqs_imx95_aon_data }, 418 { .compatible = "fsl,imx95-netcmix-mqs", .data = &fsl_mqs_imx95_netc_data }, 419 {} 420 }; 421 MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); 422 423 static struct platform_driver fsl_mqs_driver = { 424 .probe = fsl_mqs_probe, 425 .remove = fsl_mqs_remove, 426 .driver = { 427 .name = "fsl-mqs", 428 .of_match_table = fsl_mqs_dt_ids, 429 .pm = pm_ptr(&fsl_mqs_pm_ops), 430 }, 431 }; 432 433 module_platform_driver(fsl_mqs_driver); 434 435 MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>"); 436 MODULE_DESCRIPTION("MQS codec driver"); 437 MODULE_LICENSE("GPL v2"); 438 MODULE_ALIAS("platform:fsl-mqs"); 439