19e28f653SShengjiu Wang // SPDX-License-Identifier: GPL-2.0 29e28f653SShengjiu Wang // 39e28f653SShengjiu Wang // ALSA SoC IMX MQS driver 49e28f653SShengjiu Wang // 59e28f653SShengjiu Wang // Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 69e28f653SShengjiu Wang // Copyright 2019 NXP 79e28f653SShengjiu Wang 89e28f653SShengjiu Wang #include <linux/clk.h> 99e28f653SShengjiu Wang #include <linux/module.h> 109e28f653SShengjiu Wang #include <linux/moduleparam.h> 119e28f653SShengjiu Wang #include <linux/mfd/syscon.h> 129e28f653SShengjiu Wang #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 139e28f653SShengjiu Wang #include <linux/pm_runtime.h> 149e28f653SShengjiu Wang #include <linux/of.h> 159e28f653SShengjiu Wang #include <linux/pm.h> 169e28f653SShengjiu Wang #include <linux/slab.h> 179e28f653SShengjiu Wang #include <sound/soc.h> 189e28f653SShengjiu Wang #include <sound/pcm.h> 199e28f653SShengjiu Wang #include <sound/initval.h> 209e28f653SShengjiu Wang 219e28f653SShengjiu Wang #define REG_MQS_CTRL 0x00 229e28f653SShengjiu Wang 239e28f653SShengjiu Wang #define MQS_EN_MASK (0x1 << 28) 249e28f653SShengjiu Wang #define MQS_EN_SHIFT (28) 259e28f653SShengjiu Wang #define MQS_SW_RST_MASK (0x1 << 24) 269e28f653SShengjiu Wang #define MQS_SW_RST_SHIFT (24) 279e28f653SShengjiu Wang #define MQS_OVERSAMPLE_MASK (0x1 << 20) 289e28f653SShengjiu Wang #define MQS_OVERSAMPLE_SHIFT (20) 299e28f653SShengjiu Wang #define MQS_CLK_DIV_MASK (0xFF << 0) 309e28f653SShengjiu Wang #define MQS_CLK_DIV_SHIFT (0) 319e28f653SShengjiu Wang 329e28f653SShengjiu Wang /* codec private data */ 339e28f653SShengjiu Wang struct fsl_mqs { 349e28f653SShengjiu Wang struct regmap *regmap; 359e28f653SShengjiu Wang struct clk *mclk; 369e28f653SShengjiu Wang struct clk *ipg; 379e28f653SShengjiu Wang 389e28f653SShengjiu Wang unsigned int reg_iomuxc_gpr2; 399e28f653SShengjiu Wang unsigned int reg_mqs_ctrl; 409e28f653SShengjiu Wang bool use_gpr; 419e28f653SShengjiu Wang }; 429e28f653SShengjiu Wang 439e28f653SShengjiu Wang #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 449e28f653SShengjiu Wang #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE 459e28f653SShengjiu Wang 469e28f653SShengjiu Wang static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, 479e28f653SShengjiu Wang struct snd_pcm_hw_params *params, 489e28f653SShengjiu Wang struct snd_soc_dai *dai) 499e28f653SShengjiu Wang { 509e28f653SShengjiu Wang struct snd_soc_component *component = dai->component; 519e28f653SShengjiu Wang struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 529e28f653SShengjiu Wang unsigned long mclk_rate; 539e28f653SShengjiu Wang int div, res; 54e9e8fc9eSYueHaibing int lrclk; 559e28f653SShengjiu Wang 569e28f653SShengjiu Wang mclk_rate = clk_get_rate(mqs_priv->mclk); 579e28f653SShengjiu Wang lrclk = params_rate(params); 589e28f653SShengjiu Wang 599e28f653SShengjiu Wang /* 609e28f653SShengjiu Wang * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; 619e28f653SShengjiu Wang * if repeat_rate is 8, mqs can achieve better quality. 629e28f653SShengjiu Wang * oversample rate is fix to 32 currently. 639e28f653SShengjiu Wang */ 649e28f653SShengjiu Wang div = mclk_rate / (32 * lrclk * 2 * 8); 659e28f653SShengjiu Wang res = mclk_rate % (32 * lrclk * 2 * 8); 669e28f653SShengjiu Wang 679e28f653SShengjiu Wang if (res == 0 && div > 0 && div <= 256) { 689e28f653SShengjiu Wang if (mqs_priv->use_gpr) { 699e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 709e28f653SShengjiu Wang IMX6SX_GPR2_MQS_CLK_DIV_MASK, 719e28f653SShengjiu Wang (div - 1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT); 729e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 739e28f653SShengjiu Wang IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0); 749e28f653SShengjiu Wang } else { 759e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 769e28f653SShengjiu Wang MQS_CLK_DIV_MASK, 779e28f653SShengjiu Wang (div - 1) << MQS_CLK_DIV_SHIFT); 789e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 799e28f653SShengjiu Wang MQS_OVERSAMPLE_MASK, 0); 809e28f653SShengjiu Wang } 819e28f653SShengjiu Wang } else { 829e28f653SShengjiu Wang dev_err(component->dev, "can't get proper divider\n"); 839e28f653SShengjiu Wang } 849e28f653SShengjiu Wang 859e28f653SShengjiu Wang return 0; 869e28f653SShengjiu Wang } 879e28f653SShengjiu Wang 889e28f653SShengjiu Wang static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 899e28f653SShengjiu Wang { 909e28f653SShengjiu Wang /* Only LEFT_J & SLAVE mode is supported. */ 919e28f653SShengjiu Wang switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 929e28f653SShengjiu Wang case SND_SOC_DAIFMT_LEFT_J: 939e28f653SShengjiu Wang break; 949e28f653SShengjiu Wang default: 959e28f653SShengjiu Wang return -EINVAL; 969e28f653SShengjiu Wang } 979e28f653SShengjiu Wang 989e28f653SShengjiu Wang switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 999e28f653SShengjiu Wang case SND_SOC_DAIFMT_NB_NF: 1009e28f653SShengjiu Wang break; 1019e28f653SShengjiu Wang default: 1029e28f653SShengjiu Wang return -EINVAL; 1039e28f653SShengjiu Wang } 1049e28f653SShengjiu Wang 105*a51da9dcSMark Brown switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 106*a51da9dcSMark Brown case SND_SOC_DAIFMT_CBC_CFC: 1079e28f653SShengjiu Wang break; 1089e28f653SShengjiu Wang default: 1099e28f653SShengjiu Wang return -EINVAL; 1109e28f653SShengjiu Wang } 1119e28f653SShengjiu Wang 1129e28f653SShengjiu Wang return 0; 1139e28f653SShengjiu Wang } 1149e28f653SShengjiu Wang 1159e28f653SShengjiu Wang static int fsl_mqs_startup(struct snd_pcm_substream *substream, 1169e28f653SShengjiu Wang struct snd_soc_dai *dai) 1179e28f653SShengjiu Wang { 1189e28f653SShengjiu Wang struct snd_soc_component *component = dai->component; 1199e28f653SShengjiu Wang struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 1209e28f653SShengjiu Wang 1219e28f653SShengjiu Wang if (mqs_priv->use_gpr) 1229e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 1239e28f653SShengjiu Wang IMX6SX_GPR2_MQS_EN_MASK, 1249e28f653SShengjiu Wang 1 << IMX6SX_GPR2_MQS_EN_SHIFT); 1259e28f653SShengjiu Wang else 1269e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 1279e28f653SShengjiu Wang MQS_EN_MASK, 1289e28f653SShengjiu Wang 1 << MQS_EN_SHIFT); 1299e28f653SShengjiu Wang return 0; 1309e28f653SShengjiu Wang } 1319e28f653SShengjiu Wang 1329e28f653SShengjiu Wang static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, 1339e28f653SShengjiu Wang struct snd_soc_dai *dai) 1349e28f653SShengjiu Wang { 1359e28f653SShengjiu Wang struct snd_soc_component *component = dai->component; 1369e28f653SShengjiu Wang struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 1379e28f653SShengjiu Wang 1389e28f653SShengjiu Wang if (mqs_priv->use_gpr) 1399e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 1409e28f653SShengjiu Wang IMX6SX_GPR2_MQS_EN_MASK, 0); 1419e28f653SShengjiu Wang else 1429e28f653SShengjiu Wang regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 1439e28f653SShengjiu Wang MQS_EN_MASK, 0); 1449e28f653SShengjiu Wang } 1459e28f653SShengjiu Wang 146dd79841cSYueHaibing static const struct snd_soc_component_driver soc_codec_fsl_mqs = { 1479e28f653SShengjiu Wang .idle_bias_on = 1, 1489e28f653SShengjiu Wang .non_legacy_dai_naming = 1, 1499e28f653SShengjiu Wang }; 1509e28f653SShengjiu Wang 1519e28f653SShengjiu Wang static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { 1529e28f653SShengjiu Wang .startup = fsl_mqs_startup, 1539e28f653SShengjiu Wang .shutdown = fsl_mqs_shutdown, 1549e28f653SShengjiu Wang .hw_params = fsl_mqs_hw_params, 1559e28f653SShengjiu Wang .set_fmt = fsl_mqs_set_dai_fmt, 1569e28f653SShengjiu Wang }; 1579e28f653SShengjiu Wang 1589e28f653SShengjiu Wang static struct snd_soc_dai_driver fsl_mqs_dai = { 1599e28f653SShengjiu Wang .name = "fsl-mqs-dai", 1609e28f653SShengjiu Wang .playback = { 1619e28f653SShengjiu Wang .stream_name = "Playback", 1629e28f653SShengjiu Wang .channels_min = 2, 1639e28f653SShengjiu Wang .channels_max = 2, 1649e28f653SShengjiu Wang .rates = FSL_MQS_RATES, 1659e28f653SShengjiu Wang .formats = FSL_MQS_FORMATS, 1669e28f653SShengjiu Wang }, 1679e28f653SShengjiu Wang .ops = &fsl_mqs_dai_ops, 1689e28f653SShengjiu Wang }; 1699e28f653SShengjiu Wang 1709e28f653SShengjiu Wang static const struct regmap_config fsl_mqs_regmap_config = { 1719e28f653SShengjiu Wang .reg_bits = 32, 1729e28f653SShengjiu Wang .reg_stride = 4, 1739e28f653SShengjiu Wang .val_bits = 32, 1749e28f653SShengjiu Wang .max_register = REG_MQS_CTRL, 1759e28f653SShengjiu Wang .cache_type = REGCACHE_NONE, 1769e28f653SShengjiu Wang }; 1779e28f653SShengjiu Wang 1789e28f653SShengjiu Wang static int fsl_mqs_probe(struct platform_device *pdev) 1799e28f653SShengjiu Wang { 1809e28f653SShengjiu Wang struct device_node *np = pdev->dev.of_node; 181a9d27367SDan Carpenter struct device_node *gpr_np = NULL; 1829e28f653SShengjiu Wang struct fsl_mqs *mqs_priv; 1839e28f653SShengjiu Wang void __iomem *regs; 184a9d27367SDan Carpenter int ret; 1859e28f653SShengjiu Wang 1869e28f653SShengjiu Wang mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); 1879e28f653SShengjiu Wang if (!mqs_priv) 1889e28f653SShengjiu Wang return -ENOMEM; 1899e28f653SShengjiu Wang 1909e28f653SShengjiu Wang /* On i.MX6sx the MQS control register is in GPR domain 1919e28f653SShengjiu Wang * But in i.MX8QM/i.MX8QXP the control register is moved 1929e28f653SShengjiu Wang * to its own domain. 1939e28f653SShengjiu Wang */ 1949e28f653SShengjiu Wang if (of_device_is_compatible(np, "fsl,imx8qm-mqs")) 1959e28f653SShengjiu Wang mqs_priv->use_gpr = false; 1969e28f653SShengjiu Wang else 1979e28f653SShengjiu Wang mqs_priv->use_gpr = true; 1989e28f653SShengjiu Wang 1999e28f653SShengjiu Wang if (mqs_priv->use_gpr) { 2009e28f653SShengjiu Wang gpr_np = of_parse_phandle(np, "gpr", 0); 201a9d27367SDan Carpenter if (!gpr_np) { 2029e28f653SShengjiu Wang dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); 203a9d27367SDan Carpenter return -EINVAL; 2049e28f653SShengjiu Wang } 2059e28f653SShengjiu Wang 2069e28f653SShengjiu Wang mqs_priv->regmap = syscon_node_to_regmap(gpr_np); 2079e28f653SShengjiu Wang if (IS_ERR(mqs_priv->regmap)) { 2089e28f653SShengjiu Wang dev_err(&pdev->dev, "failed to get gpr regmap\n"); 2099e28f653SShengjiu Wang ret = PTR_ERR(mqs_priv->regmap); 210a9d27367SDan Carpenter goto err_free_gpr_np; 2119e28f653SShengjiu Wang } 2129e28f653SShengjiu Wang } else { 2139e28f653SShengjiu Wang regs = devm_platform_ioremap_resource(pdev, 0); 2149e28f653SShengjiu Wang if (IS_ERR(regs)) 2159e28f653SShengjiu Wang return PTR_ERR(regs); 2169e28f653SShengjiu Wang 2179e28f653SShengjiu Wang mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 2189e28f653SShengjiu Wang "core", 2199e28f653SShengjiu Wang regs, 2209e28f653SShengjiu Wang &fsl_mqs_regmap_config); 2219e28f653SShengjiu Wang if (IS_ERR(mqs_priv->regmap)) { 2229e28f653SShengjiu Wang dev_err(&pdev->dev, "failed to init regmap: %ld\n", 2239e28f653SShengjiu Wang PTR_ERR(mqs_priv->regmap)); 2249e28f653SShengjiu Wang return PTR_ERR(mqs_priv->regmap); 2259e28f653SShengjiu Wang } 2269e28f653SShengjiu Wang 2279e28f653SShengjiu Wang mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); 2289e28f653SShengjiu Wang if (IS_ERR(mqs_priv->ipg)) { 2299e28f653SShengjiu Wang dev_err(&pdev->dev, "failed to get the clock: %ld\n", 2309e28f653SShengjiu Wang PTR_ERR(mqs_priv->ipg)); 231a9d27367SDan Carpenter return PTR_ERR(mqs_priv->ipg); 2329e28f653SShengjiu Wang } 2339e28f653SShengjiu Wang } 2349e28f653SShengjiu Wang 2359e28f653SShengjiu Wang mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); 2369e28f653SShengjiu Wang if (IS_ERR(mqs_priv->mclk)) { 2379e28f653SShengjiu Wang dev_err(&pdev->dev, "failed to get the clock: %ld\n", 2389e28f653SShengjiu Wang PTR_ERR(mqs_priv->mclk)); 239a9d27367SDan Carpenter ret = PTR_ERR(mqs_priv->mclk); 240a9d27367SDan Carpenter goto err_free_gpr_np; 2419e28f653SShengjiu Wang } 2429e28f653SShengjiu Wang 2439e28f653SShengjiu Wang dev_set_drvdata(&pdev->dev, mqs_priv); 2449e28f653SShengjiu Wang pm_runtime_enable(&pdev->dev); 2459e28f653SShengjiu Wang 246a9d27367SDan Carpenter ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, 2479e28f653SShengjiu Wang &fsl_mqs_dai, 1); 248a9d27367SDan Carpenter if (ret) 249a9d27367SDan Carpenter goto err_free_gpr_np; 250a9d27367SDan Carpenter return 0; 251a9d27367SDan Carpenter 252a9d27367SDan Carpenter err_free_gpr_np: 2539e28f653SShengjiu Wang of_node_put(gpr_np); 2549e28f653SShengjiu Wang 2559e28f653SShengjiu Wang return ret; 2569e28f653SShengjiu Wang } 2579e28f653SShengjiu Wang 2589e28f653SShengjiu Wang static int fsl_mqs_remove(struct platform_device *pdev) 2599e28f653SShengjiu Wang { 2609e28f653SShengjiu Wang pm_runtime_disable(&pdev->dev); 2619e28f653SShengjiu Wang return 0; 2629e28f653SShengjiu Wang } 2639e28f653SShengjiu Wang 2649e28f653SShengjiu Wang #ifdef CONFIG_PM 2659e28f653SShengjiu Wang static int fsl_mqs_runtime_resume(struct device *dev) 2669e28f653SShengjiu Wang { 2679e28f653SShengjiu Wang struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 26815217d17SShengjiu Wang int ret; 2699e28f653SShengjiu Wang 27015217d17SShengjiu Wang ret = clk_prepare_enable(mqs_priv->ipg); 27115217d17SShengjiu Wang if (ret) { 27215217d17SShengjiu Wang dev_err(dev, "failed to enable ipg clock\n"); 27315217d17SShengjiu Wang return ret; 27415217d17SShengjiu Wang } 2759e28f653SShengjiu Wang 27615217d17SShengjiu Wang ret = clk_prepare_enable(mqs_priv->mclk); 27715217d17SShengjiu Wang if (ret) { 27815217d17SShengjiu Wang dev_err(dev, "failed to enable mclk clock\n"); 27915217d17SShengjiu Wang clk_disable_unprepare(mqs_priv->ipg); 28015217d17SShengjiu Wang return ret; 28115217d17SShengjiu Wang } 2829e28f653SShengjiu Wang 2839e28f653SShengjiu Wang if (mqs_priv->use_gpr) 2849e28f653SShengjiu Wang regmap_write(mqs_priv->regmap, IOMUXC_GPR2, 2859e28f653SShengjiu Wang mqs_priv->reg_iomuxc_gpr2); 2869e28f653SShengjiu Wang else 2879e28f653SShengjiu Wang regmap_write(mqs_priv->regmap, REG_MQS_CTRL, 2889e28f653SShengjiu Wang mqs_priv->reg_mqs_ctrl); 2899e28f653SShengjiu Wang return 0; 2909e28f653SShengjiu Wang } 2919e28f653SShengjiu Wang 2929e28f653SShengjiu Wang static int fsl_mqs_runtime_suspend(struct device *dev) 2939e28f653SShengjiu Wang { 2949e28f653SShengjiu Wang struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 2959e28f653SShengjiu Wang 2969e28f653SShengjiu Wang if (mqs_priv->use_gpr) 2979e28f653SShengjiu Wang regmap_read(mqs_priv->regmap, IOMUXC_GPR2, 2989e28f653SShengjiu Wang &mqs_priv->reg_iomuxc_gpr2); 2999e28f653SShengjiu Wang else 3009e28f653SShengjiu Wang regmap_read(mqs_priv->regmap, REG_MQS_CTRL, 3019e28f653SShengjiu Wang &mqs_priv->reg_mqs_ctrl); 3029e28f653SShengjiu Wang 3039e28f653SShengjiu Wang clk_disable_unprepare(mqs_priv->mclk); 3049e28f653SShengjiu Wang clk_disable_unprepare(mqs_priv->ipg); 3059e28f653SShengjiu Wang 3069e28f653SShengjiu Wang return 0; 3079e28f653SShengjiu Wang } 3089e28f653SShengjiu Wang #endif 3099e28f653SShengjiu Wang 3109e28f653SShengjiu Wang static const struct dev_pm_ops fsl_mqs_pm_ops = { 3119e28f653SShengjiu Wang SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, 3129e28f653SShengjiu Wang fsl_mqs_runtime_resume, 3139e28f653SShengjiu Wang NULL) 3149e28f653SShengjiu Wang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 3159e28f653SShengjiu Wang pm_runtime_force_resume) 3169e28f653SShengjiu Wang }; 3179e28f653SShengjiu Wang 3189e28f653SShengjiu Wang static const struct of_device_id fsl_mqs_dt_ids[] = { 3199e28f653SShengjiu Wang { .compatible = "fsl,imx8qm-mqs", }, 3209e28f653SShengjiu Wang { .compatible = "fsl,imx6sx-mqs", }, 3219e28f653SShengjiu Wang {} 3229e28f653SShengjiu Wang }; 3239e28f653SShengjiu Wang MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); 3249e28f653SShengjiu Wang 3259e28f653SShengjiu Wang static struct platform_driver fsl_mqs_driver = { 3269e28f653SShengjiu Wang .probe = fsl_mqs_probe, 3279e28f653SShengjiu Wang .remove = fsl_mqs_remove, 3289e28f653SShengjiu Wang .driver = { 3299e28f653SShengjiu Wang .name = "fsl-mqs", 3309e28f653SShengjiu Wang .of_match_table = fsl_mqs_dt_ids, 3319e28f653SShengjiu Wang .pm = &fsl_mqs_pm_ops, 3329e28f653SShengjiu Wang }, 3339e28f653SShengjiu Wang }; 3349e28f653SShengjiu Wang 3359e28f653SShengjiu Wang module_platform_driver(fsl_mqs_driver); 3369e28f653SShengjiu Wang 3379e28f653SShengjiu Wang MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>"); 3389e28f653SShengjiu Wang MODULE_DESCRIPTION("MQS codec driver"); 3399e28f653SShengjiu Wang MODULE_LICENSE("GPL v2"); 3409e28f653SShengjiu Wang MODULE_ALIAS("platform: fsl-mqs"); 341