1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // Copyright 2018 NXP 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/interrupt.h> 8 #include <linux/kobject.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 #include <linux/dma/imx-dma.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 26 #include "fsl_micfil.h" 27 #include "fsl_utils.h" 28 29 #define MICFIL_OSR_DEFAULT 16 30 31 #define MICFIL_NUM_RATES 7 32 #define MICFIL_CLK_SRC_NUM 3 33 /* clock source ids */ 34 #define MICFIL_AUDIO_PLL1 0 35 #define MICFIL_AUDIO_PLL2 1 36 #define MICFIL_CLK_EXT3 2 37 38 static const unsigned int fsl_micfil_rates[] = { 39 8000, 11025, 16000, 22050, 32000, 44100, 48000, 40 }; 41 42 static const struct snd_pcm_hw_constraint_list fsl_micfil_rate_constraints = { 43 .count = ARRAY_SIZE(fsl_micfil_rates), 44 .list = fsl_micfil_rates, 45 }; 46 47 enum quality { 48 QUALITY_HIGH, 49 QUALITY_MEDIUM, 50 QUALITY_LOW, 51 QUALITY_VLOW0, 52 QUALITY_VLOW1, 53 QUALITY_VLOW2, 54 }; 55 56 struct fsl_micfil { 57 struct platform_device *pdev; 58 struct regmap *regmap; 59 const struct fsl_micfil_soc_data *soc; 60 struct clk *busclk; 61 struct clk *mclk; 62 struct clk *pll8k_clk; 63 struct clk *pll11k_clk; 64 struct clk *clk_src[MICFIL_CLK_SRC_NUM]; 65 struct snd_dmaengine_dai_dma_data dma_params_rx; 66 struct sdma_peripheral_config sdmacfg; 67 struct snd_soc_card *card; 68 struct snd_pcm_hw_constraint_list constraint_rates; 69 unsigned int constraint_rates_list[MICFIL_NUM_RATES]; 70 unsigned int dataline; 71 char name[32]; 72 int irq[MICFIL_IRQ_LINES]; 73 enum quality quality; 74 int dc_remover; 75 int vad_init_mode; 76 int vad_enabled; 77 int vad_detected; 78 struct fsl_micfil_verid verid; 79 struct fsl_micfil_param param; 80 bool mclk_flag; /* mclk enable flag */ 81 }; 82 83 struct fsl_micfil_soc_data { 84 unsigned int fifos; 85 unsigned int fifo_depth; 86 unsigned int dataline; 87 bool imx; 88 bool use_edma; 89 bool use_verid; 90 bool volume_sx; 91 u64 formats; 92 int fifo_offset; 93 }; 94 95 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { 96 .imx = true, 97 .fifos = 8, 98 .fifo_depth = 8, 99 .dataline = 0xf, 100 .formats = SNDRV_PCM_FMTBIT_S16_LE, 101 .volume_sx = true, 102 .fifo_offset = 0, 103 }; 104 105 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = { 106 .imx = true, 107 .fifos = 8, 108 .fifo_depth = 32, 109 .dataline = 0xf, 110 .formats = SNDRV_PCM_FMTBIT_S32_LE, 111 .volume_sx = false, 112 .fifo_offset = 0, 113 }; 114 115 static struct fsl_micfil_soc_data fsl_micfil_imx93 = { 116 .imx = true, 117 .fifos = 8, 118 .fifo_depth = 32, 119 .dataline = 0xf, 120 .formats = SNDRV_PCM_FMTBIT_S32_LE, 121 .use_edma = true, 122 .use_verid = true, 123 .volume_sx = false, 124 .fifo_offset = 0, 125 }; 126 127 static struct fsl_micfil_soc_data fsl_micfil_imx943 = { 128 .imx = true, 129 .fifos = 8, 130 .fifo_depth = 32, 131 .dataline = 0xf, 132 .formats = SNDRV_PCM_FMTBIT_S32_LE, 133 .use_edma = true, 134 .use_verid = true, 135 .volume_sx = false, 136 .fifo_offset = -4, 137 }; 138 139 static const struct of_device_id fsl_micfil_dt_ids[] = { 140 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, 141 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp }, 142 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 }, 143 { .compatible = "fsl,imx943-micfil", .data = &fsl_micfil_imx943 }, 144 {} 145 }; 146 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); 147 148 static const char * const micfil_quality_select_texts[] = { 149 [QUALITY_HIGH] = "High", 150 [QUALITY_MEDIUM] = "Medium", 151 [QUALITY_LOW] = "Low", 152 [QUALITY_VLOW0] = "VLow0", 153 [QUALITY_VLOW1] = "Vlow1", 154 [QUALITY_VLOW2] = "Vlow2", 155 }; 156 157 static const struct soc_enum fsl_micfil_quality_enum = 158 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts), 159 micfil_quality_select_texts); 160 161 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); 162 163 static int micfil_set_quality(struct fsl_micfil *micfil) 164 { 165 u32 qsel; 166 167 switch (micfil->quality) { 168 case QUALITY_HIGH: 169 qsel = MICFIL_QSEL_HIGH_QUALITY; 170 break; 171 case QUALITY_MEDIUM: 172 qsel = MICFIL_QSEL_MEDIUM_QUALITY; 173 break; 174 case QUALITY_LOW: 175 qsel = MICFIL_QSEL_LOW_QUALITY; 176 break; 177 case QUALITY_VLOW0: 178 qsel = MICFIL_QSEL_VLOW0_QUALITY; 179 break; 180 case QUALITY_VLOW1: 181 qsel = MICFIL_QSEL_VLOW1_QUALITY; 182 break; 183 case QUALITY_VLOW2: 184 qsel = MICFIL_QSEL_VLOW2_QUALITY; 185 break; 186 } 187 188 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 189 MICFIL_CTRL2_QSEL, 190 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel)); 191 } 192 193 static int micfil_quality_get(struct snd_kcontrol *kcontrol, 194 struct snd_ctl_elem_value *ucontrol) 195 { 196 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 197 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 198 199 ucontrol->value.integer.value[0] = micfil->quality; 200 201 return 0; 202 } 203 204 static int micfil_quality_set(struct snd_kcontrol *kcontrol, 205 struct snd_ctl_elem_value *ucontrol) 206 { 207 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 208 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 209 210 micfil->quality = ucontrol->value.integer.value[0]; 211 212 return micfil_set_quality(micfil); 213 } 214 215 static const char * const micfil_hwvad_enable[] = { 216 "Disable (Record only)", 217 "Enable (Record with Vad)", 218 }; 219 220 static const char * const micfil_hwvad_init_mode[] = { 221 "Envelope mode", "Energy mode", 222 }; 223 224 static const char * const micfil_hwvad_hpf_texts[] = { 225 "Filter bypass", 226 "Cut-off @1750Hz", 227 "Cut-off @215Hz", 228 "Cut-off @102Hz", 229 }; 230 231 /* 232 * DC Remover Control 233 * Filter Bypassed 1 1 234 * Cut-off @21Hz 0 0 235 * Cut-off @83Hz 0 1 236 * Cut-off @152HZ 1 0 237 */ 238 static const char * const micfil_dc_remover_texts[] = { 239 "Cut-off @21Hz", "Cut-off @83Hz", 240 "Cut-off @152Hz", "Bypass", 241 }; 242 243 static const struct soc_enum hwvad_enable_enum = 244 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable), 245 micfil_hwvad_enable); 246 static const struct soc_enum hwvad_init_mode_enum = 247 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode), 248 micfil_hwvad_init_mode); 249 static const struct soc_enum hwvad_hpf_enum = 250 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0, 251 ARRAY_SIZE(micfil_hwvad_hpf_texts), 252 micfil_hwvad_hpf_texts); 253 static const struct soc_enum fsl_micfil_dc_remover_enum = 254 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts), 255 micfil_dc_remover_texts); 256 257 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol, 258 struct snd_ctl_elem_value *ucontrol) 259 { 260 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 261 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 262 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 263 unsigned int *item = ucontrol->value.enumerated.item; 264 int val = snd_soc_enum_item_to_val(e, item[0]); 265 int i = 0, ret = 0; 266 u32 reg_val = 0; 267 268 if (val < 0 || val > 3) 269 return -EINVAL; 270 271 micfil->dc_remover = val; 272 273 /* Calculate total value for all channels */ 274 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 275 reg_val |= val << MICFIL_DC_CHX_SHIFT(i); 276 277 /* Update DC Remover mode for all channels */ 278 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL, 279 MICFIL_DC_CTRL_CONFIG, reg_val); 280 if (ret < 0) 281 return ret; 282 283 return 0; 284 } 285 286 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol, 287 struct snd_ctl_elem_value *ucontrol) 288 { 289 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 290 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 291 292 ucontrol->value.enumerated.item[0] = micfil->dc_remover; 293 294 return 0; 295 } 296 297 static int hwvad_put_enable(struct snd_kcontrol *kcontrol, 298 struct snd_ctl_elem_value *ucontrol) 299 { 300 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 301 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 302 unsigned int *item = ucontrol->value.enumerated.item; 303 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 304 int val = snd_soc_enum_item_to_val(e, item[0]); 305 306 micfil->vad_enabled = val; 307 308 return 0; 309 } 310 311 static int hwvad_get_enable(struct snd_kcontrol *kcontrol, 312 struct snd_ctl_elem_value *ucontrol) 313 { 314 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 315 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 316 317 ucontrol->value.enumerated.item[0] = micfil->vad_enabled; 318 319 return 0; 320 } 321 322 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol, 323 struct snd_ctl_elem_value *ucontrol) 324 { 325 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 326 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 327 unsigned int *item = ucontrol->value.enumerated.item; 328 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 329 int val = snd_soc_enum_item_to_val(e, item[0]); 330 331 /* 0 - Envelope-based Mode 332 * 1 - Energy-based Mode 333 */ 334 micfil->vad_init_mode = val; 335 336 return 0; 337 } 338 339 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol, 340 struct snd_ctl_elem_value *ucontrol) 341 { 342 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 343 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 344 345 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode; 346 347 return 0; 348 } 349 350 static int hwvad_detected(struct snd_kcontrol *kcontrol, 351 struct snd_ctl_elem_value *ucontrol) 352 { 353 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 354 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 355 356 ucontrol->value.enumerated.item[0] = micfil->vad_detected; 357 358 return 0; 359 } 360 361 static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = { 362 SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 363 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv), 364 SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 365 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv), 366 SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 367 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv), 368 SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 369 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv), 370 SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 371 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv), 372 SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 373 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv), 374 SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 375 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv), 376 SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 377 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv), 378 }; 379 380 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = { 381 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 382 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv), 383 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 384 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv), 385 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 386 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv), 387 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 388 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv), 389 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 390 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv), 391 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 392 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv), 393 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 394 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv), 395 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 396 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv), 397 }; 398 399 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { 400 SOC_ENUM_EXT("MICFIL Quality Select", 401 fsl_micfil_quality_enum, 402 micfil_quality_get, micfil_quality_set), 403 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum, 404 hwvad_get_enable, hwvad_put_enable), 405 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum, 406 hwvad_get_init_mode, hwvad_put_init_mode), 407 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum), 408 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0), 409 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch", 410 REG_MICFIL_VAD0_ZCD, 2, 1, 0), 411 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum, 412 micfil_get_dc_remover_state, micfil_put_dc_remover_state), 413 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0), 414 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0), 415 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0), 416 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0), 417 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0), 418 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0), 419 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0), 420 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0), 421 SOC_SINGLE("HWVAD ZCD And Behavior Switch", 422 REG_MICFIL_VAD0_ZCD, 4, 1, 0), 423 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL), 424 }; 425 426 static int fsl_micfil_use_verid(struct device *dev) 427 { 428 struct fsl_micfil *micfil = dev_get_drvdata(dev); 429 unsigned int val; 430 int ret; 431 432 if (!micfil->soc->use_verid) 433 return 0; 434 435 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val); 436 if (ret < 0) 437 return ret; 438 439 dev_dbg(dev, "VERID: 0x%016X\n", val); 440 441 micfil->verid.version = val & 442 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK); 443 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT; 444 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK; 445 446 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val); 447 if (ret < 0) 448 return ret; 449 450 dev_dbg(dev, "PARAM: 0x%016X\n", val); 451 452 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >> 453 MICFIL_PARAM_NUM_HWVAD_SHIFT; 454 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD; 455 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE; 456 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD; 457 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS; 458 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS; 459 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER; 460 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH; 461 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >> 462 MICFIL_PARAM_FIFO_PTRWID_SHIFT; 463 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >> 464 MICFIL_PARAM_NPAIR_SHIFT; 465 466 return 0; 467 } 468 469 /* The SRES is a self-negated bit which provides the CPU with the 470 * capability to initialize the PDM Interface module through the 471 * slave-bus interface. This bit always reads as zero, and this 472 * bit is only effective when MDIS is cleared 473 */ 474 static int fsl_micfil_reset(struct device *dev) 475 { 476 struct fsl_micfil *micfil = dev_get_drvdata(dev); 477 int ret; 478 479 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 480 MICFIL_CTRL1_MDIS); 481 if (ret) 482 return ret; 483 484 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 485 MICFIL_CTRL1_SRES); 486 if (ret) 487 return ret; 488 489 /* 490 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined 491 * as non-volatile register, so SRES still remain in regmap 492 * cache after set, that every update of REG_MICFIL_CTRL1, 493 * software reset happens. so clear it explicitly. 494 */ 495 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 496 MICFIL_CTRL1_SRES); 497 if (ret) 498 return ret; 499 500 /* 501 * Set SRES should clear CHnF flags, But even add delay here 502 * the CHnF may not be cleared sometimes, so clear CHnF explicitly. 503 */ 504 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF); 505 if (ret) 506 return ret; 507 508 return 0; 509 } 510 511 static int fsl_micfil_startup(struct snd_pcm_substream *substream, 512 struct snd_soc_dai *dai) 513 { 514 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 515 516 if (!micfil) { 517 dev_err(dai->dev, "micfil dai priv_data not set\n"); 518 return -EINVAL; 519 } 520 521 if (micfil->constraint_rates.count > 0) 522 snd_pcm_hw_constraint_list(substream->runtime, 0, 523 SNDRV_PCM_HW_PARAM_RATE, 524 &micfil->constraint_rates); 525 526 return 0; 527 } 528 529 /* Enable/disable hwvad interrupts */ 530 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable) 531 { 532 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0; 533 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0; 534 535 /* Voice Activity Detector Error Interruption */ 536 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 537 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg); 538 539 /* Voice Activity Detector Interruption */ 540 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 541 MICFIL_VAD0_CTRL1_IE, vadie_reg); 542 543 return 0; 544 } 545 546 /* Configuration done only in energy-based initialization mode */ 547 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil) 548 { 549 /* Keep the VADFRENDIS bitfield cleared. */ 550 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 551 MICFIL_VAD0_CTRL2_FRENDIS); 552 553 /* Keep the VADPREFEN bitfield cleared. */ 554 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 555 MICFIL_VAD0_CTRL2_PREFEN); 556 557 /* Keep the VADSFILEN bitfield cleared. */ 558 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 559 MICFIL_VAD0_SCONFIG_SFILEN); 560 561 /* Keep the VADSMAXEN bitfield cleared. */ 562 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 563 MICFIL_VAD0_SCONFIG_SMAXEN); 564 565 /* Keep the VADNFILAUTO bitfield asserted. */ 566 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 567 MICFIL_VAD0_NCONFIG_NFILAUT); 568 569 /* Keep the VADNMINEN bitfield cleared. */ 570 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 571 MICFIL_VAD0_NCONFIG_NMINEN); 572 573 /* Keep the VADNDECEN bitfield cleared. */ 574 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 575 MICFIL_VAD0_NCONFIG_NDECEN); 576 577 /* Keep the VADNOREN bitfield cleared. */ 578 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 579 MICFIL_VAD0_NCONFIG_NOREN); 580 581 return 0; 582 } 583 584 /* Configuration done only in envelope-based initialization mode */ 585 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil) 586 { 587 /* Assert the VADFRENDIS bitfield */ 588 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 589 MICFIL_VAD0_CTRL2_FRENDIS); 590 591 /* Assert the VADPREFEN bitfield. */ 592 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 593 MICFIL_VAD0_CTRL2_PREFEN); 594 595 /* Assert the VADSFILEN bitfield. */ 596 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 597 MICFIL_VAD0_SCONFIG_SFILEN); 598 599 /* Assert the VADSMAXEN bitfield. */ 600 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 601 MICFIL_VAD0_SCONFIG_SMAXEN); 602 603 /* Clear the VADNFILAUTO bitfield */ 604 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 605 MICFIL_VAD0_NCONFIG_NFILAUT); 606 607 /* Assert the VADNMINEN bitfield. */ 608 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 609 MICFIL_VAD0_NCONFIG_NMINEN); 610 611 /* Assert the VADNDECEN bitfield. */ 612 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 613 MICFIL_VAD0_NCONFIG_NDECEN); 614 615 /* Assert VADNOREN bitfield. */ 616 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 617 MICFIL_VAD0_NCONFIG_NOREN); 618 619 return 0; 620 } 621 622 /* 623 * Hardware Voice Active Detection: The HWVAD takes data from the input 624 * of a selected PDM microphone to detect if there is any 625 * voice activity. When a voice activity is detected, an interrupt could 626 * be delivered to the system. Initialization in section 8.4: 627 * Can work in two modes: 628 * -> Eneveope-based mode (section 8.4.1) 629 * -> Energy-based mode (section 8.4.2) 630 * 631 * It is important to remark that the HWVAD detector could be enabled 632 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL 633 * bit in STAT register is cleared 634 */ 635 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil) 636 { 637 int ret; 638 639 micfil->vad_detected = 0; 640 641 /* envelope-based specific initialization */ 642 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE) 643 ret = fsl_micfil_init_hwvad_envelope_mode(micfil); 644 else 645 ret = fsl_micfil_init_hwvad_energy_mode(micfil); 646 if (ret) 647 return ret; 648 649 /* Voice Activity Detector Internal Filters Initialization*/ 650 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 651 MICFIL_VAD0_CTRL1_ST10); 652 653 /* Voice Activity Detector Internal Filter */ 654 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 655 MICFIL_VAD0_CTRL1_ST10); 656 657 /* Enable Interrupts */ 658 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1); 659 if (ret) 660 return ret; 661 662 /* Voice Activity Detector Reset */ 663 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 664 MICFIL_VAD0_CTRL1_RST); 665 666 /* Voice Activity Detector Enabled */ 667 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 668 MICFIL_VAD0_CTRL1_EN); 669 670 return 0; 671 } 672 673 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil) 674 { 675 struct device *dev = &micfil->pdev->dev; 676 int ret = 0; 677 678 /* Disable HWVAD */ 679 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 680 MICFIL_VAD0_CTRL1_EN); 681 682 /* Disable hwvad interrupts */ 683 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0); 684 if (ret) 685 dev_err(dev, "Failed to disable interrupts\n"); 686 687 return ret; 688 } 689 690 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, 691 struct snd_soc_dai *dai) 692 { 693 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 694 struct device *dev = &micfil->pdev->dev; 695 int ret; 696 697 switch (cmd) { 698 case SNDRV_PCM_TRIGGER_START: 699 case SNDRV_PCM_TRIGGER_RESUME: 700 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 701 ret = fsl_micfil_reset(dev); 702 if (ret) { 703 dev_err(dev, "failed to soft reset\n"); 704 return ret; 705 } 706 707 /* DMA Interrupt Selection - DISEL bits 708 * 00 - DMA and IRQ disabled 709 * 01 - DMA req enabled 710 * 10 - IRQ enabled 711 * 11 - reserved 712 */ 713 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 714 MICFIL_CTRL1_DISEL, 715 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); 716 if (ret) 717 return ret; 718 719 /* Enable the module */ 720 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 721 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN); 722 if (ret) 723 return ret; 724 725 if (micfil->vad_enabled) 726 fsl_micfil_hwvad_enable(micfil); 727 728 break; 729 case SNDRV_PCM_TRIGGER_STOP: 730 case SNDRV_PCM_TRIGGER_SUSPEND: 731 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 732 if (micfil->vad_enabled) 733 fsl_micfil_hwvad_disable(micfil); 734 735 /* Disable the module */ 736 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 737 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN); 738 if (ret) 739 return ret; 740 741 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 742 MICFIL_CTRL1_DISEL, 743 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); 744 if (ret) 745 return ret; 746 break; 747 default: 748 return -EINVAL; 749 } 750 return 0; 751 } 752 753 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate) 754 { 755 struct device *dev = &micfil->pdev->dev; 756 u64 ratio = sample_rate; 757 struct clk *clk; 758 int ret; 759 760 /* Get root clock */ 761 clk = micfil->mclk; 762 763 /* Disable clock first, for it was enabled by pm_runtime */ 764 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk, 765 micfil->pll11k_clk, ratio); 766 ret = clk_prepare_enable(clk); 767 if (ret) 768 return ret; 769 770 return 0; 771 } 772 773 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, 774 struct snd_pcm_hw_params *params, 775 struct snd_soc_dai *dai) 776 { 777 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 778 unsigned int channels = params_channels(params); 779 unsigned int rate = params_rate(params); 780 int clk_div = 8; 781 int osr = MICFIL_OSR_DEFAULT; 782 int ret; 783 784 /* 1. Disable the module */ 785 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 786 MICFIL_CTRL1_PDMIEN); 787 if (ret) 788 return ret; 789 790 /* enable channels */ 791 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 792 0xFF, ((1 << channels) - 1)); 793 if (ret) 794 return ret; 795 796 ret = fsl_micfil_reparent_rootclk(micfil, rate); 797 if (ret) 798 return ret; 799 800 micfil->mclk_flag = true; 801 802 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8); 803 if (ret) 804 return ret; 805 806 ret = micfil_set_quality(micfil); 807 if (ret) 808 return ret; 809 810 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 811 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR, 812 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) | 813 FIELD_PREP(MICFIL_CTRL2_CICOSR, 32 - osr)); 814 815 /* Configure CIC OSR in VADCICOSR */ 816 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 817 MICFIL_VAD0_CTRL1_CICOSR, 818 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr)); 819 820 /* Configure source channel in VADCHSEL */ 821 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 822 MICFIL_VAD0_CTRL1_CHSEL, 823 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1))); 824 825 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; 826 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); 827 micfil->sdmacfg.n_fifos_src = channels; 828 micfil->sdmacfg.sw_done = true; 829 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; 830 if (micfil->soc->use_edma) 831 micfil->dma_params_rx.maxburst = channels; 832 833 return 0; 834 } 835 836 static int fsl_micfil_hw_free(struct snd_pcm_substream *substream, 837 struct snd_soc_dai *dai) 838 { 839 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 840 841 clk_disable_unprepare(micfil->mclk); 842 micfil->mclk_flag = false; 843 844 return 0; 845 } 846 847 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) 848 { 849 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); 850 struct device *dev = cpu_dai->dev; 851 unsigned int val = 0; 852 int ret, i; 853 854 micfil->quality = QUALITY_VLOW0; 855 micfil->card = cpu_dai->component->card; 856 857 /* set default gain to 2 */ 858 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222); 859 860 /* set DC Remover in bypass mode*/ 861 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 862 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i); 863 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL, 864 MICFIL_DC_CTRL_CONFIG, val); 865 if (ret) { 866 dev_err(dev, "failed to set DC Remover mode bits\n"); 867 return ret; 868 } 869 micfil->dc_remover = MICFIL_DC_BYPASS; 870 871 snd_soc_dai_init_dma_data(cpu_dai, NULL, 872 &micfil->dma_params_rx); 873 874 /* FIFO Watermark Control - FIFOWMK*/ 875 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, 876 MICFIL_FIFO_CTRL_FIFOWMK, 877 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); 878 if (ret) 879 return ret; 880 881 return 0; 882 } 883 884 static int fsl_micfil_component_probe(struct snd_soc_component *component) 885 { 886 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component); 887 888 if (micfil->soc->volume_sx) 889 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls, 890 ARRAY_SIZE(fsl_micfil_volume_sx_controls)); 891 else 892 snd_soc_add_component_controls(component, fsl_micfil_volume_controls, 893 ARRAY_SIZE(fsl_micfil_volume_controls)); 894 895 return 0; 896 } 897 898 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { 899 .probe = fsl_micfil_dai_probe, 900 .startup = fsl_micfil_startup, 901 .trigger = fsl_micfil_trigger, 902 .hw_params = fsl_micfil_hw_params, 903 .hw_free = fsl_micfil_hw_free, 904 }; 905 906 static struct snd_soc_dai_driver fsl_micfil_dai = { 907 .capture = { 908 .stream_name = "CPU-Capture", 909 .channels_min = 1, 910 .channels_max = 8, 911 .rates = SNDRV_PCM_RATE_8000_48000, 912 .formats = SNDRV_PCM_FMTBIT_S16_LE, 913 }, 914 .ops = &fsl_micfil_dai_ops, 915 }; 916 917 static const struct snd_soc_component_driver fsl_micfil_component = { 918 .name = "fsl-micfil-dai", 919 .probe = fsl_micfil_component_probe, 920 .controls = fsl_micfil_snd_controls, 921 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), 922 .legacy_dai_naming = 1, 923 }; 924 925 /* REGMAP */ 926 static const struct reg_default fsl_micfil_reg_defaults[] = { 927 {REG_MICFIL_CTRL1, 0x00000000}, 928 {REG_MICFIL_CTRL2, 0x00000000}, 929 {REG_MICFIL_STAT, 0x00000000}, 930 {REG_MICFIL_FIFO_CTRL, 0x0000001F}, 931 {REG_MICFIL_FIFO_STAT, 0x00000000}, 932 {REG_MICFIL_DATACH0, 0x00000000}, 933 {REG_MICFIL_DATACH1, 0x00000000}, 934 {REG_MICFIL_DATACH2, 0x00000000}, 935 {REG_MICFIL_DATACH3, 0x00000000}, 936 {REG_MICFIL_DATACH4, 0x00000000}, 937 {REG_MICFIL_DATACH5, 0x00000000}, 938 {REG_MICFIL_DATACH6, 0x00000000}, 939 {REG_MICFIL_DATACH7, 0x00000000}, 940 {REG_MICFIL_DC_CTRL, 0x00000000}, 941 {REG_MICFIL_OUT_CTRL, 0x00000000}, 942 {REG_MICFIL_OUT_STAT, 0x00000000}, 943 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 944 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 945 {REG_MICFIL_VAD0_STAT, 0x00000000}, 946 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 947 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 948 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 949 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 950 }; 951 952 static const struct reg_default fsl_micfil_reg_defaults_v2[] = { 953 {REG_MICFIL_CTRL1, 0x00000000}, 954 {REG_MICFIL_CTRL2, 0x00000000}, 955 {REG_MICFIL_STAT, 0x00000000}, 956 {REG_MICFIL_FIFO_CTRL, 0x0000001F}, 957 {REG_MICFIL_FIFO_STAT, 0x00000000}, 958 {REG_MICFIL_DATACH0 - 0x4, 0x00000000}, 959 {REG_MICFIL_DATACH1 - 0x4, 0x00000000}, 960 {REG_MICFIL_DATACH2 - 0x4, 0x00000000}, 961 {REG_MICFIL_DATACH3 - 0x4, 0x00000000}, 962 {REG_MICFIL_DATACH4 - 0x4, 0x00000000}, 963 {REG_MICFIL_DATACH5 - 0x4, 0x00000000}, 964 {REG_MICFIL_DATACH6 - 0x4, 0x00000000}, 965 {REG_MICFIL_DATACH7 - 0x4, 0x00000000}, 966 {REG_MICFIL_DC_CTRL, 0x00000000}, 967 {REG_MICFIL_OUT_CTRL, 0x00000000}, 968 {REG_MICFIL_OUT_STAT, 0x00000000}, 969 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 970 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 971 {REG_MICFIL_VAD0_STAT, 0x00000000}, 972 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 973 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 974 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 975 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 976 }; 977 978 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) 979 { 980 struct fsl_micfil *micfil = dev_get_drvdata(dev); 981 int ofs = micfil->soc->fifo_offset; 982 983 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs)) 984 return true; 985 986 switch (reg) { 987 case REG_MICFIL_CTRL1: 988 case REG_MICFIL_CTRL2: 989 case REG_MICFIL_STAT: 990 case REG_MICFIL_FIFO_CTRL: 991 case REG_MICFIL_FIFO_STAT: 992 case REG_MICFIL_DC_CTRL: 993 case REG_MICFIL_OUT_CTRL: 994 case REG_MICFIL_OUT_STAT: 995 case REG_MICFIL_VAD0_CTRL1: 996 case REG_MICFIL_VAD0_CTRL2: 997 case REG_MICFIL_VAD0_STAT: 998 case REG_MICFIL_VAD0_SCONFIG: 999 case REG_MICFIL_VAD0_NCONFIG: 1000 case REG_MICFIL_VAD0_NDATA: 1001 case REG_MICFIL_VAD0_ZCD: 1002 return true; 1003 case REG_MICFIL_FSYNC_CTRL: 1004 case REG_MICFIL_VERID: 1005 case REG_MICFIL_PARAM: 1006 if (micfil->soc->use_verid) 1007 return true; 1008 fallthrough; 1009 default: 1010 return false; 1011 } 1012 } 1013 1014 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) 1015 { 1016 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1017 1018 switch (reg) { 1019 case REG_MICFIL_CTRL1: 1020 case REG_MICFIL_CTRL2: 1021 case REG_MICFIL_STAT: /* Write 1 to Clear */ 1022 case REG_MICFIL_FIFO_CTRL: 1023 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ 1024 case REG_MICFIL_DC_CTRL: 1025 case REG_MICFIL_OUT_CTRL: 1026 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ 1027 case REG_MICFIL_VAD0_CTRL1: 1028 case REG_MICFIL_VAD0_CTRL2: 1029 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ 1030 case REG_MICFIL_VAD0_SCONFIG: 1031 case REG_MICFIL_VAD0_NCONFIG: 1032 case REG_MICFIL_VAD0_ZCD: 1033 return true; 1034 case REG_MICFIL_FSYNC_CTRL: 1035 if (micfil->soc->use_verid) 1036 return true; 1037 fallthrough; 1038 default: 1039 return false; 1040 } 1041 } 1042 1043 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) 1044 { 1045 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1046 int ofs = micfil->soc->fifo_offset; 1047 1048 if (reg >= (REG_MICFIL_DATACH0 + ofs) && reg <= (REG_MICFIL_DATACH7 + ofs)) 1049 return true; 1050 1051 switch (reg) { 1052 case REG_MICFIL_STAT: 1053 case REG_MICFIL_FIFO_STAT: 1054 case REG_MICFIL_OUT_STAT: 1055 case REG_MICFIL_VERID: 1056 case REG_MICFIL_PARAM: 1057 case REG_MICFIL_VAD0_STAT: 1058 case REG_MICFIL_VAD0_NDATA: 1059 return true; 1060 default: 1061 return false; 1062 } 1063 } 1064 1065 static const struct regmap_config fsl_micfil_regmap_config = { 1066 .reg_bits = 32, 1067 .reg_stride = 4, 1068 .val_bits = 32, 1069 1070 .max_register = REG_MICFIL_VAD0_ZCD, 1071 .reg_defaults = fsl_micfil_reg_defaults, 1072 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), 1073 .readable_reg = fsl_micfil_readable_reg, 1074 .volatile_reg = fsl_micfil_volatile_reg, 1075 .writeable_reg = fsl_micfil_writeable_reg, 1076 .cache_type = REGCACHE_MAPLE, 1077 }; 1078 1079 static const struct regmap_config fsl_micfil_regmap_config_v2 = { 1080 .reg_bits = 32, 1081 .reg_stride = 4, 1082 .val_bits = 32, 1083 1084 .max_register = REG_MICFIL_VAD0_ZCD, 1085 .reg_defaults = fsl_micfil_reg_defaults_v2, 1086 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults_v2), 1087 .readable_reg = fsl_micfil_readable_reg, 1088 .volatile_reg = fsl_micfil_volatile_reg, 1089 .writeable_reg = fsl_micfil_writeable_reg, 1090 .cache_type = REGCACHE_MAPLE, 1091 }; 1092 1093 /* END OF REGMAP */ 1094 1095 static irqreturn_t micfil_isr(int irq, void *devid) 1096 { 1097 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1098 struct platform_device *pdev = micfil->pdev; 1099 u32 stat_reg; 1100 u32 fifo_stat_reg; 1101 u32 ctrl1_reg; 1102 bool dma_enabled; 1103 int i; 1104 1105 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1106 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); 1107 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 1108 1109 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; 1110 1111 /* Channel 0-7 Output Data Flags */ 1112 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { 1113 if (stat_reg & MICFIL_STAT_CHXF(i)) 1114 dev_dbg(&pdev->dev, 1115 "Data available in Data Channel %d\n", i); 1116 /* if DMA is not enabled, field must be written with 1 1117 * to clear 1118 */ 1119 if (!dma_enabled) 1120 regmap_write_bits(micfil->regmap, 1121 REG_MICFIL_STAT, 1122 MICFIL_STAT_CHXF(i), 1123 MICFIL_STAT_CHXF(i)); 1124 } 1125 1126 for (i = 0; i < MICFIL_FIFO_NUM; i++) { 1127 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) 1128 dev_dbg(&pdev->dev, 1129 "FIFO Overflow Exception flag for channel %d\n", 1130 i); 1131 1132 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) 1133 dev_dbg(&pdev->dev, 1134 "FIFO Underflow Exception flag for channel %d\n", 1135 i); 1136 } 1137 1138 return IRQ_HANDLED; 1139 } 1140 1141 static irqreturn_t micfil_err_isr(int irq, void *devid) 1142 { 1143 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1144 struct platform_device *pdev = micfil->pdev; 1145 u32 fifo_stat_reg; 1146 u32 out_stat_reg; 1147 u32 stat_reg; 1148 1149 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1150 1151 if (stat_reg & MICFIL_STAT_BSY_FIL) 1152 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); 1153 1154 if (stat_reg & MICFIL_STAT_FIR_RDY) 1155 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); 1156 1157 if (stat_reg & MICFIL_STAT_LOWFREQF) { 1158 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); 1159 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 1160 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF); 1161 } 1162 1163 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 1164 regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT, 1165 fifo_stat_reg, fifo_stat_reg); 1166 1167 regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg); 1168 regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT, 1169 out_stat_reg, out_stat_reg); 1170 1171 return IRQ_HANDLED; 1172 } 1173 1174 static irqreturn_t voice_detected_fn(int irq, void *devid) 1175 { 1176 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1177 struct snd_kcontrol *kctl; 1178 1179 if (!micfil->card) 1180 return IRQ_HANDLED; 1181 1182 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected"); 1183 if (!kctl) 1184 return IRQ_HANDLED; 1185 1186 if (micfil->vad_detected) 1187 snd_ctl_notify(micfil->card->snd_card, 1188 SNDRV_CTL_EVENT_MASK_VALUE, 1189 &kctl->id); 1190 1191 return IRQ_HANDLED; 1192 } 1193 1194 static irqreturn_t hwvad_isr(int irq, void *devid) 1195 { 1196 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1197 struct device *dev = &micfil->pdev->dev; 1198 u32 vad0_reg; 1199 int ret; 1200 1201 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1202 1203 /* 1204 * The only difference between MICFIL_VAD0_STAT_EF and 1205 * MICFIL_VAD0_STAT_IF is that the former requires Write 1206 * 1 to Clear. Since both flags are set, it is enough 1207 * to only read one of them 1208 */ 1209 if (vad0_reg & MICFIL_VAD0_STAT_IF) { 1210 /* Write 1 to clear */ 1211 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT, 1212 MICFIL_VAD0_STAT_IF, 1213 MICFIL_VAD0_STAT_IF); 1214 1215 micfil->vad_detected = 1; 1216 } 1217 1218 ret = fsl_micfil_hwvad_disable(micfil); 1219 if (ret) 1220 dev_err(dev, "Failed to disable hwvad\n"); 1221 1222 return IRQ_WAKE_THREAD; 1223 } 1224 1225 static irqreturn_t hwvad_err_isr(int irq, void *devid) 1226 { 1227 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1228 struct device *dev = &micfil->pdev->dev; 1229 u32 vad0_reg; 1230 1231 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1232 1233 if (vad0_reg & MICFIL_VAD0_STAT_INSATF) 1234 dev_dbg(dev, "voice activity input overflow/underflow detected\n"); 1235 1236 return IRQ_HANDLED; 1237 } 1238 1239 static int fsl_micfil_runtime_suspend(struct device *dev); 1240 static int fsl_micfil_runtime_resume(struct device *dev); 1241 1242 static int fsl_micfil_probe(struct platform_device *pdev) 1243 { 1244 struct device_node *np = pdev->dev.of_node; 1245 struct fsl_micfil *micfil; 1246 struct resource *res; 1247 void __iomem *regs; 1248 int ret, i; 1249 1250 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); 1251 if (!micfil) 1252 return -ENOMEM; 1253 1254 micfil->pdev = pdev; 1255 strscpy(micfil->name, np->name, sizeof(micfil->name)); 1256 1257 micfil->soc = of_device_get_match_data(&pdev->dev); 1258 1259 /* ipg_clk is used to control the registers 1260 * ipg_clk_app is used to operate the filter 1261 */ 1262 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); 1263 if (IS_ERR(micfil->mclk)) { 1264 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 1265 PTR_ERR(micfil->mclk)); 1266 return PTR_ERR(micfil->mclk); 1267 } 1268 1269 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); 1270 if (IS_ERR(micfil->busclk)) { 1271 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", 1272 PTR_ERR(micfil->busclk)); 1273 return PTR_ERR(micfil->busclk); 1274 } 1275 1276 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, 1277 &micfil->pll11k_clk); 1278 1279 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk; 1280 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk; 1281 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3"); 1282 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3])) 1283 micfil->clk_src[MICFIL_CLK_EXT3] = NULL; 1284 1285 fsl_asoc_constrain_rates(&micfil->constraint_rates, 1286 &fsl_micfil_rate_constraints, 1287 micfil->clk_src[MICFIL_AUDIO_PLL1], 1288 micfil->clk_src[MICFIL_AUDIO_PLL2], 1289 micfil->clk_src[MICFIL_CLK_EXT3], 1290 micfil->constraint_rates_list); 1291 1292 /* init regmap */ 1293 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1294 if (IS_ERR(regs)) 1295 return PTR_ERR(regs); 1296 1297 if (of_device_is_compatible(np, "fsl,imx943-micfil")) 1298 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1299 regs, 1300 &fsl_micfil_regmap_config_v2); 1301 else 1302 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1303 regs, 1304 &fsl_micfil_regmap_config); 1305 if (IS_ERR(micfil->regmap)) { 1306 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", 1307 PTR_ERR(micfil->regmap)); 1308 return PTR_ERR(micfil->regmap); 1309 } 1310 1311 /* dataline mask for RX */ 1312 ret = of_property_read_u32_index(np, 1313 "fsl,dataline", 1314 0, 1315 &micfil->dataline); 1316 if (ret) 1317 micfil->dataline = 1; 1318 1319 if (micfil->dataline & ~micfil->soc->dataline) { 1320 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", 1321 micfil->soc->dataline); 1322 return -EINVAL; 1323 } 1324 1325 /* get IRQs */ 1326 for (i = 0; i < MICFIL_IRQ_LINES; i++) { 1327 micfil->irq[i] = platform_get_irq(pdev, i); 1328 if (micfil->irq[i] < 0) 1329 return micfil->irq[i]; 1330 } 1331 1332 /* Digital Microphone interface interrupt */ 1333 ret = devm_request_irq(&pdev->dev, micfil->irq[0], 1334 micfil_isr, IRQF_SHARED, 1335 micfil->name, micfil); 1336 if (ret) { 1337 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", 1338 micfil->irq[0]); 1339 return ret; 1340 } 1341 1342 /* Digital Microphone interface error interrupt */ 1343 ret = devm_request_irq(&pdev->dev, micfil->irq[1], 1344 micfil_err_isr, IRQF_SHARED, 1345 micfil->name, micfil); 1346 if (ret) { 1347 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", 1348 micfil->irq[1]); 1349 return ret; 1350 } 1351 1352 /* Digital Microphone interface voice activity detector event */ 1353 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2], 1354 hwvad_isr, voice_detected_fn, 1355 IRQF_SHARED, micfil->name, micfil); 1356 if (ret) { 1357 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n", 1358 micfil->irq[0]); 1359 return ret; 1360 } 1361 1362 /* Digital Microphone interface voice activity detector error */ 1363 ret = devm_request_irq(&pdev->dev, micfil->irq[3], 1364 hwvad_err_isr, IRQF_SHARED, 1365 micfil->name, micfil); 1366 if (ret) { 1367 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n", 1368 micfil->irq[1]); 1369 return ret; 1370 } 1371 1372 micfil->dma_params_rx.chan_name = "rx"; 1373 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0 + micfil->soc->fifo_offset; 1374 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; 1375 1376 platform_set_drvdata(pdev, micfil); 1377 1378 pm_runtime_enable(&pdev->dev); 1379 if (!pm_runtime_enabled(&pdev->dev)) { 1380 ret = fsl_micfil_runtime_resume(&pdev->dev); 1381 if (ret) 1382 goto err_pm_disable; 1383 } 1384 1385 ret = pm_runtime_resume_and_get(&pdev->dev); 1386 if (ret < 0) 1387 goto err_pm_get_sync; 1388 1389 /* Get micfil version */ 1390 ret = fsl_micfil_use_verid(&pdev->dev); 1391 if (ret < 0) 1392 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret); 1393 1394 ret = pm_runtime_put_sync(&pdev->dev); 1395 if (ret < 0 && ret != -ENOSYS) 1396 goto err_pm_get_sync; 1397 1398 regcache_cache_only(micfil->regmap, true); 1399 1400 /* 1401 * Register platform component before registering cpu dai for there 1402 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1403 */ 1404 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1405 if (ret) { 1406 dev_err(&pdev->dev, "failed to pcm register\n"); 1407 goto err_pm_disable; 1408 } 1409 1410 fsl_micfil_dai.capture.formats = micfil->soc->formats; 1411 1412 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, 1413 &fsl_micfil_dai, 1); 1414 if (ret) { 1415 dev_err(&pdev->dev, "failed to register component %s\n", 1416 fsl_micfil_component.name); 1417 goto err_pm_disable; 1418 } 1419 1420 return ret; 1421 1422 err_pm_get_sync: 1423 if (!pm_runtime_status_suspended(&pdev->dev)) 1424 fsl_micfil_runtime_suspend(&pdev->dev); 1425 err_pm_disable: 1426 pm_runtime_disable(&pdev->dev); 1427 1428 return ret; 1429 } 1430 1431 static void fsl_micfil_remove(struct platform_device *pdev) 1432 { 1433 pm_runtime_disable(&pdev->dev); 1434 } 1435 1436 static int fsl_micfil_runtime_suspend(struct device *dev) 1437 { 1438 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1439 1440 regcache_cache_only(micfil->regmap, true); 1441 1442 if (micfil->mclk_flag) 1443 clk_disable_unprepare(micfil->mclk); 1444 clk_disable_unprepare(micfil->busclk); 1445 1446 return 0; 1447 } 1448 1449 static int fsl_micfil_runtime_resume(struct device *dev) 1450 { 1451 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1452 int ret; 1453 1454 ret = clk_prepare_enable(micfil->busclk); 1455 if (ret < 0) 1456 return ret; 1457 1458 if (micfil->mclk_flag) { 1459 ret = clk_prepare_enable(micfil->mclk); 1460 if (ret < 0) { 1461 clk_disable_unprepare(micfil->busclk); 1462 return ret; 1463 } 1464 } 1465 1466 regcache_cache_only(micfil->regmap, false); 1467 regcache_mark_dirty(micfil->regmap); 1468 regcache_sync(micfil->regmap); 1469 1470 return 0; 1471 } 1472 1473 static const struct dev_pm_ops fsl_micfil_pm_ops = { 1474 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, 1475 fsl_micfil_runtime_resume, 1476 NULL) 1477 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1478 pm_runtime_force_resume) 1479 }; 1480 1481 static struct platform_driver fsl_micfil_driver = { 1482 .probe = fsl_micfil_probe, 1483 .remove = fsl_micfil_remove, 1484 .driver = { 1485 .name = "fsl-micfil-dai", 1486 .pm = &fsl_micfil_pm_ops, 1487 .of_match_table = fsl_micfil_dt_ids, 1488 }, 1489 }; 1490 module_platform_driver(fsl_micfil_driver); 1491 1492 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); 1493 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); 1494 MODULE_LICENSE("Dual BSD/GPL"); 1495