1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // Copyright 2018 NXP 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/interrupt.h> 8 #include <linux/kobject.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 #include <linux/dma/imx-dma.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 26 #include "fsl_micfil.h" 27 #include "fsl_utils.h" 28 29 #define MICFIL_OSR_DEFAULT 16 30 31 #define MICFIL_NUM_RATES 7 32 #define MICFIL_CLK_SRC_NUM 3 33 /* clock source ids */ 34 #define MICFIL_AUDIO_PLL1 0 35 #define MICFIL_AUDIO_PLL2 1 36 #define MICFIL_CLK_EXT3 2 37 38 enum quality { 39 QUALITY_HIGH, 40 QUALITY_MEDIUM, 41 QUALITY_LOW, 42 QUALITY_VLOW0, 43 QUALITY_VLOW1, 44 QUALITY_VLOW2, 45 }; 46 47 struct fsl_micfil { 48 struct platform_device *pdev; 49 struct regmap *regmap; 50 const struct fsl_micfil_soc_data *soc; 51 struct clk *busclk; 52 struct clk *mclk; 53 struct clk *pll8k_clk; 54 struct clk *pll11k_clk; 55 struct clk *clk_src[MICFIL_CLK_SRC_NUM]; 56 struct snd_dmaengine_dai_dma_data dma_params_rx; 57 struct sdma_peripheral_config sdmacfg; 58 struct snd_soc_card *card; 59 struct snd_pcm_hw_constraint_list constraint_rates; 60 unsigned int constraint_rates_list[MICFIL_NUM_RATES]; 61 unsigned int dataline; 62 char name[32]; 63 int irq[MICFIL_IRQ_LINES]; 64 enum quality quality; 65 int dc_remover; 66 int vad_init_mode; 67 int vad_enabled; 68 int vad_detected; 69 struct fsl_micfil_verid verid; 70 struct fsl_micfil_param param; 71 bool mclk_flag; /* mclk enable flag */ 72 }; 73 74 struct fsl_micfil_soc_data { 75 unsigned int fifos; 76 unsigned int fifo_depth; 77 unsigned int dataline; 78 bool imx; 79 bool use_edma; 80 bool use_verid; 81 bool volume_sx; 82 u64 formats; 83 }; 84 85 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { 86 .imx = true, 87 .fifos = 8, 88 .fifo_depth = 8, 89 .dataline = 0xf, 90 .formats = SNDRV_PCM_FMTBIT_S16_LE, 91 .volume_sx = true, 92 }; 93 94 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = { 95 .imx = true, 96 .fifos = 8, 97 .fifo_depth = 32, 98 .dataline = 0xf, 99 .formats = SNDRV_PCM_FMTBIT_S32_LE, 100 .volume_sx = false, 101 }; 102 103 static struct fsl_micfil_soc_data fsl_micfil_imx93 = { 104 .imx = true, 105 .fifos = 8, 106 .fifo_depth = 32, 107 .dataline = 0xf, 108 .formats = SNDRV_PCM_FMTBIT_S32_LE, 109 .use_edma = true, 110 .use_verid = true, 111 .volume_sx = false, 112 }; 113 114 static const struct of_device_id fsl_micfil_dt_ids[] = { 115 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, 116 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp }, 117 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 }, 118 {} 119 }; 120 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); 121 122 static const char * const micfil_quality_select_texts[] = { 123 [QUALITY_HIGH] = "High", 124 [QUALITY_MEDIUM] = "Medium", 125 [QUALITY_LOW] = "Low", 126 [QUALITY_VLOW0] = "VLow0", 127 [QUALITY_VLOW1] = "Vlow1", 128 [QUALITY_VLOW2] = "Vlow2", 129 }; 130 131 static const struct soc_enum fsl_micfil_quality_enum = 132 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts), 133 micfil_quality_select_texts); 134 135 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); 136 137 static int micfil_set_quality(struct fsl_micfil *micfil) 138 { 139 u32 qsel; 140 141 switch (micfil->quality) { 142 case QUALITY_HIGH: 143 qsel = MICFIL_QSEL_HIGH_QUALITY; 144 break; 145 case QUALITY_MEDIUM: 146 qsel = MICFIL_QSEL_MEDIUM_QUALITY; 147 break; 148 case QUALITY_LOW: 149 qsel = MICFIL_QSEL_LOW_QUALITY; 150 break; 151 case QUALITY_VLOW0: 152 qsel = MICFIL_QSEL_VLOW0_QUALITY; 153 break; 154 case QUALITY_VLOW1: 155 qsel = MICFIL_QSEL_VLOW1_QUALITY; 156 break; 157 case QUALITY_VLOW2: 158 qsel = MICFIL_QSEL_VLOW2_QUALITY; 159 break; 160 } 161 162 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 163 MICFIL_CTRL2_QSEL, 164 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel)); 165 } 166 167 static int micfil_quality_get(struct snd_kcontrol *kcontrol, 168 struct snd_ctl_elem_value *ucontrol) 169 { 170 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 171 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 172 173 ucontrol->value.integer.value[0] = micfil->quality; 174 175 return 0; 176 } 177 178 static int micfil_quality_set(struct snd_kcontrol *kcontrol, 179 struct snd_ctl_elem_value *ucontrol) 180 { 181 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 182 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 183 184 micfil->quality = ucontrol->value.integer.value[0]; 185 186 return micfil_set_quality(micfil); 187 } 188 189 static const char * const micfil_hwvad_enable[] = { 190 "Disable (Record only)", 191 "Enable (Record with Vad)", 192 }; 193 194 static const char * const micfil_hwvad_init_mode[] = { 195 "Envelope mode", "Energy mode", 196 }; 197 198 static const char * const micfil_hwvad_hpf_texts[] = { 199 "Filter bypass", 200 "Cut-off @1750Hz", 201 "Cut-off @215Hz", 202 "Cut-off @102Hz", 203 }; 204 205 /* 206 * DC Remover Control 207 * Filter Bypassed 1 1 208 * Cut-off @21Hz 0 0 209 * Cut-off @83Hz 0 1 210 * Cut-off @152HZ 1 0 211 */ 212 static const char * const micfil_dc_remover_texts[] = { 213 "Cut-off @21Hz", "Cut-off @83Hz", 214 "Cut-off @152Hz", "Bypass", 215 }; 216 217 static const struct soc_enum hwvad_enable_enum = 218 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable), 219 micfil_hwvad_enable); 220 static const struct soc_enum hwvad_init_mode_enum = 221 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode), 222 micfil_hwvad_init_mode); 223 static const struct soc_enum hwvad_hpf_enum = 224 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0, 225 ARRAY_SIZE(micfil_hwvad_hpf_texts), 226 micfil_hwvad_hpf_texts); 227 static const struct soc_enum fsl_micfil_dc_remover_enum = 228 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts), 229 micfil_dc_remover_texts); 230 231 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol, 232 struct snd_ctl_elem_value *ucontrol) 233 { 234 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 235 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 236 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 237 unsigned int *item = ucontrol->value.enumerated.item; 238 int val = snd_soc_enum_item_to_val(e, item[0]); 239 int i = 0, ret = 0; 240 u32 reg_val = 0; 241 242 if (val < 0 || val > 3) 243 return -EINVAL; 244 245 micfil->dc_remover = val; 246 247 /* Calculate total value for all channels */ 248 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 249 reg_val |= val << MICFIL_DC_CHX_SHIFT(i); 250 251 /* Update DC Remover mode for all channels */ 252 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL, 253 MICFIL_DC_CTRL_CONFIG, reg_val); 254 if (ret < 0) 255 return ret; 256 257 return 0; 258 } 259 260 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol, 261 struct snd_ctl_elem_value *ucontrol) 262 { 263 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 264 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 265 266 ucontrol->value.enumerated.item[0] = micfil->dc_remover; 267 268 return 0; 269 } 270 271 static int hwvad_put_enable(struct snd_kcontrol *kcontrol, 272 struct snd_ctl_elem_value *ucontrol) 273 { 274 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 275 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 276 unsigned int *item = ucontrol->value.enumerated.item; 277 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 278 int val = snd_soc_enum_item_to_val(e, item[0]); 279 280 micfil->vad_enabled = val; 281 282 return 0; 283 } 284 285 static int hwvad_get_enable(struct snd_kcontrol *kcontrol, 286 struct snd_ctl_elem_value *ucontrol) 287 { 288 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 289 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 290 291 ucontrol->value.enumerated.item[0] = micfil->vad_enabled; 292 293 return 0; 294 } 295 296 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol, 297 struct snd_ctl_elem_value *ucontrol) 298 { 299 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 300 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 301 unsigned int *item = ucontrol->value.enumerated.item; 302 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 303 int val = snd_soc_enum_item_to_val(e, item[0]); 304 305 /* 0 - Envelope-based Mode 306 * 1 - Energy-based Mode 307 */ 308 micfil->vad_init_mode = val; 309 310 return 0; 311 } 312 313 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol, 314 struct snd_ctl_elem_value *ucontrol) 315 { 316 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 317 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 318 319 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode; 320 321 return 0; 322 } 323 324 static int hwvad_detected(struct snd_kcontrol *kcontrol, 325 struct snd_ctl_elem_value *ucontrol) 326 { 327 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 328 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 329 330 ucontrol->value.enumerated.item[0] = micfil->vad_detected; 331 332 return 0; 333 } 334 335 static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = { 336 SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 337 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv), 338 SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 339 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv), 340 SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 341 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv), 342 SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 343 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv), 344 SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 345 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv), 346 SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 347 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv), 348 SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 349 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv), 350 SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 351 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv), 352 }; 353 354 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = { 355 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 356 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv), 357 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 358 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv), 359 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 360 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv), 361 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 362 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv), 363 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 364 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv), 365 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 366 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv), 367 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 368 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv), 369 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 370 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv), 371 }; 372 373 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { 374 SOC_ENUM_EXT("MICFIL Quality Select", 375 fsl_micfil_quality_enum, 376 micfil_quality_get, micfil_quality_set), 377 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum, 378 hwvad_get_enable, hwvad_put_enable), 379 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum, 380 hwvad_get_init_mode, hwvad_put_init_mode), 381 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum), 382 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0), 383 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch", 384 REG_MICFIL_VAD0_ZCD, 2, 1, 0), 385 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum, 386 micfil_get_dc_remover_state, micfil_put_dc_remover_state), 387 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0), 388 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0), 389 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0), 390 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0), 391 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0), 392 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0), 393 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0), 394 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0), 395 SOC_SINGLE("HWVAD ZCD And Behavior Switch", 396 REG_MICFIL_VAD0_ZCD, 4, 1, 0), 397 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL), 398 }; 399 400 static int fsl_micfil_use_verid(struct device *dev) 401 { 402 struct fsl_micfil *micfil = dev_get_drvdata(dev); 403 unsigned int val; 404 int ret; 405 406 if (!micfil->soc->use_verid) 407 return 0; 408 409 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val); 410 if (ret < 0) 411 return ret; 412 413 dev_dbg(dev, "VERID: 0x%016X\n", val); 414 415 micfil->verid.version = val & 416 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK); 417 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT; 418 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK; 419 420 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val); 421 if (ret < 0) 422 return ret; 423 424 dev_dbg(dev, "PARAM: 0x%016X\n", val); 425 426 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >> 427 MICFIL_PARAM_NUM_HWVAD_SHIFT; 428 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD; 429 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE; 430 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD; 431 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS; 432 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS; 433 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER; 434 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH; 435 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >> 436 MICFIL_PARAM_FIFO_PTRWID_SHIFT; 437 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >> 438 MICFIL_PARAM_NPAIR_SHIFT; 439 440 return 0; 441 } 442 443 /* The SRES is a self-negated bit which provides the CPU with the 444 * capability to initialize the PDM Interface module through the 445 * slave-bus interface. This bit always reads as zero, and this 446 * bit is only effective when MDIS is cleared 447 */ 448 static int fsl_micfil_reset(struct device *dev) 449 { 450 struct fsl_micfil *micfil = dev_get_drvdata(dev); 451 int ret; 452 453 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 454 MICFIL_CTRL1_MDIS); 455 if (ret) 456 return ret; 457 458 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 459 MICFIL_CTRL1_SRES); 460 if (ret) 461 return ret; 462 463 /* 464 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined 465 * as non-volatile register, so SRES still remain in regmap 466 * cache after set, that every update of REG_MICFIL_CTRL1, 467 * software reset happens. so clear it explicitly. 468 */ 469 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 470 MICFIL_CTRL1_SRES); 471 if (ret) 472 return ret; 473 474 /* 475 * Set SRES should clear CHnF flags, But even add delay here 476 * the CHnF may not be cleared sometimes, so clear CHnF explicitly. 477 */ 478 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF); 479 if (ret) 480 return ret; 481 482 return 0; 483 } 484 485 static int fsl_micfil_startup(struct snd_pcm_substream *substream, 486 struct snd_soc_dai *dai) 487 { 488 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 489 unsigned int rates[MICFIL_NUM_RATES] = {8000, 11025, 16000, 22050, 32000, 44100, 48000}; 490 int i, j, k = 0; 491 u64 clk_rate; 492 493 if (!micfil) { 494 dev_err(dai->dev, "micfil dai priv_data not set\n"); 495 return -EINVAL; 496 } 497 498 micfil->constraint_rates.list = micfil->constraint_rates_list; 499 micfil->constraint_rates.count = 0; 500 501 for (j = 0; j < MICFIL_NUM_RATES; j++) { 502 for (i = 0; i < MICFIL_CLK_SRC_NUM; i++) { 503 clk_rate = clk_get_rate(micfil->clk_src[i]); 504 if (clk_rate != 0 && do_div(clk_rate, rates[j]) == 0) { 505 micfil->constraint_rates_list[k++] = rates[j]; 506 micfil->constraint_rates.count++; 507 break; 508 } 509 } 510 } 511 512 if (micfil->constraint_rates.count > 0) 513 snd_pcm_hw_constraint_list(substream->runtime, 0, 514 SNDRV_PCM_HW_PARAM_RATE, 515 &micfil->constraint_rates); 516 517 return 0; 518 } 519 520 /* Enable/disable hwvad interrupts */ 521 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable) 522 { 523 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0; 524 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0; 525 526 /* Voice Activity Detector Error Interruption */ 527 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 528 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg); 529 530 /* Voice Activity Detector Interruption */ 531 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 532 MICFIL_VAD0_CTRL1_IE, vadie_reg); 533 534 return 0; 535 } 536 537 /* Configuration done only in energy-based initialization mode */ 538 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil) 539 { 540 /* Keep the VADFRENDIS bitfield cleared. */ 541 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 542 MICFIL_VAD0_CTRL2_FRENDIS); 543 544 /* Keep the VADPREFEN bitfield cleared. */ 545 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 546 MICFIL_VAD0_CTRL2_PREFEN); 547 548 /* Keep the VADSFILEN bitfield cleared. */ 549 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 550 MICFIL_VAD0_SCONFIG_SFILEN); 551 552 /* Keep the VADSMAXEN bitfield cleared. */ 553 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 554 MICFIL_VAD0_SCONFIG_SMAXEN); 555 556 /* Keep the VADNFILAUTO bitfield asserted. */ 557 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 558 MICFIL_VAD0_NCONFIG_NFILAUT); 559 560 /* Keep the VADNMINEN bitfield cleared. */ 561 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 562 MICFIL_VAD0_NCONFIG_NMINEN); 563 564 /* Keep the VADNDECEN bitfield cleared. */ 565 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 566 MICFIL_VAD0_NCONFIG_NDECEN); 567 568 /* Keep the VADNOREN bitfield cleared. */ 569 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 570 MICFIL_VAD0_NCONFIG_NOREN); 571 572 return 0; 573 } 574 575 /* Configuration done only in envelope-based initialization mode */ 576 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil) 577 { 578 /* Assert the VADFRENDIS bitfield */ 579 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 580 MICFIL_VAD0_CTRL2_FRENDIS); 581 582 /* Assert the VADPREFEN bitfield. */ 583 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 584 MICFIL_VAD0_CTRL2_PREFEN); 585 586 /* Assert the VADSFILEN bitfield. */ 587 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 588 MICFIL_VAD0_SCONFIG_SFILEN); 589 590 /* Assert the VADSMAXEN bitfield. */ 591 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 592 MICFIL_VAD0_SCONFIG_SMAXEN); 593 594 /* Clear the VADNFILAUTO bitfield */ 595 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 596 MICFIL_VAD0_NCONFIG_NFILAUT); 597 598 /* Assert the VADNMINEN bitfield. */ 599 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 600 MICFIL_VAD0_NCONFIG_NMINEN); 601 602 /* Assert the VADNDECEN bitfield. */ 603 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 604 MICFIL_VAD0_NCONFIG_NDECEN); 605 606 /* Assert VADNOREN bitfield. */ 607 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 608 MICFIL_VAD0_NCONFIG_NOREN); 609 610 return 0; 611 } 612 613 /* 614 * Hardware Voice Active Detection: The HWVAD takes data from the input 615 * of a selected PDM microphone to detect if there is any 616 * voice activity. When a voice activity is detected, an interrupt could 617 * be delivered to the system. Initialization in section 8.4: 618 * Can work in two modes: 619 * -> Eneveope-based mode (section 8.4.1) 620 * -> Energy-based mode (section 8.4.2) 621 * 622 * It is important to remark that the HWVAD detector could be enabled 623 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL 624 * bit in STAT register is cleared 625 */ 626 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil) 627 { 628 int ret; 629 630 micfil->vad_detected = 0; 631 632 /* envelope-based specific initialization */ 633 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE) 634 ret = fsl_micfil_init_hwvad_envelope_mode(micfil); 635 else 636 ret = fsl_micfil_init_hwvad_energy_mode(micfil); 637 if (ret) 638 return ret; 639 640 /* Voice Activity Detector Internal Filters Initialization*/ 641 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 642 MICFIL_VAD0_CTRL1_ST10); 643 644 /* Voice Activity Detector Internal Filter */ 645 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 646 MICFIL_VAD0_CTRL1_ST10); 647 648 /* Enable Interrupts */ 649 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1); 650 if (ret) 651 return ret; 652 653 /* Voice Activity Detector Reset */ 654 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 655 MICFIL_VAD0_CTRL1_RST); 656 657 /* Voice Activity Detector Enabled */ 658 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 659 MICFIL_VAD0_CTRL1_EN); 660 661 return 0; 662 } 663 664 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil) 665 { 666 struct device *dev = &micfil->pdev->dev; 667 int ret = 0; 668 669 /* Disable HWVAD */ 670 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 671 MICFIL_VAD0_CTRL1_EN); 672 673 /* Disable hwvad interrupts */ 674 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0); 675 if (ret) 676 dev_err(dev, "Failed to disable interrupts\n"); 677 678 return ret; 679 } 680 681 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, 682 struct snd_soc_dai *dai) 683 { 684 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 685 struct device *dev = &micfil->pdev->dev; 686 int ret; 687 688 switch (cmd) { 689 case SNDRV_PCM_TRIGGER_START: 690 case SNDRV_PCM_TRIGGER_RESUME: 691 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 692 ret = fsl_micfil_reset(dev); 693 if (ret) { 694 dev_err(dev, "failed to soft reset\n"); 695 return ret; 696 } 697 698 /* DMA Interrupt Selection - DISEL bits 699 * 00 - DMA and IRQ disabled 700 * 01 - DMA req enabled 701 * 10 - IRQ enabled 702 * 11 - reserved 703 */ 704 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 705 MICFIL_CTRL1_DISEL, 706 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); 707 if (ret) 708 return ret; 709 710 /* Enable the module */ 711 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 712 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN); 713 if (ret) 714 return ret; 715 716 if (micfil->vad_enabled) 717 fsl_micfil_hwvad_enable(micfil); 718 719 break; 720 case SNDRV_PCM_TRIGGER_STOP: 721 case SNDRV_PCM_TRIGGER_SUSPEND: 722 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 723 if (micfil->vad_enabled) 724 fsl_micfil_hwvad_disable(micfil); 725 726 /* Disable the module */ 727 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 728 MICFIL_CTRL1_PDMIEN | MICFIL_CTRL1_ERREN); 729 if (ret) 730 return ret; 731 732 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 733 MICFIL_CTRL1_DISEL, 734 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); 735 if (ret) 736 return ret; 737 break; 738 default: 739 return -EINVAL; 740 } 741 return 0; 742 } 743 744 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate) 745 { 746 struct device *dev = &micfil->pdev->dev; 747 u64 ratio = sample_rate; 748 struct clk *clk; 749 int ret; 750 751 /* Get root clock */ 752 clk = micfil->mclk; 753 754 /* Disable clock first, for it was enabled by pm_runtime */ 755 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk, 756 micfil->pll11k_clk, ratio); 757 ret = clk_prepare_enable(clk); 758 if (ret) 759 return ret; 760 761 return 0; 762 } 763 764 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, 765 struct snd_pcm_hw_params *params, 766 struct snd_soc_dai *dai) 767 { 768 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 769 unsigned int channels = params_channels(params); 770 unsigned int rate = params_rate(params); 771 int clk_div = 8; 772 int osr = MICFIL_OSR_DEFAULT; 773 int ret; 774 775 /* 1. Disable the module */ 776 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 777 MICFIL_CTRL1_PDMIEN); 778 if (ret) 779 return ret; 780 781 /* enable channels */ 782 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 783 0xFF, ((1 << channels) - 1)); 784 if (ret) 785 return ret; 786 787 ret = fsl_micfil_reparent_rootclk(micfil, rate); 788 if (ret) 789 return ret; 790 791 micfil->mclk_flag = true; 792 793 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8); 794 if (ret) 795 return ret; 796 797 ret = micfil_set_quality(micfil); 798 if (ret) 799 return ret; 800 801 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 802 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR, 803 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) | 804 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr)); 805 806 /* Configure CIC OSR in VADCICOSR */ 807 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 808 MICFIL_VAD0_CTRL1_CICOSR, 809 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr)); 810 811 /* Configure source channel in VADCHSEL */ 812 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 813 MICFIL_VAD0_CTRL1_CHSEL, 814 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1))); 815 816 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; 817 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); 818 micfil->sdmacfg.n_fifos_src = channels; 819 micfil->sdmacfg.sw_done = true; 820 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; 821 if (micfil->soc->use_edma) 822 micfil->dma_params_rx.maxburst = channels; 823 824 return 0; 825 } 826 827 static int fsl_micfil_hw_free(struct snd_pcm_substream *substream, 828 struct snd_soc_dai *dai) 829 { 830 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 831 832 clk_disable_unprepare(micfil->mclk); 833 micfil->mclk_flag = false; 834 835 return 0; 836 } 837 838 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) 839 { 840 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); 841 struct device *dev = cpu_dai->dev; 842 unsigned int val = 0; 843 int ret, i; 844 845 micfil->quality = QUALITY_VLOW0; 846 micfil->card = cpu_dai->component->card; 847 848 /* set default gain to 2 */ 849 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222); 850 851 /* set DC Remover in bypass mode*/ 852 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 853 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i); 854 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL, 855 MICFIL_DC_CTRL_CONFIG, val); 856 if (ret) { 857 dev_err(dev, "failed to set DC Remover mode bits\n"); 858 return ret; 859 } 860 micfil->dc_remover = MICFIL_DC_BYPASS; 861 862 snd_soc_dai_init_dma_data(cpu_dai, NULL, 863 &micfil->dma_params_rx); 864 865 /* FIFO Watermark Control - FIFOWMK*/ 866 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, 867 MICFIL_FIFO_CTRL_FIFOWMK, 868 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); 869 if (ret) 870 return ret; 871 872 return 0; 873 } 874 875 static int fsl_micfil_component_probe(struct snd_soc_component *component) 876 { 877 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component); 878 879 if (micfil->soc->volume_sx) 880 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls, 881 ARRAY_SIZE(fsl_micfil_volume_sx_controls)); 882 else 883 snd_soc_add_component_controls(component, fsl_micfil_volume_controls, 884 ARRAY_SIZE(fsl_micfil_volume_controls)); 885 886 return 0; 887 } 888 889 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { 890 .probe = fsl_micfil_dai_probe, 891 .startup = fsl_micfil_startup, 892 .trigger = fsl_micfil_trigger, 893 .hw_params = fsl_micfil_hw_params, 894 .hw_free = fsl_micfil_hw_free, 895 }; 896 897 static struct snd_soc_dai_driver fsl_micfil_dai = { 898 .capture = { 899 .stream_name = "CPU-Capture", 900 .channels_min = 1, 901 .channels_max = 8, 902 .rates = SNDRV_PCM_RATE_8000_48000, 903 .formats = SNDRV_PCM_FMTBIT_S16_LE, 904 }, 905 .ops = &fsl_micfil_dai_ops, 906 }; 907 908 static const struct snd_soc_component_driver fsl_micfil_component = { 909 .name = "fsl-micfil-dai", 910 .probe = fsl_micfil_component_probe, 911 .controls = fsl_micfil_snd_controls, 912 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), 913 .legacy_dai_naming = 1, 914 }; 915 916 /* REGMAP */ 917 static const struct reg_default fsl_micfil_reg_defaults[] = { 918 {REG_MICFIL_CTRL1, 0x00000000}, 919 {REG_MICFIL_CTRL2, 0x00000000}, 920 {REG_MICFIL_STAT, 0x00000000}, 921 {REG_MICFIL_FIFO_CTRL, 0x0000001F}, 922 {REG_MICFIL_FIFO_STAT, 0x00000000}, 923 {REG_MICFIL_DATACH0, 0x00000000}, 924 {REG_MICFIL_DATACH1, 0x00000000}, 925 {REG_MICFIL_DATACH2, 0x00000000}, 926 {REG_MICFIL_DATACH3, 0x00000000}, 927 {REG_MICFIL_DATACH4, 0x00000000}, 928 {REG_MICFIL_DATACH5, 0x00000000}, 929 {REG_MICFIL_DATACH6, 0x00000000}, 930 {REG_MICFIL_DATACH7, 0x00000000}, 931 {REG_MICFIL_DC_CTRL, 0x00000000}, 932 {REG_MICFIL_OUT_CTRL, 0x00000000}, 933 {REG_MICFIL_OUT_STAT, 0x00000000}, 934 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 935 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 936 {REG_MICFIL_VAD0_STAT, 0x00000000}, 937 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 938 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 939 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 940 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 941 }; 942 943 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) 944 { 945 struct fsl_micfil *micfil = dev_get_drvdata(dev); 946 947 switch (reg) { 948 case REG_MICFIL_CTRL1: 949 case REG_MICFIL_CTRL2: 950 case REG_MICFIL_STAT: 951 case REG_MICFIL_FIFO_CTRL: 952 case REG_MICFIL_FIFO_STAT: 953 case REG_MICFIL_DATACH0: 954 case REG_MICFIL_DATACH1: 955 case REG_MICFIL_DATACH2: 956 case REG_MICFIL_DATACH3: 957 case REG_MICFIL_DATACH4: 958 case REG_MICFIL_DATACH5: 959 case REG_MICFIL_DATACH6: 960 case REG_MICFIL_DATACH7: 961 case REG_MICFIL_DC_CTRL: 962 case REG_MICFIL_OUT_CTRL: 963 case REG_MICFIL_OUT_STAT: 964 case REG_MICFIL_VAD0_CTRL1: 965 case REG_MICFIL_VAD0_CTRL2: 966 case REG_MICFIL_VAD0_STAT: 967 case REG_MICFIL_VAD0_SCONFIG: 968 case REG_MICFIL_VAD0_NCONFIG: 969 case REG_MICFIL_VAD0_NDATA: 970 case REG_MICFIL_VAD0_ZCD: 971 return true; 972 case REG_MICFIL_FSYNC_CTRL: 973 case REG_MICFIL_VERID: 974 case REG_MICFIL_PARAM: 975 if (micfil->soc->use_verid) 976 return true; 977 fallthrough; 978 default: 979 return false; 980 } 981 } 982 983 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) 984 { 985 struct fsl_micfil *micfil = dev_get_drvdata(dev); 986 987 switch (reg) { 988 case REG_MICFIL_CTRL1: 989 case REG_MICFIL_CTRL2: 990 case REG_MICFIL_STAT: /* Write 1 to Clear */ 991 case REG_MICFIL_FIFO_CTRL: 992 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ 993 case REG_MICFIL_DC_CTRL: 994 case REG_MICFIL_OUT_CTRL: 995 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ 996 case REG_MICFIL_VAD0_CTRL1: 997 case REG_MICFIL_VAD0_CTRL2: 998 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ 999 case REG_MICFIL_VAD0_SCONFIG: 1000 case REG_MICFIL_VAD0_NCONFIG: 1001 case REG_MICFIL_VAD0_ZCD: 1002 return true; 1003 case REG_MICFIL_FSYNC_CTRL: 1004 if (micfil->soc->use_verid) 1005 return true; 1006 fallthrough; 1007 default: 1008 return false; 1009 } 1010 } 1011 1012 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) 1013 { 1014 switch (reg) { 1015 case REG_MICFIL_STAT: 1016 case REG_MICFIL_FIFO_STAT: 1017 case REG_MICFIL_DATACH0: 1018 case REG_MICFIL_DATACH1: 1019 case REG_MICFIL_DATACH2: 1020 case REG_MICFIL_DATACH3: 1021 case REG_MICFIL_DATACH4: 1022 case REG_MICFIL_DATACH5: 1023 case REG_MICFIL_DATACH6: 1024 case REG_MICFIL_DATACH7: 1025 case REG_MICFIL_OUT_STAT: 1026 case REG_MICFIL_VERID: 1027 case REG_MICFIL_PARAM: 1028 case REG_MICFIL_VAD0_STAT: 1029 case REG_MICFIL_VAD0_NDATA: 1030 return true; 1031 default: 1032 return false; 1033 } 1034 } 1035 1036 static const struct regmap_config fsl_micfil_regmap_config = { 1037 .reg_bits = 32, 1038 .reg_stride = 4, 1039 .val_bits = 32, 1040 1041 .max_register = REG_MICFIL_VAD0_ZCD, 1042 .reg_defaults = fsl_micfil_reg_defaults, 1043 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), 1044 .readable_reg = fsl_micfil_readable_reg, 1045 .volatile_reg = fsl_micfil_volatile_reg, 1046 .writeable_reg = fsl_micfil_writeable_reg, 1047 .cache_type = REGCACHE_MAPLE, 1048 }; 1049 1050 /* END OF REGMAP */ 1051 1052 static irqreturn_t micfil_isr(int irq, void *devid) 1053 { 1054 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1055 struct platform_device *pdev = micfil->pdev; 1056 u32 stat_reg; 1057 u32 fifo_stat_reg; 1058 u32 ctrl1_reg; 1059 bool dma_enabled; 1060 int i; 1061 1062 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1063 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); 1064 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 1065 1066 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; 1067 1068 /* Channel 0-7 Output Data Flags */ 1069 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { 1070 if (stat_reg & MICFIL_STAT_CHXF(i)) 1071 dev_dbg(&pdev->dev, 1072 "Data available in Data Channel %d\n", i); 1073 /* if DMA is not enabled, field must be written with 1 1074 * to clear 1075 */ 1076 if (!dma_enabled) 1077 regmap_write_bits(micfil->regmap, 1078 REG_MICFIL_STAT, 1079 MICFIL_STAT_CHXF(i), 1080 MICFIL_STAT_CHXF(i)); 1081 } 1082 1083 for (i = 0; i < MICFIL_FIFO_NUM; i++) { 1084 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) 1085 dev_dbg(&pdev->dev, 1086 "FIFO Overflow Exception flag for channel %d\n", 1087 i); 1088 1089 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) 1090 dev_dbg(&pdev->dev, 1091 "FIFO Underflow Exception flag for channel %d\n", 1092 i); 1093 } 1094 1095 return IRQ_HANDLED; 1096 } 1097 1098 static irqreturn_t micfil_err_isr(int irq, void *devid) 1099 { 1100 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1101 struct platform_device *pdev = micfil->pdev; 1102 u32 fifo_stat_reg; 1103 u32 out_stat_reg; 1104 u32 stat_reg; 1105 1106 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1107 1108 if (stat_reg & MICFIL_STAT_BSY_FIL) 1109 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); 1110 1111 if (stat_reg & MICFIL_STAT_FIR_RDY) 1112 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); 1113 1114 if (stat_reg & MICFIL_STAT_LOWFREQF) { 1115 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); 1116 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 1117 MICFIL_STAT_LOWFREQF, MICFIL_STAT_LOWFREQF); 1118 } 1119 1120 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 1121 regmap_write_bits(micfil->regmap, REG_MICFIL_FIFO_STAT, 1122 fifo_stat_reg, fifo_stat_reg); 1123 1124 regmap_read(micfil->regmap, REG_MICFIL_OUT_STAT, &out_stat_reg); 1125 regmap_write_bits(micfil->regmap, REG_MICFIL_OUT_STAT, 1126 out_stat_reg, out_stat_reg); 1127 1128 return IRQ_HANDLED; 1129 } 1130 1131 static irqreturn_t voice_detected_fn(int irq, void *devid) 1132 { 1133 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1134 struct snd_kcontrol *kctl; 1135 1136 if (!micfil->card) 1137 return IRQ_HANDLED; 1138 1139 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected"); 1140 if (!kctl) 1141 return IRQ_HANDLED; 1142 1143 if (micfil->vad_detected) 1144 snd_ctl_notify(micfil->card->snd_card, 1145 SNDRV_CTL_EVENT_MASK_VALUE, 1146 &kctl->id); 1147 1148 return IRQ_HANDLED; 1149 } 1150 1151 static irqreturn_t hwvad_isr(int irq, void *devid) 1152 { 1153 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1154 struct device *dev = &micfil->pdev->dev; 1155 u32 vad0_reg; 1156 int ret; 1157 1158 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1159 1160 /* 1161 * The only difference between MICFIL_VAD0_STAT_EF and 1162 * MICFIL_VAD0_STAT_IF is that the former requires Write 1163 * 1 to Clear. Since both flags are set, it is enough 1164 * to only read one of them 1165 */ 1166 if (vad0_reg & MICFIL_VAD0_STAT_IF) { 1167 /* Write 1 to clear */ 1168 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT, 1169 MICFIL_VAD0_STAT_IF, 1170 MICFIL_VAD0_STAT_IF); 1171 1172 micfil->vad_detected = 1; 1173 } 1174 1175 ret = fsl_micfil_hwvad_disable(micfil); 1176 if (ret) 1177 dev_err(dev, "Failed to disable hwvad\n"); 1178 1179 return IRQ_WAKE_THREAD; 1180 } 1181 1182 static irqreturn_t hwvad_err_isr(int irq, void *devid) 1183 { 1184 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1185 struct device *dev = &micfil->pdev->dev; 1186 u32 vad0_reg; 1187 1188 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1189 1190 if (vad0_reg & MICFIL_VAD0_STAT_INSATF) 1191 dev_dbg(dev, "voice activity input overflow/underflow detected\n"); 1192 1193 return IRQ_HANDLED; 1194 } 1195 1196 static int fsl_micfil_runtime_suspend(struct device *dev); 1197 static int fsl_micfil_runtime_resume(struct device *dev); 1198 1199 static int fsl_micfil_probe(struct platform_device *pdev) 1200 { 1201 struct device_node *np = pdev->dev.of_node; 1202 struct fsl_micfil *micfil; 1203 struct resource *res; 1204 void __iomem *regs; 1205 int ret, i; 1206 1207 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); 1208 if (!micfil) 1209 return -ENOMEM; 1210 1211 micfil->pdev = pdev; 1212 strscpy(micfil->name, np->name, sizeof(micfil->name)); 1213 1214 micfil->soc = of_device_get_match_data(&pdev->dev); 1215 1216 /* ipg_clk is used to control the registers 1217 * ipg_clk_app is used to operate the filter 1218 */ 1219 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); 1220 if (IS_ERR(micfil->mclk)) { 1221 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 1222 PTR_ERR(micfil->mclk)); 1223 return PTR_ERR(micfil->mclk); 1224 } 1225 1226 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); 1227 if (IS_ERR(micfil->busclk)) { 1228 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", 1229 PTR_ERR(micfil->busclk)); 1230 return PTR_ERR(micfil->busclk); 1231 } 1232 1233 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, 1234 &micfil->pll11k_clk); 1235 1236 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk; 1237 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk; 1238 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3"); 1239 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3])) 1240 micfil->clk_src[MICFIL_CLK_EXT3] = NULL; 1241 1242 /* init regmap */ 1243 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1244 if (IS_ERR(regs)) 1245 return PTR_ERR(regs); 1246 1247 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1248 regs, 1249 &fsl_micfil_regmap_config); 1250 if (IS_ERR(micfil->regmap)) { 1251 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", 1252 PTR_ERR(micfil->regmap)); 1253 return PTR_ERR(micfil->regmap); 1254 } 1255 1256 /* dataline mask for RX */ 1257 ret = of_property_read_u32_index(np, 1258 "fsl,dataline", 1259 0, 1260 &micfil->dataline); 1261 if (ret) 1262 micfil->dataline = 1; 1263 1264 if (micfil->dataline & ~micfil->soc->dataline) { 1265 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", 1266 micfil->soc->dataline); 1267 return -EINVAL; 1268 } 1269 1270 /* get IRQs */ 1271 for (i = 0; i < MICFIL_IRQ_LINES; i++) { 1272 micfil->irq[i] = platform_get_irq(pdev, i); 1273 if (micfil->irq[i] < 0) 1274 return micfil->irq[i]; 1275 } 1276 1277 /* Digital Microphone interface interrupt */ 1278 ret = devm_request_irq(&pdev->dev, micfil->irq[0], 1279 micfil_isr, IRQF_SHARED, 1280 micfil->name, micfil); 1281 if (ret) { 1282 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", 1283 micfil->irq[0]); 1284 return ret; 1285 } 1286 1287 /* Digital Microphone interface error interrupt */ 1288 ret = devm_request_irq(&pdev->dev, micfil->irq[1], 1289 micfil_err_isr, IRQF_SHARED, 1290 micfil->name, micfil); 1291 if (ret) { 1292 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", 1293 micfil->irq[1]); 1294 return ret; 1295 } 1296 1297 /* Digital Microphone interface voice activity detector event */ 1298 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2], 1299 hwvad_isr, voice_detected_fn, 1300 IRQF_SHARED, micfil->name, micfil); 1301 if (ret) { 1302 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n", 1303 micfil->irq[0]); 1304 return ret; 1305 } 1306 1307 /* Digital Microphone interface voice activity detector error */ 1308 ret = devm_request_irq(&pdev->dev, micfil->irq[3], 1309 hwvad_err_isr, IRQF_SHARED, 1310 micfil->name, micfil); 1311 if (ret) { 1312 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n", 1313 micfil->irq[1]); 1314 return ret; 1315 } 1316 1317 micfil->dma_params_rx.chan_name = "rx"; 1318 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; 1319 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; 1320 1321 platform_set_drvdata(pdev, micfil); 1322 1323 pm_runtime_enable(&pdev->dev); 1324 if (!pm_runtime_enabled(&pdev->dev)) { 1325 ret = fsl_micfil_runtime_resume(&pdev->dev); 1326 if (ret) 1327 goto err_pm_disable; 1328 } 1329 1330 ret = pm_runtime_resume_and_get(&pdev->dev); 1331 if (ret < 0) 1332 goto err_pm_get_sync; 1333 1334 /* Get micfil version */ 1335 ret = fsl_micfil_use_verid(&pdev->dev); 1336 if (ret < 0) 1337 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret); 1338 1339 ret = pm_runtime_put_sync(&pdev->dev); 1340 if (ret < 0 && ret != -ENOSYS) 1341 goto err_pm_get_sync; 1342 1343 regcache_cache_only(micfil->regmap, true); 1344 1345 /* 1346 * Register platform component before registering cpu dai for there 1347 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1348 */ 1349 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1350 if (ret) { 1351 dev_err(&pdev->dev, "failed to pcm register\n"); 1352 goto err_pm_disable; 1353 } 1354 1355 fsl_micfil_dai.capture.formats = micfil->soc->formats; 1356 1357 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, 1358 &fsl_micfil_dai, 1); 1359 if (ret) { 1360 dev_err(&pdev->dev, "failed to register component %s\n", 1361 fsl_micfil_component.name); 1362 goto err_pm_disable; 1363 } 1364 1365 return ret; 1366 1367 err_pm_get_sync: 1368 if (!pm_runtime_status_suspended(&pdev->dev)) 1369 fsl_micfil_runtime_suspend(&pdev->dev); 1370 err_pm_disable: 1371 pm_runtime_disable(&pdev->dev); 1372 1373 return ret; 1374 } 1375 1376 static void fsl_micfil_remove(struct platform_device *pdev) 1377 { 1378 pm_runtime_disable(&pdev->dev); 1379 } 1380 1381 static int fsl_micfil_runtime_suspend(struct device *dev) 1382 { 1383 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1384 1385 regcache_cache_only(micfil->regmap, true); 1386 1387 if (micfil->mclk_flag) 1388 clk_disable_unprepare(micfil->mclk); 1389 clk_disable_unprepare(micfil->busclk); 1390 1391 return 0; 1392 } 1393 1394 static int fsl_micfil_runtime_resume(struct device *dev) 1395 { 1396 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1397 int ret; 1398 1399 ret = clk_prepare_enable(micfil->busclk); 1400 if (ret < 0) 1401 return ret; 1402 1403 if (micfil->mclk_flag) { 1404 ret = clk_prepare_enable(micfil->mclk); 1405 if (ret < 0) { 1406 clk_disable_unprepare(micfil->busclk); 1407 return ret; 1408 } 1409 } 1410 1411 regcache_cache_only(micfil->regmap, false); 1412 regcache_mark_dirty(micfil->regmap); 1413 regcache_sync(micfil->regmap); 1414 1415 return 0; 1416 } 1417 1418 static const struct dev_pm_ops fsl_micfil_pm_ops = { 1419 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, 1420 fsl_micfil_runtime_resume, 1421 NULL) 1422 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1423 pm_runtime_force_resume) 1424 }; 1425 1426 static struct platform_driver fsl_micfil_driver = { 1427 .probe = fsl_micfil_probe, 1428 .remove = fsl_micfil_remove, 1429 .driver = { 1430 .name = "fsl-micfil-dai", 1431 .pm = &fsl_micfil_pm_ops, 1432 .of_match_table = fsl_micfil_dt_ids, 1433 }, 1434 }; 1435 module_platform_driver(fsl_micfil_driver); 1436 1437 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); 1438 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); 1439 MODULE_LICENSE("Dual BSD/GPL"); 1440