1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/module.h> 10 #include <linux/of_irq.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_params.h> 15 16 #include "fsl_esai.h" 17 #include "imx-pcm.h" 18 19 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 20 SNDRV_PCM_FMTBIT_S16_LE | \ 21 SNDRV_PCM_FMTBIT_S20_3LE | \ 22 SNDRV_PCM_FMTBIT_S24_LE) 23 24 /** 25 * fsl_esai_soc_data: soc specific data 26 * 27 * @imx: for imx platform 28 * @reset_at_xrun: flags for enable reset operaton 29 */ 30 struct fsl_esai_soc_data { 31 bool imx; 32 bool reset_at_xrun; 33 }; 34 35 /** 36 * fsl_esai: ESAI private data 37 * 38 * @dma_params_rx: DMA parameters for receive channel 39 * @dma_params_tx: DMA parameters for transmit channel 40 * @pdev: platform device pointer 41 * @regmap: regmap handler 42 * @coreclk: clock source to access register 43 * @extalclk: esai clock source to derive HCK, SCK and FS 44 * @fsysclk: system clock source to derive HCK, SCK and FS 45 * @spbaclk: SPBA clock (optional, depending on SoC design) 46 * @task: tasklet to handle the reset operation 47 * @soc: soc specific data 48 * @lock: spin lock between hw_reset() and trigger() 49 * @fifo_depth: depth of tx/rx FIFO 50 * @slot_width: width of each DAI slot 51 * @slots: number of slots 52 * @channels: channel num for tx or rx 53 * @hck_rate: clock rate of desired HCKx clock 54 * @sck_rate: clock rate of desired SCKx clock 55 * @hck_dir: the direction of HCKx pads 56 * @sck_div: if using PSR/PM dividers for SCKx clock 57 * @slave_mode: if fully using DAI slave mode 58 * @synchronous: if using tx/rx synchronous mode 59 * @name: driver name 60 */ 61 struct fsl_esai { 62 struct snd_dmaengine_dai_dma_data dma_params_rx; 63 struct snd_dmaengine_dai_dma_data dma_params_tx; 64 struct platform_device *pdev; 65 struct regmap *regmap; 66 struct clk *coreclk; 67 struct clk *extalclk; 68 struct clk *fsysclk; 69 struct clk *spbaclk; 70 struct tasklet_struct task; 71 const struct fsl_esai_soc_data *soc; 72 spinlock_t lock; /* Protect hw_reset and trigger */ 73 u32 fifo_depth; 74 u32 slot_width; 75 u32 slots; 76 u32 tx_mask; 77 u32 rx_mask; 78 u32 channels[2]; 79 u32 hck_rate[2]; 80 u32 sck_rate[2]; 81 bool hck_dir[2]; 82 bool sck_div[2]; 83 bool slave_mode; 84 bool synchronous; 85 char name[32]; 86 }; 87 88 static struct fsl_esai_soc_data fsl_esai_vf610 = { 89 .imx = false, 90 .reset_at_xrun = true, 91 }; 92 93 static struct fsl_esai_soc_data fsl_esai_imx35 = { 94 .imx = true, 95 .reset_at_xrun = true, 96 }; 97 98 static struct fsl_esai_soc_data fsl_esai_imx6ull = { 99 .imx = true, 100 .reset_at_xrun = false, 101 }; 102 103 static irqreturn_t esai_isr(int irq, void *devid) 104 { 105 struct fsl_esai *esai_priv = (struct fsl_esai *)devid; 106 struct platform_device *pdev = esai_priv->pdev; 107 u32 esr; 108 u32 saisr; 109 110 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr); 111 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr); 112 113 if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) && 114 esai_priv->soc->reset_at_xrun) { 115 dev_dbg(&pdev->dev, "reset module for xrun\n"); 116 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 117 ESAI_xCR_xEIE_MASK, 0); 118 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 119 ESAI_xCR_xEIE_MASK, 0); 120 tasklet_schedule(&esai_priv->task); 121 } 122 123 if (esr & ESAI_ESR_TINIT_MASK) 124 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n"); 125 126 if (esr & ESAI_ESR_RFF_MASK) 127 dev_warn(&pdev->dev, "isr: Receiving overrun\n"); 128 129 if (esr & ESAI_ESR_TFE_MASK) 130 dev_warn(&pdev->dev, "isr: Transmission underrun\n"); 131 132 if (esr & ESAI_ESR_TLS_MASK) 133 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n"); 134 135 if (esr & ESAI_ESR_TDE_MASK) 136 dev_dbg(&pdev->dev, "isr: Transmission data exception\n"); 137 138 if (esr & ESAI_ESR_TED_MASK) 139 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n"); 140 141 if (esr & ESAI_ESR_TD_MASK) 142 dev_dbg(&pdev->dev, "isr: Transmitting data\n"); 143 144 if (esr & ESAI_ESR_RLS_MASK) 145 dev_dbg(&pdev->dev, "isr: Just received the last slot\n"); 146 147 if (esr & ESAI_ESR_RDE_MASK) 148 dev_dbg(&pdev->dev, "isr: Receiving data exception\n"); 149 150 if (esr & ESAI_ESR_RED_MASK) 151 dev_dbg(&pdev->dev, "isr: Receiving even slots\n"); 152 153 if (esr & ESAI_ESR_RD_MASK) 154 dev_dbg(&pdev->dev, "isr: Receiving data\n"); 155 156 return IRQ_HANDLED; 157 } 158 159 /** 160 * This function is used to calculate the divisors of psr, pm, fp and it is 161 * supposed to be called in set_dai_sysclk() and set_bclk(). 162 * 163 * @ratio: desired overall ratio for the paticipating dividers 164 * @usefp: for HCK setting, there is no need to set fp divider 165 * @fp: bypass other dividers by setting fp directly if fp != 0 166 * @tx: current setting is for playback or capture 167 */ 168 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 169 bool usefp, u32 fp) 170 { 171 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 172 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; 173 174 maxfp = usefp ? 16 : 1; 175 176 if (usefp && fp) 177 goto out_fp; 178 179 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) { 180 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n", 181 2 * 8 * 256 * maxfp); 182 return -EINVAL; 183 } else if (ratio % 2) { 184 dev_err(dai->dev, "the raio must be even if using upper divider\n"); 185 return -EINVAL; 186 } 187 188 ratio /= 2; 189 190 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; 191 192 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */ 193 if (ratio <= 256) { 194 pm = ratio; 195 fp = 1; 196 goto out; 197 } 198 199 /* Set the max fluctuation -- 0.1% of the max devisor */ 200 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; 201 202 /* Find the best value for PM */ 203 for (i = 1; i <= 256; i++) { 204 for (j = 1; j <= maxfp; j++) { 205 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */ 206 prod = (psr ? 1 : 8) * i * j; 207 208 if (prod == ratio) 209 sub = 0; 210 else if (prod / ratio == 1) 211 sub = prod - ratio; 212 else if (ratio / prod == 1) 213 sub = ratio - prod; 214 else 215 continue; 216 217 /* Calculate the fraction */ 218 sub = sub * 1000 / ratio; 219 if (sub < savesub) { 220 savesub = sub; 221 pm = i; 222 fp = j; 223 } 224 225 /* We are lucky */ 226 if (savesub == 0) 227 goto out; 228 } 229 } 230 231 if (pm == 999) { 232 dev_err(dai->dev, "failed to calculate proper divisors\n"); 233 return -EINVAL; 234 } 235 236 out: 237 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 238 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK, 239 psr | ESAI_xCCR_xPM(pm)); 240 241 out_fp: 242 /* Bypass fp if not being required */ 243 if (maxfp <= 1) 244 return 0; 245 246 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 247 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp)); 248 249 return 0; 250 } 251 252 /** 253 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR) 254 * 255 * @Parameters: 256 * clk_id: The clock source of HCKT/HCKR 257 * (Input from outside; output from inside, FSYS or EXTAL) 258 * freq: The required clock rate of HCKT/HCKR 259 * dir: The clock direction of HCKT/HCKR 260 * 261 * Note: If the direction is input, we do not care about clk_id. 262 */ 263 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 264 unsigned int freq, int dir) 265 { 266 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 267 struct clk *clksrc = esai_priv->extalclk; 268 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous); 269 bool in = dir == SND_SOC_CLOCK_IN; 270 u32 ratio, ecr = 0; 271 unsigned long clk_rate; 272 int ret; 273 274 if (freq == 0) { 275 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n", 276 in ? "in" : "out", tx ? 'T' : 'R'); 277 return -EINVAL; 278 } 279 280 /* Bypass divider settings if the requirement doesn't change */ 281 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx]) 282 return 0; 283 284 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ 285 esai_priv->sck_div[tx] = true; 286 287 /* Set the direction of HCKT/HCKR pins */ 288 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 289 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); 290 291 if (in) 292 goto out; 293 294 switch (clk_id) { 295 case ESAI_HCKT_FSYS: 296 case ESAI_HCKR_FSYS: 297 clksrc = esai_priv->fsysclk; 298 break; 299 case ESAI_HCKT_EXTAL: 300 ecr |= ESAI_ECR_ETI; 301 break; 302 case ESAI_HCKR_EXTAL: 303 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI; 304 break; 305 default: 306 return -EINVAL; 307 } 308 309 if (IS_ERR(clksrc)) { 310 dev_err(dai->dev, "no assigned %s clock\n", 311 clk_id % 2 ? "extal" : "fsys"); 312 return PTR_ERR(clksrc); 313 } 314 clk_rate = clk_get_rate(clksrc); 315 316 ratio = clk_rate / freq; 317 if (ratio * freq > clk_rate) 318 ret = ratio * freq - clk_rate; 319 else if (ratio * freq < clk_rate) 320 ret = clk_rate - ratio * freq; 321 else 322 ret = 0; 323 324 /* Block if clock source can not be divided into the required rate */ 325 if (ret != 0 && clk_rate / ret < 1000) { 326 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 327 tx ? 'T' : 'R'); 328 return -EINVAL; 329 } 330 331 /* Only EXTAL source can be output directly without using PSR and PM */ 332 if (ratio == 1 && clksrc == esai_priv->extalclk) { 333 /* Bypass all the dividers if not being needed */ 334 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; 335 goto out; 336 } else if (ratio < 2) { 337 /* The ratio should be no less than 2 if using other sources */ 338 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 339 tx ? 'T' : 'R'); 340 return -EINVAL; 341 } 342 343 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); 344 if (ret) 345 return ret; 346 347 esai_priv->sck_div[tx] = false; 348 349 out: 350 esai_priv->hck_dir[tx] = dir; 351 esai_priv->hck_rate[tx] = freq; 352 353 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 354 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : 355 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); 356 357 return 0; 358 } 359 360 /** 361 * This function configures the related dividers according to the bclk rate 362 */ 363 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 364 { 365 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 366 u32 hck_rate = esai_priv->hck_rate[tx]; 367 u32 sub, ratio = hck_rate / freq; 368 int ret; 369 370 /* Don't apply for fully slave mode or unchanged bclk */ 371 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq) 372 return 0; 373 374 if (ratio * freq > hck_rate) 375 sub = ratio * freq - hck_rate; 376 else if (ratio * freq < hck_rate) 377 sub = hck_rate - ratio * freq; 378 else 379 sub = 0; 380 381 /* Block if clock source can not be divided into the required rate */ 382 if (sub != 0 && hck_rate / sub < 1000) { 383 dev_err(dai->dev, "failed to derive required SCK%c rate\n", 384 tx ? 'T' : 'R'); 385 return -EINVAL; 386 } 387 388 /* The ratio should be contented by FP alone if bypassing PM and PSR */ 389 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) { 390 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n"); 391 return -EINVAL; 392 } 393 394 ret = fsl_esai_divisor_cal(dai, tx, ratio, true, 395 esai_priv->sck_div[tx] ? 0 : ratio); 396 if (ret) 397 return ret; 398 399 /* Save current bclk rate */ 400 esai_priv->sck_rate[tx] = freq; 401 402 return 0; 403 } 404 405 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 406 u32 rx_mask, int slots, int slot_width) 407 { 408 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 409 410 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 411 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 412 413 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 414 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 415 416 esai_priv->slot_width = slot_width; 417 esai_priv->slots = slots; 418 esai_priv->tx_mask = tx_mask; 419 esai_priv->rx_mask = rx_mask; 420 421 return 0; 422 } 423 424 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 425 { 426 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 427 u32 xcr = 0, xccr = 0, mask; 428 429 /* DAI mode */ 430 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 431 case SND_SOC_DAIFMT_I2S: 432 /* Data on rising edge of bclk, frame low, 1clk before data */ 433 xcr |= ESAI_xCR_xFSR; 434 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 435 break; 436 case SND_SOC_DAIFMT_LEFT_J: 437 /* Data on rising edge of bclk, frame high */ 438 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 439 break; 440 case SND_SOC_DAIFMT_RIGHT_J: 441 /* Data on rising edge of bclk, frame high, right aligned */ 442 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 443 xcr |= ESAI_xCR_xWA; 444 break; 445 case SND_SOC_DAIFMT_DSP_A: 446 /* Data on rising edge of bclk, frame high, 1clk before data */ 447 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR; 448 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 449 break; 450 case SND_SOC_DAIFMT_DSP_B: 451 /* Data on rising edge of bclk, frame high */ 452 xcr |= ESAI_xCR_xFSL; 453 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 454 break; 455 default: 456 return -EINVAL; 457 } 458 459 /* DAI clock inversion */ 460 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 461 case SND_SOC_DAIFMT_NB_NF: 462 /* Nothing to do for both normal cases */ 463 break; 464 case SND_SOC_DAIFMT_IB_NF: 465 /* Invert bit clock */ 466 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 467 break; 468 case SND_SOC_DAIFMT_NB_IF: 469 /* Invert frame clock */ 470 xccr ^= ESAI_xCCR_xFSP; 471 break; 472 case SND_SOC_DAIFMT_IB_IF: 473 /* Invert both clocks */ 474 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP; 475 break; 476 default: 477 return -EINVAL; 478 } 479 480 esai_priv->slave_mode = false; 481 482 /* DAI clock master masks */ 483 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 484 case SND_SOC_DAIFMT_CBM_CFM: 485 esai_priv->slave_mode = true; 486 break; 487 case SND_SOC_DAIFMT_CBS_CFM: 488 xccr |= ESAI_xCCR_xCKD; 489 break; 490 case SND_SOC_DAIFMT_CBM_CFS: 491 xccr |= ESAI_xCCR_xFSD; 492 break; 493 case SND_SOC_DAIFMT_CBS_CFS: 494 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA; 501 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); 502 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); 503 504 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | 505 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 506 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); 507 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); 508 509 return 0; 510 } 511 512 static int fsl_esai_startup(struct snd_pcm_substream *substream, 513 struct snd_soc_dai *dai) 514 { 515 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 516 517 if (!snd_soc_dai_active(dai)) { 518 /* Set synchronous mode */ 519 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, 520 ESAI_SAICR_SYNC, esai_priv->synchronous ? 521 ESAI_SAICR_SYNC : 0); 522 523 /* Set a default slot number -- 2 */ 524 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 525 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 526 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 527 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 528 } 529 530 return 0; 531 532 } 533 534 static int fsl_esai_hw_params(struct snd_pcm_substream *substream, 535 struct snd_pcm_hw_params *params, 536 struct snd_soc_dai *dai) 537 { 538 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 539 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 540 u32 width = params_width(params); 541 u32 channels = params_channels(params); 542 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 543 u32 slot_width = width; 544 u32 bclk, mask, val; 545 int ret; 546 547 /* Override slot_width if being specifically set */ 548 if (esai_priv->slot_width) 549 slot_width = esai_priv->slot_width; 550 551 bclk = params_rate(params) * slot_width * esai_priv->slots; 552 553 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk); 554 if (ret) 555 return ret; 556 557 mask = ESAI_xCR_xSWS_MASK; 558 val = ESAI_xCR_xSWS(slot_width, width); 559 560 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); 561 /* Recording in synchronous mode needs to set TCR also */ 562 if (!tx && esai_priv->synchronous) 563 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val); 564 565 /* Use Normal mode to support monaural audio */ 566 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 567 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ? 568 ESAI_xCR_xMOD_NETWORK : 0); 569 570 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 571 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR); 572 573 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | 574 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); 575 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | 576 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins)); 577 578 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); 579 580 if (tx) 581 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 582 ESAI_xCR_PADC, ESAI_xCR_PADC); 583 584 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */ 585 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 586 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 587 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 588 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 589 return 0; 590 } 591 592 static int fsl_esai_hw_init(struct fsl_esai *esai_priv) 593 { 594 struct platform_device *pdev = esai_priv->pdev; 595 int ret; 596 597 /* Reset ESAI unit */ 598 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 599 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 600 ESAI_ECR_ESAIEN | ESAI_ECR_ERST); 601 if (ret) { 602 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); 603 return ret; 604 } 605 606 /* 607 * We need to enable ESAI so as to access some of its registers. 608 * Otherwise, we would fail to dump regmap from user space. 609 */ 610 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 611 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 612 ESAI_ECR_ESAIEN); 613 if (ret) { 614 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); 615 return ret; 616 } 617 618 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 619 ESAI_PRRC_PDC_MASK, 0); 620 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 621 ESAI_PCRC_PC_MASK, 0); 622 623 return 0; 624 } 625 626 static int fsl_esai_register_restore(struct fsl_esai *esai_priv) 627 { 628 int ret; 629 630 /* FIFO reset for safety */ 631 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, 632 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 633 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, 634 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 635 636 regcache_mark_dirty(esai_priv->regmap); 637 ret = regcache_sync(esai_priv->regmap); 638 if (ret) 639 return ret; 640 641 /* FIFO reset done */ 642 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0); 643 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0); 644 645 return 0; 646 } 647 648 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx) 649 { 650 u8 i, channels = esai_priv->channels[tx]; 651 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 652 u32 mask; 653 654 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 655 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN); 656 657 /* Write initial words reqiured by ESAI as normal procedure */ 658 for (i = 0; tx && i < channels; i++) 659 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0); 660 661 /* 662 * When set the TE/RE in the end of enablement flow, there 663 * will be channel swap issue for multi data line case. 664 * In order to workaround this issue, we switch the bit 665 * enablement sequence to below sequence 666 * 1) clear the xSMB & xSMA: which is done in probe and 667 * stop state. 668 * 2) set TE/RE 669 * 3) set xSMB 670 * 4) set xSMA: xSMA is the last one in this flow, which 671 * will trigger esai to start. 672 */ 673 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 674 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 675 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins)); 676 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask; 677 678 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 679 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask)); 680 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 681 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask)); 682 683 /* Enable Exception interrupt */ 684 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 685 ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE); 686 } 687 688 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx) 689 { 690 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 691 ESAI_xCR_xEIE_MASK, 0); 692 693 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 694 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0); 695 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 696 ESAI_xSMA_xS_MASK, 0); 697 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 698 ESAI_xSMB_xS_MASK, 0); 699 700 /* Disable and reset FIFO */ 701 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 702 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR); 703 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 704 ESAI_xFCR_xFR, 0); 705 } 706 707 static void fsl_esai_hw_reset(unsigned long arg) 708 { 709 struct fsl_esai *esai_priv = (struct fsl_esai *)arg; 710 bool tx = true, rx = false, enabled[2]; 711 unsigned long lock_flags; 712 u32 tfcr, rfcr; 713 714 spin_lock_irqsave(&esai_priv->lock, lock_flags); 715 /* Save the registers */ 716 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr); 717 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr); 718 enabled[tx] = tfcr & ESAI_xFCR_xFEN; 719 enabled[rx] = rfcr & ESAI_xFCR_xFEN; 720 721 /* Stop the tx & rx */ 722 fsl_esai_trigger_stop(esai_priv, tx); 723 fsl_esai_trigger_stop(esai_priv, rx); 724 725 /* Reset the esai, and ignore return value */ 726 fsl_esai_hw_init(esai_priv); 727 728 /* Enforce ESAI personal resets for both TX and RX */ 729 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 730 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 731 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 732 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 733 734 /* Restore registers by regcache_sync, and ignore return value */ 735 fsl_esai_register_restore(esai_priv); 736 737 /* Remove ESAI personal resets by configuring PCRC and PRRC also */ 738 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 739 ESAI_xCR_xPR_MASK, 0); 740 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 741 ESAI_xCR_xPR_MASK, 0); 742 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 743 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 744 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 745 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 746 747 /* Restart tx / rx, if they already enabled */ 748 if (enabled[tx]) 749 fsl_esai_trigger_start(esai_priv, tx); 750 if (enabled[rx]) 751 fsl_esai_trigger_start(esai_priv, rx); 752 753 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 754 } 755 756 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, 757 struct snd_soc_dai *dai) 758 { 759 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 760 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 761 unsigned long lock_flags; 762 763 esai_priv->channels[tx] = substream->runtime->channels; 764 765 switch (cmd) { 766 case SNDRV_PCM_TRIGGER_START: 767 case SNDRV_PCM_TRIGGER_RESUME: 768 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 769 spin_lock_irqsave(&esai_priv->lock, lock_flags); 770 fsl_esai_trigger_start(esai_priv, tx); 771 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 772 break; 773 case SNDRV_PCM_TRIGGER_SUSPEND: 774 case SNDRV_PCM_TRIGGER_STOP: 775 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 776 spin_lock_irqsave(&esai_priv->lock, lock_flags); 777 fsl_esai_trigger_stop(esai_priv, tx); 778 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 779 break; 780 default: 781 return -EINVAL; 782 } 783 784 return 0; 785 } 786 787 static const struct snd_soc_dai_ops fsl_esai_dai_ops = { 788 .startup = fsl_esai_startup, 789 .trigger = fsl_esai_trigger, 790 .hw_params = fsl_esai_hw_params, 791 .set_sysclk = fsl_esai_set_dai_sysclk, 792 .set_fmt = fsl_esai_set_dai_fmt, 793 .set_tdm_slot = fsl_esai_set_dai_tdm_slot, 794 }; 795 796 static int fsl_esai_dai_probe(struct snd_soc_dai *dai) 797 { 798 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 799 800 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx, 801 &esai_priv->dma_params_rx); 802 803 return 0; 804 } 805 806 static struct snd_soc_dai_driver fsl_esai_dai = { 807 .probe = fsl_esai_dai_probe, 808 .playback = { 809 .stream_name = "CPU-Playback", 810 .channels_min = 1, 811 .channels_max = 12, 812 .rates = SNDRV_PCM_RATE_8000_192000, 813 .formats = FSL_ESAI_FORMATS, 814 }, 815 .capture = { 816 .stream_name = "CPU-Capture", 817 .channels_min = 1, 818 .channels_max = 8, 819 .rates = SNDRV_PCM_RATE_8000_192000, 820 .formats = FSL_ESAI_FORMATS, 821 }, 822 .ops = &fsl_esai_dai_ops, 823 }; 824 825 static const struct snd_soc_component_driver fsl_esai_component = { 826 .name = "fsl-esai", 827 }; 828 829 static const struct reg_default fsl_esai_reg_defaults[] = { 830 {REG_ESAI_ETDR, 0x00000000}, 831 {REG_ESAI_ECR, 0x00000000}, 832 {REG_ESAI_TFCR, 0x00000000}, 833 {REG_ESAI_RFCR, 0x00000000}, 834 {REG_ESAI_TX0, 0x00000000}, 835 {REG_ESAI_TX1, 0x00000000}, 836 {REG_ESAI_TX2, 0x00000000}, 837 {REG_ESAI_TX3, 0x00000000}, 838 {REG_ESAI_TX4, 0x00000000}, 839 {REG_ESAI_TX5, 0x00000000}, 840 {REG_ESAI_TSR, 0x00000000}, 841 {REG_ESAI_SAICR, 0x00000000}, 842 {REG_ESAI_TCR, 0x00000000}, 843 {REG_ESAI_TCCR, 0x00000000}, 844 {REG_ESAI_RCR, 0x00000000}, 845 {REG_ESAI_RCCR, 0x00000000}, 846 {REG_ESAI_TSMA, 0x0000ffff}, 847 {REG_ESAI_TSMB, 0x0000ffff}, 848 {REG_ESAI_RSMA, 0x0000ffff}, 849 {REG_ESAI_RSMB, 0x0000ffff}, 850 {REG_ESAI_PRRC, 0x00000000}, 851 {REG_ESAI_PCRC, 0x00000000}, 852 }; 853 854 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) 855 { 856 switch (reg) { 857 case REG_ESAI_ERDR: 858 case REG_ESAI_ECR: 859 case REG_ESAI_ESR: 860 case REG_ESAI_TFCR: 861 case REG_ESAI_TFSR: 862 case REG_ESAI_RFCR: 863 case REG_ESAI_RFSR: 864 case REG_ESAI_RX0: 865 case REG_ESAI_RX1: 866 case REG_ESAI_RX2: 867 case REG_ESAI_RX3: 868 case REG_ESAI_SAISR: 869 case REG_ESAI_SAICR: 870 case REG_ESAI_TCR: 871 case REG_ESAI_TCCR: 872 case REG_ESAI_RCR: 873 case REG_ESAI_RCCR: 874 case REG_ESAI_TSMA: 875 case REG_ESAI_TSMB: 876 case REG_ESAI_RSMA: 877 case REG_ESAI_RSMB: 878 case REG_ESAI_PRRC: 879 case REG_ESAI_PCRC: 880 return true; 881 default: 882 return false; 883 } 884 } 885 886 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg) 887 { 888 switch (reg) { 889 case REG_ESAI_ERDR: 890 case REG_ESAI_ESR: 891 case REG_ESAI_TFSR: 892 case REG_ESAI_RFSR: 893 case REG_ESAI_RX0: 894 case REG_ESAI_RX1: 895 case REG_ESAI_RX2: 896 case REG_ESAI_RX3: 897 case REG_ESAI_SAISR: 898 return true; 899 default: 900 return false; 901 } 902 } 903 904 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) 905 { 906 switch (reg) { 907 case REG_ESAI_ETDR: 908 case REG_ESAI_ECR: 909 case REG_ESAI_TFCR: 910 case REG_ESAI_RFCR: 911 case REG_ESAI_TX0: 912 case REG_ESAI_TX1: 913 case REG_ESAI_TX2: 914 case REG_ESAI_TX3: 915 case REG_ESAI_TX4: 916 case REG_ESAI_TX5: 917 case REG_ESAI_TSR: 918 case REG_ESAI_SAICR: 919 case REG_ESAI_TCR: 920 case REG_ESAI_TCCR: 921 case REG_ESAI_RCR: 922 case REG_ESAI_RCCR: 923 case REG_ESAI_TSMA: 924 case REG_ESAI_TSMB: 925 case REG_ESAI_RSMA: 926 case REG_ESAI_RSMB: 927 case REG_ESAI_PRRC: 928 case REG_ESAI_PCRC: 929 return true; 930 default: 931 return false; 932 } 933 } 934 935 static const struct regmap_config fsl_esai_regmap_config = { 936 .reg_bits = 32, 937 .reg_stride = 4, 938 .val_bits = 32, 939 940 .max_register = REG_ESAI_PCRC, 941 .reg_defaults = fsl_esai_reg_defaults, 942 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults), 943 .readable_reg = fsl_esai_readable_reg, 944 .volatile_reg = fsl_esai_volatile_reg, 945 .writeable_reg = fsl_esai_writeable_reg, 946 .cache_type = REGCACHE_FLAT, 947 }; 948 949 static int fsl_esai_probe(struct platform_device *pdev) 950 { 951 struct device_node *np = pdev->dev.of_node; 952 struct fsl_esai *esai_priv; 953 struct resource *res; 954 const __be32 *iprop; 955 void __iomem *regs; 956 int irq, ret; 957 958 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); 959 if (!esai_priv) 960 return -ENOMEM; 961 962 esai_priv->pdev = pdev; 963 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np); 964 965 esai_priv->soc = of_device_get_match_data(&pdev->dev); 966 if (!esai_priv->soc) { 967 dev_err(&pdev->dev, "failed to get soc data\n"); 968 return -ENODEV; 969 } 970 971 /* Get the addresses and IRQ */ 972 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 973 regs = devm_ioremap_resource(&pdev->dev, res); 974 if (IS_ERR(regs)) 975 return PTR_ERR(regs); 976 977 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 978 "core", regs, &fsl_esai_regmap_config); 979 if (IS_ERR(esai_priv->regmap)) { 980 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 981 PTR_ERR(esai_priv->regmap)); 982 return PTR_ERR(esai_priv->regmap); 983 } 984 985 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 986 if (IS_ERR(esai_priv->coreclk)) { 987 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 988 PTR_ERR(esai_priv->coreclk)); 989 return PTR_ERR(esai_priv->coreclk); 990 } 991 992 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); 993 if (IS_ERR(esai_priv->extalclk)) 994 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", 995 PTR_ERR(esai_priv->extalclk)); 996 997 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); 998 if (IS_ERR(esai_priv->fsysclk)) 999 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", 1000 PTR_ERR(esai_priv->fsysclk)); 1001 1002 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1003 if (IS_ERR(esai_priv->spbaclk)) 1004 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n", 1005 PTR_ERR(esai_priv->spbaclk)); 1006 1007 irq = platform_get_irq(pdev, 0); 1008 if (irq < 0) 1009 return irq; 1010 1011 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0, 1012 esai_priv->name, esai_priv); 1013 if (ret) { 1014 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 1015 return ret; 1016 } 1017 1018 /* Set a default slot number */ 1019 esai_priv->slots = 2; 1020 1021 /* Set a default master/slave state */ 1022 esai_priv->slave_mode = true; 1023 1024 /* Determine the FIFO depth */ 1025 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1026 if (iprop) 1027 esai_priv->fifo_depth = be32_to_cpup(iprop); 1028 else 1029 esai_priv->fifo_depth = 64; 1030 1031 esai_priv->dma_params_tx.maxburst = 16; 1032 esai_priv->dma_params_rx.maxburst = 16; 1033 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; 1034 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; 1035 1036 esai_priv->synchronous = 1037 of_property_read_bool(np, "fsl,esai-synchronous"); 1038 1039 /* Implement full symmetry for synchronous mode */ 1040 if (esai_priv->synchronous) { 1041 fsl_esai_dai.symmetric_rates = 1; 1042 fsl_esai_dai.symmetric_channels = 1; 1043 fsl_esai_dai.symmetric_samplebits = 1; 1044 } 1045 1046 dev_set_drvdata(&pdev->dev, esai_priv); 1047 1048 spin_lock_init(&esai_priv->lock); 1049 ret = fsl_esai_hw_init(esai_priv); 1050 if (ret) 1051 return ret; 1052 1053 esai_priv->tx_mask = 0xFFFFFFFF; 1054 esai_priv->rx_mask = 0xFFFFFFFF; 1055 1056 /* Clear the TSMA, TSMB, RSMA, RSMB */ 1057 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0); 1058 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0); 1059 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0); 1060 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0); 1061 1062 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, 1063 &fsl_esai_dai, 1); 1064 if (ret) { 1065 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1066 return ret; 1067 } 1068 1069 tasklet_init(&esai_priv->task, fsl_esai_hw_reset, 1070 (unsigned long)esai_priv); 1071 1072 pm_runtime_enable(&pdev->dev); 1073 1074 regcache_cache_only(esai_priv->regmap, true); 1075 1076 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE); 1077 if (ret) 1078 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); 1079 1080 return ret; 1081 } 1082 1083 static int fsl_esai_remove(struct platform_device *pdev) 1084 { 1085 struct fsl_esai *esai_priv = platform_get_drvdata(pdev); 1086 1087 pm_runtime_disable(&pdev->dev); 1088 tasklet_kill(&esai_priv->task); 1089 1090 return 0; 1091 } 1092 1093 static const struct of_device_id fsl_esai_dt_ids[] = { 1094 { .compatible = "fsl,imx35-esai", .data = &fsl_esai_imx35 }, 1095 { .compatible = "fsl,vf610-esai", .data = &fsl_esai_vf610 }, 1096 { .compatible = "fsl,imx6ull-esai", .data = &fsl_esai_imx6ull }, 1097 {} 1098 }; 1099 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids); 1100 1101 #ifdef CONFIG_PM 1102 static int fsl_esai_runtime_resume(struct device *dev) 1103 { 1104 struct fsl_esai *esai = dev_get_drvdata(dev); 1105 int ret; 1106 1107 /* 1108 * Some platforms might use the same bit to gate all three or two of 1109 * clocks, so keep all clocks open/close at the same time for safety 1110 */ 1111 ret = clk_prepare_enable(esai->coreclk); 1112 if (ret) 1113 return ret; 1114 if (!IS_ERR(esai->spbaclk)) { 1115 ret = clk_prepare_enable(esai->spbaclk); 1116 if (ret) 1117 goto err_spbaclk; 1118 } 1119 if (!IS_ERR(esai->extalclk)) { 1120 ret = clk_prepare_enable(esai->extalclk); 1121 if (ret) 1122 goto err_extalclk; 1123 } 1124 if (!IS_ERR(esai->fsysclk)) { 1125 ret = clk_prepare_enable(esai->fsysclk); 1126 if (ret) 1127 goto err_fsysclk; 1128 } 1129 1130 regcache_cache_only(esai->regmap, false); 1131 1132 ret = fsl_esai_register_restore(esai); 1133 if (ret) 1134 goto err_regcache_sync; 1135 1136 return 0; 1137 1138 err_regcache_sync: 1139 if (!IS_ERR(esai->fsysclk)) 1140 clk_disable_unprepare(esai->fsysclk); 1141 err_fsysclk: 1142 if (!IS_ERR(esai->extalclk)) 1143 clk_disable_unprepare(esai->extalclk); 1144 err_extalclk: 1145 if (!IS_ERR(esai->spbaclk)) 1146 clk_disable_unprepare(esai->spbaclk); 1147 err_spbaclk: 1148 clk_disable_unprepare(esai->coreclk); 1149 1150 return ret; 1151 } 1152 1153 static int fsl_esai_runtime_suspend(struct device *dev) 1154 { 1155 struct fsl_esai *esai = dev_get_drvdata(dev); 1156 1157 regcache_cache_only(esai->regmap, true); 1158 1159 if (!IS_ERR(esai->fsysclk)) 1160 clk_disable_unprepare(esai->fsysclk); 1161 if (!IS_ERR(esai->extalclk)) 1162 clk_disable_unprepare(esai->extalclk); 1163 if (!IS_ERR(esai->spbaclk)) 1164 clk_disable_unprepare(esai->spbaclk); 1165 clk_disable_unprepare(esai->coreclk); 1166 1167 return 0; 1168 } 1169 #endif /* CONFIG_PM */ 1170 1171 static const struct dev_pm_ops fsl_esai_pm_ops = { 1172 SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend, 1173 fsl_esai_runtime_resume, 1174 NULL) 1175 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1176 pm_runtime_force_resume) 1177 }; 1178 1179 static struct platform_driver fsl_esai_driver = { 1180 .probe = fsl_esai_probe, 1181 .remove = fsl_esai_remove, 1182 .driver = { 1183 .name = "fsl-esai-dai", 1184 .pm = &fsl_esai_pm_ops, 1185 .of_match_table = fsl_esai_dt_ids, 1186 }, 1187 }; 1188 1189 module_platform_driver(fsl_esai_driver); 1190 1191 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1192 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver"); 1193 MODULE_LICENSE("GPL v2"); 1194 MODULE_ALIAS("platform:fsl-esai-dai"); 1195