1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * This driver implements ASoC support for the Elo DMA controller, which is 13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 14 * the PCM driver is what handles the DMA buffer. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/gfp.h> 24 #include <linux/of_platform.h> 25 #include <linux/list.h> 26 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 32 #include <asm/io.h> 33 34 #include "fsl_dma.h" 35 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 36 37 /* 38 * The formats that the DMA controller supports, which is anything 39 * that is 8, 16, or 32 bits. 40 */ 41 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 42 SNDRV_PCM_FMTBIT_U8 | \ 43 SNDRV_PCM_FMTBIT_S16_LE | \ 44 SNDRV_PCM_FMTBIT_S16_BE | \ 45 SNDRV_PCM_FMTBIT_U16_LE | \ 46 SNDRV_PCM_FMTBIT_U16_BE | \ 47 SNDRV_PCM_FMTBIT_S24_LE | \ 48 SNDRV_PCM_FMTBIT_S24_BE | \ 49 SNDRV_PCM_FMTBIT_U24_LE | \ 50 SNDRV_PCM_FMTBIT_U24_BE | \ 51 SNDRV_PCM_FMTBIT_S32_LE | \ 52 SNDRV_PCM_FMTBIT_S32_BE | \ 53 SNDRV_PCM_FMTBIT_U32_LE | \ 54 SNDRV_PCM_FMTBIT_U32_BE) 55 56 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 57 SNDRV_PCM_RATE_CONTINUOUS) 58 59 struct dma_object { 60 struct list_head list; 61 struct snd_soc_platform_driver dai; 62 dma_addr_t ssi_stx_phys; 63 dma_addr_t ssi_srx_phys; 64 struct ccsr_dma_channel __iomem *channel; 65 unsigned int irq; 66 bool assigned; 67 char path[1]; 68 }; 69 70 /* 71 * The number of DMA links to use. Two is the bare minimum, but if you 72 * have really small links you might need more. 73 */ 74 #define NUM_DMA_LINKS 2 75 76 /** fsl_dma_private: p-substream DMA data 77 * 78 * Each substream has a 1-to-1 association with a DMA channel. 79 * 80 * The link[] array is first because it needs to be aligned on a 32-byte 81 * boundary, so putting it first will ensure alignment without padding the 82 * structure. 83 * 84 * @link[]: array of link descriptors 85 * @dma_channel: pointer to the DMA channel's registers 86 * @irq: IRQ for this DMA channel 87 * @substream: pointer to the substream object, needed by the ISR 88 * @ssi_sxx_phys: bus address of the STX or SRX register to use 89 * @ld_buf_phys: physical address of the LD buffer 90 * @current_link: index into link[] of the link currently being processed 91 * @dma_buf_phys: physical address of the DMA buffer 92 * @dma_buf_next: physical address of the next period to process 93 * @dma_buf_end: physical address of the byte after the end of the DMA 94 * @buffer period_size: the size of a single period 95 * @num_periods: the number of periods in the DMA buffer 96 */ 97 struct fsl_dma_private { 98 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 99 struct ccsr_dma_channel __iomem *dma_channel; 100 unsigned int irq; 101 struct snd_pcm_substream *substream; 102 dma_addr_t ssi_sxx_phys; 103 dma_addr_t ld_buf_phys; 104 unsigned int current_link; 105 dma_addr_t dma_buf_phys; 106 dma_addr_t dma_buf_next; 107 dma_addr_t dma_buf_end; 108 size_t period_size; 109 unsigned int num_periods; 110 }; 111 112 /** 113 * fsl_dma_hardare: define characteristics of the PCM hardware. 114 * 115 * The PCM hardware is the Freescale DMA controller. This structure defines 116 * the capabilities of that hardware. 117 * 118 * Since the sampling rate and data format are not controlled by the DMA 119 * controller, we specify no limits for those values. The only exception is 120 * period_bytes_min, which is set to a reasonably low value to prevent the 121 * DMA controller from generating too many interrupts per second. 122 * 123 * Since each link descriptor has a 32-bit byte count field, we set 124 * period_bytes_max to the largest 32-bit number. We also have no maximum 125 * number of periods. 126 * 127 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 128 * limitation in the SSI driver requires the sample rates for playback and 129 * capture to be the same. 130 */ 131 static const struct snd_pcm_hardware fsl_dma_hardware = { 132 133 .info = SNDRV_PCM_INFO_INTERLEAVED | 134 SNDRV_PCM_INFO_MMAP | 135 SNDRV_PCM_INFO_MMAP_VALID | 136 SNDRV_PCM_INFO_JOINT_DUPLEX | 137 SNDRV_PCM_INFO_PAUSE, 138 .formats = FSLDMA_PCM_FORMATS, 139 .rates = FSLDMA_PCM_RATES, 140 .rate_min = 5512, 141 .rate_max = 192000, 142 .period_bytes_min = 512, /* A reasonable limit */ 143 .period_bytes_max = (u32) -1, 144 .periods_min = NUM_DMA_LINKS, 145 .periods_max = (unsigned int) -1, 146 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 147 }; 148 149 /** 150 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 151 * 152 * This function should be called by the ISR whenever the DMA controller 153 * halts data transfer. 154 */ 155 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 156 { 157 unsigned long flags; 158 159 snd_pcm_stream_lock_irqsave(substream, flags); 160 161 if (snd_pcm_running(substream)) 162 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 163 164 snd_pcm_stream_unlock_irqrestore(substream, flags); 165 } 166 167 /** 168 * fsl_dma_update_pointers - update LD pointers to point to the next period 169 * 170 * As each period is completed, this function changes the the link 171 * descriptor pointers for that period to point to the next period. 172 */ 173 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 174 { 175 struct fsl_dma_link_descriptor *link = 176 &dma_private->link[dma_private->current_link]; 177 178 /* Update our link descriptors to point to the next period */ 179 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 180 link->source_addr = 181 cpu_to_be32(dma_private->dma_buf_next); 182 else 183 link->dest_addr = 184 cpu_to_be32(dma_private->dma_buf_next); 185 186 /* Update our variables for next time */ 187 dma_private->dma_buf_next += dma_private->period_size; 188 189 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 190 dma_private->dma_buf_next = dma_private->dma_buf_phys; 191 192 if (++dma_private->current_link >= NUM_DMA_LINKS) 193 dma_private->current_link = 0; 194 } 195 196 /** 197 * fsl_dma_isr: interrupt handler for the DMA controller 198 * 199 * @irq: IRQ of the DMA channel 200 * @dev_id: pointer to the dma_private structure for this DMA channel 201 */ 202 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 203 { 204 struct fsl_dma_private *dma_private = dev_id; 205 struct snd_pcm_substream *substream = dma_private->substream; 206 struct snd_soc_pcm_runtime *rtd = substream->private_data; 207 struct device *dev = rtd->platform->dev; 208 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 209 irqreturn_t ret = IRQ_NONE; 210 u32 sr, sr2 = 0; 211 212 /* We got an interrupt, so read the status register to see what we 213 were interrupted for. 214 */ 215 sr = in_be32(&dma_channel->sr); 216 217 if (sr & CCSR_DMA_SR_TE) { 218 dev_err(dev, "dma transmit error\n"); 219 fsl_dma_abort_stream(substream); 220 sr2 |= CCSR_DMA_SR_TE; 221 ret = IRQ_HANDLED; 222 } 223 224 if (sr & CCSR_DMA_SR_CH) 225 ret = IRQ_HANDLED; 226 227 if (sr & CCSR_DMA_SR_PE) { 228 dev_err(dev, "dma programming error\n"); 229 fsl_dma_abort_stream(substream); 230 sr2 |= CCSR_DMA_SR_PE; 231 ret = IRQ_HANDLED; 232 } 233 234 if (sr & CCSR_DMA_SR_EOLNI) { 235 sr2 |= CCSR_DMA_SR_EOLNI; 236 ret = IRQ_HANDLED; 237 } 238 239 if (sr & CCSR_DMA_SR_CB) 240 ret = IRQ_HANDLED; 241 242 if (sr & CCSR_DMA_SR_EOSI) { 243 /* Tell ALSA we completed a period. */ 244 snd_pcm_period_elapsed(substream); 245 246 /* 247 * Update our link descriptors to point to the next period. We 248 * only need to do this if the number of periods is not equal to 249 * the number of links. 250 */ 251 if (dma_private->num_periods != NUM_DMA_LINKS) 252 fsl_dma_update_pointers(dma_private); 253 254 sr2 |= CCSR_DMA_SR_EOSI; 255 ret = IRQ_HANDLED; 256 } 257 258 if (sr & CCSR_DMA_SR_EOLSI) { 259 sr2 |= CCSR_DMA_SR_EOLSI; 260 ret = IRQ_HANDLED; 261 } 262 263 /* Clear the bits that we set */ 264 if (sr2) 265 out_be32(&dma_channel->sr, sr2); 266 267 return ret; 268 } 269 270 /** 271 * fsl_dma_new: initialize this PCM driver. 272 * 273 * This function is called when the codec driver calls snd_soc_new_pcms(), 274 * once for each .dai_link in the machine driver's snd_soc_card 275 * structure. 276 */ 277 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, 278 struct snd_pcm *pcm) 279 { 280 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32); 281 int ret; 282 283 if (!card->dev->dma_mask) 284 card->dev->dma_mask = &fsl_dma_dmamask; 285 286 if (!card->dev->coherent_dma_mask) 287 card->dev->coherent_dma_mask = fsl_dma_dmamask; 288 289 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 290 fsl_dma_hardware.buffer_bytes_max, 291 &pcm->streams[0].substream->dma_buffer); 292 if (ret) { 293 dev_err(card->dev, "can't allocate playback dma buffer\n"); 294 return ret; 295 } 296 297 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 298 fsl_dma_hardware.buffer_bytes_max, 299 &pcm->streams[1].substream->dma_buffer); 300 if (ret) { 301 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 302 dev_err(card->dev, "can't allocate capture dma buffer\n"); 303 return ret; 304 } 305 306 return 0; 307 } 308 309 /** 310 * fsl_dma_open: open a new substream. 311 * 312 * Each substream has its own DMA buffer. 313 * 314 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 315 * descriptors that ping-pong from one period to the next. For example, if 316 * there are six periods and two link descriptors, this is how they look 317 * before playback starts: 318 * 319 * The last link descriptor 320 * ____________ points back to the first 321 * | | 322 * V | 323 * ___ ___ | 324 * | |->| |->| 325 * |___| |___| 326 * | | 327 * | | 328 * V V 329 * _________________________________________ 330 * | | | | | | | The DMA buffer is 331 * | | | | | | | divided into 6 parts 332 * |______|______|______|______|______|______| 333 * 334 * and here's how they look after the first period is finished playing: 335 * 336 * ____________ 337 * | | 338 * V | 339 * ___ ___ | 340 * | |->| |->| 341 * |___| |___| 342 * | | 343 * |______________ 344 * | | 345 * V V 346 * _________________________________________ 347 * | | | | | | | 348 * | | | | | | | 349 * |______|______|______|______|______|______| 350 * 351 * The first link descriptor now points to the third period. The DMA 352 * controller is currently playing the second period. When it finishes, it 353 * will jump back to the first descriptor and play the third period. 354 * 355 * There are four reasons we do this: 356 * 357 * 1. The only way to get the DMA controller to automatically restart the 358 * transfer when it gets to the end of the buffer is to use chaining 359 * mode. Basic direct mode doesn't offer that feature. 360 * 2. We need to receive an interrupt at the end of every period. The DMA 361 * controller can generate an interrupt at the end of every link transfer 362 * (aka segment). Making each period into a DMA segment will give us the 363 * interrupts we need. 364 * 3. By creating only two link descriptors, regardless of the number of 365 * periods, we do not need to reallocate the link descriptors if the 366 * number of periods changes. 367 * 4. All of the audio data is still stored in a single, contiguous DMA 368 * buffer, which is what ALSA expects. We're just dividing it into 369 * contiguous parts, and creating a link descriptor for each one. 370 */ 371 static int fsl_dma_open(struct snd_pcm_substream *substream) 372 { 373 struct snd_pcm_runtime *runtime = substream->runtime; 374 struct snd_soc_pcm_runtime *rtd = substream->private_data; 375 struct device *dev = rtd->platform->dev; 376 struct dma_object *dma = 377 container_of(rtd->platform->driver, struct dma_object, dai); 378 struct fsl_dma_private *dma_private; 379 struct ccsr_dma_channel __iomem *dma_channel; 380 dma_addr_t ld_buf_phys; 381 u64 temp_link; /* Pointer to next link descriptor */ 382 u32 mr; 383 unsigned int channel; 384 int ret = 0; 385 unsigned int i; 386 387 /* 388 * Reject any DMA buffer whose size is not a multiple of the period 389 * size. We need to make sure that the DMA buffer can be evenly divided 390 * into periods. 391 */ 392 ret = snd_pcm_hw_constraint_integer(runtime, 393 SNDRV_PCM_HW_PARAM_PERIODS); 394 if (ret < 0) { 395 dev_err(dev, "invalid buffer size\n"); 396 return ret; 397 } 398 399 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 400 401 if (dma->assigned) { 402 dev_err(dev, "dma channel already assigned\n"); 403 return -EBUSY; 404 } 405 406 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 407 &ld_buf_phys, GFP_KERNEL); 408 if (!dma_private) { 409 dev_err(dev, "can't allocate dma private data\n"); 410 return -ENOMEM; 411 } 412 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 413 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 414 else 415 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 416 417 dma_private->dma_channel = dma->channel; 418 dma_private->irq = dma->irq; 419 dma_private->substream = substream; 420 dma_private->ld_buf_phys = ld_buf_phys; 421 dma_private->dma_buf_phys = substream->dma_buffer.addr; 422 423 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 424 if (ret) { 425 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 426 dma_private->irq, ret); 427 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 428 dma_private, dma_private->ld_buf_phys); 429 return ret; 430 } 431 432 dma->assigned = 1; 433 434 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 435 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 436 runtime->private_data = dma_private; 437 438 /* Program the fixed DMA controller parameters */ 439 440 dma_channel = dma_private->dma_channel; 441 442 temp_link = dma_private->ld_buf_phys + 443 sizeof(struct fsl_dma_link_descriptor); 444 445 for (i = 0; i < NUM_DMA_LINKS; i++) { 446 dma_private->link[i].next = cpu_to_be64(temp_link); 447 448 temp_link += sizeof(struct fsl_dma_link_descriptor); 449 } 450 /* The last link descriptor points to the first */ 451 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 452 453 /* Tell the DMA controller where the first link descriptor is */ 454 out_be32(&dma_channel->clndar, 455 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 456 out_be32(&dma_channel->eclndar, 457 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 458 459 /* The manual says the BCR must be clear before enabling EMP */ 460 out_be32(&dma_channel->bcr, 0); 461 462 /* 463 * Program the mode register for interrupts, external master control, 464 * and source/destination hold. Also clear the Channel Abort bit. 465 */ 466 mr = in_be32(&dma_channel->mr) & 467 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 468 469 /* 470 * We want External Master Start and External Master Pause enabled, 471 * because the SSI is controlling the DMA controller. We want the DMA 472 * controller to be set up in advance, and then we signal only the SSI 473 * to start transferring. 474 * 475 * We want End-Of-Segment Interrupts enabled, because this will generate 476 * an interrupt at the end of each segment (each link descriptor 477 * represents one segment). Each DMA segment is the same thing as an 478 * ALSA period, so this is how we get an interrupt at the end of every 479 * period. 480 * 481 * We want Error Interrupt enabled, so that we can get an error if 482 * the DMA controller is mis-programmed somehow. 483 */ 484 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 485 CCSR_DMA_MR_EMS_EN; 486 487 /* For playback, we want the destination address to be held. For 488 capture, set the source address to be held. */ 489 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 490 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 491 492 out_be32(&dma_channel->mr, mr); 493 494 return 0; 495 } 496 497 /** 498 * fsl_dma_hw_params: continue initializing the DMA links 499 * 500 * This function obtains hardware parameters about the opened stream and 501 * programs the DMA controller accordingly. 502 * 503 * One drawback of big-endian is that when copying integers of different 504 * sizes to a fixed-sized register, the address to which the integer must be 505 * copied is dependent on the size of the integer. 506 * 507 * For example, if P is the address of a 32-bit register, and X is a 32-bit 508 * integer, then X should be copied to address P. However, if X is a 16-bit 509 * integer, then it should be copied to P+2. If X is an 8-bit register, 510 * then it should be copied to P+3. 511 * 512 * So for playback of 8-bit samples, the DMA controller must transfer single 513 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 514 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 515 * 516 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 517 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 518 * and 8 bytes at a time). So we do not support packed 24-bit samples. 519 * 24-bit data must be padded to 32 bits. 520 */ 521 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 522 struct snd_pcm_hw_params *hw_params) 523 { 524 struct snd_pcm_runtime *runtime = substream->runtime; 525 struct fsl_dma_private *dma_private = runtime->private_data; 526 struct snd_soc_pcm_runtime *rtd = substream->private_data; 527 struct device *dev = rtd->platform->dev; 528 529 /* Number of bits per sample */ 530 unsigned int sample_size = 531 snd_pcm_format_physical_width(params_format(hw_params)); 532 533 /* Number of bytes per frame */ 534 unsigned int frame_size = 2 * (sample_size / 8); 535 536 /* Bus address of SSI STX register */ 537 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 538 539 /* Size of the DMA buffer, in bytes */ 540 size_t buffer_size = params_buffer_bytes(hw_params); 541 542 /* Number of bytes per period */ 543 size_t period_size = params_period_bytes(hw_params); 544 545 /* Pointer to next period */ 546 dma_addr_t temp_addr = substream->dma_buffer.addr; 547 548 /* Pointer to DMA controller */ 549 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 550 551 u32 mr; /* DMA Mode Register */ 552 553 unsigned int i; 554 555 /* Initialize our DMA tracking variables */ 556 dma_private->period_size = period_size; 557 dma_private->num_periods = params_periods(hw_params); 558 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 559 dma_private->dma_buf_next = dma_private->dma_buf_phys + 560 (NUM_DMA_LINKS * period_size); 561 562 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 563 /* This happens if the number of periods == NUM_DMA_LINKS */ 564 dma_private->dma_buf_next = dma_private->dma_buf_phys; 565 566 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 567 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 568 569 /* Due to a quirk of the SSI's STX register, the target address 570 * for the DMA operations depends on the sample size. So we calculate 571 * that offset here. While we're at it, also tell the DMA controller 572 * how much data to transfer per sample. 573 */ 574 switch (sample_size) { 575 case 8: 576 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 577 ssi_sxx_phys += 3; 578 break; 579 case 16: 580 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 581 ssi_sxx_phys += 2; 582 break; 583 case 32: 584 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 585 break; 586 default: 587 /* We should never get here */ 588 dev_err(dev, "unsupported sample size %u\n", sample_size); 589 return -EINVAL; 590 } 591 592 /* 593 * BWC should always be a multiple of the frame size. BWC determines 594 * how many bytes are sent/received before the DMA controller checks the 595 * SSI to see if it needs to stop. For playback, the transmit FIFO can 596 * hold three frames, so we want to send two frames at a time. For 597 * capture, the receive FIFO is triggered when it contains one frame, so 598 * we want to receive one frame at a time. 599 */ 600 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 601 mr |= CCSR_DMA_MR_BWC(2 * frame_size); 602 else 603 mr |= CCSR_DMA_MR_BWC(frame_size); 604 605 out_be32(&dma_channel->mr, mr); 606 607 for (i = 0; i < NUM_DMA_LINKS; i++) { 608 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 609 610 link->count = cpu_to_be32(period_size); 611 612 /* Even though the DMA controller supports 36-bit addressing, 613 * for simplicity we allow only 32-bit addresses for the audio 614 * buffer itself. This was enforced in fsl_dma_new() with the 615 * DMA mask. 616 * 617 * The snoop bit tells the DMA controller whether it should tell 618 * the ECM to snoop during a read or write to an address. For 619 * audio, we use DMA to transfer data between memory and an I/O 620 * device (the SSI's STX0 or SRX0 register). Snooping is only 621 * needed if there is a cache, so we need to snoop memory 622 * addresses only. For playback, that means we snoop the source 623 * but not the destination. For capture, we snoop the 624 * destination but not the source. 625 * 626 * Note that failing to snoop properly is unlikely to cause 627 * cache incoherency if the period size is larger than the 628 * size of L1 cache. This is because filling in one period will 629 * flush out the data for the previous period. So if you 630 * increased period_bytes_min to a large enough size, you might 631 * get more performance by not snooping, and you'll still be 632 * okay. 633 */ 634 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 635 link->source_addr = cpu_to_be32(temp_addr); 636 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 637 638 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 639 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); 640 } else { 641 link->source_addr = cpu_to_be32(ssi_sxx_phys); 642 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP); 643 644 link->dest_addr = cpu_to_be32(temp_addr); 645 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 646 } 647 648 temp_addr += period_size; 649 } 650 651 return 0; 652 } 653 654 /** 655 * fsl_dma_pointer: determine the current position of the DMA transfer 656 * 657 * This function is called by ALSA when ALSA wants to know where in the 658 * stream buffer the hardware currently is. 659 * 660 * For playback, the SAR register contains the physical address of the most 661 * recent DMA transfer. For capture, the value is in the DAR register. 662 * 663 * The base address of the buffer is stored in the source_addr field of the 664 * first link descriptor. 665 */ 666 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 667 { 668 struct snd_pcm_runtime *runtime = substream->runtime; 669 struct fsl_dma_private *dma_private = runtime->private_data; 670 struct snd_soc_pcm_runtime *rtd = substream->private_data; 671 struct device *dev = rtd->platform->dev; 672 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 673 dma_addr_t position; 674 snd_pcm_uframes_t frames; 675 676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 677 position = in_be32(&dma_channel->sar); 678 else 679 position = in_be32(&dma_channel->dar); 680 681 /* 682 * When capture is started, the SSI immediately starts to fill its FIFO. 683 * This means that the DMA controller is not started until the FIFO is 684 * full. However, ALSA calls this function before that happens, when 685 * MR.DAR is still zero. In this case, just return zero to indicate 686 * that nothing has been received yet. 687 */ 688 if (!position) 689 return 0; 690 691 if ((position < dma_private->dma_buf_phys) || 692 (position > dma_private->dma_buf_end)) { 693 dev_err(dev, "dma pointer is out of range, halting stream\n"); 694 return SNDRV_PCM_POS_XRUN; 695 } 696 697 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 698 699 /* 700 * If the current address is just past the end of the buffer, wrap it 701 * around. 702 */ 703 if (frames == runtime->buffer_size) 704 frames = 0; 705 706 return frames; 707 } 708 709 /** 710 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 711 * 712 * Release the resources allocated in fsl_dma_hw_params() and de-program the 713 * registers. 714 * 715 * This function can be called multiple times. 716 */ 717 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 718 { 719 struct snd_pcm_runtime *runtime = substream->runtime; 720 struct fsl_dma_private *dma_private = runtime->private_data; 721 722 if (dma_private) { 723 struct ccsr_dma_channel __iomem *dma_channel; 724 725 dma_channel = dma_private->dma_channel; 726 727 /* Stop the DMA */ 728 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 729 out_be32(&dma_channel->mr, 0); 730 731 /* Reset all the other registers */ 732 out_be32(&dma_channel->sr, -1); 733 out_be32(&dma_channel->clndar, 0); 734 out_be32(&dma_channel->eclndar, 0); 735 out_be32(&dma_channel->satr, 0); 736 out_be32(&dma_channel->sar, 0); 737 out_be32(&dma_channel->datr, 0); 738 out_be32(&dma_channel->dar, 0); 739 out_be32(&dma_channel->bcr, 0); 740 out_be32(&dma_channel->nlndar, 0); 741 out_be32(&dma_channel->enlndar, 0); 742 } 743 744 return 0; 745 } 746 747 /** 748 * fsl_dma_close: close the stream. 749 */ 750 static int fsl_dma_close(struct snd_pcm_substream *substream) 751 { 752 struct snd_pcm_runtime *runtime = substream->runtime; 753 struct fsl_dma_private *dma_private = runtime->private_data; 754 struct snd_soc_pcm_runtime *rtd = substream->private_data; 755 struct device *dev = rtd->platform->dev; 756 struct dma_object *dma = 757 container_of(rtd->platform->driver, struct dma_object, dai); 758 759 if (dma_private) { 760 if (dma_private->irq) 761 free_irq(dma_private->irq, dma_private); 762 763 if (dma_private->ld_buf_phys) { 764 dma_unmap_single(dev, dma_private->ld_buf_phys, 765 sizeof(dma_private->link), 766 DMA_TO_DEVICE); 767 } 768 769 /* Deallocate the fsl_dma_private structure */ 770 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 771 dma_private, dma_private->ld_buf_phys); 772 substream->runtime->private_data = NULL; 773 } 774 775 dma->assigned = 0; 776 777 return 0; 778 } 779 780 /* 781 * Remove this PCM driver. 782 */ 783 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 784 { 785 struct snd_pcm_substream *substream; 786 unsigned int i; 787 788 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 789 substream = pcm->streams[i].substream; 790 if (substream) { 791 snd_dma_free_pages(&substream->dma_buffer); 792 substream->dma_buffer.area = NULL; 793 substream->dma_buffer.addr = 0; 794 } 795 } 796 } 797 798 /* List of DMA nodes that we've probed */ 799 static LIST_HEAD(dma_list); 800 801 /** 802 * find_ssi_node -- returns the SSI node that points to his DMA channel node 803 * 804 * Although this DMA driver attempts to operate independently of the other 805 * devices, it still needs to determine some information about the SSI device 806 * that it's working with. Unfortunately, the device tree does not contain 807 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 808 * other way. So we need to scan the device tree for SSI nodes until we find 809 * the one that points to the given DMA channel node. It's ugly, but at least 810 * it's contained in this one function. 811 */ 812 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 813 { 814 struct device_node *ssi_np, *np; 815 816 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 817 /* Check each DMA phandle to see if it points to us. We 818 * assume that device_node pointers are a valid comparison. 819 */ 820 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 821 if (np == dma_channel_np) 822 return ssi_np; 823 824 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 825 if (np == dma_channel_np) 826 return ssi_np; 827 } 828 829 return NULL; 830 } 831 832 static struct snd_pcm_ops fsl_dma_ops = { 833 .open = fsl_dma_open, 834 .close = fsl_dma_close, 835 .ioctl = snd_pcm_lib_ioctl, 836 .hw_params = fsl_dma_hw_params, 837 .hw_free = fsl_dma_hw_free, 838 .pointer = fsl_dma_pointer, 839 }; 840 841 static int __devinit fsl_soc_dma_probe(struct of_device *of_dev, 842 const struct of_device_id *match) 843 { 844 struct dma_object *dma; 845 struct device_node *np = of_dev->dev.of_node; 846 struct device_node *ssi_np; 847 struct resource res; 848 int ret; 849 850 /* Find the SSI node that points to us. */ 851 ssi_np = find_ssi_node(np); 852 if (!ssi_np) { 853 dev_err(&of_dev->dev, "cannot find parent SSI node\n"); 854 return -ENODEV; 855 } 856 857 ret = of_address_to_resource(ssi_np, 0, &res); 858 of_node_put(ssi_np); 859 if (ret) { 860 dev_err(&of_dev->dev, "could not determine device resources\n"); 861 return ret; 862 } 863 864 dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL); 865 if (!dma) { 866 dev_err(&of_dev->dev, "could not allocate dma object\n"); 867 return -ENOMEM; 868 } 869 870 strcpy(dma->path, np->full_name); 871 dma->dai.ops = &fsl_dma_ops; 872 dma->dai.pcm_new = fsl_dma_new; 873 dma->dai.pcm_free = fsl_dma_free_dma_buffers; 874 875 /* Store the SSI-specific information that we need */ 876 dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0); 877 dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0); 878 879 ret = snd_soc_register_platform(&of_dev->dev, &dma->dai); 880 if (ret) { 881 dev_err(&of_dev->dev, "could not register platform\n"); 882 kfree(dma); 883 return ret; 884 } 885 886 dma->channel = of_iomap(np, 0); 887 dma->irq = irq_of_parse_and_map(np, 0); 888 list_add(&dma->list, &dma_list); 889 890 return 0; 891 } 892 893 static int __devexit fsl_soc_dma_remove(struct of_device *of_dev) 894 { 895 struct list_head *n, *ptr; 896 struct dma_object *dma; 897 898 list_for_each_safe(ptr, n, &dma_list) { 899 dma = list_entry(ptr, struct dma_object, list); 900 list_del_init(ptr); 901 902 snd_soc_unregister_platform(&of_dev->dev); 903 iounmap(dma->channel); 904 irq_dispose_mapping(dma->irq); 905 kfree(dma); 906 } 907 908 return 0; 909 } 910 911 static const struct of_device_id fsl_soc_dma_ids[] = { 912 { .compatible = "fsl,ssi-dma-channel", }, 913 {} 914 }; 915 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 916 917 static struct of_platform_driver fsl_soc_dma_driver = { 918 .driver = { 919 .name = "fsl-pcm-audio", 920 .owner = THIS_MODULE, 921 .of_match_table = fsl_soc_dma_ids, 922 }, 923 .probe = fsl_soc_dma_probe, 924 .remove = __devexit_p(fsl_soc_dma_remove), 925 }; 926 927 static int __init fsl_soc_dma_init(void) 928 { 929 pr_info("Freescale Elo DMA ASoC PCM Driver\n"); 930 931 return of_register_platform_driver(&fsl_soc_dma_driver); 932 } 933 934 static void __exit fsl_soc_dma_exit(void) 935 { 936 of_unregister_platform_driver(&fsl_soc_dma_driver); 937 } 938 939 /* We want the DMA driver to be initialized before the SSI driver, so that 940 * when the SSI driver calls fsl_soc_dma_dai_from_node(), the DMA driver 941 * will already have been probed. The easiest way to do that is to make the 942 * __init function called via arch_initcall(). 943 */ 944 module_init(fsl_soc_dma_init); 945 module_exit(fsl_soc_dma_exit); 946 947 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 948 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 949 MODULE_LICENSE("GPL v2"); 950