1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * This driver implements ASoC support for the Elo DMA controller, which is 13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 14 * the PCM driver is what handles the DMA buffer. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/gfp.h> 24 #include <linux/of_platform.h> 25 #include <linux/list.h> 26 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 32 #include <asm/io.h> 33 34 #include "fsl_dma.h" 35 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 36 37 /* 38 * The formats that the DMA controller supports, which is anything 39 * that is 8, 16, or 32 bits. 40 */ 41 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 42 SNDRV_PCM_FMTBIT_U8 | \ 43 SNDRV_PCM_FMTBIT_S16_LE | \ 44 SNDRV_PCM_FMTBIT_S16_BE | \ 45 SNDRV_PCM_FMTBIT_U16_LE | \ 46 SNDRV_PCM_FMTBIT_U16_BE | \ 47 SNDRV_PCM_FMTBIT_S24_LE | \ 48 SNDRV_PCM_FMTBIT_S24_BE | \ 49 SNDRV_PCM_FMTBIT_U24_LE | \ 50 SNDRV_PCM_FMTBIT_U24_BE | \ 51 SNDRV_PCM_FMTBIT_S32_LE | \ 52 SNDRV_PCM_FMTBIT_S32_BE | \ 53 SNDRV_PCM_FMTBIT_U32_LE | \ 54 SNDRV_PCM_FMTBIT_U32_BE) 55 56 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 57 SNDRV_PCM_RATE_CONTINUOUS) 58 59 struct dma_object { 60 struct snd_soc_platform_driver dai; 61 dma_addr_t ssi_stx_phys; 62 dma_addr_t ssi_srx_phys; 63 struct ccsr_dma_channel __iomem *channel; 64 unsigned int irq; 65 bool assigned; 66 char path[1]; 67 }; 68 69 /* 70 * The number of DMA links to use. Two is the bare minimum, but if you 71 * have really small links you might need more. 72 */ 73 #define NUM_DMA_LINKS 2 74 75 /** fsl_dma_private: p-substream DMA data 76 * 77 * Each substream has a 1-to-1 association with a DMA channel. 78 * 79 * The link[] array is first because it needs to be aligned on a 32-byte 80 * boundary, so putting it first will ensure alignment without padding the 81 * structure. 82 * 83 * @link[]: array of link descriptors 84 * @dma_channel: pointer to the DMA channel's registers 85 * @irq: IRQ for this DMA channel 86 * @substream: pointer to the substream object, needed by the ISR 87 * @ssi_sxx_phys: bus address of the STX or SRX register to use 88 * @ld_buf_phys: physical address of the LD buffer 89 * @current_link: index into link[] of the link currently being processed 90 * @dma_buf_phys: physical address of the DMA buffer 91 * @dma_buf_next: physical address of the next period to process 92 * @dma_buf_end: physical address of the byte after the end of the DMA 93 * @buffer period_size: the size of a single period 94 * @num_periods: the number of periods in the DMA buffer 95 */ 96 struct fsl_dma_private { 97 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 98 struct ccsr_dma_channel __iomem *dma_channel; 99 unsigned int irq; 100 struct snd_pcm_substream *substream; 101 dma_addr_t ssi_sxx_phys; 102 dma_addr_t ld_buf_phys; 103 unsigned int current_link; 104 dma_addr_t dma_buf_phys; 105 dma_addr_t dma_buf_next; 106 dma_addr_t dma_buf_end; 107 size_t period_size; 108 unsigned int num_periods; 109 }; 110 111 /** 112 * fsl_dma_hardare: define characteristics of the PCM hardware. 113 * 114 * The PCM hardware is the Freescale DMA controller. This structure defines 115 * the capabilities of that hardware. 116 * 117 * Since the sampling rate and data format are not controlled by the DMA 118 * controller, we specify no limits for those values. The only exception is 119 * period_bytes_min, which is set to a reasonably low value to prevent the 120 * DMA controller from generating too many interrupts per second. 121 * 122 * Since each link descriptor has a 32-bit byte count field, we set 123 * period_bytes_max to the largest 32-bit number. We also have no maximum 124 * number of periods. 125 * 126 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 127 * limitation in the SSI driver requires the sample rates for playback and 128 * capture to be the same. 129 */ 130 static const struct snd_pcm_hardware fsl_dma_hardware = { 131 132 .info = SNDRV_PCM_INFO_INTERLEAVED | 133 SNDRV_PCM_INFO_MMAP | 134 SNDRV_PCM_INFO_MMAP_VALID | 135 SNDRV_PCM_INFO_JOINT_DUPLEX | 136 SNDRV_PCM_INFO_PAUSE, 137 .formats = FSLDMA_PCM_FORMATS, 138 .rates = FSLDMA_PCM_RATES, 139 .rate_min = 5512, 140 .rate_max = 192000, 141 .period_bytes_min = 512, /* A reasonable limit */ 142 .period_bytes_max = (u32) -1, 143 .periods_min = NUM_DMA_LINKS, 144 .periods_max = (unsigned int) -1, 145 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 146 }; 147 148 /** 149 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 150 * 151 * This function should be called by the ISR whenever the DMA controller 152 * halts data transfer. 153 */ 154 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 155 { 156 unsigned long flags; 157 158 snd_pcm_stream_lock_irqsave(substream, flags); 159 160 if (snd_pcm_running(substream)) 161 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 162 163 snd_pcm_stream_unlock_irqrestore(substream, flags); 164 } 165 166 /** 167 * fsl_dma_update_pointers - update LD pointers to point to the next period 168 * 169 * As each period is completed, this function changes the the link 170 * descriptor pointers for that period to point to the next period. 171 */ 172 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 173 { 174 struct fsl_dma_link_descriptor *link = 175 &dma_private->link[dma_private->current_link]; 176 177 /* Update our link descriptors to point to the next period. On a 36-bit 178 * system, we also need to update the ESAD bits. We also set (keep) the 179 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 180 */ 181 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 182 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 183 #ifdef CONFIG_PHYS_64BIT 184 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 185 upper_32_bits(dma_private->dma_buf_next)); 186 #endif 187 } else { 188 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 189 #ifdef CONFIG_PHYS_64BIT 190 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 191 upper_32_bits(dma_private->dma_buf_next)); 192 #endif 193 } 194 195 /* Update our variables for next time */ 196 dma_private->dma_buf_next += dma_private->period_size; 197 198 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 199 dma_private->dma_buf_next = dma_private->dma_buf_phys; 200 201 if (++dma_private->current_link >= NUM_DMA_LINKS) 202 dma_private->current_link = 0; 203 } 204 205 /** 206 * fsl_dma_isr: interrupt handler for the DMA controller 207 * 208 * @irq: IRQ of the DMA channel 209 * @dev_id: pointer to the dma_private structure for this DMA channel 210 */ 211 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 212 { 213 struct fsl_dma_private *dma_private = dev_id; 214 struct snd_pcm_substream *substream = dma_private->substream; 215 struct snd_soc_pcm_runtime *rtd = substream->private_data; 216 struct device *dev = rtd->platform->dev; 217 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 218 irqreturn_t ret = IRQ_NONE; 219 u32 sr, sr2 = 0; 220 221 /* We got an interrupt, so read the status register to see what we 222 were interrupted for. 223 */ 224 sr = in_be32(&dma_channel->sr); 225 226 if (sr & CCSR_DMA_SR_TE) { 227 dev_err(dev, "dma transmit error\n"); 228 fsl_dma_abort_stream(substream); 229 sr2 |= CCSR_DMA_SR_TE; 230 ret = IRQ_HANDLED; 231 } 232 233 if (sr & CCSR_DMA_SR_CH) 234 ret = IRQ_HANDLED; 235 236 if (sr & CCSR_DMA_SR_PE) { 237 dev_err(dev, "dma programming error\n"); 238 fsl_dma_abort_stream(substream); 239 sr2 |= CCSR_DMA_SR_PE; 240 ret = IRQ_HANDLED; 241 } 242 243 if (sr & CCSR_DMA_SR_EOLNI) { 244 sr2 |= CCSR_DMA_SR_EOLNI; 245 ret = IRQ_HANDLED; 246 } 247 248 if (sr & CCSR_DMA_SR_CB) 249 ret = IRQ_HANDLED; 250 251 if (sr & CCSR_DMA_SR_EOSI) { 252 /* Tell ALSA we completed a period. */ 253 snd_pcm_period_elapsed(substream); 254 255 /* 256 * Update our link descriptors to point to the next period. We 257 * only need to do this if the number of periods is not equal to 258 * the number of links. 259 */ 260 if (dma_private->num_periods != NUM_DMA_LINKS) 261 fsl_dma_update_pointers(dma_private); 262 263 sr2 |= CCSR_DMA_SR_EOSI; 264 ret = IRQ_HANDLED; 265 } 266 267 if (sr & CCSR_DMA_SR_EOLSI) { 268 sr2 |= CCSR_DMA_SR_EOLSI; 269 ret = IRQ_HANDLED; 270 } 271 272 /* Clear the bits that we set */ 273 if (sr2) 274 out_be32(&dma_channel->sr, sr2); 275 276 return ret; 277 } 278 279 /** 280 * fsl_dma_new: initialize this PCM driver. 281 * 282 * This function is called when the codec driver calls snd_soc_new_pcms(), 283 * once for each .dai_link in the machine driver's snd_soc_card 284 * structure. 285 * 286 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 287 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 288 * is specified. Therefore, any DMA buffers we allocate will always be in low 289 * memory, but we support for 36-bit physical addresses anyway. 290 * 291 * Regardless of where the memory is actually allocated, since the device can 292 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 293 */ 294 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, 295 struct snd_pcm *pcm) 296 { 297 static u64 fsl_dma_dmamask = DMA_BIT_MASK(36); 298 int ret; 299 300 if (!card->dev->dma_mask) 301 card->dev->dma_mask = &fsl_dma_dmamask; 302 303 if (!card->dev->coherent_dma_mask) 304 card->dev->coherent_dma_mask = fsl_dma_dmamask; 305 306 /* Some codecs have separate DAIs for playback and capture, so we 307 * should allocate a DMA buffer only for the streams that are valid. 308 */ 309 310 if (dai->driver->playback.channels_min) { 311 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 312 fsl_dma_hardware.buffer_bytes_max, 313 &pcm->streams[0].substream->dma_buffer); 314 if (ret) { 315 dev_err(card->dev, "can't alloc playback dma buffer\n"); 316 return ret; 317 } 318 } 319 320 if (dai->driver->capture.channels_min) { 321 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 322 fsl_dma_hardware.buffer_bytes_max, 323 &pcm->streams[1].substream->dma_buffer); 324 if (ret) { 325 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 326 dev_err(card->dev, "can't alloc capture dma buffer\n"); 327 return ret; 328 } 329 } 330 331 return 0; 332 } 333 334 /** 335 * fsl_dma_open: open a new substream. 336 * 337 * Each substream has its own DMA buffer. 338 * 339 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 340 * descriptors that ping-pong from one period to the next. For example, if 341 * there are six periods and two link descriptors, this is how they look 342 * before playback starts: 343 * 344 * The last link descriptor 345 * ____________ points back to the first 346 * | | 347 * V | 348 * ___ ___ | 349 * | |->| |->| 350 * |___| |___| 351 * | | 352 * | | 353 * V V 354 * _________________________________________ 355 * | | | | | | | The DMA buffer is 356 * | | | | | | | divided into 6 parts 357 * |______|______|______|______|______|______| 358 * 359 * and here's how they look after the first period is finished playing: 360 * 361 * ____________ 362 * | | 363 * V | 364 * ___ ___ | 365 * | |->| |->| 366 * |___| |___| 367 * | | 368 * |______________ 369 * | | 370 * V V 371 * _________________________________________ 372 * | | | | | | | 373 * | | | | | | | 374 * |______|______|______|______|______|______| 375 * 376 * The first link descriptor now points to the third period. The DMA 377 * controller is currently playing the second period. When it finishes, it 378 * will jump back to the first descriptor and play the third period. 379 * 380 * There are four reasons we do this: 381 * 382 * 1. The only way to get the DMA controller to automatically restart the 383 * transfer when it gets to the end of the buffer is to use chaining 384 * mode. Basic direct mode doesn't offer that feature. 385 * 2. We need to receive an interrupt at the end of every period. The DMA 386 * controller can generate an interrupt at the end of every link transfer 387 * (aka segment). Making each period into a DMA segment will give us the 388 * interrupts we need. 389 * 3. By creating only two link descriptors, regardless of the number of 390 * periods, we do not need to reallocate the link descriptors if the 391 * number of periods changes. 392 * 4. All of the audio data is still stored in a single, contiguous DMA 393 * buffer, which is what ALSA expects. We're just dividing it into 394 * contiguous parts, and creating a link descriptor for each one. 395 */ 396 static int fsl_dma_open(struct snd_pcm_substream *substream) 397 { 398 struct snd_pcm_runtime *runtime = substream->runtime; 399 struct snd_soc_pcm_runtime *rtd = substream->private_data; 400 struct device *dev = rtd->platform->dev; 401 struct dma_object *dma = 402 container_of(rtd->platform->driver, struct dma_object, dai); 403 struct fsl_dma_private *dma_private; 404 struct ccsr_dma_channel __iomem *dma_channel; 405 dma_addr_t ld_buf_phys; 406 u64 temp_link; /* Pointer to next link descriptor */ 407 u32 mr; 408 unsigned int channel; 409 int ret = 0; 410 unsigned int i; 411 412 /* 413 * Reject any DMA buffer whose size is not a multiple of the period 414 * size. We need to make sure that the DMA buffer can be evenly divided 415 * into periods. 416 */ 417 ret = snd_pcm_hw_constraint_integer(runtime, 418 SNDRV_PCM_HW_PARAM_PERIODS); 419 if (ret < 0) { 420 dev_err(dev, "invalid buffer size\n"); 421 return ret; 422 } 423 424 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 425 426 if (dma->assigned) { 427 dev_err(dev, "dma channel already assigned\n"); 428 return -EBUSY; 429 } 430 431 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 432 &ld_buf_phys, GFP_KERNEL); 433 if (!dma_private) { 434 dev_err(dev, "can't allocate dma private data\n"); 435 return -ENOMEM; 436 } 437 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 438 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 439 else 440 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 441 442 dma_private->dma_channel = dma->channel; 443 dma_private->irq = dma->irq; 444 dma_private->substream = substream; 445 dma_private->ld_buf_phys = ld_buf_phys; 446 dma_private->dma_buf_phys = substream->dma_buffer.addr; 447 448 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 449 if (ret) { 450 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 451 dma_private->irq, ret); 452 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 453 dma_private, dma_private->ld_buf_phys); 454 return ret; 455 } 456 457 dma->assigned = 1; 458 459 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 460 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 461 runtime->private_data = dma_private; 462 463 /* Program the fixed DMA controller parameters */ 464 465 dma_channel = dma_private->dma_channel; 466 467 temp_link = dma_private->ld_buf_phys + 468 sizeof(struct fsl_dma_link_descriptor); 469 470 for (i = 0; i < NUM_DMA_LINKS; i++) { 471 dma_private->link[i].next = cpu_to_be64(temp_link); 472 473 temp_link += sizeof(struct fsl_dma_link_descriptor); 474 } 475 /* The last link descriptor points to the first */ 476 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 477 478 /* Tell the DMA controller where the first link descriptor is */ 479 out_be32(&dma_channel->clndar, 480 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 481 out_be32(&dma_channel->eclndar, 482 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 483 484 /* The manual says the BCR must be clear before enabling EMP */ 485 out_be32(&dma_channel->bcr, 0); 486 487 /* 488 * Program the mode register for interrupts, external master control, 489 * and source/destination hold. Also clear the Channel Abort bit. 490 */ 491 mr = in_be32(&dma_channel->mr) & 492 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 493 494 /* 495 * We want External Master Start and External Master Pause enabled, 496 * because the SSI is controlling the DMA controller. We want the DMA 497 * controller to be set up in advance, and then we signal only the SSI 498 * to start transferring. 499 * 500 * We want End-Of-Segment Interrupts enabled, because this will generate 501 * an interrupt at the end of each segment (each link descriptor 502 * represents one segment). Each DMA segment is the same thing as an 503 * ALSA period, so this is how we get an interrupt at the end of every 504 * period. 505 * 506 * We want Error Interrupt enabled, so that we can get an error if 507 * the DMA controller is mis-programmed somehow. 508 */ 509 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 510 CCSR_DMA_MR_EMS_EN; 511 512 /* For playback, we want the destination address to be held. For 513 capture, set the source address to be held. */ 514 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 515 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 516 517 out_be32(&dma_channel->mr, mr); 518 519 return 0; 520 } 521 522 /** 523 * fsl_dma_hw_params: continue initializing the DMA links 524 * 525 * This function obtains hardware parameters about the opened stream and 526 * programs the DMA controller accordingly. 527 * 528 * One drawback of big-endian is that when copying integers of different 529 * sizes to a fixed-sized register, the address to which the integer must be 530 * copied is dependent on the size of the integer. 531 * 532 * For example, if P is the address of a 32-bit register, and X is a 32-bit 533 * integer, then X should be copied to address P. However, if X is a 16-bit 534 * integer, then it should be copied to P+2. If X is an 8-bit register, 535 * then it should be copied to P+3. 536 * 537 * So for playback of 8-bit samples, the DMA controller must transfer single 538 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 539 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 540 * 541 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 542 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 543 * and 8 bytes at a time). So we do not support packed 24-bit samples. 544 * 24-bit data must be padded to 32 bits. 545 */ 546 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 547 struct snd_pcm_hw_params *hw_params) 548 { 549 struct snd_pcm_runtime *runtime = substream->runtime; 550 struct fsl_dma_private *dma_private = runtime->private_data; 551 struct snd_soc_pcm_runtime *rtd = substream->private_data; 552 struct device *dev = rtd->platform->dev; 553 554 /* Number of bits per sample */ 555 unsigned int sample_size = 556 snd_pcm_format_physical_width(params_format(hw_params)); 557 558 /* Number of bytes per frame */ 559 unsigned int frame_size = 2 * (sample_size / 8); 560 561 /* Bus address of SSI STX register */ 562 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 563 564 /* Size of the DMA buffer, in bytes */ 565 size_t buffer_size = params_buffer_bytes(hw_params); 566 567 /* Number of bytes per period */ 568 size_t period_size = params_period_bytes(hw_params); 569 570 /* Pointer to next period */ 571 dma_addr_t temp_addr = substream->dma_buffer.addr; 572 573 /* Pointer to DMA controller */ 574 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 575 576 u32 mr; /* DMA Mode Register */ 577 578 unsigned int i; 579 580 /* Initialize our DMA tracking variables */ 581 dma_private->period_size = period_size; 582 dma_private->num_periods = params_periods(hw_params); 583 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 584 dma_private->dma_buf_next = dma_private->dma_buf_phys + 585 (NUM_DMA_LINKS * period_size); 586 587 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 588 /* This happens if the number of periods == NUM_DMA_LINKS */ 589 dma_private->dma_buf_next = dma_private->dma_buf_phys; 590 591 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 592 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 593 594 /* Due to a quirk of the SSI's STX register, the target address 595 * for the DMA operations depends on the sample size. So we calculate 596 * that offset here. While we're at it, also tell the DMA controller 597 * how much data to transfer per sample. 598 */ 599 switch (sample_size) { 600 case 8: 601 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 602 ssi_sxx_phys += 3; 603 break; 604 case 16: 605 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 606 ssi_sxx_phys += 2; 607 break; 608 case 32: 609 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 610 break; 611 default: 612 /* We should never get here */ 613 dev_err(dev, "unsupported sample size %u\n", sample_size); 614 return -EINVAL; 615 } 616 617 /* 618 * BWC should always be a multiple of the frame size. BWC determines 619 * how many bytes are sent/received before the DMA controller checks the 620 * SSI to see if it needs to stop. For playback, the transmit FIFO can 621 * hold three frames, so we want to send two frames at a time. For 622 * capture, the receive FIFO is triggered when it contains one frame, so 623 * we want to receive one frame at a time. 624 */ 625 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 626 mr |= CCSR_DMA_MR_BWC(2 * frame_size); 627 else 628 mr |= CCSR_DMA_MR_BWC(frame_size); 629 630 out_be32(&dma_channel->mr, mr); 631 632 for (i = 0; i < NUM_DMA_LINKS; i++) { 633 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 634 635 link->count = cpu_to_be32(period_size); 636 637 /* The snoop bit tells the DMA controller whether it should tell 638 * the ECM to snoop during a read or write to an address. For 639 * audio, we use DMA to transfer data between memory and an I/O 640 * device (the SSI's STX0 or SRX0 register). Snooping is only 641 * needed if there is a cache, so we need to snoop memory 642 * addresses only. For playback, that means we snoop the source 643 * but not the destination. For capture, we snoop the 644 * destination but not the source. 645 * 646 * Note that failing to snoop properly is unlikely to cause 647 * cache incoherency if the period size is larger than the 648 * size of L1 cache. This is because filling in one period will 649 * flush out the data for the previous period. So if you 650 * increased period_bytes_min to a large enough size, you might 651 * get more performance by not snooping, and you'll still be 652 * okay. You'll need to update fsl_dma_update_pointers() also. 653 */ 654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 655 link->source_addr = cpu_to_be32(temp_addr); 656 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 657 upper_32_bits(temp_addr)); 658 659 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 660 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 661 upper_32_bits(ssi_sxx_phys)); 662 } else { 663 link->source_addr = cpu_to_be32(ssi_sxx_phys); 664 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 665 upper_32_bits(ssi_sxx_phys)); 666 667 link->dest_addr = cpu_to_be32(temp_addr); 668 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 669 upper_32_bits(temp_addr)); 670 } 671 672 temp_addr += period_size; 673 } 674 675 return 0; 676 } 677 678 /** 679 * fsl_dma_pointer: determine the current position of the DMA transfer 680 * 681 * This function is called by ALSA when ALSA wants to know where in the 682 * stream buffer the hardware currently is. 683 * 684 * For playback, the SAR register contains the physical address of the most 685 * recent DMA transfer. For capture, the value is in the DAR register. 686 * 687 * The base address of the buffer is stored in the source_addr field of the 688 * first link descriptor. 689 */ 690 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 691 { 692 struct snd_pcm_runtime *runtime = substream->runtime; 693 struct fsl_dma_private *dma_private = runtime->private_data; 694 struct snd_soc_pcm_runtime *rtd = substream->private_data; 695 struct device *dev = rtd->platform->dev; 696 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 697 dma_addr_t position; 698 snd_pcm_uframes_t frames; 699 700 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 701 * only have 32-bit DMA addresses. This function is typically called 702 * in interrupt context, so we need to optimize it. 703 */ 704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 705 position = in_be32(&dma_channel->sar); 706 #ifdef CONFIG_PHYS_64BIT 707 position |= (u64)(in_be32(&dma_channel->satr) & 708 CCSR_DMA_ATR_ESAD_MASK) << 32; 709 #endif 710 } else { 711 position = in_be32(&dma_channel->dar); 712 #ifdef CONFIG_PHYS_64BIT 713 position |= (u64)(in_be32(&dma_channel->datr) & 714 CCSR_DMA_ATR_ESAD_MASK) << 32; 715 #endif 716 } 717 718 /* 719 * When capture is started, the SSI immediately starts to fill its FIFO. 720 * This means that the DMA controller is not started until the FIFO is 721 * full. However, ALSA calls this function before that happens, when 722 * MR.DAR is still zero. In this case, just return zero to indicate 723 * that nothing has been received yet. 724 */ 725 if (!position) 726 return 0; 727 728 if ((position < dma_private->dma_buf_phys) || 729 (position > dma_private->dma_buf_end)) { 730 dev_err(dev, "dma pointer is out of range, halting stream\n"); 731 return SNDRV_PCM_POS_XRUN; 732 } 733 734 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 735 736 /* 737 * If the current address is just past the end of the buffer, wrap it 738 * around. 739 */ 740 if (frames == runtime->buffer_size) 741 frames = 0; 742 743 return frames; 744 } 745 746 /** 747 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 748 * 749 * Release the resources allocated in fsl_dma_hw_params() and de-program the 750 * registers. 751 * 752 * This function can be called multiple times. 753 */ 754 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 755 { 756 struct snd_pcm_runtime *runtime = substream->runtime; 757 struct fsl_dma_private *dma_private = runtime->private_data; 758 759 if (dma_private) { 760 struct ccsr_dma_channel __iomem *dma_channel; 761 762 dma_channel = dma_private->dma_channel; 763 764 /* Stop the DMA */ 765 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 766 out_be32(&dma_channel->mr, 0); 767 768 /* Reset all the other registers */ 769 out_be32(&dma_channel->sr, -1); 770 out_be32(&dma_channel->clndar, 0); 771 out_be32(&dma_channel->eclndar, 0); 772 out_be32(&dma_channel->satr, 0); 773 out_be32(&dma_channel->sar, 0); 774 out_be32(&dma_channel->datr, 0); 775 out_be32(&dma_channel->dar, 0); 776 out_be32(&dma_channel->bcr, 0); 777 out_be32(&dma_channel->nlndar, 0); 778 out_be32(&dma_channel->enlndar, 0); 779 } 780 781 return 0; 782 } 783 784 /** 785 * fsl_dma_close: close the stream. 786 */ 787 static int fsl_dma_close(struct snd_pcm_substream *substream) 788 { 789 struct snd_pcm_runtime *runtime = substream->runtime; 790 struct fsl_dma_private *dma_private = runtime->private_data; 791 struct snd_soc_pcm_runtime *rtd = substream->private_data; 792 struct device *dev = rtd->platform->dev; 793 struct dma_object *dma = 794 container_of(rtd->platform->driver, struct dma_object, dai); 795 796 if (dma_private) { 797 if (dma_private->irq) 798 free_irq(dma_private->irq, dma_private); 799 800 if (dma_private->ld_buf_phys) { 801 dma_unmap_single(dev, dma_private->ld_buf_phys, 802 sizeof(dma_private->link), 803 DMA_TO_DEVICE); 804 } 805 806 /* Deallocate the fsl_dma_private structure */ 807 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 808 dma_private, dma_private->ld_buf_phys); 809 substream->runtime->private_data = NULL; 810 } 811 812 dma->assigned = 0; 813 814 return 0; 815 } 816 817 /* 818 * Remove this PCM driver. 819 */ 820 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 821 { 822 struct snd_pcm_substream *substream; 823 unsigned int i; 824 825 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 826 substream = pcm->streams[i].substream; 827 if (substream) { 828 snd_dma_free_pages(&substream->dma_buffer); 829 substream->dma_buffer.area = NULL; 830 substream->dma_buffer.addr = 0; 831 } 832 } 833 } 834 835 /** 836 * find_ssi_node -- returns the SSI node that points to his DMA channel node 837 * 838 * Although this DMA driver attempts to operate independently of the other 839 * devices, it still needs to determine some information about the SSI device 840 * that it's working with. Unfortunately, the device tree does not contain 841 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 842 * other way. So we need to scan the device tree for SSI nodes until we find 843 * the one that points to the given DMA channel node. It's ugly, but at least 844 * it's contained in this one function. 845 */ 846 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 847 { 848 struct device_node *ssi_np, *np; 849 850 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 851 /* Check each DMA phandle to see if it points to us. We 852 * assume that device_node pointers are a valid comparison. 853 */ 854 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 855 if (np == dma_channel_np) 856 return ssi_np; 857 858 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 859 if (np == dma_channel_np) 860 return ssi_np; 861 } 862 863 return NULL; 864 } 865 866 static struct snd_pcm_ops fsl_dma_ops = { 867 .open = fsl_dma_open, 868 .close = fsl_dma_close, 869 .ioctl = snd_pcm_lib_ioctl, 870 .hw_params = fsl_dma_hw_params, 871 .hw_free = fsl_dma_hw_free, 872 .pointer = fsl_dma_pointer, 873 }; 874 875 static int __devinit fsl_soc_dma_probe(struct of_device *of_dev, 876 const struct of_device_id *match) 877 { 878 struct dma_object *dma; 879 struct device_node *np = of_dev->dev.of_node; 880 struct device_node *ssi_np; 881 struct resource res; 882 int ret; 883 884 /* Find the SSI node that points to us. */ 885 ssi_np = find_ssi_node(np); 886 if (!ssi_np) { 887 dev_err(&of_dev->dev, "cannot find parent SSI node\n"); 888 return -ENODEV; 889 } 890 891 ret = of_address_to_resource(ssi_np, 0, &res); 892 of_node_put(ssi_np); 893 if (ret) { 894 dev_err(&of_dev->dev, "could not determine device resources\n"); 895 return ret; 896 } 897 898 dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL); 899 if (!dma) { 900 dev_err(&of_dev->dev, "could not allocate dma object\n"); 901 return -ENOMEM; 902 } 903 904 strcpy(dma->path, np->full_name); 905 dma->dai.ops = &fsl_dma_ops; 906 dma->dai.pcm_new = fsl_dma_new; 907 dma->dai.pcm_free = fsl_dma_free_dma_buffers; 908 909 /* Store the SSI-specific information that we need */ 910 dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0); 911 dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0); 912 913 ret = snd_soc_register_platform(&of_dev->dev, &dma->dai); 914 if (ret) { 915 dev_err(&of_dev->dev, "could not register platform\n"); 916 kfree(dma); 917 return ret; 918 } 919 920 dma->channel = of_iomap(np, 0); 921 dma->irq = irq_of_parse_and_map(np, 0); 922 923 dev_set_drvdata(&of_dev->dev, dma); 924 925 return 0; 926 } 927 928 static int __devexit fsl_soc_dma_remove(struct of_device *of_dev) 929 { 930 struct dma_object *dma = dev_get_drvdata(&of_dev->dev); 931 932 snd_soc_unregister_platform(&of_dev->dev); 933 iounmap(dma->channel); 934 irq_dispose_mapping(dma->irq); 935 kfree(dma); 936 937 return 0; 938 } 939 940 static const struct of_device_id fsl_soc_dma_ids[] = { 941 { .compatible = "fsl,ssi-dma-channel", }, 942 {} 943 }; 944 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 945 946 static struct of_platform_driver fsl_soc_dma_driver = { 947 .driver = { 948 .name = "fsl-pcm-audio", 949 .owner = THIS_MODULE, 950 .of_match_table = fsl_soc_dma_ids, 951 }, 952 .probe = fsl_soc_dma_probe, 953 .remove = __devexit_p(fsl_soc_dma_remove), 954 }; 955 956 static int __init fsl_soc_dma_init(void) 957 { 958 pr_info("Freescale Elo DMA ASoC PCM Driver\n"); 959 960 return of_register_platform_driver(&fsl_soc_dma_driver); 961 } 962 963 static void __exit fsl_soc_dma_exit(void) 964 { 965 of_unregister_platform_driver(&fsl_soc_dma_driver); 966 } 967 968 module_init(fsl_soc_dma_init); 969 module_exit(fsl_soc_dma_exit); 970 971 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 972 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 973 MODULE_LICENSE("GPL v2"); 974