1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * This driver implements ASoC support for the Elo DMA controller, which is 13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 14 * the PCM driver is what handles the DMA buffer. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/gfp.h> 24 #include <linux/of_platform.h> 25 #include <linux/list.h> 26 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 32 #include <asm/io.h> 33 34 #include "fsl_dma.h" 35 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 36 37 /* 38 * The formats that the DMA controller supports, which is anything 39 * that is 8, 16, or 32 bits. 40 */ 41 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 42 SNDRV_PCM_FMTBIT_U8 | \ 43 SNDRV_PCM_FMTBIT_S16_LE | \ 44 SNDRV_PCM_FMTBIT_S16_BE | \ 45 SNDRV_PCM_FMTBIT_U16_LE | \ 46 SNDRV_PCM_FMTBIT_U16_BE | \ 47 SNDRV_PCM_FMTBIT_S24_LE | \ 48 SNDRV_PCM_FMTBIT_S24_BE | \ 49 SNDRV_PCM_FMTBIT_U24_LE | \ 50 SNDRV_PCM_FMTBIT_U24_BE | \ 51 SNDRV_PCM_FMTBIT_S32_LE | \ 52 SNDRV_PCM_FMTBIT_S32_BE | \ 53 SNDRV_PCM_FMTBIT_U32_LE | \ 54 SNDRV_PCM_FMTBIT_U32_BE) 55 56 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 57 SNDRV_PCM_RATE_CONTINUOUS) 58 59 struct dma_object { 60 struct snd_soc_platform_driver dai; 61 dma_addr_t ssi_stx_phys; 62 dma_addr_t ssi_srx_phys; 63 unsigned int ssi_fifo_depth; 64 struct ccsr_dma_channel __iomem *channel; 65 unsigned int irq; 66 bool assigned; 67 char path[1]; 68 }; 69 70 /* 71 * The number of DMA links to use. Two is the bare minimum, but if you 72 * have really small links you might need more. 73 */ 74 #define NUM_DMA_LINKS 2 75 76 /** fsl_dma_private: p-substream DMA data 77 * 78 * Each substream has a 1-to-1 association with a DMA channel. 79 * 80 * The link[] array is first because it needs to be aligned on a 32-byte 81 * boundary, so putting it first will ensure alignment without padding the 82 * structure. 83 * 84 * @link[]: array of link descriptors 85 * @dma_channel: pointer to the DMA channel's registers 86 * @irq: IRQ for this DMA channel 87 * @substream: pointer to the substream object, needed by the ISR 88 * @ssi_sxx_phys: bus address of the STX or SRX register to use 89 * @ld_buf_phys: physical address of the LD buffer 90 * @current_link: index into link[] of the link currently being processed 91 * @dma_buf_phys: physical address of the DMA buffer 92 * @dma_buf_next: physical address of the next period to process 93 * @dma_buf_end: physical address of the byte after the end of the DMA 94 * @buffer period_size: the size of a single period 95 * @num_periods: the number of periods in the DMA buffer 96 */ 97 struct fsl_dma_private { 98 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 99 struct ccsr_dma_channel __iomem *dma_channel; 100 unsigned int irq; 101 struct snd_pcm_substream *substream; 102 dma_addr_t ssi_sxx_phys; 103 unsigned int ssi_fifo_depth; 104 dma_addr_t ld_buf_phys; 105 unsigned int current_link; 106 dma_addr_t dma_buf_phys; 107 dma_addr_t dma_buf_next; 108 dma_addr_t dma_buf_end; 109 size_t period_size; 110 unsigned int num_periods; 111 }; 112 113 /** 114 * fsl_dma_hardare: define characteristics of the PCM hardware. 115 * 116 * The PCM hardware is the Freescale DMA controller. This structure defines 117 * the capabilities of that hardware. 118 * 119 * Since the sampling rate and data format are not controlled by the DMA 120 * controller, we specify no limits for those values. The only exception is 121 * period_bytes_min, which is set to a reasonably low value to prevent the 122 * DMA controller from generating too many interrupts per second. 123 * 124 * Since each link descriptor has a 32-bit byte count field, we set 125 * period_bytes_max to the largest 32-bit number. We also have no maximum 126 * number of periods. 127 * 128 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 129 * limitation in the SSI driver requires the sample rates for playback and 130 * capture to be the same. 131 */ 132 static const struct snd_pcm_hardware fsl_dma_hardware = { 133 134 .info = SNDRV_PCM_INFO_INTERLEAVED | 135 SNDRV_PCM_INFO_MMAP | 136 SNDRV_PCM_INFO_MMAP_VALID | 137 SNDRV_PCM_INFO_JOINT_DUPLEX | 138 SNDRV_PCM_INFO_PAUSE, 139 .formats = FSLDMA_PCM_FORMATS, 140 .rates = FSLDMA_PCM_RATES, 141 .rate_min = 5512, 142 .rate_max = 192000, 143 .period_bytes_min = 512, /* A reasonable limit */ 144 .period_bytes_max = (u32) -1, 145 .periods_min = NUM_DMA_LINKS, 146 .periods_max = (unsigned int) -1, 147 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 148 }; 149 150 /** 151 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 152 * 153 * This function should be called by the ISR whenever the DMA controller 154 * halts data transfer. 155 */ 156 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 157 { 158 unsigned long flags; 159 160 snd_pcm_stream_lock_irqsave(substream, flags); 161 162 if (snd_pcm_running(substream)) 163 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 164 165 snd_pcm_stream_unlock_irqrestore(substream, flags); 166 } 167 168 /** 169 * fsl_dma_update_pointers - update LD pointers to point to the next period 170 * 171 * As each period is completed, this function changes the the link 172 * descriptor pointers for that period to point to the next period. 173 */ 174 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 175 { 176 struct fsl_dma_link_descriptor *link = 177 &dma_private->link[dma_private->current_link]; 178 179 /* Update our link descriptors to point to the next period. On a 36-bit 180 * system, we also need to update the ESAD bits. We also set (keep) the 181 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 182 */ 183 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 184 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 185 #ifdef CONFIG_PHYS_64BIT 186 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 187 upper_32_bits(dma_private->dma_buf_next)); 188 #endif 189 } else { 190 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 191 #ifdef CONFIG_PHYS_64BIT 192 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 193 upper_32_bits(dma_private->dma_buf_next)); 194 #endif 195 } 196 197 /* Update our variables for next time */ 198 dma_private->dma_buf_next += dma_private->period_size; 199 200 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 201 dma_private->dma_buf_next = dma_private->dma_buf_phys; 202 203 if (++dma_private->current_link >= NUM_DMA_LINKS) 204 dma_private->current_link = 0; 205 } 206 207 /** 208 * fsl_dma_isr: interrupt handler for the DMA controller 209 * 210 * @irq: IRQ of the DMA channel 211 * @dev_id: pointer to the dma_private structure for this DMA channel 212 */ 213 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 214 { 215 struct fsl_dma_private *dma_private = dev_id; 216 struct snd_pcm_substream *substream = dma_private->substream; 217 struct snd_soc_pcm_runtime *rtd = substream->private_data; 218 struct device *dev = rtd->platform->dev; 219 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 220 irqreturn_t ret = IRQ_NONE; 221 u32 sr, sr2 = 0; 222 223 /* We got an interrupt, so read the status register to see what we 224 were interrupted for. 225 */ 226 sr = in_be32(&dma_channel->sr); 227 228 if (sr & CCSR_DMA_SR_TE) { 229 dev_err(dev, "dma transmit error\n"); 230 fsl_dma_abort_stream(substream); 231 sr2 |= CCSR_DMA_SR_TE; 232 ret = IRQ_HANDLED; 233 } 234 235 if (sr & CCSR_DMA_SR_CH) 236 ret = IRQ_HANDLED; 237 238 if (sr & CCSR_DMA_SR_PE) { 239 dev_err(dev, "dma programming error\n"); 240 fsl_dma_abort_stream(substream); 241 sr2 |= CCSR_DMA_SR_PE; 242 ret = IRQ_HANDLED; 243 } 244 245 if (sr & CCSR_DMA_SR_EOLNI) { 246 sr2 |= CCSR_DMA_SR_EOLNI; 247 ret = IRQ_HANDLED; 248 } 249 250 if (sr & CCSR_DMA_SR_CB) 251 ret = IRQ_HANDLED; 252 253 if (sr & CCSR_DMA_SR_EOSI) { 254 /* Tell ALSA we completed a period. */ 255 snd_pcm_period_elapsed(substream); 256 257 /* 258 * Update our link descriptors to point to the next period. We 259 * only need to do this if the number of periods is not equal to 260 * the number of links. 261 */ 262 if (dma_private->num_periods != NUM_DMA_LINKS) 263 fsl_dma_update_pointers(dma_private); 264 265 sr2 |= CCSR_DMA_SR_EOSI; 266 ret = IRQ_HANDLED; 267 } 268 269 if (sr & CCSR_DMA_SR_EOLSI) { 270 sr2 |= CCSR_DMA_SR_EOLSI; 271 ret = IRQ_HANDLED; 272 } 273 274 /* Clear the bits that we set */ 275 if (sr2) 276 out_be32(&dma_channel->sr, sr2); 277 278 return ret; 279 } 280 281 /** 282 * fsl_dma_new: initialize this PCM driver. 283 * 284 * This function is called when the codec driver calls snd_soc_new_pcms(), 285 * once for each .dai_link in the machine driver's snd_soc_card 286 * structure. 287 * 288 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 289 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 290 * is specified. Therefore, any DMA buffers we allocate will always be in low 291 * memory, but we support for 36-bit physical addresses anyway. 292 * 293 * Regardless of where the memory is actually allocated, since the device can 294 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 295 */ 296 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, 297 struct snd_pcm *pcm) 298 { 299 static u64 fsl_dma_dmamask = DMA_BIT_MASK(36); 300 int ret; 301 302 if (!card->dev->dma_mask) 303 card->dev->dma_mask = &fsl_dma_dmamask; 304 305 if (!card->dev->coherent_dma_mask) 306 card->dev->coherent_dma_mask = fsl_dma_dmamask; 307 308 /* Some codecs have separate DAIs for playback and capture, so we 309 * should allocate a DMA buffer only for the streams that are valid. 310 */ 311 312 if (dai->driver->playback.channels_min) { 313 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 314 fsl_dma_hardware.buffer_bytes_max, 315 &pcm->streams[0].substream->dma_buffer); 316 if (ret) { 317 dev_err(card->dev, "can't alloc playback dma buffer\n"); 318 return ret; 319 } 320 } 321 322 if (dai->driver->capture.channels_min) { 323 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 324 fsl_dma_hardware.buffer_bytes_max, 325 &pcm->streams[1].substream->dma_buffer); 326 if (ret) { 327 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 328 dev_err(card->dev, "can't alloc capture dma buffer\n"); 329 return ret; 330 } 331 } 332 333 return 0; 334 } 335 336 /** 337 * fsl_dma_open: open a new substream. 338 * 339 * Each substream has its own DMA buffer. 340 * 341 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 342 * descriptors that ping-pong from one period to the next. For example, if 343 * there are six periods and two link descriptors, this is how they look 344 * before playback starts: 345 * 346 * The last link descriptor 347 * ____________ points back to the first 348 * | | 349 * V | 350 * ___ ___ | 351 * | |->| |->| 352 * |___| |___| 353 * | | 354 * | | 355 * V V 356 * _________________________________________ 357 * | | | | | | | The DMA buffer is 358 * | | | | | | | divided into 6 parts 359 * |______|______|______|______|______|______| 360 * 361 * and here's how they look after the first period is finished playing: 362 * 363 * ____________ 364 * | | 365 * V | 366 * ___ ___ | 367 * | |->| |->| 368 * |___| |___| 369 * | | 370 * |______________ 371 * | | 372 * V V 373 * _________________________________________ 374 * | | | | | | | 375 * | | | | | | | 376 * |______|______|______|______|______|______| 377 * 378 * The first link descriptor now points to the third period. The DMA 379 * controller is currently playing the second period. When it finishes, it 380 * will jump back to the first descriptor and play the third period. 381 * 382 * There are four reasons we do this: 383 * 384 * 1. The only way to get the DMA controller to automatically restart the 385 * transfer when it gets to the end of the buffer is to use chaining 386 * mode. Basic direct mode doesn't offer that feature. 387 * 2. We need to receive an interrupt at the end of every period. The DMA 388 * controller can generate an interrupt at the end of every link transfer 389 * (aka segment). Making each period into a DMA segment will give us the 390 * interrupts we need. 391 * 3. By creating only two link descriptors, regardless of the number of 392 * periods, we do not need to reallocate the link descriptors if the 393 * number of periods changes. 394 * 4. All of the audio data is still stored in a single, contiguous DMA 395 * buffer, which is what ALSA expects. We're just dividing it into 396 * contiguous parts, and creating a link descriptor for each one. 397 */ 398 static int fsl_dma_open(struct snd_pcm_substream *substream) 399 { 400 struct snd_pcm_runtime *runtime = substream->runtime; 401 struct snd_soc_pcm_runtime *rtd = substream->private_data; 402 struct device *dev = rtd->platform->dev; 403 struct dma_object *dma = 404 container_of(rtd->platform->driver, struct dma_object, dai); 405 struct fsl_dma_private *dma_private; 406 struct ccsr_dma_channel __iomem *dma_channel; 407 dma_addr_t ld_buf_phys; 408 u64 temp_link; /* Pointer to next link descriptor */ 409 u32 mr; 410 unsigned int channel; 411 int ret = 0; 412 unsigned int i; 413 414 /* 415 * Reject any DMA buffer whose size is not a multiple of the period 416 * size. We need to make sure that the DMA buffer can be evenly divided 417 * into periods. 418 */ 419 ret = snd_pcm_hw_constraint_integer(runtime, 420 SNDRV_PCM_HW_PARAM_PERIODS); 421 if (ret < 0) { 422 dev_err(dev, "invalid buffer size\n"); 423 return ret; 424 } 425 426 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 427 428 if (dma->assigned) { 429 dev_err(dev, "dma channel already assigned\n"); 430 return -EBUSY; 431 } 432 433 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 434 &ld_buf_phys, GFP_KERNEL); 435 if (!dma_private) { 436 dev_err(dev, "can't allocate dma private data\n"); 437 return -ENOMEM; 438 } 439 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 440 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 441 else 442 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 443 444 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 445 dma_private->dma_channel = dma->channel; 446 dma_private->irq = dma->irq; 447 dma_private->substream = substream; 448 dma_private->ld_buf_phys = ld_buf_phys; 449 dma_private->dma_buf_phys = substream->dma_buffer.addr; 450 451 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 452 if (ret) { 453 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 454 dma_private->irq, ret); 455 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 456 dma_private, dma_private->ld_buf_phys); 457 return ret; 458 } 459 460 dma->assigned = 1; 461 462 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 463 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 464 runtime->private_data = dma_private; 465 466 /* Program the fixed DMA controller parameters */ 467 468 dma_channel = dma_private->dma_channel; 469 470 temp_link = dma_private->ld_buf_phys + 471 sizeof(struct fsl_dma_link_descriptor); 472 473 for (i = 0; i < NUM_DMA_LINKS; i++) { 474 dma_private->link[i].next = cpu_to_be64(temp_link); 475 476 temp_link += sizeof(struct fsl_dma_link_descriptor); 477 } 478 /* The last link descriptor points to the first */ 479 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 480 481 /* Tell the DMA controller where the first link descriptor is */ 482 out_be32(&dma_channel->clndar, 483 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 484 out_be32(&dma_channel->eclndar, 485 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 486 487 /* The manual says the BCR must be clear before enabling EMP */ 488 out_be32(&dma_channel->bcr, 0); 489 490 /* 491 * Program the mode register for interrupts, external master control, 492 * and source/destination hold. Also clear the Channel Abort bit. 493 */ 494 mr = in_be32(&dma_channel->mr) & 495 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 496 497 /* 498 * We want External Master Start and External Master Pause enabled, 499 * because the SSI is controlling the DMA controller. We want the DMA 500 * controller to be set up in advance, and then we signal only the SSI 501 * to start transferring. 502 * 503 * We want End-Of-Segment Interrupts enabled, because this will generate 504 * an interrupt at the end of each segment (each link descriptor 505 * represents one segment). Each DMA segment is the same thing as an 506 * ALSA period, so this is how we get an interrupt at the end of every 507 * period. 508 * 509 * We want Error Interrupt enabled, so that we can get an error if 510 * the DMA controller is mis-programmed somehow. 511 */ 512 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 513 CCSR_DMA_MR_EMS_EN; 514 515 /* For playback, we want the destination address to be held. For 516 capture, set the source address to be held. */ 517 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 518 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 519 520 out_be32(&dma_channel->mr, mr); 521 522 return 0; 523 } 524 525 /** 526 * fsl_dma_hw_params: continue initializing the DMA links 527 * 528 * This function obtains hardware parameters about the opened stream and 529 * programs the DMA controller accordingly. 530 * 531 * One drawback of big-endian is that when copying integers of different 532 * sizes to a fixed-sized register, the address to which the integer must be 533 * copied is dependent on the size of the integer. 534 * 535 * For example, if P is the address of a 32-bit register, and X is a 32-bit 536 * integer, then X should be copied to address P. However, if X is a 16-bit 537 * integer, then it should be copied to P+2. If X is an 8-bit register, 538 * then it should be copied to P+3. 539 * 540 * So for playback of 8-bit samples, the DMA controller must transfer single 541 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 542 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 543 * 544 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 545 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 546 * and 8 bytes at a time). So we do not support packed 24-bit samples. 547 * 24-bit data must be padded to 32 bits. 548 */ 549 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 550 struct snd_pcm_hw_params *hw_params) 551 { 552 struct snd_pcm_runtime *runtime = substream->runtime; 553 struct fsl_dma_private *dma_private = runtime->private_data; 554 struct snd_soc_pcm_runtime *rtd = substream->private_data; 555 struct device *dev = rtd->platform->dev; 556 557 /* Number of bits per sample */ 558 unsigned int sample_bits = 559 snd_pcm_format_physical_width(params_format(hw_params)); 560 561 /* Number of bytes per frame */ 562 unsigned int sample_bytes = sample_bits / 8; 563 564 /* Bus address of SSI STX register */ 565 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 566 567 /* Size of the DMA buffer, in bytes */ 568 size_t buffer_size = params_buffer_bytes(hw_params); 569 570 /* Number of bytes per period */ 571 size_t period_size = params_period_bytes(hw_params); 572 573 /* Pointer to next period */ 574 dma_addr_t temp_addr = substream->dma_buffer.addr; 575 576 /* Pointer to DMA controller */ 577 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 578 579 u32 mr; /* DMA Mode Register */ 580 581 unsigned int i; 582 583 /* Initialize our DMA tracking variables */ 584 dma_private->period_size = period_size; 585 dma_private->num_periods = params_periods(hw_params); 586 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 587 dma_private->dma_buf_next = dma_private->dma_buf_phys + 588 (NUM_DMA_LINKS * period_size); 589 590 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 591 /* This happens if the number of periods == NUM_DMA_LINKS */ 592 dma_private->dma_buf_next = dma_private->dma_buf_phys; 593 594 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 595 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 596 597 /* Due to a quirk of the SSI's STX register, the target address 598 * for the DMA operations depends on the sample size. So we calculate 599 * that offset here. While we're at it, also tell the DMA controller 600 * how much data to transfer per sample. 601 */ 602 switch (sample_bits) { 603 case 8: 604 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 605 ssi_sxx_phys += 3; 606 break; 607 case 16: 608 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 609 ssi_sxx_phys += 2; 610 break; 611 case 32: 612 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 613 break; 614 default: 615 /* We should never get here */ 616 dev_err(dev, "unsupported sample size %u\n", sample_bits); 617 return -EINVAL; 618 } 619 620 /* 621 * BWC determines how many bytes are sent/received before the DMA 622 * controller checks the SSI to see if it needs to stop. BWC should 623 * always be a multiple of the frame size, so that we always transmit 624 * whole frames. Each frame occupies two slots in the FIFO. The 625 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 626 * (MR[BWC] can only represent even powers of two). 627 * 628 * To simplify the process, we set BWC to the largest value that is 629 * less than or equal to the FIFO watermark. For playback, this ensures 630 * that we transfer the maximum amount without overrunning the FIFO. 631 * For capture, this ensures that we transfer the maximum amount without 632 * underrunning the FIFO. 633 * 634 * f = SSI FIFO depth 635 * w = SSI watermark value (which equals f - 2) 636 * b = DMA bandwidth count (in bytes) 637 * s = sample size (in bytes, which equals frame_size * 2) 638 * 639 * For playback, we never transmit more than the transmit FIFO 640 * watermark, otherwise we might write more data than the FIFO can hold. 641 * The watermark is equal to the FIFO depth minus two. 642 * 643 * For capture, two equations must hold: 644 * w > f - (b / s) 645 * w >= b / s 646 * 647 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 648 * b = s * w, which is equal to 649 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 650 */ 651 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 652 653 out_be32(&dma_channel->mr, mr); 654 655 for (i = 0; i < NUM_DMA_LINKS; i++) { 656 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 657 658 link->count = cpu_to_be32(period_size); 659 660 /* The snoop bit tells the DMA controller whether it should tell 661 * the ECM to snoop during a read or write to an address. For 662 * audio, we use DMA to transfer data between memory and an I/O 663 * device (the SSI's STX0 or SRX0 register). Snooping is only 664 * needed if there is a cache, so we need to snoop memory 665 * addresses only. For playback, that means we snoop the source 666 * but not the destination. For capture, we snoop the 667 * destination but not the source. 668 * 669 * Note that failing to snoop properly is unlikely to cause 670 * cache incoherency if the period size is larger than the 671 * size of L1 cache. This is because filling in one period will 672 * flush out the data for the previous period. So if you 673 * increased period_bytes_min to a large enough size, you might 674 * get more performance by not snooping, and you'll still be 675 * okay. You'll need to update fsl_dma_update_pointers() also. 676 */ 677 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 678 link->source_addr = cpu_to_be32(temp_addr); 679 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 680 upper_32_bits(temp_addr)); 681 682 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 683 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 684 upper_32_bits(ssi_sxx_phys)); 685 } else { 686 link->source_addr = cpu_to_be32(ssi_sxx_phys); 687 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 688 upper_32_bits(ssi_sxx_phys)); 689 690 link->dest_addr = cpu_to_be32(temp_addr); 691 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 692 upper_32_bits(temp_addr)); 693 } 694 695 temp_addr += period_size; 696 } 697 698 return 0; 699 } 700 701 /** 702 * fsl_dma_pointer: determine the current position of the DMA transfer 703 * 704 * This function is called by ALSA when ALSA wants to know where in the 705 * stream buffer the hardware currently is. 706 * 707 * For playback, the SAR register contains the physical address of the most 708 * recent DMA transfer. For capture, the value is in the DAR register. 709 * 710 * The base address of the buffer is stored in the source_addr field of the 711 * first link descriptor. 712 */ 713 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 714 { 715 struct snd_pcm_runtime *runtime = substream->runtime; 716 struct fsl_dma_private *dma_private = runtime->private_data; 717 struct snd_soc_pcm_runtime *rtd = substream->private_data; 718 struct device *dev = rtd->platform->dev; 719 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 720 dma_addr_t position; 721 snd_pcm_uframes_t frames; 722 723 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 724 * only have 32-bit DMA addresses. This function is typically called 725 * in interrupt context, so we need to optimize it. 726 */ 727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 728 position = in_be32(&dma_channel->sar); 729 #ifdef CONFIG_PHYS_64BIT 730 position |= (u64)(in_be32(&dma_channel->satr) & 731 CCSR_DMA_ATR_ESAD_MASK) << 32; 732 #endif 733 } else { 734 position = in_be32(&dma_channel->dar); 735 #ifdef CONFIG_PHYS_64BIT 736 position |= (u64)(in_be32(&dma_channel->datr) & 737 CCSR_DMA_ATR_ESAD_MASK) << 32; 738 #endif 739 } 740 741 /* 742 * When capture is started, the SSI immediately starts to fill its FIFO. 743 * This means that the DMA controller is not started until the FIFO is 744 * full. However, ALSA calls this function before that happens, when 745 * MR.DAR is still zero. In this case, just return zero to indicate 746 * that nothing has been received yet. 747 */ 748 if (!position) 749 return 0; 750 751 if ((position < dma_private->dma_buf_phys) || 752 (position > dma_private->dma_buf_end)) { 753 dev_err(dev, "dma pointer is out of range, halting stream\n"); 754 return SNDRV_PCM_POS_XRUN; 755 } 756 757 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 758 759 /* 760 * If the current address is just past the end of the buffer, wrap it 761 * around. 762 */ 763 if (frames == runtime->buffer_size) 764 frames = 0; 765 766 return frames; 767 } 768 769 /** 770 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 771 * 772 * Release the resources allocated in fsl_dma_hw_params() and de-program the 773 * registers. 774 * 775 * This function can be called multiple times. 776 */ 777 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 778 { 779 struct snd_pcm_runtime *runtime = substream->runtime; 780 struct fsl_dma_private *dma_private = runtime->private_data; 781 782 if (dma_private) { 783 struct ccsr_dma_channel __iomem *dma_channel; 784 785 dma_channel = dma_private->dma_channel; 786 787 /* Stop the DMA */ 788 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 789 out_be32(&dma_channel->mr, 0); 790 791 /* Reset all the other registers */ 792 out_be32(&dma_channel->sr, -1); 793 out_be32(&dma_channel->clndar, 0); 794 out_be32(&dma_channel->eclndar, 0); 795 out_be32(&dma_channel->satr, 0); 796 out_be32(&dma_channel->sar, 0); 797 out_be32(&dma_channel->datr, 0); 798 out_be32(&dma_channel->dar, 0); 799 out_be32(&dma_channel->bcr, 0); 800 out_be32(&dma_channel->nlndar, 0); 801 out_be32(&dma_channel->enlndar, 0); 802 } 803 804 return 0; 805 } 806 807 /** 808 * fsl_dma_close: close the stream. 809 */ 810 static int fsl_dma_close(struct snd_pcm_substream *substream) 811 { 812 struct snd_pcm_runtime *runtime = substream->runtime; 813 struct fsl_dma_private *dma_private = runtime->private_data; 814 struct snd_soc_pcm_runtime *rtd = substream->private_data; 815 struct device *dev = rtd->platform->dev; 816 struct dma_object *dma = 817 container_of(rtd->platform->driver, struct dma_object, dai); 818 819 if (dma_private) { 820 if (dma_private->irq) 821 free_irq(dma_private->irq, dma_private); 822 823 if (dma_private->ld_buf_phys) { 824 dma_unmap_single(dev, dma_private->ld_buf_phys, 825 sizeof(dma_private->link), 826 DMA_TO_DEVICE); 827 } 828 829 /* Deallocate the fsl_dma_private structure */ 830 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 831 dma_private, dma_private->ld_buf_phys); 832 substream->runtime->private_data = NULL; 833 } 834 835 dma->assigned = 0; 836 837 return 0; 838 } 839 840 /* 841 * Remove this PCM driver. 842 */ 843 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 844 { 845 struct snd_pcm_substream *substream; 846 unsigned int i; 847 848 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 849 substream = pcm->streams[i].substream; 850 if (substream) { 851 snd_dma_free_pages(&substream->dma_buffer); 852 substream->dma_buffer.area = NULL; 853 substream->dma_buffer.addr = 0; 854 } 855 } 856 } 857 858 /** 859 * find_ssi_node -- returns the SSI node that points to his DMA channel node 860 * 861 * Although this DMA driver attempts to operate independently of the other 862 * devices, it still needs to determine some information about the SSI device 863 * that it's working with. Unfortunately, the device tree does not contain 864 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 865 * other way. So we need to scan the device tree for SSI nodes until we find 866 * the one that points to the given DMA channel node. It's ugly, but at least 867 * it's contained in this one function. 868 */ 869 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 870 { 871 struct device_node *ssi_np, *np; 872 873 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 874 /* Check each DMA phandle to see if it points to us. We 875 * assume that device_node pointers are a valid comparison. 876 */ 877 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 878 if (np == dma_channel_np) 879 return ssi_np; 880 881 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 882 if (np == dma_channel_np) 883 return ssi_np; 884 } 885 886 return NULL; 887 } 888 889 static struct snd_pcm_ops fsl_dma_ops = { 890 .open = fsl_dma_open, 891 .close = fsl_dma_close, 892 .ioctl = snd_pcm_lib_ioctl, 893 .hw_params = fsl_dma_hw_params, 894 .hw_free = fsl_dma_hw_free, 895 .pointer = fsl_dma_pointer, 896 }; 897 898 static int __devinit fsl_soc_dma_probe(struct of_device *of_dev, 899 const struct of_device_id *match) 900 { 901 struct dma_object *dma; 902 struct device_node *np = of_dev->dev.of_node; 903 struct device_node *ssi_np; 904 struct resource res; 905 const uint32_t *iprop; 906 int ret; 907 908 /* Find the SSI node that points to us. */ 909 ssi_np = find_ssi_node(np); 910 if (!ssi_np) { 911 dev_err(&of_dev->dev, "cannot find parent SSI node\n"); 912 return -ENODEV; 913 } 914 915 ret = of_address_to_resource(ssi_np, 0, &res); 916 if (ret) { 917 dev_err(&of_dev->dev, "could not determine resources for %s\n", 918 ssi_np->full_name); 919 of_node_put(ssi_np); 920 return ret; 921 } 922 923 dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL); 924 if (!dma) { 925 dev_err(&of_dev->dev, "could not allocate dma object\n"); 926 of_node_put(ssi_np); 927 return -ENOMEM; 928 } 929 930 strcpy(dma->path, np->full_name); 931 dma->dai.ops = &fsl_dma_ops; 932 dma->dai.pcm_new = fsl_dma_new; 933 dma->dai.pcm_free = fsl_dma_free_dma_buffers; 934 935 /* Store the SSI-specific information that we need */ 936 dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0); 937 dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0); 938 939 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 940 if (iprop) 941 dma->ssi_fifo_depth = *iprop; 942 else 943 /* Older 8610 DTs didn't have the fifo-depth property */ 944 dma->ssi_fifo_depth = 8; 945 946 of_node_put(ssi_np); 947 948 ret = snd_soc_register_platform(&of_dev->dev, &dma->dai); 949 if (ret) { 950 dev_err(&of_dev->dev, "could not register platform\n"); 951 kfree(dma); 952 return ret; 953 } 954 955 dma->channel = of_iomap(np, 0); 956 dma->irq = irq_of_parse_and_map(np, 0); 957 958 dev_set_drvdata(&of_dev->dev, dma); 959 960 return 0; 961 } 962 963 static int __devexit fsl_soc_dma_remove(struct of_device *of_dev) 964 { 965 struct dma_object *dma = dev_get_drvdata(&of_dev->dev); 966 967 snd_soc_unregister_platform(&of_dev->dev); 968 iounmap(dma->channel); 969 irq_dispose_mapping(dma->irq); 970 kfree(dma); 971 972 return 0; 973 } 974 975 static const struct of_device_id fsl_soc_dma_ids[] = { 976 { .compatible = "fsl,ssi-dma-channel", }, 977 {} 978 }; 979 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 980 981 static struct of_platform_driver fsl_soc_dma_driver = { 982 .driver = { 983 .name = "fsl-pcm-audio", 984 .owner = THIS_MODULE, 985 .of_match_table = fsl_soc_dma_ids, 986 }, 987 .probe = fsl_soc_dma_probe, 988 .remove = __devexit_p(fsl_soc_dma_remove), 989 }; 990 991 static int __init fsl_soc_dma_init(void) 992 { 993 pr_info("Freescale Elo DMA ASoC PCM Driver\n"); 994 995 return of_register_platform_driver(&fsl_soc_dma_driver); 996 } 997 998 static void __exit fsl_soc_dma_exit(void) 999 { 1000 of_unregister_platform_driver(&fsl_soc_dma_driver); 1001 } 1002 1003 module_init(fsl_soc_dma_init); 1004 module_exit(fsl_soc_dma_exit); 1005 1006 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1007 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 1008 MODULE_LICENSE("GPL v2"); 1009