1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * This driver implements ASoC support for the Elo DMA controller, which is 13 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 14 * the PCM driver is what handles the DMA buffer. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/gfp.h> 24 #include <linux/of_platform.h> 25 #include <linux/list.h> 26 #include <linux/slab.h> 27 28 #include <sound/core.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 33 #include <asm/io.h> 34 35 #include "fsl_dma.h" 36 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 37 38 /* 39 * The formats that the DMA controller supports, which is anything 40 * that is 8, 16, or 32 bits. 41 */ 42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 43 SNDRV_PCM_FMTBIT_U8 | \ 44 SNDRV_PCM_FMTBIT_S16_LE | \ 45 SNDRV_PCM_FMTBIT_S16_BE | \ 46 SNDRV_PCM_FMTBIT_U16_LE | \ 47 SNDRV_PCM_FMTBIT_U16_BE | \ 48 SNDRV_PCM_FMTBIT_S24_LE | \ 49 SNDRV_PCM_FMTBIT_S24_BE | \ 50 SNDRV_PCM_FMTBIT_U24_LE | \ 51 SNDRV_PCM_FMTBIT_U24_BE | \ 52 SNDRV_PCM_FMTBIT_S32_LE | \ 53 SNDRV_PCM_FMTBIT_S32_BE | \ 54 SNDRV_PCM_FMTBIT_U32_LE | \ 55 SNDRV_PCM_FMTBIT_U32_BE) 56 57 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 58 SNDRV_PCM_RATE_CONTINUOUS) 59 60 struct dma_object { 61 struct snd_soc_platform_driver dai; 62 dma_addr_t ssi_stx_phys; 63 dma_addr_t ssi_srx_phys; 64 unsigned int ssi_fifo_depth; 65 struct ccsr_dma_channel __iomem *channel; 66 unsigned int irq; 67 bool assigned; 68 char path[1]; 69 }; 70 71 /* 72 * The number of DMA links to use. Two is the bare minimum, but if you 73 * have really small links you might need more. 74 */ 75 #define NUM_DMA_LINKS 2 76 77 /** fsl_dma_private: p-substream DMA data 78 * 79 * Each substream has a 1-to-1 association with a DMA channel. 80 * 81 * The link[] array is first because it needs to be aligned on a 32-byte 82 * boundary, so putting it first will ensure alignment without padding the 83 * structure. 84 * 85 * @link[]: array of link descriptors 86 * @dma_channel: pointer to the DMA channel's registers 87 * @irq: IRQ for this DMA channel 88 * @substream: pointer to the substream object, needed by the ISR 89 * @ssi_sxx_phys: bus address of the STX or SRX register to use 90 * @ld_buf_phys: physical address of the LD buffer 91 * @current_link: index into link[] of the link currently being processed 92 * @dma_buf_phys: physical address of the DMA buffer 93 * @dma_buf_next: physical address of the next period to process 94 * @dma_buf_end: physical address of the byte after the end of the DMA 95 * @buffer period_size: the size of a single period 96 * @num_periods: the number of periods in the DMA buffer 97 */ 98 struct fsl_dma_private { 99 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 100 struct ccsr_dma_channel __iomem *dma_channel; 101 unsigned int irq; 102 struct snd_pcm_substream *substream; 103 dma_addr_t ssi_sxx_phys; 104 unsigned int ssi_fifo_depth; 105 dma_addr_t ld_buf_phys; 106 unsigned int current_link; 107 dma_addr_t dma_buf_phys; 108 dma_addr_t dma_buf_next; 109 dma_addr_t dma_buf_end; 110 size_t period_size; 111 unsigned int num_periods; 112 }; 113 114 /** 115 * fsl_dma_hardare: define characteristics of the PCM hardware. 116 * 117 * The PCM hardware is the Freescale DMA controller. This structure defines 118 * the capabilities of that hardware. 119 * 120 * Since the sampling rate and data format are not controlled by the DMA 121 * controller, we specify no limits for those values. The only exception is 122 * period_bytes_min, which is set to a reasonably low value to prevent the 123 * DMA controller from generating too many interrupts per second. 124 * 125 * Since each link descriptor has a 32-bit byte count field, we set 126 * period_bytes_max to the largest 32-bit number. We also have no maximum 127 * number of periods. 128 * 129 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 130 * limitation in the SSI driver requires the sample rates for playback and 131 * capture to be the same. 132 */ 133 static const struct snd_pcm_hardware fsl_dma_hardware = { 134 135 .info = SNDRV_PCM_INFO_INTERLEAVED | 136 SNDRV_PCM_INFO_MMAP | 137 SNDRV_PCM_INFO_MMAP_VALID | 138 SNDRV_PCM_INFO_JOINT_DUPLEX | 139 SNDRV_PCM_INFO_PAUSE, 140 .formats = FSLDMA_PCM_FORMATS, 141 .rates = FSLDMA_PCM_RATES, 142 .rate_min = 5512, 143 .rate_max = 192000, 144 .period_bytes_min = 512, /* A reasonable limit */ 145 .period_bytes_max = (u32) -1, 146 .periods_min = NUM_DMA_LINKS, 147 .periods_max = (unsigned int) -1, 148 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 149 }; 150 151 /** 152 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 153 * 154 * This function should be called by the ISR whenever the DMA controller 155 * halts data transfer. 156 */ 157 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 158 { 159 unsigned long flags; 160 161 snd_pcm_stream_lock_irqsave(substream, flags); 162 163 if (snd_pcm_running(substream)) 164 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 165 166 snd_pcm_stream_unlock_irqrestore(substream, flags); 167 } 168 169 /** 170 * fsl_dma_update_pointers - update LD pointers to point to the next period 171 * 172 * As each period is completed, this function changes the the link 173 * descriptor pointers for that period to point to the next period. 174 */ 175 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 176 { 177 struct fsl_dma_link_descriptor *link = 178 &dma_private->link[dma_private->current_link]; 179 180 /* Update our link descriptors to point to the next period. On a 36-bit 181 * system, we also need to update the ESAD bits. We also set (keep) the 182 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 183 */ 184 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 185 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 186 #ifdef CONFIG_PHYS_64BIT 187 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 188 upper_32_bits(dma_private->dma_buf_next)); 189 #endif 190 } else { 191 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 192 #ifdef CONFIG_PHYS_64BIT 193 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 194 upper_32_bits(dma_private->dma_buf_next)); 195 #endif 196 } 197 198 /* Update our variables for next time */ 199 dma_private->dma_buf_next += dma_private->period_size; 200 201 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 202 dma_private->dma_buf_next = dma_private->dma_buf_phys; 203 204 if (++dma_private->current_link >= NUM_DMA_LINKS) 205 dma_private->current_link = 0; 206 } 207 208 /** 209 * fsl_dma_isr: interrupt handler for the DMA controller 210 * 211 * @irq: IRQ of the DMA channel 212 * @dev_id: pointer to the dma_private structure for this DMA channel 213 */ 214 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 215 { 216 struct fsl_dma_private *dma_private = dev_id; 217 struct snd_pcm_substream *substream = dma_private->substream; 218 struct snd_soc_pcm_runtime *rtd = substream->private_data; 219 struct device *dev = rtd->platform->dev; 220 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 221 irqreturn_t ret = IRQ_NONE; 222 u32 sr, sr2 = 0; 223 224 /* We got an interrupt, so read the status register to see what we 225 were interrupted for. 226 */ 227 sr = in_be32(&dma_channel->sr); 228 229 if (sr & CCSR_DMA_SR_TE) { 230 dev_err(dev, "dma transmit error\n"); 231 fsl_dma_abort_stream(substream); 232 sr2 |= CCSR_DMA_SR_TE; 233 ret = IRQ_HANDLED; 234 } 235 236 if (sr & CCSR_DMA_SR_CH) 237 ret = IRQ_HANDLED; 238 239 if (sr & CCSR_DMA_SR_PE) { 240 dev_err(dev, "dma programming error\n"); 241 fsl_dma_abort_stream(substream); 242 sr2 |= CCSR_DMA_SR_PE; 243 ret = IRQ_HANDLED; 244 } 245 246 if (sr & CCSR_DMA_SR_EOLNI) { 247 sr2 |= CCSR_DMA_SR_EOLNI; 248 ret = IRQ_HANDLED; 249 } 250 251 if (sr & CCSR_DMA_SR_CB) 252 ret = IRQ_HANDLED; 253 254 if (sr & CCSR_DMA_SR_EOSI) { 255 /* Tell ALSA we completed a period. */ 256 snd_pcm_period_elapsed(substream); 257 258 /* 259 * Update our link descriptors to point to the next period. We 260 * only need to do this if the number of periods is not equal to 261 * the number of links. 262 */ 263 if (dma_private->num_periods != NUM_DMA_LINKS) 264 fsl_dma_update_pointers(dma_private); 265 266 sr2 |= CCSR_DMA_SR_EOSI; 267 ret = IRQ_HANDLED; 268 } 269 270 if (sr & CCSR_DMA_SR_EOLSI) { 271 sr2 |= CCSR_DMA_SR_EOLSI; 272 ret = IRQ_HANDLED; 273 } 274 275 /* Clear the bits that we set */ 276 if (sr2) 277 out_be32(&dma_channel->sr, sr2); 278 279 return ret; 280 } 281 282 /** 283 * fsl_dma_new: initialize this PCM driver. 284 * 285 * This function is called when the codec driver calls snd_soc_new_pcms(), 286 * once for each .dai_link in the machine driver's snd_soc_card 287 * structure. 288 * 289 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 290 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 291 * is specified. Therefore, any DMA buffers we allocate will always be in low 292 * memory, but we support for 36-bit physical addresses anyway. 293 * 294 * Regardless of where the memory is actually allocated, since the device can 295 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 296 */ 297 static int fsl_dma_new(struct snd_soc_pcm_runtime *rtd) 298 { 299 struct snd_card *card = rtd->card->snd_card; 300 struct snd_soc_dai *dai = rtd->cpu_dai; 301 struct snd_pcm *pcm = rtd->pcm; 302 static u64 fsl_dma_dmamask = DMA_BIT_MASK(36); 303 int ret; 304 305 if (!card->dev->dma_mask) 306 card->dev->dma_mask = &fsl_dma_dmamask; 307 308 if (!card->dev->coherent_dma_mask) 309 card->dev->coherent_dma_mask = fsl_dma_dmamask; 310 311 /* Some codecs have separate DAIs for playback and capture, so we 312 * should allocate a DMA buffer only for the streams that are valid. 313 */ 314 315 if (pcm->streams[0].substream) { 316 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 317 fsl_dma_hardware.buffer_bytes_max, 318 &pcm->streams[0].substream->dma_buffer); 319 if (ret) { 320 dev_err(card->dev, "can't alloc playback dma buffer\n"); 321 return ret; 322 } 323 } 324 325 if (pcm->streams[1].substream) { 326 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 327 fsl_dma_hardware.buffer_bytes_max, 328 &pcm->streams[1].substream->dma_buffer); 329 if (ret) { 330 dev_err(card->dev, "can't alloc capture dma buffer\n"); 331 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 332 return ret; 333 } 334 } 335 336 return 0; 337 } 338 339 /** 340 * fsl_dma_open: open a new substream. 341 * 342 * Each substream has its own DMA buffer. 343 * 344 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 345 * descriptors that ping-pong from one period to the next. For example, if 346 * there are six periods and two link descriptors, this is how they look 347 * before playback starts: 348 * 349 * The last link descriptor 350 * ____________ points back to the first 351 * | | 352 * V | 353 * ___ ___ | 354 * | |->| |->| 355 * |___| |___| 356 * | | 357 * | | 358 * V V 359 * _________________________________________ 360 * | | | | | | | The DMA buffer is 361 * | | | | | | | divided into 6 parts 362 * |______|______|______|______|______|______| 363 * 364 * and here's how they look after the first period is finished playing: 365 * 366 * ____________ 367 * | | 368 * V | 369 * ___ ___ | 370 * | |->| |->| 371 * |___| |___| 372 * | | 373 * |______________ 374 * | | 375 * V V 376 * _________________________________________ 377 * | | | | | | | 378 * | | | | | | | 379 * |______|______|______|______|______|______| 380 * 381 * The first link descriptor now points to the third period. The DMA 382 * controller is currently playing the second period. When it finishes, it 383 * will jump back to the first descriptor and play the third period. 384 * 385 * There are four reasons we do this: 386 * 387 * 1. The only way to get the DMA controller to automatically restart the 388 * transfer when it gets to the end of the buffer is to use chaining 389 * mode. Basic direct mode doesn't offer that feature. 390 * 2. We need to receive an interrupt at the end of every period. The DMA 391 * controller can generate an interrupt at the end of every link transfer 392 * (aka segment). Making each period into a DMA segment will give us the 393 * interrupts we need. 394 * 3. By creating only two link descriptors, regardless of the number of 395 * periods, we do not need to reallocate the link descriptors if the 396 * number of periods changes. 397 * 4. All of the audio data is still stored in a single, contiguous DMA 398 * buffer, which is what ALSA expects. We're just dividing it into 399 * contiguous parts, and creating a link descriptor for each one. 400 */ 401 static int fsl_dma_open(struct snd_pcm_substream *substream) 402 { 403 struct snd_pcm_runtime *runtime = substream->runtime; 404 struct snd_soc_pcm_runtime *rtd = substream->private_data; 405 struct device *dev = rtd->platform->dev; 406 struct dma_object *dma = 407 container_of(rtd->platform->driver, struct dma_object, dai); 408 struct fsl_dma_private *dma_private; 409 struct ccsr_dma_channel __iomem *dma_channel; 410 dma_addr_t ld_buf_phys; 411 u64 temp_link; /* Pointer to next link descriptor */ 412 u32 mr; 413 unsigned int channel; 414 int ret = 0; 415 unsigned int i; 416 417 /* 418 * Reject any DMA buffer whose size is not a multiple of the period 419 * size. We need to make sure that the DMA buffer can be evenly divided 420 * into periods. 421 */ 422 ret = snd_pcm_hw_constraint_integer(runtime, 423 SNDRV_PCM_HW_PARAM_PERIODS); 424 if (ret < 0) { 425 dev_err(dev, "invalid buffer size\n"); 426 return ret; 427 } 428 429 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 430 431 if (dma->assigned) { 432 dev_err(dev, "dma channel already assigned\n"); 433 return -EBUSY; 434 } 435 436 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 437 &ld_buf_phys, GFP_KERNEL); 438 if (!dma_private) { 439 dev_err(dev, "can't allocate dma private data\n"); 440 return -ENOMEM; 441 } 442 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 443 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 444 else 445 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 446 447 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 448 dma_private->dma_channel = dma->channel; 449 dma_private->irq = dma->irq; 450 dma_private->substream = substream; 451 dma_private->ld_buf_phys = ld_buf_phys; 452 dma_private->dma_buf_phys = substream->dma_buffer.addr; 453 454 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 455 dma_private); 456 if (ret) { 457 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 458 dma_private->irq, ret); 459 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 460 dma_private, dma_private->ld_buf_phys); 461 return ret; 462 } 463 464 dma->assigned = 1; 465 466 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 467 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 468 runtime->private_data = dma_private; 469 470 /* Program the fixed DMA controller parameters */ 471 472 dma_channel = dma_private->dma_channel; 473 474 temp_link = dma_private->ld_buf_phys + 475 sizeof(struct fsl_dma_link_descriptor); 476 477 for (i = 0; i < NUM_DMA_LINKS; i++) { 478 dma_private->link[i].next = cpu_to_be64(temp_link); 479 480 temp_link += sizeof(struct fsl_dma_link_descriptor); 481 } 482 /* The last link descriptor points to the first */ 483 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 484 485 /* Tell the DMA controller where the first link descriptor is */ 486 out_be32(&dma_channel->clndar, 487 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 488 out_be32(&dma_channel->eclndar, 489 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 490 491 /* The manual says the BCR must be clear before enabling EMP */ 492 out_be32(&dma_channel->bcr, 0); 493 494 /* 495 * Program the mode register for interrupts, external master control, 496 * and source/destination hold. Also clear the Channel Abort bit. 497 */ 498 mr = in_be32(&dma_channel->mr) & 499 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 500 501 /* 502 * We want External Master Start and External Master Pause enabled, 503 * because the SSI is controlling the DMA controller. We want the DMA 504 * controller to be set up in advance, and then we signal only the SSI 505 * to start transferring. 506 * 507 * We want End-Of-Segment Interrupts enabled, because this will generate 508 * an interrupt at the end of each segment (each link descriptor 509 * represents one segment). Each DMA segment is the same thing as an 510 * ALSA period, so this is how we get an interrupt at the end of every 511 * period. 512 * 513 * We want Error Interrupt enabled, so that we can get an error if 514 * the DMA controller is mis-programmed somehow. 515 */ 516 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 517 CCSR_DMA_MR_EMS_EN; 518 519 /* For playback, we want the destination address to be held. For 520 capture, set the source address to be held. */ 521 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 522 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 523 524 out_be32(&dma_channel->mr, mr); 525 526 return 0; 527 } 528 529 /** 530 * fsl_dma_hw_params: continue initializing the DMA links 531 * 532 * This function obtains hardware parameters about the opened stream and 533 * programs the DMA controller accordingly. 534 * 535 * One drawback of big-endian is that when copying integers of different 536 * sizes to a fixed-sized register, the address to which the integer must be 537 * copied is dependent on the size of the integer. 538 * 539 * For example, if P is the address of a 32-bit register, and X is a 32-bit 540 * integer, then X should be copied to address P. However, if X is a 16-bit 541 * integer, then it should be copied to P+2. If X is an 8-bit register, 542 * then it should be copied to P+3. 543 * 544 * So for playback of 8-bit samples, the DMA controller must transfer single 545 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 546 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 547 * 548 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 549 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 550 * and 8 bytes at a time). So we do not support packed 24-bit samples. 551 * 24-bit data must be padded to 32 bits. 552 */ 553 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 554 struct snd_pcm_hw_params *hw_params) 555 { 556 struct snd_pcm_runtime *runtime = substream->runtime; 557 struct fsl_dma_private *dma_private = runtime->private_data; 558 struct snd_soc_pcm_runtime *rtd = substream->private_data; 559 struct device *dev = rtd->platform->dev; 560 561 /* Number of bits per sample */ 562 unsigned int sample_bits = 563 snd_pcm_format_physical_width(params_format(hw_params)); 564 565 /* Number of bytes per frame */ 566 unsigned int sample_bytes = sample_bits / 8; 567 568 /* Bus address of SSI STX register */ 569 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 570 571 /* Size of the DMA buffer, in bytes */ 572 size_t buffer_size = params_buffer_bytes(hw_params); 573 574 /* Number of bytes per period */ 575 size_t period_size = params_period_bytes(hw_params); 576 577 /* Pointer to next period */ 578 dma_addr_t temp_addr = substream->dma_buffer.addr; 579 580 /* Pointer to DMA controller */ 581 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 582 583 u32 mr; /* DMA Mode Register */ 584 585 unsigned int i; 586 587 /* Initialize our DMA tracking variables */ 588 dma_private->period_size = period_size; 589 dma_private->num_periods = params_periods(hw_params); 590 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 591 dma_private->dma_buf_next = dma_private->dma_buf_phys + 592 (NUM_DMA_LINKS * period_size); 593 594 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 595 /* This happens if the number of periods == NUM_DMA_LINKS */ 596 dma_private->dma_buf_next = dma_private->dma_buf_phys; 597 598 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 599 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 600 601 /* Due to a quirk of the SSI's STX register, the target address 602 * for the DMA operations depends on the sample size. So we calculate 603 * that offset here. While we're at it, also tell the DMA controller 604 * how much data to transfer per sample. 605 */ 606 switch (sample_bits) { 607 case 8: 608 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 609 ssi_sxx_phys += 3; 610 break; 611 case 16: 612 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 613 ssi_sxx_phys += 2; 614 break; 615 case 32: 616 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 617 break; 618 default: 619 /* We should never get here */ 620 dev_err(dev, "unsupported sample size %u\n", sample_bits); 621 return -EINVAL; 622 } 623 624 /* 625 * BWC determines how many bytes are sent/received before the DMA 626 * controller checks the SSI to see if it needs to stop. BWC should 627 * always be a multiple of the frame size, so that we always transmit 628 * whole frames. Each frame occupies two slots in the FIFO. The 629 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 630 * (MR[BWC] can only represent even powers of two). 631 * 632 * To simplify the process, we set BWC to the largest value that is 633 * less than or equal to the FIFO watermark. For playback, this ensures 634 * that we transfer the maximum amount without overrunning the FIFO. 635 * For capture, this ensures that we transfer the maximum amount without 636 * underrunning the FIFO. 637 * 638 * f = SSI FIFO depth 639 * w = SSI watermark value (which equals f - 2) 640 * b = DMA bandwidth count (in bytes) 641 * s = sample size (in bytes, which equals frame_size * 2) 642 * 643 * For playback, we never transmit more than the transmit FIFO 644 * watermark, otherwise we might write more data than the FIFO can hold. 645 * The watermark is equal to the FIFO depth minus two. 646 * 647 * For capture, two equations must hold: 648 * w > f - (b / s) 649 * w >= b / s 650 * 651 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 652 * b = s * w, which is equal to 653 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 654 */ 655 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 656 657 out_be32(&dma_channel->mr, mr); 658 659 for (i = 0; i < NUM_DMA_LINKS; i++) { 660 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 661 662 link->count = cpu_to_be32(period_size); 663 664 /* The snoop bit tells the DMA controller whether it should tell 665 * the ECM to snoop during a read or write to an address. For 666 * audio, we use DMA to transfer data between memory and an I/O 667 * device (the SSI's STX0 or SRX0 register). Snooping is only 668 * needed if there is a cache, so we need to snoop memory 669 * addresses only. For playback, that means we snoop the source 670 * but not the destination. For capture, we snoop the 671 * destination but not the source. 672 * 673 * Note that failing to snoop properly is unlikely to cause 674 * cache incoherency if the period size is larger than the 675 * size of L1 cache. This is because filling in one period will 676 * flush out the data for the previous period. So if you 677 * increased period_bytes_min to a large enough size, you might 678 * get more performance by not snooping, and you'll still be 679 * okay. You'll need to update fsl_dma_update_pointers() also. 680 */ 681 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 682 link->source_addr = cpu_to_be32(temp_addr); 683 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 684 upper_32_bits(temp_addr)); 685 686 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 687 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 688 upper_32_bits(ssi_sxx_phys)); 689 } else { 690 link->source_addr = cpu_to_be32(ssi_sxx_phys); 691 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 692 upper_32_bits(ssi_sxx_phys)); 693 694 link->dest_addr = cpu_to_be32(temp_addr); 695 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 696 upper_32_bits(temp_addr)); 697 } 698 699 temp_addr += period_size; 700 } 701 702 return 0; 703 } 704 705 /** 706 * fsl_dma_pointer: determine the current position of the DMA transfer 707 * 708 * This function is called by ALSA when ALSA wants to know where in the 709 * stream buffer the hardware currently is. 710 * 711 * For playback, the SAR register contains the physical address of the most 712 * recent DMA transfer. For capture, the value is in the DAR register. 713 * 714 * The base address of the buffer is stored in the source_addr field of the 715 * first link descriptor. 716 */ 717 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 718 { 719 struct snd_pcm_runtime *runtime = substream->runtime; 720 struct fsl_dma_private *dma_private = runtime->private_data; 721 struct snd_soc_pcm_runtime *rtd = substream->private_data; 722 struct device *dev = rtd->platform->dev; 723 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 724 dma_addr_t position; 725 snd_pcm_uframes_t frames; 726 727 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 728 * only have 32-bit DMA addresses. This function is typically called 729 * in interrupt context, so we need to optimize it. 730 */ 731 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 732 position = in_be32(&dma_channel->sar); 733 #ifdef CONFIG_PHYS_64BIT 734 position |= (u64)(in_be32(&dma_channel->satr) & 735 CCSR_DMA_ATR_ESAD_MASK) << 32; 736 #endif 737 } else { 738 position = in_be32(&dma_channel->dar); 739 #ifdef CONFIG_PHYS_64BIT 740 position |= (u64)(in_be32(&dma_channel->datr) & 741 CCSR_DMA_ATR_ESAD_MASK) << 32; 742 #endif 743 } 744 745 /* 746 * When capture is started, the SSI immediately starts to fill its FIFO. 747 * This means that the DMA controller is not started until the FIFO is 748 * full. However, ALSA calls this function before that happens, when 749 * MR.DAR is still zero. In this case, just return zero to indicate 750 * that nothing has been received yet. 751 */ 752 if (!position) 753 return 0; 754 755 if ((position < dma_private->dma_buf_phys) || 756 (position > dma_private->dma_buf_end)) { 757 dev_err(dev, "dma pointer is out of range, halting stream\n"); 758 return SNDRV_PCM_POS_XRUN; 759 } 760 761 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 762 763 /* 764 * If the current address is just past the end of the buffer, wrap it 765 * around. 766 */ 767 if (frames == runtime->buffer_size) 768 frames = 0; 769 770 return frames; 771 } 772 773 /** 774 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 775 * 776 * Release the resources allocated in fsl_dma_hw_params() and de-program the 777 * registers. 778 * 779 * This function can be called multiple times. 780 */ 781 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 782 { 783 struct snd_pcm_runtime *runtime = substream->runtime; 784 struct fsl_dma_private *dma_private = runtime->private_data; 785 786 if (dma_private) { 787 struct ccsr_dma_channel __iomem *dma_channel; 788 789 dma_channel = dma_private->dma_channel; 790 791 /* Stop the DMA */ 792 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 793 out_be32(&dma_channel->mr, 0); 794 795 /* Reset all the other registers */ 796 out_be32(&dma_channel->sr, -1); 797 out_be32(&dma_channel->clndar, 0); 798 out_be32(&dma_channel->eclndar, 0); 799 out_be32(&dma_channel->satr, 0); 800 out_be32(&dma_channel->sar, 0); 801 out_be32(&dma_channel->datr, 0); 802 out_be32(&dma_channel->dar, 0); 803 out_be32(&dma_channel->bcr, 0); 804 out_be32(&dma_channel->nlndar, 0); 805 out_be32(&dma_channel->enlndar, 0); 806 } 807 808 return 0; 809 } 810 811 /** 812 * fsl_dma_close: close the stream. 813 */ 814 static int fsl_dma_close(struct snd_pcm_substream *substream) 815 { 816 struct snd_pcm_runtime *runtime = substream->runtime; 817 struct fsl_dma_private *dma_private = runtime->private_data; 818 struct snd_soc_pcm_runtime *rtd = substream->private_data; 819 struct device *dev = rtd->platform->dev; 820 struct dma_object *dma = 821 container_of(rtd->platform->driver, struct dma_object, dai); 822 823 if (dma_private) { 824 if (dma_private->irq) 825 free_irq(dma_private->irq, dma_private); 826 827 if (dma_private->ld_buf_phys) { 828 dma_unmap_single(dev, dma_private->ld_buf_phys, 829 sizeof(dma_private->link), 830 DMA_TO_DEVICE); 831 } 832 833 /* Deallocate the fsl_dma_private structure */ 834 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 835 dma_private, dma_private->ld_buf_phys); 836 substream->runtime->private_data = NULL; 837 } 838 839 dma->assigned = 0; 840 841 return 0; 842 } 843 844 /* 845 * Remove this PCM driver. 846 */ 847 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 848 { 849 struct snd_pcm_substream *substream; 850 unsigned int i; 851 852 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 853 substream = pcm->streams[i].substream; 854 if (substream) { 855 snd_dma_free_pages(&substream->dma_buffer); 856 substream->dma_buffer.area = NULL; 857 substream->dma_buffer.addr = 0; 858 } 859 } 860 } 861 862 /** 863 * find_ssi_node -- returns the SSI node that points to his DMA channel node 864 * 865 * Although this DMA driver attempts to operate independently of the other 866 * devices, it still needs to determine some information about the SSI device 867 * that it's working with. Unfortunately, the device tree does not contain 868 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 869 * other way. So we need to scan the device tree for SSI nodes until we find 870 * the one that points to the given DMA channel node. It's ugly, but at least 871 * it's contained in this one function. 872 */ 873 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 874 { 875 struct device_node *ssi_np, *np; 876 877 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 878 /* Check each DMA phandle to see if it points to us. We 879 * assume that device_node pointers are a valid comparison. 880 */ 881 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 882 of_node_put(np); 883 if (np == dma_channel_np) 884 return ssi_np; 885 886 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 887 of_node_put(np); 888 if (np == dma_channel_np) 889 return ssi_np; 890 } 891 892 return NULL; 893 } 894 895 static struct snd_pcm_ops fsl_dma_ops = { 896 .open = fsl_dma_open, 897 .close = fsl_dma_close, 898 .ioctl = snd_pcm_lib_ioctl, 899 .hw_params = fsl_dma_hw_params, 900 .hw_free = fsl_dma_hw_free, 901 .pointer = fsl_dma_pointer, 902 }; 903 904 static int __devinit fsl_soc_dma_probe(struct platform_device *pdev) 905 { 906 struct dma_object *dma; 907 struct device_node *np = pdev->dev.of_node; 908 struct device_node *ssi_np; 909 struct resource res; 910 const uint32_t *iprop; 911 int ret; 912 913 /* Find the SSI node that points to us. */ 914 ssi_np = find_ssi_node(np); 915 if (!ssi_np) { 916 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 917 return -ENODEV; 918 } 919 920 ret = of_address_to_resource(ssi_np, 0, &res); 921 if (ret) { 922 dev_err(&pdev->dev, "could not determine resources for %s\n", 923 ssi_np->full_name); 924 of_node_put(ssi_np); 925 return ret; 926 } 927 928 dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL); 929 if (!dma) { 930 dev_err(&pdev->dev, "could not allocate dma object\n"); 931 of_node_put(ssi_np); 932 return -ENOMEM; 933 } 934 935 strcpy(dma->path, np->full_name); 936 dma->dai.ops = &fsl_dma_ops; 937 dma->dai.pcm_new = fsl_dma_new; 938 dma->dai.pcm_free = fsl_dma_free_dma_buffers; 939 940 /* Store the SSI-specific information that we need */ 941 dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0); 942 dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0); 943 944 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 945 if (iprop) 946 dma->ssi_fifo_depth = be32_to_cpup(iprop); 947 else 948 /* Older 8610 DTs didn't have the fifo-depth property */ 949 dma->ssi_fifo_depth = 8; 950 951 of_node_put(ssi_np); 952 953 ret = snd_soc_register_platform(&pdev->dev, &dma->dai); 954 if (ret) { 955 dev_err(&pdev->dev, "could not register platform\n"); 956 kfree(dma); 957 return ret; 958 } 959 960 dma->channel = of_iomap(np, 0); 961 dma->irq = irq_of_parse_and_map(np, 0); 962 963 dev_set_drvdata(&pdev->dev, dma); 964 965 return 0; 966 } 967 968 static int __devexit fsl_soc_dma_remove(struct platform_device *pdev) 969 { 970 struct dma_object *dma = dev_get_drvdata(&pdev->dev); 971 972 snd_soc_unregister_platform(&pdev->dev); 973 iounmap(dma->channel); 974 irq_dispose_mapping(dma->irq); 975 kfree(dma); 976 977 return 0; 978 } 979 980 static const struct of_device_id fsl_soc_dma_ids[] = { 981 { .compatible = "fsl,ssi-dma-channel", }, 982 {} 983 }; 984 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 985 986 static struct platform_driver fsl_soc_dma_driver = { 987 .driver = { 988 .name = "fsl-pcm-audio", 989 .owner = THIS_MODULE, 990 .of_match_table = fsl_soc_dma_ids, 991 }, 992 .probe = fsl_soc_dma_probe, 993 .remove = __devexit_p(fsl_soc_dma_remove), 994 }; 995 996 static int __init fsl_soc_dma_init(void) 997 { 998 pr_info("Freescale Elo DMA ASoC PCM Driver\n"); 999 1000 return platform_driver_register(&fsl_soc_dma_driver); 1001 } 1002 1003 static void __exit fsl_soc_dma_exit(void) 1004 { 1005 platform_driver_unregister(&fsl_soc_dma_driver); 1006 } 1007 1008 module_init(fsl_soc_dma_init); 1009 module_exit(fsl_soc_dma_exit); 1010 1011 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1012 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 1013 MODULE_LICENSE("GPL v2"); 1014