1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale DMA ALSA SoC PCM driver 4 // 5 // Author: Timur Tabi <timur@freescale.com> 6 // 7 // Copyright 2007-2010 Freescale Semiconductor, Inc. 8 // 9 // This driver implements ASoC support for the Elo DMA controller, which is 10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 11 // the PCM driver is what handles the DMA buffer. 12 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/delay.h> 19 #include <linux/gfp.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/list.h> 24 #include <linux/slab.h> 25 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 31 #include <asm/io.h> 32 33 #include "fsl_dma.h" 34 #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ 35 36 #define DRV_NAME "fsl_dma" 37 38 /* 39 * The formats that the DMA controller supports, which is anything 40 * that is 8, 16, or 32 bits. 41 */ 42 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 43 SNDRV_PCM_FMTBIT_U8 | \ 44 SNDRV_PCM_FMTBIT_S16_LE | \ 45 SNDRV_PCM_FMTBIT_S16_BE | \ 46 SNDRV_PCM_FMTBIT_U16_LE | \ 47 SNDRV_PCM_FMTBIT_U16_BE | \ 48 SNDRV_PCM_FMTBIT_S24_LE | \ 49 SNDRV_PCM_FMTBIT_S24_BE | \ 50 SNDRV_PCM_FMTBIT_U24_LE | \ 51 SNDRV_PCM_FMTBIT_U24_BE | \ 52 SNDRV_PCM_FMTBIT_S32_LE | \ 53 SNDRV_PCM_FMTBIT_S32_BE | \ 54 SNDRV_PCM_FMTBIT_U32_LE | \ 55 SNDRV_PCM_FMTBIT_U32_BE) 56 struct dma_object { 57 struct snd_soc_component_driver dai; 58 dma_addr_t ssi_stx_phys; 59 dma_addr_t ssi_srx_phys; 60 unsigned int ssi_fifo_depth; 61 struct ccsr_dma_channel __iomem *channel; 62 unsigned int irq; 63 bool assigned; 64 }; 65 66 /* 67 * The number of DMA links to use. Two is the bare minimum, but if you 68 * have really small links you might need more. 69 */ 70 #define NUM_DMA_LINKS 2 71 72 /** fsl_dma_private: p-substream DMA data 73 * 74 * Each substream has a 1-to-1 association with a DMA channel. 75 * 76 * The link[] array is first because it needs to be aligned on a 32-byte 77 * boundary, so putting it first will ensure alignment without padding the 78 * structure. 79 * 80 * @link[]: array of link descriptors 81 * @dma_channel: pointer to the DMA channel's registers 82 * @irq: IRQ for this DMA channel 83 * @substream: pointer to the substream object, needed by the ISR 84 * @ssi_sxx_phys: bus address of the STX or SRX register to use 85 * @ld_buf_phys: physical address of the LD buffer 86 * @current_link: index into link[] of the link currently being processed 87 * @dma_buf_phys: physical address of the DMA buffer 88 * @dma_buf_next: physical address of the next period to process 89 * @dma_buf_end: physical address of the byte after the end of the DMA 90 * @buffer period_size: the size of a single period 91 * @num_periods: the number of periods in the DMA buffer 92 */ 93 struct fsl_dma_private { 94 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 95 struct ccsr_dma_channel __iomem *dma_channel; 96 unsigned int irq; 97 struct snd_pcm_substream *substream; 98 dma_addr_t ssi_sxx_phys; 99 unsigned int ssi_fifo_depth; 100 dma_addr_t ld_buf_phys; 101 unsigned int current_link; 102 dma_addr_t dma_buf_phys; 103 dma_addr_t dma_buf_next; 104 dma_addr_t dma_buf_end; 105 size_t period_size; 106 unsigned int num_periods; 107 }; 108 109 /** 110 * fsl_dma_hardare: define characteristics of the PCM hardware. 111 * 112 * The PCM hardware is the Freescale DMA controller. This structure defines 113 * the capabilities of that hardware. 114 * 115 * Since the sampling rate and data format are not controlled by the DMA 116 * controller, we specify no limits for those values. The only exception is 117 * period_bytes_min, which is set to a reasonably low value to prevent the 118 * DMA controller from generating too many interrupts per second. 119 * 120 * Since each link descriptor has a 32-bit byte count field, we set 121 * period_bytes_max to the largest 32-bit number. We also have no maximum 122 * number of periods. 123 * 124 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a 125 * limitation in the SSI driver requires the sample rates for playback and 126 * capture to be the same. 127 */ 128 static const struct snd_pcm_hardware fsl_dma_hardware = { 129 130 .info = SNDRV_PCM_INFO_INTERLEAVED | 131 SNDRV_PCM_INFO_MMAP | 132 SNDRV_PCM_INFO_MMAP_VALID | 133 SNDRV_PCM_INFO_JOINT_DUPLEX | 134 SNDRV_PCM_INFO_PAUSE, 135 .formats = FSLDMA_PCM_FORMATS, 136 .period_bytes_min = 512, /* A reasonable limit */ 137 .period_bytes_max = (u32) -1, 138 .periods_min = NUM_DMA_LINKS, 139 .periods_max = (unsigned int) -1, 140 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 141 }; 142 143 /** 144 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 145 * 146 * This function should be called by the ISR whenever the DMA controller 147 * halts data transfer. 148 */ 149 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 150 { 151 snd_pcm_stop_xrun(substream); 152 } 153 154 /** 155 * fsl_dma_update_pointers - update LD pointers to point to the next period 156 * 157 * As each period is completed, this function changes the the link 158 * descriptor pointers for that period to point to the next period. 159 */ 160 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 161 { 162 struct fsl_dma_link_descriptor *link = 163 &dma_private->link[dma_private->current_link]; 164 165 /* Update our link descriptors to point to the next period. On a 36-bit 166 * system, we also need to update the ESAD bits. We also set (keep) the 167 * snoop bits. See the comments in fsl_dma_hw_params() about snooping. 168 */ 169 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 170 link->source_addr = cpu_to_be32(dma_private->dma_buf_next); 171 #ifdef CONFIG_PHYS_64BIT 172 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 173 upper_32_bits(dma_private->dma_buf_next)); 174 #endif 175 } else { 176 link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); 177 #ifdef CONFIG_PHYS_64BIT 178 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 179 upper_32_bits(dma_private->dma_buf_next)); 180 #endif 181 } 182 183 /* Update our variables for next time */ 184 dma_private->dma_buf_next += dma_private->period_size; 185 186 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 187 dma_private->dma_buf_next = dma_private->dma_buf_phys; 188 189 if (++dma_private->current_link >= NUM_DMA_LINKS) 190 dma_private->current_link = 0; 191 } 192 193 /** 194 * fsl_dma_isr: interrupt handler for the DMA controller 195 * 196 * @irq: IRQ of the DMA channel 197 * @dev_id: pointer to the dma_private structure for this DMA channel 198 */ 199 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 200 { 201 struct fsl_dma_private *dma_private = dev_id; 202 struct snd_pcm_substream *substream = dma_private->substream; 203 struct snd_soc_pcm_runtime *rtd = substream->private_data; 204 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); 205 struct device *dev = component->dev; 206 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 207 irqreturn_t ret = IRQ_NONE; 208 u32 sr, sr2 = 0; 209 210 /* We got an interrupt, so read the status register to see what we 211 were interrupted for. 212 */ 213 sr = in_be32(&dma_channel->sr); 214 215 if (sr & CCSR_DMA_SR_TE) { 216 dev_err(dev, "dma transmit error\n"); 217 fsl_dma_abort_stream(substream); 218 sr2 |= CCSR_DMA_SR_TE; 219 ret = IRQ_HANDLED; 220 } 221 222 if (sr & CCSR_DMA_SR_CH) 223 ret = IRQ_HANDLED; 224 225 if (sr & CCSR_DMA_SR_PE) { 226 dev_err(dev, "dma programming error\n"); 227 fsl_dma_abort_stream(substream); 228 sr2 |= CCSR_DMA_SR_PE; 229 ret = IRQ_HANDLED; 230 } 231 232 if (sr & CCSR_DMA_SR_EOLNI) { 233 sr2 |= CCSR_DMA_SR_EOLNI; 234 ret = IRQ_HANDLED; 235 } 236 237 if (sr & CCSR_DMA_SR_CB) 238 ret = IRQ_HANDLED; 239 240 if (sr & CCSR_DMA_SR_EOSI) { 241 /* Tell ALSA we completed a period. */ 242 snd_pcm_period_elapsed(substream); 243 244 /* 245 * Update our link descriptors to point to the next period. We 246 * only need to do this if the number of periods is not equal to 247 * the number of links. 248 */ 249 if (dma_private->num_periods != NUM_DMA_LINKS) 250 fsl_dma_update_pointers(dma_private); 251 252 sr2 |= CCSR_DMA_SR_EOSI; 253 ret = IRQ_HANDLED; 254 } 255 256 if (sr & CCSR_DMA_SR_EOLSI) { 257 sr2 |= CCSR_DMA_SR_EOLSI; 258 ret = IRQ_HANDLED; 259 } 260 261 /* Clear the bits that we set */ 262 if (sr2) 263 out_be32(&dma_channel->sr, sr2); 264 265 return ret; 266 } 267 268 /** 269 * fsl_dma_new: initialize this PCM driver. 270 * 271 * This function is called when the codec driver calls snd_soc_new_pcms(), 272 * once for each .dai_link in the machine driver's snd_soc_card 273 * structure. 274 * 275 * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which 276 * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM 277 * is specified. Therefore, any DMA buffers we allocate will always be in low 278 * memory, but we support for 36-bit physical addresses anyway. 279 * 280 * Regardless of where the memory is actually allocated, since the device can 281 * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. 282 */ 283 static int fsl_dma_new(struct snd_soc_component *component, 284 struct snd_soc_pcm_runtime *rtd) 285 { 286 struct snd_card *card = rtd->card->snd_card; 287 struct snd_pcm *pcm = rtd->pcm; 288 int ret; 289 290 ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36)); 291 if (ret) 292 return ret; 293 294 /* Some codecs have separate DAIs for playback and capture, so we 295 * should allocate a DMA buffer only for the streams that are valid. 296 */ 297 298 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { 299 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 300 fsl_dma_hardware.buffer_bytes_max, 301 &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 302 if (ret) { 303 dev_err(card->dev, "can't alloc playback dma buffer\n"); 304 return ret; 305 } 306 } 307 308 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { 309 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, 310 fsl_dma_hardware.buffer_bytes_max, 311 &pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->dma_buffer); 312 if (ret) { 313 dev_err(card->dev, "can't alloc capture dma buffer\n"); 314 snd_dma_free_pages(&pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->dma_buffer); 315 return ret; 316 } 317 } 318 319 return 0; 320 } 321 322 /** 323 * fsl_dma_open: open a new substream. 324 * 325 * Each substream has its own DMA buffer. 326 * 327 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 328 * descriptors that ping-pong from one period to the next. For example, if 329 * there are six periods and two link descriptors, this is how they look 330 * before playback starts: 331 * 332 * The last link descriptor 333 * ____________ points back to the first 334 * | | 335 * V | 336 * ___ ___ | 337 * | |->| |->| 338 * |___| |___| 339 * | | 340 * | | 341 * V V 342 * _________________________________________ 343 * | | | | | | | The DMA buffer is 344 * | | | | | | | divided into 6 parts 345 * |______|______|______|______|______|______| 346 * 347 * and here's how they look after the first period is finished playing: 348 * 349 * ____________ 350 * | | 351 * V | 352 * ___ ___ | 353 * | |->| |->| 354 * |___| |___| 355 * | | 356 * |______________ 357 * | | 358 * V V 359 * _________________________________________ 360 * | | | | | | | 361 * | | | | | | | 362 * |______|______|______|______|______|______| 363 * 364 * The first link descriptor now points to the third period. The DMA 365 * controller is currently playing the second period. When it finishes, it 366 * will jump back to the first descriptor and play the third period. 367 * 368 * There are four reasons we do this: 369 * 370 * 1. The only way to get the DMA controller to automatically restart the 371 * transfer when it gets to the end of the buffer is to use chaining 372 * mode. Basic direct mode doesn't offer that feature. 373 * 2. We need to receive an interrupt at the end of every period. The DMA 374 * controller can generate an interrupt at the end of every link transfer 375 * (aka segment). Making each period into a DMA segment will give us the 376 * interrupts we need. 377 * 3. By creating only two link descriptors, regardless of the number of 378 * periods, we do not need to reallocate the link descriptors if the 379 * number of periods changes. 380 * 4. All of the audio data is still stored in a single, contiguous DMA 381 * buffer, which is what ALSA expects. We're just dividing it into 382 * contiguous parts, and creating a link descriptor for each one. 383 */ 384 static int fsl_dma_open(struct snd_soc_component *component, 385 struct snd_pcm_substream *substream) 386 { 387 struct snd_pcm_runtime *runtime = substream->runtime; 388 struct device *dev = component->dev; 389 struct dma_object *dma = 390 container_of(component->driver, struct dma_object, dai); 391 struct fsl_dma_private *dma_private; 392 struct ccsr_dma_channel __iomem *dma_channel; 393 dma_addr_t ld_buf_phys; 394 u64 temp_link; /* Pointer to next link descriptor */ 395 u32 mr; 396 unsigned int channel; 397 int ret = 0; 398 unsigned int i; 399 400 /* 401 * Reject any DMA buffer whose size is not a multiple of the period 402 * size. We need to make sure that the DMA buffer can be evenly divided 403 * into periods. 404 */ 405 ret = snd_pcm_hw_constraint_integer(runtime, 406 SNDRV_PCM_HW_PARAM_PERIODS); 407 if (ret < 0) { 408 dev_err(dev, "invalid buffer size\n"); 409 return ret; 410 } 411 412 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 413 414 if (dma->assigned) { 415 dev_err(dev, "dma channel already assigned\n"); 416 return -EBUSY; 417 } 418 419 dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), 420 &ld_buf_phys, GFP_KERNEL); 421 if (!dma_private) { 422 dev_err(dev, "can't allocate dma private data\n"); 423 return -ENOMEM; 424 } 425 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 426 dma_private->ssi_sxx_phys = dma->ssi_stx_phys; 427 else 428 dma_private->ssi_sxx_phys = dma->ssi_srx_phys; 429 430 dma_private->ssi_fifo_depth = dma->ssi_fifo_depth; 431 dma_private->dma_channel = dma->channel; 432 dma_private->irq = dma->irq; 433 dma_private->substream = substream; 434 dma_private->ld_buf_phys = ld_buf_phys; 435 dma_private->dma_buf_phys = substream->dma_buffer.addr; 436 437 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio", 438 dma_private); 439 if (ret) { 440 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 441 dma_private->irq, ret); 442 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 443 dma_private, dma_private->ld_buf_phys); 444 return ret; 445 } 446 447 dma->assigned = true; 448 449 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 450 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 451 runtime->private_data = dma_private; 452 453 /* Program the fixed DMA controller parameters */ 454 455 dma_channel = dma_private->dma_channel; 456 457 temp_link = dma_private->ld_buf_phys + 458 sizeof(struct fsl_dma_link_descriptor); 459 460 for (i = 0; i < NUM_DMA_LINKS; i++) { 461 dma_private->link[i].next = cpu_to_be64(temp_link); 462 463 temp_link += sizeof(struct fsl_dma_link_descriptor); 464 } 465 /* The last link descriptor points to the first */ 466 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 467 468 /* Tell the DMA controller where the first link descriptor is */ 469 out_be32(&dma_channel->clndar, 470 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 471 out_be32(&dma_channel->eclndar, 472 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 473 474 /* The manual says the BCR must be clear before enabling EMP */ 475 out_be32(&dma_channel->bcr, 0); 476 477 /* 478 * Program the mode register for interrupts, external master control, 479 * and source/destination hold. Also clear the Channel Abort bit. 480 */ 481 mr = in_be32(&dma_channel->mr) & 482 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 483 484 /* 485 * We want External Master Start and External Master Pause enabled, 486 * because the SSI is controlling the DMA controller. We want the DMA 487 * controller to be set up in advance, and then we signal only the SSI 488 * to start transferring. 489 * 490 * We want End-Of-Segment Interrupts enabled, because this will generate 491 * an interrupt at the end of each segment (each link descriptor 492 * represents one segment). Each DMA segment is the same thing as an 493 * ALSA period, so this is how we get an interrupt at the end of every 494 * period. 495 * 496 * We want Error Interrupt enabled, so that we can get an error if 497 * the DMA controller is mis-programmed somehow. 498 */ 499 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 500 CCSR_DMA_MR_EMS_EN; 501 502 /* For playback, we want the destination address to be held. For 503 capture, set the source address to be held. */ 504 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 505 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 506 507 out_be32(&dma_channel->mr, mr); 508 509 return 0; 510 } 511 512 /** 513 * fsl_dma_hw_params: continue initializing the DMA links 514 * 515 * This function obtains hardware parameters about the opened stream and 516 * programs the DMA controller accordingly. 517 * 518 * One drawback of big-endian is that when copying integers of different 519 * sizes to a fixed-sized register, the address to which the integer must be 520 * copied is dependent on the size of the integer. 521 * 522 * For example, if P is the address of a 32-bit register, and X is a 32-bit 523 * integer, then X should be copied to address P. However, if X is a 16-bit 524 * integer, then it should be copied to P+2. If X is an 8-bit register, 525 * then it should be copied to P+3. 526 * 527 * So for playback of 8-bit samples, the DMA controller must transfer single 528 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 529 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 530 * 531 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 532 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 533 * and 8 bytes at a time). So we do not support packed 24-bit samples. 534 * 24-bit data must be padded to 32 bits. 535 */ 536 static int fsl_dma_hw_params(struct snd_soc_component *component, 537 struct snd_pcm_substream *substream, 538 struct snd_pcm_hw_params *hw_params) 539 { 540 struct snd_pcm_runtime *runtime = substream->runtime; 541 struct fsl_dma_private *dma_private = runtime->private_data; 542 struct device *dev = component->dev; 543 544 /* Number of bits per sample */ 545 unsigned int sample_bits = 546 snd_pcm_format_physical_width(params_format(hw_params)); 547 548 /* Number of bytes per frame */ 549 unsigned int sample_bytes = sample_bits / 8; 550 551 /* Bus address of SSI STX register */ 552 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; 553 554 /* Size of the DMA buffer, in bytes */ 555 size_t buffer_size = params_buffer_bytes(hw_params); 556 557 /* Number of bytes per period */ 558 size_t period_size = params_period_bytes(hw_params); 559 560 /* Pointer to next period */ 561 dma_addr_t temp_addr = substream->dma_buffer.addr; 562 563 /* Pointer to DMA controller */ 564 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 565 566 u32 mr; /* DMA Mode Register */ 567 568 unsigned int i; 569 570 /* Initialize our DMA tracking variables */ 571 dma_private->period_size = period_size; 572 dma_private->num_periods = params_periods(hw_params); 573 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 574 dma_private->dma_buf_next = dma_private->dma_buf_phys + 575 (NUM_DMA_LINKS * period_size); 576 577 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 578 /* This happens if the number of periods == NUM_DMA_LINKS */ 579 dma_private->dma_buf_next = dma_private->dma_buf_phys; 580 581 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 582 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 583 584 /* Due to a quirk of the SSI's STX register, the target address 585 * for the DMA operations depends on the sample size. So we calculate 586 * that offset here. While we're at it, also tell the DMA controller 587 * how much data to transfer per sample. 588 */ 589 switch (sample_bits) { 590 case 8: 591 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 592 ssi_sxx_phys += 3; 593 break; 594 case 16: 595 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 596 ssi_sxx_phys += 2; 597 break; 598 case 32: 599 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 600 break; 601 default: 602 /* We should never get here */ 603 dev_err(dev, "unsupported sample size %u\n", sample_bits); 604 return -EINVAL; 605 } 606 607 /* 608 * BWC determines how many bytes are sent/received before the DMA 609 * controller checks the SSI to see if it needs to stop. BWC should 610 * always be a multiple of the frame size, so that we always transmit 611 * whole frames. Each frame occupies two slots in the FIFO. The 612 * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two 613 * (MR[BWC] can only represent even powers of two). 614 * 615 * To simplify the process, we set BWC to the largest value that is 616 * less than or equal to the FIFO watermark. For playback, this ensures 617 * that we transfer the maximum amount without overrunning the FIFO. 618 * For capture, this ensures that we transfer the maximum amount without 619 * underrunning the FIFO. 620 * 621 * f = SSI FIFO depth 622 * w = SSI watermark value (which equals f - 2) 623 * b = DMA bandwidth count (in bytes) 624 * s = sample size (in bytes, which equals frame_size * 2) 625 * 626 * For playback, we never transmit more than the transmit FIFO 627 * watermark, otherwise we might write more data than the FIFO can hold. 628 * The watermark is equal to the FIFO depth minus two. 629 * 630 * For capture, two equations must hold: 631 * w > f - (b / s) 632 * w >= b / s 633 * 634 * So, b > 2 * s, but b must also be <= s * w. To simplify, we set 635 * b = s * w, which is equal to 636 * (dma_private->ssi_fifo_depth - 2) * sample_bytes. 637 */ 638 mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes); 639 640 out_be32(&dma_channel->mr, mr); 641 642 for (i = 0; i < NUM_DMA_LINKS; i++) { 643 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 644 645 link->count = cpu_to_be32(period_size); 646 647 /* The snoop bit tells the DMA controller whether it should tell 648 * the ECM to snoop during a read or write to an address. For 649 * audio, we use DMA to transfer data between memory and an I/O 650 * device (the SSI's STX0 or SRX0 register). Snooping is only 651 * needed if there is a cache, so we need to snoop memory 652 * addresses only. For playback, that means we snoop the source 653 * but not the destination. For capture, we snoop the 654 * destination but not the source. 655 * 656 * Note that failing to snoop properly is unlikely to cause 657 * cache incoherency if the period size is larger than the 658 * size of L1 cache. This is because filling in one period will 659 * flush out the data for the previous period. So if you 660 * increased period_bytes_min to a large enough size, you might 661 * get more performance by not snooping, and you'll still be 662 * okay. You'll need to update fsl_dma_update_pointers() also. 663 */ 664 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 665 link->source_addr = cpu_to_be32(temp_addr); 666 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 667 upper_32_bits(temp_addr)); 668 669 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 670 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 671 upper_32_bits(ssi_sxx_phys)); 672 } else { 673 link->source_addr = cpu_to_be32(ssi_sxx_phys); 674 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | 675 upper_32_bits(ssi_sxx_phys)); 676 677 link->dest_addr = cpu_to_be32(temp_addr); 678 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | 679 upper_32_bits(temp_addr)); 680 } 681 682 temp_addr += period_size; 683 } 684 685 return 0; 686 } 687 688 /** 689 * fsl_dma_pointer: determine the current position of the DMA transfer 690 * 691 * This function is called by ALSA when ALSA wants to know where in the 692 * stream buffer the hardware currently is. 693 * 694 * For playback, the SAR register contains the physical address of the most 695 * recent DMA transfer. For capture, the value is in the DAR register. 696 * 697 * The base address of the buffer is stored in the source_addr field of the 698 * first link descriptor. 699 */ 700 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component, 701 struct snd_pcm_substream *substream) 702 { 703 struct snd_pcm_runtime *runtime = substream->runtime; 704 struct fsl_dma_private *dma_private = runtime->private_data; 705 struct device *dev = component->dev; 706 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 707 dma_addr_t position; 708 snd_pcm_uframes_t frames; 709 710 /* Obtain the current DMA pointer, but don't read the ESAD bits if we 711 * only have 32-bit DMA addresses. This function is typically called 712 * in interrupt context, so we need to optimize it. 713 */ 714 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 715 position = in_be32(&dma_channel->sar); 716 #ifdef CONFIG_PHYS_64BIT 717 position |= (u64)(in_be32(&dma_channel->satr) & 718 CCSR_DMA_ATR_ESAD_MASK) << 32; 719 #endif 720 } else { 721 position = in_be32(&dma_channel->dar); 722 #ifdef CONFIG_PHYS_64BIT 723 position |= (u64)(in_be32(&dma_channel->datr) & 724 CCSR_DMA_ATR_ESAD_MASK) << 32; 725 #endif 726 } 727 728 /* 729 * When capture is started, the SSI immediately starts to fill its FIFO. 730 * This means that the DMA controller is not started until the FIFO is 731 * full. However, ALSA calls this function before that happens, when 732 * MR.DAR is still zero. In this case, just return zero to indicate 733 * that nothing has been received yet. 734 */ 735 if (!position) 736 return 0; 737 738 if ((position < dma_private->dma_buf_phys) || 739 (position > dma_private->dma_buf_end)) { 740 dev_err(dev, "dma pointer is out of range, halting stream\n"); 741 return SNDRV_PCM_POS_XRUN; 742 } 743 744 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 745 746 /* 747 * If the current address is just past the end of the buffer, wrap it 748 * around. 749 */ 750 if (frames == runtime->buffer_size) 751 frames = 0; 752 753 return frames; 754 } 755 756 /** 757 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 758 * 759 * Release the resources allocated in fsl_dma_hw_params() and de-program the 760 * registers. 761 * 762 * This function can be called multiple times. 763 */ 764 static int fsl_dma_hw_free(struct snd_soc_component *component, 765 struct snd_pcm_substream *substream) 766 { 767 struct snd_pcm_runtime *runtime = substream->runtime; 768 struct fsl_dma_private *dma_private = runtime->private_data; 769 770 if (dma_private) { 771 struct ccsr_dma_channel __iomem *dma_channel; 772 773 dma_channel = dma_private->dma_channel; 774 775 /* Stop the DMA */ 776 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 777 out_be32(&dma_channel->mr, 0); 778 779 /* Reset all the other registers */ 780 out_be32(&dma_channel->sr, -1); 781 out_be32(&dma_channel->clndar, 0); 782 out_be32(&dma_channel->eclndar, 0); 783 out_be32(&dma_channel->satr, 0); 784 out_be32(&dma_channel->sar, 0); 785 out_be32(&dma_channel->datr, 0); 786 out_be32(&dma_channel->dar, 0); 787 out_be32(&dma_channel->bcr, 0); 788 out_be32(&dma_channel->nlndar, 0); 789 out_be32(&dma_channel->enlndar, 0); 790 } 791 792 return 0; 793 } 794 795 /** 796 * fsl_dma_close: close the stream. 797 */ 798 static int fsl_dma_close(struct snd_soc_component *component, 799 struct snd_pcm_substream *substream) 800 { 801 struct snd_pcm_runtime *runtime = substream->runtime; 802 struct fsl_dma_private *dma_private = runtime->private_data; 803 struct device *dev = component->dev; 804 struct dma_object *dma = 805 container_of(component->driver, struct dma_object, dai); 806 807 if (dma_private) { 808 if (dma_private->irq) 809 free_irq(dma_private->irq, dma_private); 810 811 /* Deallocate the fsl_dma_private structure */ 812 dma_free_coherent(dev, sizeof(struct fsl_dma_private), 813 dma_private, dma_private->ld_buf_phys); 814 substream->runtime->private_data = NULL; 815 } 816 817 dma->assigned = false; 818 819 return 0; 820 } 821 822 /* 823 * Remove this PCM driver. 824 */ 825 static void fsl_dma_free_dma_buffers(struct snd_soc_component *component, 826 struct snd_pcm *pcm) 827 { 828 struct snd_pcm_substream *substream; 829 unsigned int i; 830 831 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 832 substream = pcm->streams[i].substream; 833 if (substream) { 834 snd_dma_free_pages(&substream->dma_buffer); 835 substream->dma_buffer.area = NULL; 836 substream->dma_buffer.addr = 0; 837 } 838 } 839 } 840 841 /** 842 * find_ssi_node -- returns the SSI node that points to its DMA channel node 843 * 844 * Although this DMA driver attempts to operate independently of the other 845 * devices, it still needs to determine some information about the SSI device 846 * that it's working with. Unfortunately, the device tree does not contain 847 * a pointer from the DMA channel node to the SSI node -- the pointer goes the 848 * other way. So we need to scan the device tree for SSI nodes until we find 849 * the one that points to the given DMA channel node. It's ugly, but at least 850 * it's contained in this one function. 851 */ 852 static struct device_node *find_ssi_node(struct device_node *dma_channel_np) 853 { 854 struct device_node *ssi_np, *np; 855 856 for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { 857 /* Check each DMA phandle to see if it points to us. We 858 * assume that device_node pointers are a valid comparison. 859 */ 860 np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); 861 of_node_put(np); 862 if (np == dma_channel_np) 863 return ssi_np; 864 865 np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); 866 of_node_put(np); 867 if (np == dma_channel_np) 868 return ssi_np; 869 } 870 871 return NULL; 872 } 873 874 static int fsl_soc_dma_probe(struct platform_device *pdev) 875 { 876 struct dma_object *dma; 877 struct device_node *np = pdev->dev.of_node; 878 struct device_node *ssi_np; 879 struct resource res; 880 const uint32_t *iprop; 881 int ret; 882 883 /* Find the SSI node that points to us. */ 884 ssi_np = find_ssi_node(np); 885 if (!ssi_np) { 886 dev_err(&pdev->dev, "cannot find parent SSI node\n"); 887 return -ENODEV; 888 } 889 890 ret = of_address_to_resource(ssi_np, 0, &res); 891 if (ret) { 892 dev_err(&pdev->dev, "could not determine resources for %pOF\n", 893 ssi_np); 894 of_node_put(ssi_np); 895 return ret; 896 } 897 898 dma = kzalloc(sizeof(*dma), GFP_KERNEL); 899 if (!dma) { 900 of_node_put(ssi_np); 901 return -ENOMEM; 902 } 903 904 dma->dai.name = DRV_NAME; 905 dma->dai.ops = &fsl_dma_ops; 906 dma->dai.open = fsl_dma_open; 907 dma->dai.close = fsl_dma_close; 908 dma->dai.ioctl = snd_soc_pcm_lib_ioctl; 909 dma->dai.hw_params = fsl_dma_hw_params; 910 dma->dai.hw_free = fsl_dma_hw_free; 911 dma->dai.pointer = fsl_dma_pointer; 912 dma->dai.pcm_construct = fsl_dma_new; 913 dma->dai.pcm_destruct = fsl_dma_free_dma_buffers; 914 915 /* Store the SSI-specific information that we need */ 916 dma->ssi_stx_phys = res.start + REG_SSI_STX0; 917 dma->ssi_srx_phys = res.start + REG_SSI_SRX0; 918 919 iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL); 920 if (iprop) 921 dma->ssi_fifo_depth = be32_to_cpup(iprop); 922 else 923 /* Older 8610 DTs didn't have the fifo-depth property */ 924 dma->ssi_fifo_depth = 8; 925 926 of_node_put(ssi_np); 927 928 ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0); 929 if (ret) { 930 dev_err(&pdev->dev, "could not register platform\n"); 931 kfree(dma); 932 return ret; 933 } 934 935 dma->channel = of_iomap(np, 0); 936 dma->irq = irq_of_parse_and_map(np, 0); 937 938 dev_set_drvdata(&pdev->dev, dma); 939 940 return 0; 941 } 942 943 static int fsl_soc_dma_remove(struct platform_device *pdev) 944 { 945 struct dma_object *dma = dev_get_drvdata(&pdev->dev); 946 947 iounmap(dma->channel); 948 irq_dispose_mapping(dma->irq); 949 kfree(dma); 950 951 return 0; 952 } 953 954 static const struct of_device_id fsl_soc_dma_ids[] = { 955 { .compatible = "fsl,ssi-dma-channel", }, 956 {} 957 }; 958 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); 959 960 static struct platform_driver fsl_soc_dma_driver = { 961 .driver = { 962 .name = "fsl-pcm-audio", 963 .of_match_table = fsl_soc_dma_ids, 964 }, 965 .probe = fsl_soc_dma_probe, 966 .remove = fsl_soc_dma_remove, 967 }; 968 969 module_platform_driver(fsl_soc_dma_driver); 970 971 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 972 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); 973 MODULE_LICENSE("GPL v2"); 974