1 /* 2 * Freescale DMA ALSA SoC PCM driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 * 11 * This driver implements ASoC support for the Elo DMA controller, which is 12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, 13 * the PCM driver is what handles the DMA buffer. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/interrupt.h> 21 #include <linux/delay.h> 22 23 #include <sound/driver.h> 24 #include <sound/core.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 29 #include <asm/io.h> 30 31 #include "fsl_dma.h" 32 33 /* 34 * The formats that the DMA controller supports, which is anything 35 * that is 8, 16, or 32 bits. 36 */ 37 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 38 SNDRV_PCM_FMTBIT_U8 | \ 39 SNDRV_PCM_FMTBIT_S16_LE | \ 40 SNDRV_PCM_FMTBIT_S16_BE | \ 41 SNDRV_PCM_FMTBIT_U16_LE | \ 42 SNDRV_PCM_FMTBIT_U16_BE | \ 43 SNDRV_PCM_FMTBIT_S24_LE | \ 44 SNDRV_PCM_FMTBIT_S24_BE | \ 45 SNDRV_PCM_FMTBIT_U24_LE | \ 46 SNDRV_PCM_FMTBIT_U24_BE | \ 47 SNDRV_PCM_FMTBIT_S32_LE | \ 48 SNDRV_PCM_FMTBIT_S32_BE | \ 49 SNDRV_PCM_FMTBIT_U32_LE | \ 50 SNDRV_PCM_FMTBIT_U32_BE) 51 52 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 53 SNDRV_PCM_RATE_CONTINUOUS) 54 55 /* DMA global data. This structure is used by fsl_dma_open() to determine 56 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does 57 * not allow the machine driver to provide this information to the PCM 58 * driver in advance, and there's no way to differentiate between the two 59 * DMA controllers. So for now, this driver only supports one SSI device 60 * using two DMA channels. We cannot support multiple DMA devices. 61 * 62 * ssi_stx_phys: bus address of SSI STX register 63 * ssi_srx_phys: bus address of SSI SRX register 64 * dma_channel: pointer to the DMA channel's registers 65 * irq: IRQ for this DMA channel 66 * assigned: set to 1 if that DMA channel is assigned to a substream 67 */ 68 static struct { 69 dma_addr_t ssi_stx_phys; 70 dma_addr_t ssi_srx_phys; 71 struct ccsr_dma_channel __iomem *dma_channel[2]; 72 unsigned int irq[2]; 73 unsigned int assigned[2]; 74 } dma_global_data; 75 76 /* 77 * The number of DMA links to use. Two is the bare minimum, but if you 78 * have really small links you might need more. 79 */ 80 #define NUM_DMA_LINKS 2 81 82 /** fsl_dma_private: p-substream DMA data 83 * 84 * Each substream has a 1-to-1 association with a DMA channel. 85 * 86 * The link[] array is first because it needs to be aligned on a 32-byte 87 * boundary, so putting it first will ensure alignment without padding the 88 * structure. 89 * 90 * @link[]: array of link descriptors 91 * @controller_id: which DMA controller (0, 1, ...) 92 * @channel_id: which DMA channel on the controller (0, 1, 2, ...) 93 * @dma_channel: pointer to the DMA channel's registers 94 * @irq: IRQ for this DMA channel 95 * @substream: pointer to the substream object, needed by the ISR 96 * @ssi_sxx_phys: bus address of the STX or SRX register to use 97 * @ld_buf_phys: physical address of the LD buffer 98 * @current_link: index into link[] of the link currently being processed 99 * @dma_buf_phys: physical address of the DMA buffer 100 * @dma_buf_next: physical address of the next period to process 101 * @dma_buf_end: physical address of the byte after the end of the DMA 102 * @buffer period_size: the size of a single period 103 * @num_periods: the number of periods in the DMA buffer 104 */ 105 struct fsl_dma_private { 106 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; 107 unsigned int controller_id; 108 unsigned int channel_id; 109 struct ccsr_dma_channel __iomem *dma_channel; 110 unsigned int irq; 111 struct snd_pcm_substream *substream; 112 dma_addr_t ssi_sxx_phys; 113 dma_addr_t ld_buf_phys; 114 unsigned int current_link; 115 dma_addr_t dma_buf_phys; 116 dma_addr_t dma_buf_next; 117 dma_addr_t dma_buf_end; 118 size_t period_size; 119 unsigned int num_periods; 120 }; 121 122 /** 123 * fsl_dma_hardare: define characteristics of the PCM hardware. 124 * 125 * The PCM hardware is the Freescale DMA controller. This structure defines 126 * the capabilities of that hardware. 127 * 128 * Since the sampling rate and data format are not controlled by the DMA 129 * controller, we specify no limits for those values. The only exception is 130 * period_bytes_min, which is set to a reasonably low value to prevent the 131 * DMA controller from generating too many interrupts per second. 132 * 133 * Since each link descriptor has a 32-bit byte count field, we set 134 * period_bytes_max to the largest 32-bit number. We also have no maximum 135 * number of periods. 136 */ 137 static const struct snd_pcm_hardware fsl_dma_hardware = { 138 139 .info = SNDRV_PCM_INFO_INTERLEAVED | 140 SNDRV_PCM_INFO_MMAP | 141 SNDRV_PCM_INFO_MMAP_VALID, 142 .formats = FSLDMA_PCM_FORMATS, 143 .rates = FSLDMA_PCM_RATES, 144 .rate_min = 5512, 145 .rate_max = 192000, 146 .period_bytes_min = 512, /* A reasonable limit */ 147 .period_bytes_max = (u32) -1, 148 .periods_min = NUM_DMA_LINKS, 149 .periods_max = (unsigned int) -1, 150 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ 151 }; 152 153 /** 154 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted 155 * 156 * This function should be called by the ISR whenever the DMA controller 157 * halts data transfer. 158 */ 159 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) 160 { 161 unsigned long flags; 162 163 snd_pcm_stream_lock_irqsave(substream, flags); 164 165 if (snd_pcm_running(substream)) 166 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 167 168 snd_pcm_stream_unlock_irqrestore(substream, flags); 169 } 170 171 /** 172 * fsl_dma_update_pointers - update LD pointers to point to the next period 173 * 174 * As each period is completed, this function changes the the link 175 * descriptor pointers for that period to point to the next period. 176 */ 177 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) 178 { 179 struct fsl_dma_link_descriptor *link = 180 &dma_private->link[dma_private->current_link]; 181 182 /* Update our link descriptors to point to the next period */ 183 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 184 link->source_addr = 185 cpu_to_be32(dma_private->dma_buf_next); 186 else 187 link->dest_addr = 188 cpu_to_be32(dma_private->dma_buf_next); 189 190 /* Update our variables for next time */ 191 dma_private->dma_buf_next += dma_private->period_size; 192 193 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 194 dma_private->dma_buf_next = dma_private->dma_buf_phys; 195 196 if (++dma_private->current_link >= NUM_DMA_LINKS) 197 dma_private->current_link = 0; 198 } 199 200 /** 201 * fsl_dma_isr: interrupt handler for the DMA controller 202 * 203 * @irq: IRQ of the DMA channel 204 * @dev_id: pointer to the dma_private structure for this DMA channel 205 */ 206 static irqreturn_t fsl_dma_isr(int irq, void *dev_id) 207 { 208 struct fsl_dma_private *dma_private = dev_id; 209 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 210 irqreturn_t ret = IRQ_NONE; 211 u32 sr, sr2 = 0; 212 213 /* We got an interrupt, so read the status register to see what we 214 were interrupted for. 215 */ 216 sr = in_be32(&dma_channel->sr); 217 218 if (sr & CCSR_DMA_SR_TE) { 219 dev_err(dma_private->substream->pcm->card->dev, 220 "DMA transmit error (controller=%u channel=%u irq=%u\n", 221 dma_private->controller_id, 222 dma_private->channel_id, irq); 223 fsl_dma_abort_stream(dma_private->substream); 224 sr2 |= CCSR_DMA_SR_TE; 225 ret = IRQ_HANDLED; 226 } 227 228 if (sr & CCSR_DMA_SR_CH) 229 ret = IRQ_HANDLED; 230 231 if (sr & CCSR_DMA_SR_PE) { 232 dev_err(dma_private->substream->pcm->card->dev, 233 "DMA%u programming error (channel=%u irq=%u)\n", 234 dma_private->controller_id, 235 dma_private->channel_id, irq); 236 fsl_dma_abort_stream(dma_private->substream); 237 sr2 |= CCSR_DMA_SR_PE; 238 ret = IRQ_HANDLED; 239 } 240 241 if (sr & CCSR_DMA_SR_EOLNI) { 242 sr2 |= CCSR_DMA_SR_EOLNI; 243 ret = IRQ_HANDLED; 244 } 245 246 if (sr & CCSR_DMA_SR_CB) 247 ret = IRQ_HANDLED; 248 249 if (sr & CCSR_DMA_SR_EOSI) { 250 struct snd_pcm_substream *substream = dma_private->substream; 251 252 /* Tell ALSA we completed a period. */ 253 snd_pcm_period_elapsed(substream); 254 255 /* 256 * Update our link descriptors to point to the next period. We 257 * only need to do this if the number of periods is not equal to 258 * the number of links. 259 */ 260 if (dma_private->num_periods != NUM_DMA_LINKS) 261 fsl_dma_update_pointers(dma_private); 262 263 sr2 |= CCSR_DMA_SR_EOSI; 264 ret = IRQ_HANDLED; 265 } 266 267 if (sr & CCSR_DMA_SR_EOLSI) { 268 sr2 |= CCSR_DMA_SR_EOLSI; 269 ret = IRQ_HANDLED; 270 } 271 272 /* Clear the bits that we set */ 273 if (sr2) 274 out_be32(&dma_channel->sr, sr2); 275 276 return ret; 277 } 278 279 /** 280 * fsl_dma_new: initialize this PCM driver. 281 * 282 * This function is called when the codec driver calls snd_soc_new_pcms(), 283 * once for each .dai_link in the machine driver's snd_soc_machine 284 * structure. 285 */ 286 static int fsl_dma_new(struct snd_card *card, struct snd_soc_codec_dai *dai, 287 struct snd_pcm *pcm) 288 { 289 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32); 290 int ret; 291 292 if (!card->dev->dma_mask) 293 card->dev->dma_mask = &fsl_dma_dmamask; 294 295 if (!card->dev->coherent_dma_mask) 296 card->dev->coherent_dma_mask = fsl_dma_dmamask; 297 298 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 299 fsl_dma_hardware.buffer_bytes_max, 300 &pcm->streams[0].substream->dma_buffer); 301 if (ret) { 302 dev_err(card->dev, 303 "Can't allocate playback DMA buffer (size=%u)\n", 304 fsl_dma_hardware.buffer_bytes_max); 305 return -ENOMEM; 306 } 307 308 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->dev, 309 fsl_dma_hardware.buffer_bytes_max, 310 &pcm->streams[1].substream->dma_buffer); 311 if (ret) { 312 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); 313 dev_err(card->dev, 314 "Can't allocate capture DMA buffer (size=%u)\n", 315 fsl_dma_hardware.buffer_bytes_max); 316 return -ENOMEM; 317 } 318 319 return 0; 320 } 321 322 /** 323 * fsl_dma_open: open a new substream. 324 * 325 * Each substream has its own DMA buffer. 326 */ 327 static int fsl_dma_open(struct snd_pcm_substream *substream) 328 { 329 struct snd_pcm_runtime *runtime = substream->runtime; 330 struct fsl_dma_private *dma_private; 331 dma_addr_t ld_buf_phys; 332 unsigned int channel; 333 int ret = 0; 334 335 /* 336 * Reject any DMA buffer whose size is not a multiple of the period 337 * size. We need to make sure that the DMA buffer can be evenly divided 338 * into periods. 339 */ 340 ret = snd_pcm_hw_constraint_integer(runtime, 341 SNDRV_PCM_HW_PARAM_PERIODS); 342 if (ret < 0) { 343 dev_err(substream->pcm->card->dev, "invalid buffer size\n"); 344 return ret; 345 } 346 347 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 348 349 if (dma_global_data.assigned[channel]) { 350 dev_err(substream->pcm->card->dev, 351 "DMA channel already assigned\n"); 352 return -EBUSY; 353 } 354 355 dma_private = dma_alloc_coherent(substream->pcm->dev, 356 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL); 357 if (!dma_private) { 358 dev_err(substream->pcm->card->dev, 359 "can't allocate DMA private data\n"); 360 return -ENOMEM; 361 } 362 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 363 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys; 364 else 365 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys; 366 367 dma_private->dma_channel = dma_global_data.dma_channel[channel]; 368 dma_private->irq = dma_global_data.irq[channel]; 369 dma_private->substream = substream; 370 dma_private->ld_buf_phys = ld_buf_phys; 371 dma_private->dma_buf_phys = substream->dma_buffer.addr; 372 373 /* We only support one DMA controller for now */ 374 dma_private->controller_id = 0; 375 dma_private->channel_id = channel; 376 377 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); 378 if (ret) { 379 dev_err(substream->pcm->card->dev, 380 "can't register ISR for IRQ %u (ret=%i)\n", 381 dma_private->irq, ret); 382 dma_free_coherent(substream->pcm->dev, 383 sizeof(struct fsl_dma_private), 384 dma_private, dma_private->ld_buf_phys); 385 return ret; 386 } 387 388 dma_global_data.assigned[channel] = 1; 389 390 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 391 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); 392 runtime->private_data = dma_private; 393 394 return 0; 395 } 396 397 /** 398 * fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors. 399 * 400 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link 401 * descriptors that ping-pong from one period to the next. For example, if 402 * there are six periods and two link descriptors, this is how they look 403 * before playback starts: 404 * 405 * The last link descriptor 406 * ____________ points back to the first 407 * | | 408 * V | 409 * ___ ___ | 410 * | |->| |->| 411 * |___| |___| 412 * | | 413 * | | 414 * V V 415 * _________________________________________ 416 * | | | | | | | The DMA buffer is 417 * | | | | | | | divided into 6 parts 418 * |______|______|______|______|______|______| 419 * 420 * and here's how they look after the first period is finished playing: 421 * 422 * ____________ 423 * | | 424 * V | 425 * ___ ___ | 426 * | |->| |->| 427 * |___| |___| 428 * | | 429 * |______________ 430 * | | 431 * V V 432 * _________________________________________ 433 * | | | | | | | 434 * | | | | | | | 435 * |______|______|______|______|______|______| 436 * 437 * The first link descriptor now points to the third period. The DMA 438 * controller is currently playing the second period. When it finishes, it 439 * will jump back to the first descriptor and play the third period. 440 * 441 * There are four reasons we do this: 442 * 443 * 1. The only way to get the DMA controller to automatically restart the 444 * transfer when it gets to the end of the buffer is to use chaining 445 * mode. Basic direct mode doesn't offer that feature. 446 * 2. We need to receive an interrupt at the end of every period. The DMA 447 * controller can generate an interrupt at the end of every link transfer 448 * (aka segment). Making each period into a DMA segment will give us the 449 * interrupts we need. 450 * 3. By creating only two link descriptors, regardless of the number of 451 * periods, we do not need to reallocate the link descriptors if the 452 * number of periods changes. 453 * 4. All of the audio data is still stored in a single, contiguous DMA 454 * buffer, which is what ALSA expects. We're just dividing it into 455 * contiguous parts, and creating a link descriptor for each one. 456 * 457 * Note that due to a quirk of the SSI's STX register, the target address 458 * for the DMA operations depends on the sample size. So we don't program 459 * the dest_addr (for playback -- source_addr for capture) fields in the 460 * link descriptors here. We do that in fsl_dma_prepare() 461 */ 462 static int fsl_dma_hw_params(struct snd_pcm_substream *substream, 463 struct snd_pcm_hw_params *hw_params) 464 { 465 struct snd_pcm_runtime *runtime = substream->runtime; 466 struct fsl_dma_private *dma_private = runtime->private_data; 467 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 468 469 dma_addr_t temp_addr; /* Pointer to next period */ 470 u64 temp_link; /* Pointer to next link descriptor */ 471 u32 mr; /* Temporary variable for MR register */ 472 473 unsigned int i; 474 475 /* Get all the parameters we need */ 476 size_t buffer_size = params_buffer_bytes(hw_params); 477 size_t period_size = params_period_bytes(hw_params); 478 479 /* Initialize our DMA tracking variables */ 480 dma_private->period_size = period_size; 481 dma_private->num_periods = params_periods(hw_params); 482 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; 483 dma_private->dma_buf_next = dma_private->dma_buf_phys + 484 (NUM_DMA_LINKS * period_size); 485 if (dma_private->dma_buf_next >= dma_private->dma_buf_end) 486 dma_private->dma_buf_next = dma_private->dma_buf_phys; 487 488 /* 489 * Initialize each link descriptor. 490 * 491 * The actual address in STX0 (destination for playback, source for 492 * capture) is based on the sample size, but we don't know the sample 493 * size in this function, so we'll have to adjust that later. See 494 * comments in fsl_dma_prepare(). 495 * 496 * The DMA controller does not have a cache, so the CPU does not 497 * need to tell it to flush its cache. However, the DMA 498 * controller does need to tell the CPU to flush its cache. 499 * That's what the SNOOP bit does. 500 * 501 * Also, even though the DMA controller supports 36-bit addressing, for 502 * simplicity we currently support only 32-bit addresses for the audio 503 * buffer itself. 504 */ 505 temp_addr = substream->dma_buffer.addr; 506 temp_link = dma_private->ld_buf_phys + 507 sizeof(struct fsl_dma_link_descriptor); 508 509 for (i = 0; i < NUM_DMA_LINKS; i++) { 510 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 511 512 link->count = cpu_to_be32(period_size); 513 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 514 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); 515 link->next = cpu_to_be64(temp_link); 516 517 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 518 link->source_addr = cpu_to_be32(temp_addr); 519 else 520 link->dest_addr = cpu_to_be32(temp_addr); 521 522 temp_addr += period_size; 523 temp_link += sizeof(struct fsl_dma_link_descriptor); 524 } 525 /* The last link descriptor points to the first */ 526 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); 527 528 /* Tell the DMA controller where the first link descriptor is */ 529 out_be32(&dma_channel->clndar, 530 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); 531 out_be32(&dma_channel->eclndar, 532 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); 533 534 /* The manual says the BCR must be clear before enabling EMP */ 535 out_be32(&dma_channel->bcr, 0); 536 537 /* 538 * Program the mode register for interrupts, external master control, 539 * and source/destination hold. Also clear the Channel Abort bit. 540 */ 541 mr = in_be32(&dma_channel->mr) & 542 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); 543 544 /* 545 * We want External Master Start and External Master Pause enabled, 546 * because the SSI is controlling the DMA controller. We want the DMA 547 * controller to be set up in advance, and then we signal only the SSI 548 * to start transfering. 549 * 550 * We want End-Of-Segment Interrupts enabled, because this will generate 551 * an interrupt at the end of each segment (each link descriptor 552 * represents one segment). Each DMA segment is the same thing as an 553 * ALSA period, so this is how we get an interrupt at the end of every 554 * period. 555 * 556 * We want Error Interrupt enabled, so that we can get an error if 557 * the DMA controller is mis-programmed somehow. 558 */ 559 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | 560 CCSR_DMA_MR_EMS_EN; 561 562 /* For playback, we want the destination address to be held. For 563 capture, set the source address to be held. */ 564 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 565 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; 566 567 out_be32(&dma_channel->mr, mr); 568 569 return 0; 570 } 571 572 /** 573 * fsl_dma_prepare - prepare the DMA registers for playback. 574 * 575 * This function is called after the specifics of the audio data are known, 576 * i.e. snd_pcm_runtime is initialized. 577 * 578 * In this function, we finish programming the registers of the DMA 579 * controller that are dependent on the sample size. 580 * 581 * One of the drawbacks with big-endian is that when copying integers of 582 * different sizes to a fixed-sized register, the address to which the 583 * integer must be copied is dependent on the size of the integer. 584 * 585 * For example, if P is the address of a 32-bit register, and X is a 32-bit 586 * integer, then X should be copied to address P. However, if X is a 16-bit 587 * integer, then it should be copied to P+2. If X is an 8-bit register, 588 * then it should be copied to P+3. 589 * 590 * So for playback of 8-bit samples, the DMA controller must transfer single 591 * bytes from the DMA buffer to the last byte of the STX0 register, i.e. 592 * offset by 3 bytes. For 16-bit samples, the offset is two bytes. 593 * 594 * For 24-bit samples, the offset is 1 byte. However, the DMA controller 595 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, 596 * and 8 bytes at a time). So we do not support packed 24-bit samples. 597 * 24-bit data must be padded to 32 bits. 598 */ 599 static int fsl_dma_prepare(struct snd_pcm_substream *substream) 600 { 601 struct snd_pcm_runtime *runtime = substream->runtime; 602 struct fsl_dma_private *dma_private = runtime->private_data; 603 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 604 u32 mr; 605 unsigned int i; 606 dma_addr_t ssi_sxx_phys; /* Bus address of SSI STX register */ 607 unsigned int frame_size; /* Number of bytes per frame */ 608 609 ssi_sxx_phys = dma_private->ssi_sxx_phys; 610 611 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | 612 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); 613 614 switch (runtime->sample_bits) { 615 case 8: 616 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; 617 ssi_sxx_phys += 3; 618 break; 619 case 16: 620 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; 621 ssi_sxx_phys += 2; 622 break; 623 case 32: 624 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; 625 break; 626 default: 627 dev_err(substream->pcm->card->dev, 628 "unsupported sample size %u\n", runtime->sample_bits); 629 return -EINVAL; 630 } 631 632 frame_size = runtime->frame_bits / 8; 633 /* 634 * BWC should always be a multiple of the frame size. BWC determines 635 * how many bytes are sent/received before the DMA controller checks the 636 * SSI to see if it needs to stop. For playback, the transmit FIFO can 637 * hold three frames, so we want to send two frames at a time. For 638 * capture, the receive FIFO is triggered when it contains one frame, so 639 * we want to receive one frame at a time. 640 */ 641 642 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 643 mr |= CCSR_DMA_MR_BWC(2 * frame_size); 644 else 645 mr |= CCSR_DMA_MR_BWC(frame_size); 646 647 out_be32(&dma_channel->mr, mr); 648 649 /* 650 * Program the address of the DMA transfer to/from the SSI. 651 */ 652 for (i = 0; i < NUM_DMA_LINKS; i++) { 653 struct fsl_dma_link_descriptor *link = &dma_private->link[i]; 654 655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 656 link->dest_addr = cpu_to_be32(ssi_sxx_phys); 657 else 658 link->source_addr = cpu_to_be32(ssi_sxx_phys); 659 } 660 661 return 0; 662 } 663 664 /** 665 * fsl_dma_pointer: determine the current position of the DMA transfer 666 * 667 * This function is called by ALSA when ALSA wants to know where in the 668 * stream buffer the hardware currently is. 669 * 670 * For playback, the SAR register contains the physical address of the most 671 * recent DMA transfer. For capture, the value is in the DAR register. 672 * 673 * The base address of the buffer is stored in the source_addr field of the 674 * first link descriptor. 675 */ 676 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) 677 { 678 struct snd_pcm_runtime *runtime = substream->runtime; 679 struct fsl_dma_private *dma_private = runtime->private_data; 680 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; 681 dma_addr_t position; 682 snd_pcm_uframes_t frames; 683 684 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 685 position = in_be32(&dma_channel->sar); 686 else 687 position = in_be32(&dma_channel->dar); 688 689 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); 690 691 /* 692 * If the current address is just past the end of the buffer, wrap it 693 * around. 694 */ 695 if (frames == runtime->buffer_size) 696 frames = 0; 697 698 return frames; 699 } 700 701 /** 702 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() 703 * 704 * Release the resources allocated in fsl_dma_hw_params() and de-program the 705 * registers. 706 * 707 * This function can be called multiple times. 708 */ 709 static int fsl_dma_hw_free(struct snd_pcm_substream *substream) 710 { 711 struct snd_pcm_runtime *runtime = substream->runtime; 712 struct fsl_dma_private *dma_private = runtime->private_data; 713 714 if (dma_private) { 715 struct ccsr_dma_channel __iomem *dma_channel; 716 717 dma_channel = dma_private->dma_channel; 718 719 /* Stop the DMA */ 720 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); 721 out_be32(&dma_channel->mr, 0); 722 723 /* Reset all the other registers */ 724 out_be32(&dma_channel->sr, -1); 725 out_be32(&dma_channel->clndar, 0); 726 out_be32(&dma_channel->eclndar, 0); 727 out_be32(&dma_channel->satr, 0); 728 out_be32(&dma_channel->sar, 0); 729 out_be32(&dma_channel->datr, 0); 730 out_be32(&dma_channel->dar, 0); 731 out_be32(&dma_channel->bcr, 0); 732 out_be32(&dma_channel->nlndar, 0); 733 out_be32(&dma_channel->enlndar, 0); 734 } 735 736 return 0; 737 } 738 739 /** 740 * fsl_dma_close: close the stream. 741 */ 742 static int fsl_dma_close(struct snd_pcm_substream *substream) 743 { 744 struct snd_pcm_runtime *runtime = substream->runtime; 745 struct fsl_dma_private *dma_private = runtime->private_data; 746 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; 747 748 if (dma_private) { 749 if (dma_private->irq) 750 free_irq(dma_private->irq, dma_private); 751 752 if (dma_private->ld_buf_phys) { 753 dma_unmap_single(substream->pcm->dev, 754 dma_private->ld_buf_phys, 755 sizeof(dma_private->link), DMA_TO_DEVICE); 756 } 757 758 /* Deallocate the fsl_dma_private structure */ 759 dma_free_coherent(substream->pcm->dev, 760 sizeof(struct fsl_dma_private), 761 dma_private, dma_private->ld_buf_phys); 762 substream->runtime->private_data = NULL; 763 } 764 765 dma_global_data.assigned[dir] = 0; 766 767 return 0; 768 } 769 770 /* 771 * Remove this PCM driver. 772 */ 773 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) 774 { 775 struct snd_pcm_substream *substream; 776 unsigned int i; 777 778 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 779 substream = pcm->streams[i].substream; 780 if (substream) { 781 snd_dma_free_pages(&substream->dma_buffer); 782 substream->dma_buffer.area = NULL; 783 substream->dma_buffer.addr = 0; 784 } 785 } 786 } 787 788 static struct snd_pcm_ops fsl_dma_ops = { 789 .open = fsl_dma_open, 790 .close = fsl_dma_close, 791 .ioctl = snd_pcm_lib_ioctl, 792 .hw_params = fsl_dma_hw_params, 793 .hw_free = fsl_dma_hw_free, 794 .prepare = fsl_dma_prepare, 795 .pointer = fsl_dma_pointer, 796 }; 797 798 struct snd_soc_platform fsl_soc_platform = { 799 .name = "fsl-dma", 800 .pcm_ops = &fsl_dma_ops, 801 .pcm_new = fsl_dma_new, 802 .pcm_free = fsl_dma_free_dma_buffers, 803 }; 804 EXPORT_SYMBOL_GPL(fsl_soc_platform); 805 806 /** 807 * fsl_dma_configure: store the DMA parameters from the fabric driver. 808 * 809 * This function is called by the ASoC fabric driver to give us the DMA and 810 * SSI channel information. 811 * 812 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI 813 * data when a substream is created, so for now we need to store this data 814 * into a global variable. This means that we can only support one DMA 815 * controller, and hence only one SSI. 816 */ 817 int fsl_dma_configure(struct fsl_dma_info *dma_info) 818 { 819 static int initialized; 820 821 /* We only support one DMA controller for now */ 822 if (initialized) 823 return 0; 824 825 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys; 826 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys; 827 dma_global_data.dma_channel[0] = dma_info->dma_channel[0]; 828 dma_global_data.dma_channel[1] = dma_info->dma_channel[1]; 829 dma_global_data.irq[0] = dma_info->dma_irq[0]; 830 dma_global_data.irq[1] = dma_info->dma_irq[1]; 831 dma_global_data.assigned[0] = 0; 832 dma_global_data.assigned[1] = 0; 833 834 initialized = 1; 835 return 1; 836 } 837 EXPORT_SYMBOL_GPL(fsl_dma_configure); 838 839 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 840 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module"); 841 MODULE_LICENSE("GPL"); 842