1*8a24c834SShengjiu Wang /* SPDX-License-Identifier: GPL-2.0 */ 2*8a24c834SShengjiu Wang /* 3*8a24c834SShengjiu Wang * Copyright 2020 NXP 4*8a24c834SShengjiu Wang */ 5*8a24c834SShengjiu Wang 6*8a24c834SShengjiu Wang #ifndef _FSL_AUD2HTX_H 7*8a24c834SShengjiu Wang #define _FSL_AUD2HTX_H 8*8a24c834SShengjiu Wang 9*8a24c834SShengjiu Wang #define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 10*8a24c834SShengjiu Wang SNDRV_PCM_FMTBIT_S32_LE) 11*8a24c834SShengjiu Wang 12*8a24c834SShengjiu Wang /* AUD2HTX Register Map */ 13*8a24c834SShengjiu Wang #define AUD2HTX_CTRL 0x0 /* AUD2HTX Control Register */ 14*8a24c834SShengjiu Wang #define AUD2HTX_CTRL_EXT 0x4 /* AUD2HTX Control Extended Register */ 15*8a24c834SShengjiu Wang #define AUD2HTX_WR 0x8 /* AUD2HTX Write Register */ 16*8a24c834SShengjiu Wang #define AUD2HTX_STATUS 0xC /* AUD2HTX Status Register */ 17*8a24c834SShengjiu Wang #define AUD2HTX_IRQ_NOMASK 0x10 /* AUD2HTX Nonmasked Interrupt Flags Register */ 18*8a24c834SShengjiu Wang #define AUD2HTX_IRQ_MASKED 0x14 /* AUD2HTX Masked Interrupt Flags Register */ 19*8a24c834SShengjiu Wang #define AUD2HTX_IRQ_MASK 0x18 /* AUD2HTX IRQ Masks Register */ 20*8a24c834SShengjiu Wang 21*8a24c834SShengjiu Wang /* AUD2HTX Control Register */ 22*8a24c834SShengjiu Wang #define AUD2HTX_CTRL_EN BIT(0) 23*8a24c834SShengjiu Wang 24*8a24c834SShengjiu Wang /* AUD2HTX Control Extended Register */ 25*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_DE BIT(0) 26*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_DT_SHIFT 0x1 27*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_DT_WIDTH 0x2 28*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_DT_MASK ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \ 29*8a24c834SShengjiu Wang << AUD2HTX_CTRE_DT_SHIFT) 30*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_WL_SHIFT 16 31*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_WL_WIDTH 5 32*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_WL_MASK ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \ 33*8a24c834SShengjiu Wang << AUD2HTX_CTRE_WL_SHIFT) 34*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_WH_SHIFT 24 35*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_WH_WIDTH 5 36*8a24c834SShengjiu Wang #define AUD2HTX_CTRE_WH_MASK ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \ 37*8a24c834SShengjiu Wang << AUD2HTX_CTRE_WH_SHIFT) 38*8a24c834SShengjiu Wang 39*8a24c834SShengjiu Wang /* AUD2HTX IRQ Masks Register */ 40*8a24c834SShengjiu Wang #define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2) 41*8a24c834SShengjiu Wang #define AUD2HTX_WM_LOW_IRQ_MASK BIT(1) 42*8a24c834SShengjiu Wang #define AUD2HTX_OVF_MASK BIT(0) 43*8a24c834SShengjiu Wang 44*8a24c834SShengjiu Wang #define AUD2HTX_FIFO_DEPTH 0x20 45*8a24c834SShengjiu Wang #define AUD2HTX_WTMK_LOW 0x10 46*8a24c834SShengjiu Wang #define AUD2HTX_WTMK_HIGH 0x10 47*8a24c834SShengjiu Wang #define AUD2HTX_MAXBURST 0x10 48*8a24c834SShengjiu Wang 49*8a24c834SShengjiu Wang /** 50*8a24c834SShengjiu Wang * fsl_aud2htx: AUD2HTX private data 51*8a24c834SShengjiu Wang * 52*8a24c834SShengjiu Wang * @pdev: platform device pointer 53*8a24c834SShengjiu Wang * @regmap: regmap handler 54*8a24c834SShengjiu Wang * @bus_clk: clock source to access register 55*8a24c834SShengjiu Wang * @dma_params_rx: DMA parameters for receive channel 56*8a24c834SShengjiu Wang * @dma_params_tx: DMA parameters for transmit channel 57*8a24c834SShengjiu Wang */ 58*8a24c834SShengjiu Wang struct fsl_aud2htx { 59*8a24c834SShengjiu Wang struct platform_device *pdev; 60*8a24c834SShengjiu Wang struct regmap *regmap; 61*8a24c834SShengjiu Wang struct clk *bus_clk; 62*8a24c834SShengjiu Wang 63*8a24c834SShengjiu Wang struct snd_dmaengine_dai_dma_data dma_params_rx; 64*8a24c834SShengjiu Wang struct snd_dmaengine_dai_dma_data dma_params_tx; 65*8a24c834SShengjiu Wang }; 66*8a24c834SShengjiu Wang 67*8a24c834SShengjiu Wang #endif /* _FSL_AUD2HTX_H */ 68