1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 // 7 // Author: Nicolin Chen <nicoleotsuka@gmail.com> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_data/dma-imx.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 19 #include "fsl_asrc.h" 20 21 #define IDEAL_RATIO_DECIMAL_DEPTH 26 22 23 #define pair_err(fmt, ...) \ 24 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 25 26 #define pair_dbg(fmt, ...) \ 27 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 28 29 /* Corresponding to process_option */ 30 static unsigned int supported_asrc_rate[] = { 31 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 32 64000, 88200, 96000, 128000, 176400, 192000, 33 }; 34 35 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { 36 .count = ARRAY_SIZE(supported_asrc_rate), 37 .list = supported_asrc_rate, 38 }; 39 40 /** 41 * The following tables map the relationship between asrc_inclk/asrc_outclk in 42 * fsl_asrc.h and the registers of ASRCSR 43 */ 44 static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 45 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 46 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 47 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 48 }; 49 50 static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 51 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 52 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 53 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 54 }; 55 56 /* i.MX53 uses the same map for input and output */ 57 static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 58 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 59 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 60 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 61 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 62 }; 63 64 static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 65 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 66 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 67 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 68 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 69 }; 70 71 /** 72 * i.MX8QM/i.MX8QXP uses the same map for input and output. 73 * clk_map_imx8qm[0] is for i.MX8QM asrc0 74 * clk_map_imx8qm[1] is for i.MX8QM asrc1 75 * clk_map_imx8qxp[0] is for i.MX8QXP asrc0 76 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1 77 */ 78 static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = { 79 { 80 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 81 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 82 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 83 }, 84 { 85 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 86 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 87 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 88 }, 89 }; 90 91 static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = { 92 { 93 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 94 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf, 95 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 96 }, 97 { 98 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 99 0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 100 0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 101 }, 102 }; 103 104 /** 105 * Select the pre-processing and post-processing options 106 * Make sure to exclude following unsupported cases before 107 * calling this function: 108 * 1) inrate > 8.125 * outrate 109 * 2) inrate > 16.125 * outrate 110 * 111 * inrate: input sample rate 112 * outrate: output sample rate 113 * pre_proc: return value for pre-processing option 114 * post_proc: return value for post-processing option 115 */ 116 static void fsl_asrc_sel_proc(int inrate, int outrate, 117 int *pre_proc, int *post_proc) 118 { 119 bool post_proc_cond2; 120 bool post_proc_cond0; 121 122 /* select pre_proc between [0, 2] */ 123 if (inrate * 8 > 33 * outrate) 124 *pre_proc = 2; 125 else if (inrate * 8 > 15 * outrate) { 126 if (inrate > 152000) 127 *pre_proc = 2; 128 else 129 *pre_proc = 1; 130 } else if (inrate < 76000) 131 *pre_proc = 0; 132 else if (inrate > 152000) 133 *pre_proc = 2; 134 else 135 *pre_proc = 1; 136 137 /* Condition for selection of post-processing */ 138 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) || 139 (inrate > 56000 && outrate < 56000); 140 post_proc_cond0 = inrate * 23 < outrate * 8; 141 142 if (post_proc_cond2) 143 *post_proc = 2; 144 else if (post_proc_cond0) 145 *post_proc = 0; 146 else 147 *post_proc = 1; 148 } 149 150 /** 151 * Request ASRC pair 152 * 153 * It assigns pair by the order of A->C->B because allocation of pair B, 154 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 155 * while pair A and pair C are comparatively independent. 156 */ 157 int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 158 { 159 enum asrc_pair_index index = ASRC_INVALID_PAIR; 160 struct fsl_asrc *asrc_priv = pair->asrc_priv; 161 struct device *dev = &asrc_priv->pdev->dev; 162 unsigned long lock_flags; 163 int i, ret = 0; 164 165 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 166 167 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 168 if (asrc_priv->pair[i] != NULL) 169 continue; 170 171 index = i; 172 173 if (i != ASRC_PAIR_B) 174 break; 175 } 176 177 if (index == ASRC_INVALID_PAIR) { 178 dev_err(dev, "all pairs are busy now\n"); 179 ret = -EBUSY; 180 } else if (asrc_priv->channel_avail < channels) { 181 dev_err(dev, "can't afford required channels: %d\n", channels); 182 ret = -EINVAL; 183 } else { 184 asrc_priv->channel_avail -= channels; 185 asrc_priv->pair[index] = pair; 186 pair->channels = channels; 187 pair->index = index; 188 } 189 190 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 191 192 return ret; 193 } 194 195 /** 196 * Release ASRC pair 197 * 198 * It clears the resource from asrc_priv and releases the occupied channels. 199 */ 200 void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 201 { 202 struct fsl_asrc *asrc_priv = pair->asrc_priv; 203 enum asrc_pair_index index = pair->index; 204 unsigned long lock_flags; 205 206 /* Make sure the pair is disabled */ 207 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 208 ASRCTR_ASRCEi_MASK(index), 0); 209 210 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 211 212 asrc_priv->channel_avail += pair->channels; 213 asrc_priv->pair[index] = NULL; 214 pair->error = 0; 215 216 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 217 } 218 219 /** 220 * Configure input and output thresholds 221 */ 222 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 223 { 224 struct fsl_asrc *asrc_priv = pair->asrc_priv; 225 enum asrc_pair_index index = pair->index; 226 227 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 228 ASRMCRi_EXTTHRSHi_MASK | 229 ASRMCRi_INFIFO_THRESHOLD_MASK | 230 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 231 ASRMCRi_EXTTHRSHi | 232 ASRMCRi_INFIFO_THRESHOLD(in) | 233 ASRMCRi_OUTFIFO_THRESHOLD(out)); 234 } 235 236 /** 237 * Calculate the total divisor between asrck clock rate and sample rate 238 * 239 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 240 */ 241 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 242 { 243 u32 ps; 244 245 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 246 for (ps = 0; div > 8; ps++) 247 div >>= 1; 248 249 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 250 } 251 252 /** 253 * Calculate and set the ratio for Ideal Ratio mode only 254 * 255 * The ratio is a 32-bit fixed point value with 26 fractional bits. 256 */ 257 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 258 int inrate, int outrate) 259 { 260 struct fsl_asrc *asrc_priv = pair->asrc_priv; 261 enum asrc_pair_index index = pair->index; 262 unsigned long ratio; 263 int i; 264 265 if (!outrate) { 266 pair_err("output rate should not be zero\n"); 267 return -EINVAL; 268 } 269 270 /* Calculate the intergal part of the ratio */ 271 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 272 273 /* ... and then the 26 depth decimal part */ 274 inrate %= outrate; 275 276 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 277 inrate <<= 1; 278 279 if (inrate < outrate) 280 continue; 281 282 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 283 inrate -= outrate; 284 285 if (!inrate) 286 break; 287 } 288 289 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio); 290 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24); 291 292 return 0; 293 } 294 295 /** 296 * Configure the assigned ASRC pair 297 * 298 * It configures those ASRC registers according to a configuration instance 299 * of struct asrc_config which includes in/output sample rate, width, channel 300 * and clock settings. 301 * 302 * Note: 303 * The ideal ratio configuration can work with a flexible clock rate setting. 304 * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC. 305 * For a regular audio playback, the clock rate should not be slower than an 306 * clock rate aligning with the output sample rate; For a use case requiring 307 * faster conversion, set use_ideal_rate to have the faster speed. 308 */ 309 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate) 310 { 311 struct asrc_config *config = pair->config; 312 struct fsl_asrc *asrc_priv = pair->asrc_priv; 313 enum asrc_pair_index index = pair->index; 314 enum asrc_word_width input_word_width; 315 enum asrc_word_width output_word_width; 316 u32 inrate, outrate, indiv, outdiv; 317 u32 clk_index[2], div[2], rem[2]; 318 u64 clk_rate; 319 int in, out, channels; 320 int pre_proc, post_proc; 321 struct clk *clk; 322 bool ideal; 323 324 if (!config) { 325 pair_err("invalid pair config\n"); 326 return -EINVAL; 327 } 328 329 /* Validate channels */ 330 if (config->channel_num < 1 || config->channel_num > 10) { 331 pair_err("does not support %d channels\n", config->channel_num); 332 return -EINVAL; 333 } 334 335 switch (snd_pcm_format_width(config->input_format)) { 336 case 8: 337 input_word_width = ASRC_WIDTH_8_BIT; 338 break; 339 case 16: 340 input_word_width = ASRC_WIDTH_16_BIT; 341 break; 342 case 24: 343 input_word_width = ASRC_WIDTH_24_BIT; 344 break; 345 default: 346 pair_err("does not support this input format, %d\n", 347 config->input_format); 348 return -EINVAL; 349 } 350 351 switch (snd_pcm_format_width(config->output_format)) { 352 case 16: 353 output_word_width = ASRC_WIDTH_16_BIT; 354 break; 355 case 24: 356 output_word_width = ASRC_WIDTH_24_BIT; 357 break; 358 default: 359 pair_err("does not support this output format, %d\n", 360 config->output_format); 361 return -EINVAL; 362 } 363 364 inrate = config->input_sample_rate; 365 outrate = config->output_sample_rate; 366 ideal = config->inclk == INCLK_NONE; 367 368 /* Validate input and output sample rates */ 369 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++) 370 if (inrate == supported_asrc_rate[in]) 371 break; 372 373 if (in == ARRAY_SIZE(supported_asrc_rate)) { 374 pair_err("unsupported input sample rate: %dHz\n", inrate); 375 return -EINVAL; 376 } 377 378 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 379 if (outrate == supported_asrc_rate[out]) 380 break; 381 382 if (out == ARRAY_SIZE(supported_asrc_rate)) { 383 pair_err("unsupported output sample rate: %dHz\n", outrate); 384 return -EINVAL; 385 } 386 387 if ((outrate >= 5512 && outrate <= 30000) && 388 (outrate > 24 * inrate || inrate > 8 * outrate)) { 389 pair_err("exceed supported ratio range [1/24, 8] for \ 390 inrate/outrate: %d/%d\n", inrate, outrate); 391 return -EINVAL; 392 } 393 394 /* Validate input and output clock sources */ 395 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk]; 396 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk]; 397 398 /* We only have output clock for ideal ratio mode */ 399 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 400 401 clk_rate = clk_get_rate(clk); 402 rem[IN] = do_div(clk_rate, inrate); 403 div[IN] = (u32)clk_rate; 404 405 /* 406 * The divider range is [1, 1024], defined by the hardware. For non- 407 * ideal ratio configuration, clock rate has to be strictly aligned 408 * with the sample rate. For ideal ratio configuration, clock rates 409 * only result in different converting speeds. So remainder does not 410 * matter, as long as we keep the divider within its valid range. 411 */ 412 if (div[IN] == 0 || (!ideal && (div[IN] > 1024 || rem[IN] != 0))) { 413 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 414 inrate, clk_index[ideal ? OUT : IN]); 415 return -EINVAL; 416 } 417 418 div[IN] = min_t(u32, 1024, div[IN]); 419 420 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 421 clk_rate = clk_get_rate(clk); 422 if (ideal && use_ideal_rate) 423 rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE); 424 else 425 rem[OUT] = do_div(clk_rate, outrate); 426 div[OUT] = clk_rate; 427 428 /* Output divider has the same limitation as the input one */ 429 if (div[OUT] == 0 || (!ideal && (div[OUT] > 1024 || rem[OUT] != 0))) { 430 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 431 outrate, clk_index[OUT]); 432 return -EINVAL; 433 } 434 435 div[OUT] = min_t(u32, 1024, div[OUT]); 436 437 /* Set the channel number */ 438 channels = config->channel_num; 439 440 if (asrc_priv->soc->channel_bits < 4) 441 channels /= 2; 442 443 /* Update channels for current pair */ 444 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR, 445 ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits), 446 ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits)); 447 448 /* Default setting: Automatic selection for processing mode */ 449 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 450 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 451 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 452 ASRCTR_USRi_MASK(index), 0); 453 454 /* Set the input and output clock sources */ 455 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR, 456 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 457 ASRCSR_AICS(index, clk_index[IN]) | 458 ASRCSR_AOCS(index, clk_index[OUT])); 459 460 /* Calculate the input clock divisors */ 461 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 462 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 463 464 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 465 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index), 466 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 467 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 468 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 469 470 /* Implement word_width configurations */ 471 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index), 472 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 473 ASRMCR1i_OW16(output_word_width) | 474 ASRMCR1i_IWD(input_word_width)); 475 476 /* Enable BUFFER STALL */ 477 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 478 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 479 480 /* Set default thresholds for input and output FIFO */ 481 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 482 ASRC_INPUTFIFO_THRESHOLD); 483 484 /* Configure the following only for Ideal Ratio mode */ 485 if (!ideal) 486 return 0; 487 488 /* Clear ASTSx bit to use Ideal Ratio mode */ 489 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 490 ASRCTR_ATSi_MASK(index), 0); 491 492 /* Enable Ideal Ratio mode */ 493 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 494 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 495 ASRCTR_IDR(index) | ASRCTR_USR(index)); 496 497 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc); 498 499 /* Apply configurations for pre- and post-processing */ 500 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 501 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 502 ASRCFG_PREMOD(index, pre_proc) | 503 ASRCFG_POSTMOD(index, post_proc)); 504 505 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 506 } 507 508 /** 509 * Start the assigned ASRC pair 510 * 511 * It enables the assigned pair and makes it stopped at the stall level. 512 */ 513 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 514 { 515 struct fsl_asrc *asrc_priv = pair->asrc_priv; 516 enum asrc_pair_index index = pair->index; 517 int reg, retry = 10, i; 518 519 /* Enable the current pair */ 520 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 521 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 522 523 /* Wait for status of initialization */ 524 do { 525 udelay(5); 526 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®); 527 reg &= ASRCFG_INIRQi_MASK(index); 528 } while (!reg && --retry); 529 530 /* Make the input fifo to ASRC STALL level */ 531 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®); 532 for (i = 0; i < pair->channels * 4; i++) 533 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0); 534 535 /* Enable overload interrupt */ 536 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE); 537 } 538 539 /** 540 * Stop the assigned ASRC pair 541 */ 542 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 543 { 544 struct fsl_asrc *asrc_priv = pair->asrc_priv; 545 enum asrc_pair_index index = pair->index; 546 547 /* Stop the current pair */ 548 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 549 ASRCTR_ASRCEi_MASK(index), 0); 550 } 551 552 /** 553 * Get DMA channel according to the pair and direction. 554 */ 555 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir) 556 { 557 struct fsl_asrc *asrc_priv = pair->asrc_priv; 558 enum asrc_pair_index index = pair->index; 559 char name[4]; 560 561 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 562 563 return dma_request_slave_channel(&asrc_priv->pdev->dev, name); 564 } 565 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel); 566 567 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, 568 struct snd_soc_dai *dai) 569 { 570 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 571 572 /* Odd channel number is not valid for older ASRC (channel_bits==3) */ 573 if (asrc_priv->soc->channel_bits == 3) 574 snd_pcm_hw_constraint_step(substream->runtime, 0, 575 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 576 577 578 return snd_pcm_hw_constraint_list(substream->runtime, 0, 579 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints); 580 } 581 582 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 583 struct snd_pcm_hw_params *params, 584 struct snd_soc_dai *dai) 585 { 586 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 587 struct snd_pcm_runtime *runtime = substream->runtime; 588 struct fsl_asrc_pair *pair = runtime->private_data; 589 unsigned int channels = params_channels(params); 590 unsigned int rate = params_rate(params); 591 struct asrc_config config; 592 snd_pcm_format_t format; 593 int ret; 594 595 ret = fsl_asrc_request_pair(channels, pair); 596 if (ret) { 597 dev_err(dai->dev, "fail to request asrc pair\n"); 598 return ret; 599 } 600 601 pair->config = &config; 602 603 if (asrc_priv->asrc_width == 16) 604 format = SNDRV_PCM_FORMAT_S16_LE; 605 else 606 format = SNDRV_PCM_FORMAT_S24_LE; 607 608 config.pair = pair->index; 609 config.channel_num = channels; 610 config.inclk = INCLK_NONE; 611 config.outclk = OUTCLK_ASRCK1_CLK; 612 613 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 614 config.input_format = params_format(params); 615 config.output_format = format; 616 config.input_sample_rate = rate; 617 config.output_sample_rate = asrc_priv->asrc_rate; 618 } else { 619 config.input_format = format; 620 config.output_format = params_format(params); 621 config.input_sample_rate = asrc_priv->asrc_rate; 622 config.output_sample_rate = rate; 623 } 624 625 ret = fsl_asrc_config_pair(pair, false); 626 if (ret) { 627 dev_err(dai->dev, "fail to config asrc pair\n"); 628 return ret; 629 } 630 631 return 0; 632 } 633 634 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 635 struct snd_soc_dai *dai) 636 { 637 struct snd_pcm_runtime *runtime = substream->runtime; 638 struct fsl_asrc_pair *pair = runtime->private_data; 639 640 if (pair) 641 fsl_asrc_release_pair(pair); 642 643 return 0; 644 } 645 646 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 647 struct snd_soc_dai *dai) 648 { 649 struct snd_pcm_runtime *runtime = substream->runtime; 650 struct fsl_asrc_pair *pair = runtime->private_data; 651 652 switch (cmd) { 653 case SNDRV_PCM_TRIGGER_START: 654 case SNDRV_PCM_TRIGGER_RESUME: 655 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 656 fsl_asrc_start_pair(pair); 657 break; 658 case SNDRV_PCM_TRIGGER_STOP: 659 case SNDRV_PCM_TRIGGER_SUSPEND: 660 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 661 fsl_asrc_stop_pair(pair); 662 break; 663 default: 664 return -EINVAL; 665 } 666 667 return 0; 668 } 669 670 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = { 671 .startup = fsl_asrc_dai_startup, 672 .hw_params = fsl_asrc_dai_hw_params, 673 .hw_free = fsl_asrc_dai_hw_free, 674 .trigger = fsl_asrc_dai_trigger, 675 }; 676 677 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 678 { 679 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 680 681 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx, 682 &asrc_priv->dma_params_rx); 683 684 return 0; 685 } 686 687 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 688 SNDRV_PCM_FMTBIT_S16_LE | \ 689 SNDRV_PCM_FMTBIT_S24_3LE) 690 691 static struct snd_soc_dai_driver fsl_asrc_dai = { 692 .probe = fsl_asrc_dai_probe, 693 .playback = { 694 .stream_name = "ASRC-Playback", 695 .channels_min = 1, 696 .channels_max = 10, 697 .rate_min = 5512, 698 .rate_max = 192000, 699 .rates = SNDRV_PCM_RATE_KNOT, 700 .formats = FSL_ASRC_FORMATS | 701 SNDRV_PCM_FMTBIT_S8, 702 }, 703 .capture = { 704 .stream_name = "ASRC-Capture", 705 .channels_min = 1, 706 .channels_max = 10, 707 .rate_min = 5512, 708 .rate_max = 192000, 709 .rates = SNDRV_PCM_RATE_KNOT, 710 .formats = FSL_ASRC_FORMATS, 711 }, 712 .ops = &fsl_asrc_dai_ops, 713 }; 714 715 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 716 { 717 switch (reg) { 718 case REG_ASRCTR: 719 case REG_ASRIER: 720 case REG_ASRCNCR: 721 case REG_ASRCFG: 722 case REG_ASRCSR: 723 case REG_ASRCDR1: 724 case REG_ASRCDR2: 725 case REG_ASRSTR: 726 case REG_ASRPM1: 727 case REG_ASRPM2: 728 case REG_ASRPM3: 729 case REG_ASRPM4: 730 case REG_ASRPM5: 731 case REG_ASRTFR1: 732 case REG_ASRCCR: 733 case REG_ASRDOA: 734 case REG_ASRDOB: 735 case REG_ASRDOC: 736 case REG_ASRIDRHA: 737 case REG_ASRIDRLA: 738 case REG_ASRIDRHB: 739 case REG_ASRIDRLB: 740 case REG_ASRIDRHC: 741 case REG_ASRIDRLC: 742 case REG_ASR76K: 743 case REG_ASR56K: 744 case REG_ASRMCRA: 745 case REG_ASRFSTA: 746 case REG_ASRMCRB: 747 case REG_ASRFSTB: 748 case REG_ASRMCRC: 749 case REG_ASRFSTC: 750 case REG_ASRMCR1A: 751 case REG_ASRMCR1B: 752 case REG_ASRMCR1C: 753 return true; 754 default: 755 return false; 756 } 757 } 758 759 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 760 { 761 switch (reg) { 762 case REG_ASRSTR: 763 case REG_ASRDIA: 764 case REG_ASRDIB: 765 case REG_ASRDIC: 766 case REG_ASRDOA: 767 case REG_ASRDOB: 768 case REG_ASRDOC: 769 case REG_ASRFSTA: 770 case REG_ASRFSTB: 771 case REG_ASRFSTC: 772 case REG_ASRCFG: 773 return true; 774 default: 775 return false; 776 } 777 } 778 779 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 780 { 781 switch (reg) { 782 case REG_ASRCTR: 783 case REG_ASRIER: 784 case REG_ASRCNCR: 785 case REG_ASRCFG: 786 case REG_ASRCSR: 787 case REG_ASRCDR1: 788 case REG_ASRCDR2: 789 case REG_ASRSTR: 790 case REG_ASRPM1: 791 case REG_ASRPM2: 792 case REG_ASRPM3: 793 case REG_ASRPM4: 794 case REG_ASRPM5: 795 case REG_ASRTFR1: 796 case REG_ASRCCR: 797 case REG_ASRDIA: 798 case REG_ASRDIB: 799 case REG_ASRDIC: 800 case REG_ASRIDRHA: 801 case REG_ASRIDRLA: 802 case REG_ASRIDRHB: 803 case REG_ASRIDRLB: 804 case REG_ASRIDRHC: 805 case REG_ASRIDRLC: 806 case REG_ASR76K: 807 case REG_ASR56K: 808 case REG_ASRMCRA: 809 case REG_ASRMCRB: 810 case REG_ASRMCRC: 811 case REG_ASRMCR1A: 812 case REG_ASRMCR1B: 813 case REG_ASRMCR1C: 814 return true; 815 default: 816 return false; 817 } 818 } 819 820 static struct reg_default fsl_asrc_reg[] = { 821 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 822 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 823 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 824 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 825 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 826 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 827 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 828 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 829 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 830 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 831 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 832 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 833 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 834 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 835 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 836 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 837 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 838 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 839 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 840 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 841 { REG_ASRMCR1C, 0x0000 }, 842 }; 843 844 static const struct regmap_config fsl_asrc_regmap_config = { 845 .reg_bits = 32, 846 .reg_stride = 4, 847 .val_bits = 32, 848 849 .max_register = REG_ASRMCR1C, 850 .reg_defaults = fsl_asrc_reg, 851 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 852 .readable_reg = fsl_asrc_readable_reg, 853 .volatile_reg = fsl_asrc_volatile_reg, 854 .writeable_reg = fsl_asrc_writeable_reg, 855 .cache_type = REGCACHE_FLAT, 856 }; 857 858 /** 859 * Initialize ASRC registers with a default configurations 860 */ 861 static int fsl_asrc_init(struct fsl_asrc *asrc_priv) 862 { 863 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 864 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 865 866 /* Disable interrupt by default */ 867 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0); 868 869 /* Apply recommended settings for parameters from Reference Manual */ 870 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff); 871 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555); 872 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280); 873 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280); 874 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280); 875 876 /* Base address for task queue FIFO. Set to 0x7C */ 877 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1, 878 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 879 880 /* Set the processing clock for 76KHz to 133M */ 881 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6); 882 883 /* Set the processing clock for 56KHz to 133M */ 884 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947); 885 } 886 887 /** 888 * Interrupt handler for ASRC 889 */ 890 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 891 { 892 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id; 893 struct device *dev = &asrc_priv->pdev->dev; 894 enum asrc_pair_index index; 895 u32 status; 896 897 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status); 898 899 /* Clean overload error */ 900 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE); 901 902 /* 903 * We here use dev_dbg() for all exceptions because ASRC itself does 904 * not care if FIFO overflowed or underrun while a warning in the 905 * interrupt would result a ridged conversion. 906 */ 907 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 908 if (!asrc_priv->pair[index]) 909 continue; 910 911 if (status & ASRSTR_ATQOL) { 912 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 913 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 914 } 915 916 if (status & ASRSTR_AOOL(index)) { 917 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 918 pair_dbg("Output Task Overload\n"); 919 } 920 921 if (status & ASRSTR_AIOL(index)) { 922 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 923 pair_dbg("Input Task Overload\n"); 924 } 925 926 if (status & ASRSTR_AODO(index)) { 927 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 928 pair_dbg("Output Data Buffer has overflowed\n"); 929 } 930 931 if (status & ASRSTR_AIDU(index)) { 932 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 933 pair_dbg("Input Data Buffer has underflowed\n"); 934 } 935 } 936 937 return IRQ_HANDLED; 938 } 939 940 static int fsl_asrc_probe(struct platform_device *pdev) 941 { 942 struct device_node *np = pdev->dev.of_node; 943 struct fsl_asrc *asrc_priv; 944 struct resource *res; 945 void __iomem *regs; 946 int irq, ret, i; 947 u32 map_idx; 948 char tmp[16]; 949 950 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 951 if (!asrc_priv) 952 return -ENOMEM; 953 954 asrc_priv->pdev = pdev; 955 956 /* Get the addresses and IRQ */ 957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 958 regs = devm_ioremap_resource(&pdev->dev, res); 959 if (IS_ERR(regs)) 960 return PTR_ERR(regs); 961 962 asrc_priv->paddr = res->start; 963 964 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, 965 &fsl_asrc_regmap_config); 966 if (IS_ERR(asrc_priv->regmap)) { 967 dev_err(&pdev->dev, "failed to init regmap\n"); 968 return PTR_ERR(asrc_priv->regmap); 969 } 970 971 irq = platform_get_irq(pdev, 0); 972 if (irq < 0) 973 return irq; 974 975 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 976 dev_name(&pdev->dev), asrc_priv); 977 if (ret) { 978 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 979 return ret; 980 } 981 982 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem"); 983 if (IS_ERR(asrc_priv->mem_clk)) { 984 dev_err(&pdev->dev, "failed to get mem clock\n"); 985 return PTR_ERR(asrc_priv->mem_clk); 986 } 987 988 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 989 if (IS_ERR(asrc_priv->ipg_clk)) { 990 dev_err(&pdev->dev, "failed to get ipg clock\n"); 991 return PTR_ERR(asrc_priv->ipg_clk); 992 } 993 994 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba"); 995 if (IS_ERR(asrc_priv->spba_clk)) 996 dev_warn(&pdev->dev, "failed to get spba clock\n"); 997 998 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 999 sprintf(tmp, "asrck_%x", i); 1000 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 1001 if (IS_ERR(asrc_priv->asrck_clk[i])) { 1002 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 1003 return PTR_ERR(asrc_priv->asrck_clk[i]); 1004 } 1005 } 1006 1007 asrc_priv->soc = of_device_get_match_data(&pdev->dev); 1008 if (!asrc_priv->soc) { 1009 dev_err(&pdev->dev, "failed to get soc data\n"); 1010 return -ENODEV; 1011 } 1012 1013 if (of_device_is_compatible(np, "fsl,imx35-asrc")) { 1014 asrc_priv->clk_map[IN] = input_clk_map_imx35; 1015 asrc_priv->clk_map[OUT] = output_clk_map_imx35; 1016 } else if (of_device_is_compatible(np, "fsl,imx53-asrc")) { 1017 asrc_priv->clk_map[IN] = input_clk_map_imx53; 1018 asrc_priv->clk_map[OUT] = output_clk_map_imx53; 1019 } else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") || 1020 of_device_is_compatible(np, "fsl,imx8qxp-asrc")) { 1021 ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx); 1022 if (ret) { 1023 dev_err(&pdev->dev, "failed to get clk map index\n"); 1024 return ret; 1025 } 1026 1027 if (map_idx > 1) { 1028 dev_err(&pdev->dev, "unsupported clk map index\n"); 1029 return -EINVAL; 1030 } 1031 if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) { 1032 asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx]; 1033 asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx]; 1034 } else { 1035 asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx]; 1036 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx]; 1037 } 1038 } 1039 1040 ret = fsl_asrc_init(asrc_priv); 1041 if (ret) { 1042 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 1043 return ret; 1044 } 1045 1046 asrc_priv->channel_avail = 10; 1047 1048 ret = of_property_read_u32(np, "fsl,asrc-rate", 1049 &asrc_priv->asrc_rate); 1050 if (ret) { 1051 dev_err(&pdev->dev, "failed to get output rate\n"); 1052 return ret; 1053 } 1054 1055 ret = of_property_read_u32(np, "fsl,asrc-width", 1056 &asrc_priv->asrc_width); 1057 if (ret) { 1058 dev_err(&pdev->dev, "failed to get output width\n"); 1059 return ret; 1060 } 1061 1062 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) { 1063 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n"); 1064 asrc_priv->asrc_width = 24; 1065 } 1066 1067 platform_set_drvdata(pdev, asrc_priv); 1068 pm_runtime_enable(&pdev->dev); 1069 spin_lock_init(&asrc_priv->lock); 1070 1071 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 1072 &fsl_asrc_dai, 1); 1073 if (ret) { 1074 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 1075 return ret; 1076 } 1077 1078 return 0; 1079 } 1080 1081 #ifdef CONFIG_PM 1082 static int fsl_asrc_runtime_resume(struct device *dev) 1083 { 1084 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1085 int i, ret; 1086 1087 ret = clk_prepare_enable(asrc_priv->mem_clk); 1088 if (ret) 1089 return ret; 1090 ret = clk_prepare_enable(asrc_priv->ipg_clk); 1091 if (ret) 1092 goto disable_mem_clk; 1093 if (!IS_ERR(asrc_priv->spba_clk)) { 1094 ret = clk_prepare_enable(asrc_priv->spba_clk); 1095 if (ret) 1096 goto disable_ipg_clk; 1097 } 1098 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1099 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]); 1100 if (ret) 1101 goto disable_asrck_clk; 1102 } 1103 1104 return 0; 1105 1106 disable_asrck_clk: 1107 for (i--; i >= 0; i--) 1108 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1109 if (!IS_ERR(asrc_priv->spba_clk)) 1110 clk_disable_unprepare(asrc_priv->spba_clk); 1111 disable_ipg_clk: 1112 clk_disable_unprepare(asrc_priv->ipg_clk); 1113 disable_mem_clk: 1114 clk_disable_unprepare(asrc_priv->mem_clk); 1115 return ret; 1116 } 1117 1118 static int fsl_asrc_runtime_suspend(struct device *dev) 1119 { 1120 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1121 int i; 1122 1123 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 1124 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1125 if (!IS_ERR(asrc_priv->spba_clk)) 1126 clk_disable_unprepare(asrc_priv->spba_clk); 1127 clk_disable_unprepare(asrc_priv->ipg_clk); 1128 clk_disable_unprepare(asrc_priv->mem_clk); 1129 1130 return 0; 1131 } 1132 #endif /* CONFIG_PM */ 1133 1134 #ifdef CONFIG_PM_SLEEP 1135 static int fsl_asrc_suspend(struct device *dev) 1136 { 1137 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1138 1139 regmap_read(asrc_priv->regmap, REG_ASRCFG, 1140 &asrc_priv->regcache_cfg); 1141 1142 regcache_cache_only(asrc_priv->regmap, true); 1143 regcache_mark_dirty(asrc_priv->regmap); 1144 1145 return 0; 1146 } 1147 1148 static int fsl_asrc_resume(struct device *dev) 1149 { 1150 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1151 u32 asrctr; 1152 1153 /* Stop all pairs provisionally */ 1154 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr); 1155 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1156 ASRCTR_ASRCEi_ALL_MASK, 0); 1157 1158 /* Restore all registers */ 1159 regcache_cache_only(asrc_priv->regmap, false); 1160 regcache_sync(asrc_priv->regmap); 1161 1162 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 1163 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK | 1164 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg); 1165 1166 /* Restart enabled pairs */ 1167 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1168 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1169 1170 return 0; 1171 } 1172 #endif /* CONFIG_PM_SLEEP */ 1173 1174 static const struct dev_pm_ops fsl_asrc_pm = { 1175 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 1176 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) 1177 }; 1178 1179 static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = { 1180 .use_edma = false, 1181 .channel_bits = 3, 1182 }; 1183 1184 static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = { 1185 .use_edma = false, 1186 .channel_bits = 4, 1187 }; 1188 1189 static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = { 1190 .use_edma = true, 1191 .channel_bits = 4, 1192 }; 1193 1194 static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = { 1195 .use_edma = true, 1196 .channel_bits = 4, 1197 }; 1198 1199 static const struct of_device_id fsl_asrc_ids[] = { 1200 { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data }, 1201 { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data }, 1202 { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data }, 1203 { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data }, 1204 {} 1205 }; 1206 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1207 1208 static struct platform_driver fsl_asrc_driver = { 1209 .probe = fsl_asrc_probe, 1210 .driver = { 1211 .name = "fsl-asrc", 1212 .of_match_table = fsl_asrc_ids, 1213 .pm = &fsl_asrc_pm, 1214 }, 1215 }; 1216 module_platform_driver(fsl_asrc_driver); 1217 1218 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1219 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1220 MODULE_ALIAS("platform:fsl-asrc"); 1221 MODULE_LICENSE("GPL v2"); 1222