1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 /* WSA885X codec driver */ 7 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/mutex.h> 14 #include <linux/module.h> 15 #include <linux/property.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/string.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/soc-dapm.h> 26 #include <sound/tlv.h> 27 28 /* Control Registers - Audio Processing */ 29 #define WSA885X_SMP_AMP_CTRL_STEREO_STEREO_SMP_AMP_CTRL_I2S 0x0000 30 #define WSA885X_SMP_AMP_CTRL_STEREO_CMT_GRP_MASK 0x0004 31 #define WSA885X_SMP_AMP_CTRL_STEREO_IT21_CLUSERINDEX 0x0140 32 #define WSA885X_SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID 0x0208 33 #define WSA885X_SMP_AMP_CTRL_STEREO_CS21_SAMPLERATEINDEX 0x0240 34 #define WSA885X_SMP_AMP_CTRL_STEREO_PPU21_POSTURENUMBER 0x0340 35 #define WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X0 0x4405 36 #define WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X1 0x4406 37 #define WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB 0x4409 38 #define WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_MSB 0x6409 39 #define WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB 0x440a 40 #define WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_MSB 0x640a 41 #define WSA885X_SMP_AMP_CTRL_STEREO_PDE23_REQ_PS 0x0a04 42 #define WSA885X_SMP_AMP_CTRL_STEREO_PDE23_ACT_PS 0x0a40 43 #define WSA885X_SMP_AMP_CTRL_STEREO_OT23_USAGE 0x0b10 44 #define WSA885X_SMP_AMP_CTRL_STEREO_CS24_SAMPLERATEINDEX 0x0e40 45 46 /* Analog Top Registers - Power and Clock Control */ 47 #define WSA885X_ANA_TOP_PON_CKSK_CTL_0 0x800d 48 #define WSA885X_ANA_TOP_BG_TVP_UVLO1_PROG 0x8024 49 #define WSA885X_ANA_TOP_BG_TVP_UVLO2_PROG 0x8025 50 #define WSA885X_ANA_TOP_BG_TVP_OVRD_CTL 0x8034 51 52 /* Analog PLL Registers */ 53 #define WSA885X_ANA_PLL_DIV_CTL_0 0x8090 54 #define WSA885X_ANA_PLL_DIV_CTL_1 0x8091 55 #define WSA885X_ANA_TOP_PLL_VCO_CTL 0x8092 56 #define WSA885X_ANA_TOP_PLL_LOOPFILT_0 0x8093 57 #define WSA885X_ANA_TOP_PLL_OVRD_CTL 0x8098 58 #define WSA885X_ANA_TOP_PLL_STATUS_0 0x809a 59 #define WSA885X_ANA_TOP_PLL_STATUS_1 0x809b 60 61 /* Analog Boost Control Registers */ 62 #define WSA885X_ANA_TOP_BOOST_STB_CTRL2 0x805b 63 #define WSA885X_ANA_TOP_BOOST_STB_CTRL3 0x805c 64 #define WSA885X_ANA_TOP_BOOST_BYP_CTRL2 0x805e 65 #define WSA885X_ANA_TOP_BOOST_BYP_CTRL3 0x805f 66 #define WSA885X_ANA_TOP_BOOST_MISC 0x8063 67 #define WSA885X_ANA_TOP_BOOST_PWRSTAGE_CTRL2 0x8065 68 #define WSA885X_ANA_TOP_BOOST_PWRSTAGE_CTRL4 0x8067 69 70 /* Analog IV Sense ADC Registers */ 71 #define WSA885X_ANA_TOP_IVSENSE_ADC_MODE_CTL2 0x80ca 72 #define WSA885X_ANA_TOP_IVSENSE_ADC_MODE_CTL3 0x80cb 73 #define WSA885X_ANA_TOP_IVSENSE_ADC_REF_CTL 0x80cc 74 #define WSA885X_ANA_TOP_IVSENSE_ADC_CDAC_CAL_CTL2 0x80d0 75 76 /* Analog Speaker Power Stage Registers */ 77 #define WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH1_CTRL3 0x8108 78 #define WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH1_TUNE3 0x810b 79 #define WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH2_CTRL3 0x810e 80 #define WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3 0x8111 81 #define WSA885X_ANA_TOP_SPK_TOP_SPARE3 0x813c 82 #define WSA885X_SPK_TOP_LF_CH1_CTRL11 0x811c 83 #define WSA885X_SPK_TOP_LF_CH1_TUNE1 0x811d 84 #define WSA885X_SPK_TOP_LF_CH2_TUNE1 0x8129 85 #define WSA885X_SPK_TOP_LF_CH1_CTRL9 0x811a 86 #define WSA885X_SPK_TOP_LF_CH2_CTRL9 0x8126 87 #define WSA885X_SPK_TOP_LF_CH2_CTRL11 0x8128 88 #define WSA885X_SPK_TOP_COMMON_CTRL2 0x8102 89 #define WSA885X_SPK_TOP_COMMON_TUNE1 0x8103 90 #define WSA885X_IVSENSE_VSNS_ISNS_CTL_CH1 0x80ba 91 #define WSA885X_DIG_CTRL0_TOP_CLK_CFG 0x8418 92 #define WSA885X_DIG_CTRL0_SDCA_COMMIT 0x8419 93 #define WSA885X_DIG_CTRL0_CLK_SOURCE_ENABLE 0x841a 94 #define WSA885X_DIG_CTRL0_SYS_CLK_SEL 0x841b 95 #define WSA885X_DIG_CTRL0_CDC_CLK_CTL 0x841c 96 #define WSA885X_DIG_CTRL0_PA_FSM_CTL 0x8420 97 #define WSA885X_DIG_CTRL0_POWER_FSM_CTL0 0x8423 98 #define WSA885X_DIG_CTRL0_POWER_FSM_CTL1 0x8424 99 #define WSA885X_DIG_CTRL0_PA0_FSM_CTL1 0x842b 100 #define WSA885X_DIG_CTRL0_PA1_FSM_CTL1 0x8435 101 #define WSA885X_DIG_CTRL0_VBAT_THRM_FLT_CTL 0x8458 102 #define WSA885X_DIG_CTRL0_CDC_RXTX_FSCNT_CTL 0x8470 103 #define WSA885X_DIG_CTRL0_GAIN_RAMP0_CTL1 0x84b4 104 #define WSA885X_DIG_CTRL0_GAIN_RAMP1_CTL1 0x84b7 105 #define WSA885X_DIG_CTRL0_PCM_DATA_WD0_CTL1 0x84A0 106 #define WSA885X_DIG_CTRL0_PCM_DATA_WD1_CTL1 0x84A4 107 108 /* Digital Control 1 Registers - I2S/TDM Interface */ 109 #define WSA885X_DIG_CTRL1_I2S_CTL0 0x85A0 110 #define WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX 0x85A2 111 #define WSA885X_DIG_CTRL1_I2S_CFG1_TDM_TX 0x85A3 112 #define WSA885X_DIG_CTRL1_I2S_TDM_CTL0 0x85A7 113 #define WSA885X_DIG_CTRL1_I2S_TDM_CTL1 0x85A9 114 #define WSA885X_DIG_CTRL1_I2S_TDM_CH_RX 0x85AA 115 #define WSA885X_DIG_CTRL1_I2S_TDM_CH_TX 0x85AB 116 #define WSA885X_DIG_CTRL1_I2S_RESET_CTL 0x85AE 117 118 /* CDC RX Path Registers - Audio Data Path */ 119 #define WSA885X_CDC_RX0_RX_PATH_CFG0 0x8601 120 #define WSA885X_CDC_RX0_RX_PATH_CFG1 0x8602 121 #define WSA885X_CDC_RX0_RX_PATH_CTL 0x8606 122 #define WSA885X_RX0_RX_PATH_DSMDEM_CTL 0x8613 123 #define WSA885X_CDC_RX1_RX_PATH_CFG0 0x8621 124 #define WSA885X_CDC_RX1_RX_PATH_CFG1 0x8622 125 #define WSA885X_CDC_RX1_RX_PATH_CTL 0x8626 126 #define WSA885X_RX1_RX_PATH_DSMDEM_CTL 0x8633 127 128 /* CDC Compander Registers - Dynamic Range Control */ 129 #define WSA885X_CDC_COMPANDER0_CTL0 0x8640 130 #define WSA885X_CDC_COMPANDER0_CTL7 0x8647 131 #define WSA885X_CDC_COMPANDER1_CTL0 0x8660 132 #define WSA885X_CDC_COMPANDER1_CTL7 0x8667 133 134 /* CDC Speaker Protection Registers - IV Sense */ 135 #define WSA885X_CDC_VSENSE0_SPKR_PROT_PATH_CTL 0x86A1 136 #define WSA885X_CDC_VSENSE1_SPKR_PROT_PATH_CTL 0x86B1 137 #define WSA885X_CDC_ISENSE0_SPKR_PROT_PATH_CTL 0x86A9 138 #define WSA885X_CDC_ISENSE1_SPKR_PROT_PATH_CTL 0x86B9 139 140 /* CDC Class-H Registers - Headroom Control */ 141 #define WSA885X_CDC_CLSH_V1P8_BP_CTL1 0x86CD 142 #define WSA885X_CDC_CLSH_V1P8_BP_CTL0 0x86CC 143 #define WSA885X_CDC_CLSH_CLSH_SIG_DP_CTL0 0x86C7 144 #define WSA885X_CDC_CLSH_CLSH_V_HD_PA 0x86C3 145 #define WSA885X_CDC_CLSH_V1P8_BP_CTL2 0x86CE 146 147 /* Driver Constants */ 148 #define WSA885X_CLK_RATE_FIXED 73728000 149 #define WSA885X_NUM_REGS 0x03 150 151 /* Interrupt Registers */ 152 #define WSA885X_INTR_STATUS0 0x8584 153 #define WSA885X_INTR_MASK0 0x8581 154 #define WSA885X_INTR_CLEAR0 0x8587 155 156 /* Power and PA FSM Control Registers */ 157 #define WSA885X_PA0_FSM_CTL0 0x842A 158 #define WSA885X_PA1_FSM_CTL0 0x8434 159 160 /* Digital Control GPIO and Interrupt Registers */ 161 #define WSA885X_DIG_CTRL1_PIN_CT 0x8510 162 #define WSA885X_DIG_CTRL1_SPMI_PAD_GPIO2_CTL 0x8518 163 #define WSA885X_DIG_CTRL1_INTR_MODE 0x8580 164 165 #define WSA885X_I2S_CTL0_PCM_RATE_MASK GENMASK(4, 1) 166 #define WSA885X_I2S_CTL0_ENABLE_MASK BIT(0) 167 #define WSA885X_I2S_CTL0_PCM_RATE(v) \ 168 FIELD_PREP(WSA885X_I2S_CTL0_PCM_RATE_MASK, (v)) 169 #define WSA885X_I2S_CTL0_PCM_RATE_8KHZ 0x0 170 #define WSA885X_I2S_CTL0_PCM_RATE_16KHZ 0x1 171 #define WSA885X_I2S_CTL0_PCM_RATE_32KHZ 0x2 172 #define WSA885X_I2S_CTL0_PCM_RATE_48_OR_44KHZ 0x3 173 #define WSA885X_I2S_CTL0_PCM_RATE_96_OR_88KHZ 0x4 174 #define WSA885X_I2S_CTL0_PCM_RATE_192_OR_176KHZ 0x5 175 #define WSA885X_I2S_CTL0_PCM_RATE_384_OR_352KHZ 0x6 176 #define WSA885X_I2S_CFG0_TDM_TX_SLOT0_MASK GENMASK(2, 0) 177 #define WSA885X_I2S_CFG0_TDM_TX_SLOT1_MASK GENMASK(6, 4) 178 #define WSA885X_I2S_CFG0_TDM_TX_SLOT0(v) \ 179 FIELD_PREP_CONST(WSA885X_I2S_CFG0_TDM_TX_SLOT0_MASK, (v)) 180 #define WSA885X_I2S_CFG0_TDM_TX_SLOT1(v) \ 181 FIELD_PREP_CONST(WSA885X_I2S_CFG0_TDM_TX_SLOT1_MASK, (v)) 182 #define WSA885X_I2S_CFG1_TDM_TX_SLOT2_MASK GENMASK(2, 0) 183 #define WSA885X_I2S_CFG1_TDM_TX_SLOT3_MASK GENMASK(6, 4) 184 #define WSA885X_I2S_CFG1_TDM_TX_SLOT2(v) \ 185 FIELD_PREP_CONST(WSA885X_I2S_CFG1_TDM_TX_SLOT2_MASK, (v)) 186 #define WSA885X_I2S_CFG1_TDM_TX_SLOT3(v) \ 187 FIELD_PREP_CONST(WSA885X_I2S_CFG1_TDM_TX_SLOT3_MASK, (v)) 188 #define WSA885X_I2S_TDM_CTL0_I2S_TDM_EN_MASK BIT(0) 189 #define WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_MASK GENMASK(3, 2) 190 #define WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_2 \ 191 FIELD_PREP_CONST(WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_MASK, 0) 192 #define WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_4 \ 193 FIELD_PREP_CONST(WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_MASK, 1) 194 #define WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_8 \ 195 FIELD_PREP_CONST(WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_MASK, 3) 196 #define WSA885X_I2S_TDM_CH_TX_CH0_EN BIT(0) 197 #define WSA885X_I2S_TDM_CH_TX_CH1_EN BIT(1) 198 #define WSA885X_I2S_TDM_CH_TX_CH2_EN BIT(2) 199 #define WSA885X_I2S_TDM_CH_TX_CH3_EN BIT(3) 200 #define WSA885X_I2S_TDM_CH_RX_CH0_EN BIT(0) 201 #define WSA885X_I2S_TDM_CH_RX_CH3_EN BIT(3) 202 #define WSA885X_I2S_RESET_CTL_RESET_MASK BIT(0) 203 #define WSA885X_PCM_DATA_WD_CTL1_PCM_DATA_WD_EN_MASK BIT(2) 204 #define WSA885X_POWER_FSM_CTL0_CLEAR_ERROR_MASK BIT(3) 205 #define WSA885X_PA_FSM_CTL0_CLEAR_ERROR_MASK BIT(2) 206 207 #define WSA885X_I2S_TX_SLOT_ISENSE0 0x1 208 #define WSA885X_I2S_TX_SLOT_ISENSE1 0x2 209 #define WSA885X_I2S_TX_SLOT_CUR_SENSE0 0x5 210 #define WSA885X_I2S_TX_SLOT_CUR_SENSE1 0x6 211 212 /* RX Sample Rate Index Values - Audio Playback Path */ 213 #define WSA885X_RX_RATE_8000HZ 0x00 214 #define WSA885X_RX_RATE_16000HZ 0x01 215 #define WSA885X_RX_RATE_32000HZ 0x02 216 #define WSA885X_RX_RATE_44100HZ 0x03 217 #define WSA885X_RX_RATE_48000HZ 0x04 218 #define WSA885X_RX_RATE_96000HZ 0x05 219 #define WSA885X_RX_RATE_192000HZ 0x06 220 #define WSA885X_RX_RATE_384000HZ 0x07 221 222 /* VI Sample Rate Index Values - Voltage/Current Sensing Path */ 223 #define WSA885X_VI_RATE_8000HZ 0x00 224 #define WSA885X_VI_RATE_16000HZ 0x01 225 #define WSA885X_VI_RATE_44100HZ 0x02 226 #define WSA885X_VI_RATE_48000HZ 0x03 227 #define WSA885X_VI_RATE_96000HZ 0x04 228 #define WSA885X_VI_RATE_22050HZ 0x05 229 #define WSA885X_VI_RATE_24000HZ 0x06 230 #define WSA885X_VI_RATE_192000HZ 0x07 231 #define WSA885X_VI_RATE_384000HZ 0x08 232 233 /* Channel Configuration Masks */ 234 #define WSA885X_CHANNEL_STEREO 0x03 235 #define WSA885X_CHANNEL_MONO_LEFT 0x01 236 #define WSA885X_CHANNEL_MONO_RIGHT 0x02 237 238 #define WSA885X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \ 239 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 | \ 240 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 241 242 #define WSA885X_PLL_LOCK_BIT BIT(0) 243 244 #define WSA885X_FU21_VOL_STEPS 124 245 #define WSA885X_USAGE_MODE_MAX 8 246 static const DECLARE_TLV_DB_SCALE(wsa885x_fu21_digital_gain, -8400, 100, 0); 247 248 static bool wsa885x_is_valid_rx_slot_mask(u32 mask) 249 { 250 return mask == WSA885X_CHANNEL_MONO_LEFT || 251 mask == WSA885X_CHANNEL_MONO_RIGHT || 252 mask == WSA885X_CHANNEL_STEREO; 253 } 254 255 static const char *const wsa885x_supply_name[] = { 256 "vdd-1p8", 257 "vdd-io", 258 }; 259 260 enum { 261 WSA885X_BATT_1S = 1, 262 WSA885X_BATT_2S, 263 }; 264 265 enum { 266 WSA885X_IRQ_INT_SAF2WAR = 0, 267 WSA885X_IRQ_INT_WAR2SAF, 268 WSA885X_IRQ_INT_DISABLE, 269 WSA885X_IRQ_INT_PA0_OCP, 270 WSA885X_IRQ_INT_PA1_OCP, 271 WSA885X_IRQ_INT_CLIP0, 272 WSA885X_IRQ_INT_CLIP1, 273 WSA885X_IRQ_INT_CLK_WD, 274 WSA885X_IRQ_INT_INTR_GPIO1_PIN, 275 WSA885X_IRQ_INT_INTR_GPIO2_PIN, 276 WSA885X_IRQ_INT_UVLO, 277 WSA885X_IRQ_INT_BOP, 278 WSA885X_IRQ_INT_PA0_FSM_ERR, 279 WSA885X_IRQ_INT_PA1_FSM_ERR, 280 WSA885X_IRQ_INT_MAIN_FSM_ERR, 281 WSA885X_IRQ_INT_PCM_DATA0_WD, 282 WSA885X_IRQ_INT_PCM_DATA1_WD, 283 WSA885X_IRQ_INT_PCM_DATA0_DC, 284 WSA885X_IRQ_INT_PCM_DATA1_DC, 285 WSA885X_IRQ_INT_PLL_UNLOCKED, 286 WSA885X_IRQ_INT_PROT_MODE_CHANGE, 287 WSA885X_IRQ_INT_PB_CLOCK_VALID, 288 WSA885X_IRQ_INT_SENSE_CLOCK_VALID, 289 WSA885X_IRQ_MAX, 290 }; 291 292 struct wsa885x_priv { 293 struct i2c_client *client; 294 struct regmap *regmap; 295 struct device *dev; 296 struct snd_soc_component *component; 297 struct gpio_desc *sd_n; 298 struct reset_control *sd_reset; 299 u32 usage_mode; 300 u32 rx_slot_mask; 301 u32 batt_conf; 302 int stereo_vol_db; 303 struct mutex state_lock; /* protects mutable control state */ 304 }; 305 306 struct wsa885x_reg_update { 307 unsigned int reg; 308 unsigned int mask; 309 unsigned int val; 310 }; 311 312 static const struct regmap_range_cfg wsa885x_regmap_ranges[] = { 313 { 314 .range_min = 0, 315 .range_max = 0x88ff, 316 .selector_reg = 0x0, 317 .selector_mask = 0xFF, 318 .selector_shift = 0, 319 .window_start = 0, 320 .window_len = 0x100, 321 }, 322 }; 323 324 static const struct reg_default wsa885x_codec_reg_defaults[] = { 325 {WSA885X_SMP_AMP_CTRL_STEREO_STEREO_SMP_AMP_CTRL_I2S, 0x00}, 326 {WSA885X_SMP_AMP_CTRL_STEREO_IT21_CLUSERINDEX, 0x01}, 327 {WSA885X_SMP_AMP_CTRL_STEREO_CMT_GRP_MASK, 0x00}, 328 {WSA885X_SMP_AMP_CTRL_STEREO_OT23_USAGE, 0x00}, 329 {WSA885X_SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID, 0x00}, 330 {WSA885X_SMP_AMP_CTRL_STEREO_CS21_SAMPLERATEINDEX, 0x04}, 331 {WSA885X_SMP_AMP_CTRL_STEREO_PPU21_POSTURENUMBER, 0x01}, 332 {WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X0, 0x01}, 333 {WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X1, 0x01}, 334 {WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_MSB, 0xac}, 335 {WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB, 0x00}, 336 {WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_MSB, 0xac}, 337 {WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB, 0x00}, 338 {WSA885X_SMP_AMP_CTRL_STEREO_PDE23_REQ_PS, 0x03}, 339 {WSA885X_SMP_AMP_CTRL_STEREO_PDE23_ACT_PS, 0x03}, 340 {WSA885X_SMP_AMP_CTRL_STEREO_CS24_SAMPLERATEINDEX, 0x03}, 341 {WSA885X_ANA_TOP_PON_CKSK_CTL_0, 0x00}, 342 {WSA885X_ANA_TOP_BG_TVP_UVLO1_PROG, 0x19}, 343 {WSA885X_ANA_TOP_BG_TVP_UVLO2_PROG, 0x22}, 344 {WSA885X_ANA_PLL_DIV_CTL_0, 0x0c}, 345 {WSA885X_ANA_PLL_DIV_CTL_1, 0x50}, 346 {WSA885X_ANA_TOP_PLL_VCO_CTL, 0x00}, 347 {WSA885X_ANA_TOP_PLL_LOOPFILT_0, 0xb4}, 348 {WSA885X_ANA_TOP_PLL_OVRD_CTL, 0x00}, 349 {WSA885X_ANA_TOP_BG_TVP_OVRD_CTL, 0x00}, 350 {WSA885X_ANA_TOP_BOOST_STB_CTRL2, 0x03}, 351 {WSA885X_ANA_TOP_BOOST_STB_CTRL3, 0x3c}, 352 {WSA885X_ANA_TOP_BOOST_BYP_CTRL2, 0xc5}, 353 {WSA885X_ANA_TOP_BOOST_BYP_CTRL3, 0x13}, 354 {WSA885X_ANA_TOP_BOOST_MISC, 0x79}, 355 {WSA885X_ANA_TOP_SPK_TOP_SPARE3, 0x00}, 356 {WSA885X_SPK_TOP_COMMON_CTRL2, 0x08}, 357 {WSA885X_SPK_TOP_LF_CH1_CTRL11, 0x09}, 358 {WSA885X_SPK_TOP_LF_CH1_TUNE1, 0x00}, 359 {WSA885X_SPK_TOP_LF_CH2_TUNE1, 0x00}, 360 {WSA885X_SPK_TOP_LF_CH1_CTRL9, 0x00}, 361 {WSA885X_SPK_TOP_LF_CH2_CTRL9, 0x00}, 362 {WSA885X_SPK_TOP_LF_CH2_CTRL11, 0x09}, 363 {WSA885X_SPK_TOP_COMMON_TUNE1, 0x03}, 364 {WSA885X_IVSENSE_VSNS_ISNS_CTL_CH1, 0x00}, 365 {WSA885X_DIG_CTRL0_CDC_CLK_CTL, 0x0e}, 366 {WSA885X_ANA_TOP_BOOST_PWRSTAGE_CTRL2, 0x40}, 367 {WSA885X_ANA_TOP_BOOST_PWRSTAGE_CTRL4, 0xff}, 368 {WSA885X_ANA_TOP_PLL_STATUS_0, 0x00}, 369 {WSA885X_ANA_TOP_PLL_STATUS_1, 0x00}, 370 {WSA885X_ANA_TOP_IVSENSE_ADC_MODE_CTL2, 0x84}, 371 {WSA885X_ANA_TOP_IVSENSE_ADC_MODE_CTL3, 0x02}, 372 {WSA885X_ANA_TOP_IVSENSE_ADC_REF_CTL, 0x00}, 373 {WSA885X_ANA_TOP_IVSENSE_ADC_CDAC_CAL_CTL2, 0xe0}, 374 {WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH1_CTRL3, 0xa4}, 375 {WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH1_TUNE3, 0xc9}, 376 {WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH2_CTRL3, 0xa4}, 377 {WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3, 0xc9}, 378 {WSA885X_DIG_CTRL0_TOP_CLK_CFG, 0x00}, 379 {WSA885X_DIG_CTRL0_SDCA_COMMIT, 0x00}, 380 {WSA885X_DIG_CTRL0_CLK_SOURCE_ENABLE, 0x00}, 381 {WSA885X_DIG_CTRL0_SYS_CLK_SEL, 0x00}, 382 {WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x00}, 383 {WSA885X_DIG_CTRL0_POWER_FSM_CTL0, 0x05}, 384 {WSA885X_DIG_CTRL0_POWER_FSM_CTL1, 0x00}, 385 {WSA885X_DIG_CTRL0_PA0_FSM_CTL1, 0x45}, 386 {WSA885X_DIG_CTRL0_PA1_FSM_CTL1, 0x45}, 387 {WSA885X_DIG_CTRL0_VBAT_THRM_FLT_CTL, 0x7f}, 388 {WSA885X_DIG_CTRL0_CDC_RXTX_FSCNT_CTL, 0x00}, 389 {WSA885X_DIG_CTRL0_GAIN_RAMP0_CTL1, 0x01}, 390 {WSA885X_DIG_CTRL0_GAIN_RAMP1_CTL1, 0x01}, 391 {WSA885X_DIG_CTRL1_I2S_CTL0, 0x06}, 392 {WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, 0x00}, 393 {WSA885X_DIG_CTRL1_I2S_CFG1_TDM_TX, 0x00}, 394 {WSA885X_DIG_CTRL1_I2S_TDM_CTL0, 0x00}, 395 {WSA885X_DIG_CTRL1_I2S_TDM_CTL1, 0x05}, 396 {WSA885X_DIG_CTRL1_I2S_TDM_CH_TX, 0x00}, 397 {WSA885X_DIG_CTRL1_I2S_RESET_CTL, 0x00}, 398 {WSA885X_DIG_CTRL1_I2S_TDM_CH_RX, WSA885X_I2S_TDM_CH_RX_CH3_EN}, 399 {WSA885X_CDC_RX0_RX_PATH_CFG0, 0x89}, 400 {WSA885X_CDC_RX0_RX_PATH_CFG1, 0x64}, 401 {WSA885X_CDC_RX0_RX_PATH_CTL, 0x24}, 402 {WSA885X_RX0_RX_PATH_DSMDEM_CTL, 0x01}, 403 {WSA885X_CDC_RX1_RX_PATH_CFG0, 0x89}, 404 {WSA885X_CDC_RX1_RX_PATH_CFG1, 0x64}, 405 {WSA885X_CDC_RX1_RX_PATH_CTL, 0x04}, 406 {WSA885X_RX1_RX_PATH_DSMDEM_CTL, 0x01}, 407 {WSA885X_CDC_COMPANDER0_CTL0, 0x01}, 408 {WSA885X_CDC_COMPANDER0_CTL7, 0x2a}, 409 {WSA885X_CDC_COMPANDER1_CTL0, 0x01}, 410 {WSA885X_CDC_COMPANDER1_CTL7, 0x2a}, 411 {WSA885X_CDC_VSENSE0_SPKR_PROT_PATH_CTL, 0x14}, 412 {WSA885X_CDC_VSENSE1_SPKR_PROT_PATH_CTL, 0x14}, 413 {WSA885X_CDC_ISENSE0_SPKR_PROT_PATH_CTL, 0x14}, 414 {WSA885X_CDC_ISENSE1_SPKR_PROT_PATH_CTL, 0x14}, 415 {WSA885X_CDC_CLSH_V1P8_BP_CTL1, 0x50}, 416 {WSA885X_CDC_CLSH_V1P8_BP_CTL0, 0x6c}, 417 {WSA885X_CDC_CLSH_CLSH_SIG_DP_CTL0, 0x0d}, 418 {WSA885X_CDC_CLSH_CLSH_V_HD_PA, 0x03}, 419 {WSA885X_CDC_CLSH_V1P8_BP_CTL2, 0x05}, 420 }; 421 422 static void wsa885x_multi_update_bits(struct regmap *regmap, 423 const struct wsa885x_reg_update *updates, 424 size_t num_updates) 425 { 426 size_t i; 427 428 for (i = 0; i < num_updates; i++) 429 regmap_update_bits(regmap, updates[i].reg, 430 updates[i].mask, updates[i].val); 431 } 432 433 static void wsa885x_toggle_irq_bit(struct wsa885x_priv *wsa885x, 434 unsigned int reg, unsigned int mask) 435 { 436 regmap_update_bits(wsa885x->regmap, reg, mask, 0); 437 regmap_update_bits(wsa885x->regmap, reg, mask, mask); 438 } 439 440 static void wsa885x_pulse_irq_bit(struct wsa885x_priv *wsa885x, 441 unsigned int reg, unsigned int mask) 442 { 443 regmap_update_bits(wsa885x->regmap, reg, mask, 0); 444 regmap_update_bits(wsa885x->regmap, reg, mask, mask); 445 regmap_update_bits(wsa885x->regmap, reg, mask, 0); 446 } 447 448 static int wsa885x_tdm_ctl0_slot_num_val(int slots, unsigned int *slot_num_val) 449 { 450 if (!slot_num_val) 451 return -EINVAL; 452 453 switch (slots) { 454 case 2: 455 *slot_num_val = WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_2; 456 return 0; 457 case 4: 458 *slot_num_val = WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_4; 459 return 0; 460 case 8: 461 *slot_num_val = WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_8; 462 return 0; 463 default: 464 return -EINVAL; 465 } 466 } 467 468 static int wsa885x_reg_update_sequence(struct regmap *regmap, int slots) 469 { 470 static const struct reg_sequence regs[] = { 471 { WSA885X_DIG_CTRL1_I2S_TDM_CTL1, 0x15 }, 472 { WSA885X_DIG_CTRL1_I2S_TDM_CTL1, 0x11 }, 473 }; 474 unsigned int slot_num_val; 475 int ret; 476 477 if (!regmap) 478 return -EINVAL; 479 480 ret = wsa885x_tdm_ctl0_slot_num_val(slots, &slot_num_val); 481 if (ret) 482 return ret; 483 484 regmap_multi_reg_write(regmap, regs, ARRAY_SIZE(regs)); 485 486 regmap_update_bits(regmap, WSA885X_DIG_CTRL1_I2S_TDM_CTL0, 487 WSA885X_I2S_TDM_CTL0_NUM_CHANNELS_MASK, 488 slot_num_val); 489 regmap_update_bits(regmap, WSA885X_DIG_CTRL1_I2S_TDM_CTL0, 490 WSA885X_I2S_TDM_CTL0_I2S_TDM_EN_MASK, 491 WSA885X_I2S_TDM_CTL0_I2S_TDM_EN_MASK); 492 regmap_write(regmap, WSA885X_DIG_CTRL1_I2S_TDM_CH_TX, 493 WSA885X_I2S_TDM_CH_TX_CH0_EN); 494 regmap_update_bits(regmap, WSA885X_DIG_CTRL1_I2S_TDM_CH_TX, 495 WSA885X_I2S_TDM_CH_TX_CH1_EN, 496 WSA885X_I2S_TDM_CH_TX_CH1_EN); 497 498 return 0; 499 } 500 501 static int wsa885x_wait_for_pll_lock(struct wsa885x_priv *wsa885x) 502 { 503 unsigned int status = 0; 504 int cnt = 0, ret = 0; 505 506 do { 507 usleep_range(1000, 1100); 508 ret = regmap_read(wsa885x->regmap, WSA885X_ANA_TOP_PLL_STATUS_0, &status); 509 if (ret) { 510 dev_err(wsa885x->dev, "PLL status read failed: %d\n", ret); 511 return ret; 512 } 513 514 if (status & WSA885X_PLL_LOCK_BIT) 515 return 0; 516 } while (++cnt < 20); 517 518 dev_warn(wsa885x->dev, "PLL lock timeout after 20ms, status=0x%x\n", status); 519 return -ETIMEDOUT; 520 } 521 522 static int wsa885x_2s_conf(struct wsa885x_priv *wsa885x) 523 { 524 static const struct reg_sequence regs[] = { 525 { WSA885X_SPK_TOP_COMMON_TUNE1, 0x26 }, 526 { WSA885X_SPK_TOP_LF_CH1_CTRL11, 0x0d }, 527 { WSA885X_SPK_TOP_LF_CH2_CTRL11, 0x0d }, 528 { WSA885X_CDC_CLSH_V1P8_BP_CTL1, 0x71 }, 529 { WSA885X_CDC_CLSH_V1P8_BP_CTL0, 0xAA }, 530 }; 531 532 return regmap_multi_reg_write(wsa885x->regmap, regs, ARRAY_SIZE(regs)); 533 } 534 535 static const struct reg_sequence wsa885x_reg_init[] = { 536 { WSA885X_CDC_RX0_RX_PATH_CTL, 0x24 }, 537 { WSA885X_CDC_RX1_RX_PATH_CTL, 0x24 }, 538 { WSA885X_RX0_RX_PATH_DSMDEM_CTL, 0x01 }, 539 { WSA885X_RX1_RX_PATH_DSMDEM_CTL, 0x01 }, 540 { WSA885X_CDC_COMPANDER0_CTL0, 0x01 }, 541 { WSA885X_CDC_COMPANDER1_CTL0, 0x01 }, 542 { WSA885X_CDC_VSENSE0_SPKR_PROT_PATH_CTL, 0x14 }, 543 { WSA885X_CDC_VSENSE1_SPKR_PROT_PATH_CTL, 0x14 }, 544 { WSA885X_CDC_ISENSE0_SPKR_PROT_PATH_CTL, 0x14 }, 545 { WSA885X_CDC_ISENSE1_SPKR_PROT_PATH_CTL, 0x14 }, 546 { WSA885X_DIG_CTRL0_CDC_CLK_CTL, 0x0f }, 547 { WSA885X_DIG_CTRL0_CDC_CLK_CTL, 0x4f }, 548 { WSA885X_DIG_CTRL0_CDC_RXTX_FSCNT_CTL, 0x02 }, 549 { WSA885X_DIG_CTRL0_CDC_RXTX_FSCNT_CTL, 0x00 }, 550 { WSA885X_DIG_CTRL0_CDC_RXTX_FSCNT_CTL, 0x01 }, 551 { WSA885X_SMP_AMP_CTRL_STEREO_CMT_GRP_MASK, 0x01 }, 552 { WSA885X_CDC_RX0_RX_PATH_CFG1, 0x60 }, 553 { WSA885X_CDC_RX1_RX_PATH_CFG1, 0x60 }, 554 { WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH1_CTRL3, 0xa5 }, 555 { WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH2_CTRL3, 0xa5 }, 556 { WSA885X_ANA_TOP_IVSENSE_ADC_MODE_CTL2, 0x85 }, 557 { WSA885X_ANA_TOP_IVSENSE_ADC_MODE_CTL3, 0x0c }, 558 { WSA885X_ANA_TOP_IVSENSE_ADC_MODE_CTL3, 0x0e }, 559 { WSA885X_ANA_TOP_IVSENSE_ADC_REF_CTL, 0x0c }, 560 { WSA885X_DIG_CTRL0_GAIN_RAMP0_CTL1, 0x01 }, 561 { WSA885X_DIG_CTRL0_GAIN_RAMP1_CTL1, 0x01 }, 562 { WSA885X_CDC_RX0_RX_PATH_CFG0, 0x88 }, 563 { WSA885X_CDC_RX0_RX_PATH_CFG0, 0x89 }, 564 { WSA885X_CDC_RX1_RX_PATH_CFG0, 0x88 }, 565 { WSA885X_CDC_RX1_RX_PATH_CFG0, 0x89 }, 566 { WSA885X_ANA_TOP_BOOST_STB_CTRL2, 0x82 }, 567 { WSA885X_ANA_TOP_BOOST_STB_CTRL3, 0x34 }, 568 { WSA885X_ANA_TOP_BOOST_PWRSTAGE_CTRL2, 0x41 }, 569 { WSA885X_ANA_TOP_BOOST_PWRSTAGE_CTRL4, 0x7f }, 570 { WSA885X_CDC_CLSH_V1P8_BP_CTL1, 0x50 }, 571 { WSA885X_CDC_CLSH_V1P8_BP_CTL0, 0x6c }, 572 { WSA885X_CDC_CLSH_CLSH_SIG_DP_CTL0, 0x0d }, 573 { WSA885X_CDC_CLSH_CLSH_V_HD_PA, 0x03 }, 574 { WSA885X_DIG_CTRL0_POWER_FSM_CTL0, 0x05 }, 575 { WSA885X_ANA_TOP_PON_CKSK_CTL_0, 0x20 }, 576 { WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH1_TUNE3, 0x45 }, 577 { WSA885X_ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3, 0x45 }, 578 { WSA885X_CDC_CLSH_V1P8_BP_CTL2, 0x05 }, 579 { WSA885X_ANA_TOP_BG_TVP_UVLO1_PROG, 0x35 }, 580 { WSA885X_ANA_TOP_BG_TVP_UVLO2_PROG, 0x21 }, 581 { WSA885X_ANA_TOP_BOOST_BYP_CTRL2, 0xc7 }, 582 { WSA885X_ANA_TOP_BOOST_BYP_CTRL3, 0x11 }, 583 { WSA885X_ANA_TOP_IVSENSE_ADC_CDAC_CAL_CTL2, 0x80 }, 584 { WSA885X_ANA_TOP_SPK_TOP_SPARE3, 0x08 }, 585 { WSA885X_DIG_CTRL0_PA0_FSM_CTL1, 0x47 }, 586 { WSA885X_DIG_CTRL0_PA1_FSM_CTL1, 0x47 }, 587 { WSA885X_CDC_COMPANDER0_CTL7, 0x34 }, 588 { WSA885X_CDC_COMPANDER1_CTL7, 0x34 }, 589 { WSA885X_DIG_CTRL0_VBAT_THRM_FLT_CTL, 0x79 }, 590 }; 591 592 static int wsa885x_hw_init(struct wsa885x_priv *wsa885x) 593 { 594 static const struct reg_sequence regs[] = { 595 { WSA885X_DIG_CTRL1_SPMI_PAD_GPIO2_CTL, 0x2e }, 596 { WSA885X_DIG_CTRL1_INTR_MODE, 0x01 }, 597 { WSA885X_DIG_CTRL1_PIN_CT, 0x04 }, 598 }; 599 int ret; 600 601 ret = regmap_multi_reg_write(wsa885x->regmap, wsa885x_reg_init, 602 ARRAY_SIZE(wsa885x_reg_init)); 603 if (ret) 604 return ret; 605 606 if (wsa885x->batt_conf == WSA885X_BATT_2S) { 607 ret = wsa885x_2s_conf(wsa885x); 608 if (ret) 609 return ret; 610 } 611 612 return regmap_multi_reg_write(wsa885x->regmap, regs, ARRAY_SIZE(regs)); 613 } 614 615 static int wsa885x_unmask_interrupts(struct wsa885x_priv *wsa885x) 616 { 617 static const struct reg_sequence regs[] = { 618 { WSA885X_INTR_MASK0, 0x00 }, 619 { WSA885X_INTR_MASK0 + 1, 0x00 }, 620 { WSA885X_INTR_MASK0 + 2, 0xf8 }, 621 }; 622 623 return regmap_multi_reg_write(wsa885x->regmap, regs, ARRAY_SIZE(regs)); 624 } 625 626 static int wsa885x_wait_for_pde_state(struct wsa885x_priv *wsa885x, int ps) 627 { 628 unsigned int act_ps = 0, clock_valid = 0; 629 int rc = 0, cnt = 0; 630 631 if (ps < 0 || ps > 3) 632 return -EINVAL; 633 634 do { 635 usleep_range(1000, 1500); 636 rc = regmap_read(wsa885x->regmap, 637 WSA885X_SMP_AMP_CTRL_STEREO_PDE23_ACT_PS, 638 &act_ps); 639 if (rc) { 640 dev_err(wsa885x->dev, "PDE state read failed: %d\n", rc); 641 return rc; 642 } 643 if (act_ps == ps) 644 return 0; 645 } while (++cnt < 5); 646 647 if (regmap_read(wsa885x->regmap, 648 WSA885X_SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID, 649 &clock_valid)) 650 dev_err(wsa885x->dev, 651 "PDE power state %d request failed, actual_ps %d, clock_valid read failed\n", 652 ps, act_ps); 653 else 654 dev_err(wsa885x->dev, 655 "PDE power state %d request failed, actual_ps %d, clock_valid:%d\n", 656 ps, act_ps, clock_valid); 657 658 return -ETIMEDOUT; 659 } 660 661 static void wsa885x_program_stereo_volume(struct wsa885x_priv *wsa885x, 662 int stereo_vol_db, bool commit) 663 { 664 regmap_write(wsa885x->regmap, 665 WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_MSB, 666 (u8)(s8)stereo_vol_db); 667 regmap_write(wsa885x->regmap, 668 WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB, 0x00); 669 regmap_write(wsa885x->regmap, 670 WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_MSB, 671 (u8)(s8)stereo_vol_db); 672 regmap_write(wsa885x->regmap, 673 WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB, 0x00); 674 675 if (commit) 676 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_SDCA_COMMIT, 0x01); 677 } 678 679 static int wsa885x_codec_hw_params(struct snd_pcm_substream *substream, 680 struct snd_pcm_hw_params *params, 681 struct snd_soc_dai *dai) 682 { 683 struct wsa885x_priv *wsa885x; 684 u8 pcm_rate, cs21_sample_rate_idx, cs24_sample_rate_idx; 685 686 wsa885x = snd_soc_component_get_drvdata(dai->component); 687 688 switch (params_rate(params)) { 689 case 8000: 690 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_8KHZ; 691 cs21_sample_rate_idx = WSA885X_RX_RATE_8000HZ; 692 cs24_sample_rate_idx = WSA885X_VI_RATE_8000HZ; 693 break; 694 case 16000: 695 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_16KHZ; 696 cs21_sample_rate_idx = WSA885X_RX_RATE_16000HZ; 697 cs24_sample_rate_idx = WSA885X_VI_RATE_16000HZ; 698 break; 699 case 32000: 700 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_32KHZ; 701 cs21_sample_rate_idx = WSA885X_RX_RATE_32000HZ; 702 cs24_sample_rate_idx = WSA885X_VI_RATE_48000HZ; 703 break; 704 case 44100: 705 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_48_OR_44KHZ; 706 cs21_sample_rate_idx = WSA885X_RX_RATE_44100HZ; 707 cs24_sample_rate_idx = WSA885X_VI_RATE_44100HZ; 708 break; 709 case 48000: 710 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_48_OR_44KHZ; 711 cs21_sample_rate_idx = WSA885X_RX_RATE_48000HZ; 712 cs24_sample_rate_idx = WSA885X_VI_RATE_48000HZ; 713 break; 714 case 88200: 715 case 96000: 716 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_96_OR_88KHZ; 717 cs21_sample_rate_idx = WSA885X_RX_RATE_96000HZ; 718 cs24_sample_rate_idx = WSA885X_VI_RATE_96000HZ; 719 break; 720 case 176400: 721 case 192000: 722 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_192_OR_176KHZ; 723 cs21_sample_rate_idx = WSA885X_RX_RATE_192000HZ; 724 cs24_sample_rate_idx = WSA885X_VI_RATE_192000HZ; 725 break; 726 case 352800: 727 case 384000: 728 pcm_rate = WSA885X_I2S_CTL0_PCM_RATE_384_OR_352KHZ; 729 cs21_sample_rate_idx = WSA885X_RX_RATE_384000HZ; 730 cs24_sample_rate_idx = WSA885X_VI_RATE_384000HZ; 731 break; 732 default: 733 dev_err(wsa885x->dev, "sampling rate %d is not supported\n", params_rate(params)); 734 return -EINVAL; 735 } 736 737 regmap_update_bits(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_CTL0, 738 WSA885X_I2S_CTL0_PCM_RATE_MASK | 739 WSA885X_I2S_CTL0_ENABLE_MASK, 740 WSA885X_I2S_CTL0_PCM_RATE(pcm_rate) | 741 WSA885X_I2S_CTL0_ENABLE_MASK); 742 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_RESET_CTL, 0x00); 743 regmap_write(wsa885x->regmap, WSA885X_SMP_AMP_CTRL_STEREO_CS21_SAMPLERATEINDEX, 744 cs21_sample_rate_idx); 745 regmap_write(wsa885x->regmap, WSA885X_SMP_AMP_CTRL_STEREO_CS24_SAMPLERATEINDEX, 746 cs24_sample_rate_idx); 747 748 mutex_lock(&wsa885x->state_lock); 749 wsa885x_program_stereo_volume(wsa885x, wsa885x->stereo_vol_db, false); 750 mutex_unlock(&wsa885x->state_lock); 751 752 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_SDCA_COMMIT, 0x01); 753 754 return 0; 755 } 756 757 static int wsa885x_codec_set_tdm_slot(struct snd_soc_dai *dai, 758 unsigned int tx_slot_mask, 759 unsigned int rx_slot_mask, int slots, 760 int slot_width) 761 { 762 static const struct wsa885x_reg_update stereo_updates[] = { 763 { WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, WSA885X_I2S_CFG0_TDM_TX_SLOT0_MASK, 764 WSA885X_I2S_CFG0_TDM_TX_SLOT0(WSA885X_I2S_TX_SLOT_ISENSE0) }, 765 { WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, WSA885X_I2S_CFG0_TDM_TX_SLOT1_MASK, 766 WSA885X_I2S_CFG0_TDM_TX_SLOT1(WSA885X_I2S_TX_SLOT_ISENSE1) }, 767 { WSA885X_DIG_CTRL1_I2S_CFG1_TDM_TX, WSA885X_I2S_CFG1_TDM_TX_SLOT2_MASK, 768 WSA885X_I2S_CFG1_TDM_TX_SLOT2(WSA885X_I2S_TX_SLOT_CUR_SENSE0) }, 769 { WSA885X_DIG_CTRL1_I2S_CFG1_TDM_TX, WSA885X_I2S_CFG1_TDM_TX_SLOT3_MASK, 770 WSA885X_I2S_CFG1_TDM_TX_SLOT3(WSA885X_I2S_TX_SLOT_CUR_SENSE1) }, 771 }; 772 static const struct wsa885x_reg_update mono_left_updates[] = { 773 { WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, WSA885X_I2S_CFG0_TDM_TX_SLOT0_MASK, 774 WSA885X_I2S_CFG0_TDM_TX_SLOT0(WSA885X_I2S_TX_SLOT_ISENSE0) }, 775 { WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, WSA885X_I2S_CFG0_TDM_TX_SLOT1_MASK, 776 WSA885X_I2S_CFG0_TDM_TX_SLOT1(WSA885X_I2S_TX_SLOT_CUR_SENSE0) }, 777 }; 778 static const struct wsa885x_reg_update mono_right_updates[] = { 779 { WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, WSA885X_I2S_CFG0_TDM_TX_SLOT0_MASK, 780 WSA885X_I2S_CFG0_TDM_TX_SLOT0(WSA885X_I2S_TX_SLOT_ISENSE1) }, 781 { WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, WSA885X_I2S_CFG0_TDM_TX_SLOT1_MASK, 782 WSA885X_I2S_CFG0_TDM_TX_SLOT1(WSA885X_I2S_TX_SLOT_CUR_SENSE1) }, 783 }; 784 struct wsa885x_priv *wsa885x; 785 unsigned int slot_num_val; 786 u32 mask; 787 int ret; 788 789 wsa885x = snd_soc_component_get_drvdata(dai->component); 790 791 ret = wsa885x_tdm_ctl0_slot_num_val(slots, &slot_num_val); 792 if (ret) { 793 dev_err(wsa885x->dev, "%s: unsupported slot count %d\n", 794 __func__, slots); 795 return ret; 796 } 797 798 if (rx_slot_mask && !wsa885x_is_valid_rx_slot_mask(rx_slot_mask)) { 799 dev_err(wsa885x->dev, 800 "%s: unsupported rx_slot_mask 0x%x\n", 801 __func__, rx_slot_mask); 802 return -EINVAL; 803 } 804 805 mutex_lock(&wsa885x->state_lock); 806 if (rx_slot_mask) 807 wsa885x->rx_slot_mask = rx_slot_mask; 808 else if (!wsa885x_is_valid_rx_slot_mask(wsa885x->rx_slot_mask)) 809 wsa885x->rx_slot_mask = WSA885X_CHANNEL_STEREO; 810 mask = wsa885x->rx_slot_mask; 811 812 regmap_update_bits(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_RESET_CTL, 813 WSA885X_I2S_RESET_CTL_RESET_MASK, 814 WSA885X_I2S_RESET_CTL_RESET_MASK); 815 816 if (mask == WSA885X_CHANNEL_STEREO) { 817 wsa885x_multi_update_bits(wsa885x->regmap, stereo_updates, 818 ARRAY_SIZE(stereo_updates)); 819 ret = wsa885x_reg_update_sequence(wsa885x->regmap, slots); 820 if (ret) 821 goto exit_unlock; 822 regmap_update_bits(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_TDM_CH_TX, 823 WSA885X_I2S_TDM_CH_TX_CH2_EN, 824 WSA885X_I2S_TDM_CH_TX_CH2_EN); 825 regmap_update_bits(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_TDM_CH_TX, 826 WSA885X_I2S_TDM_CH_TX_CH3_EN, 827 WSA885X_I2S_TDM_CH_TX_CH3_EN); 828 } else if (mask == WSA885X_CHANNEL_MONO_LEFT) { 829 wsa885x_multi_update_bits(wsa885x->regmap, mono_left_updates, 830 ARRAY_SIZE(mono_left_updates)); 831 ret = wsa885x_reg_update_sequence(wsa885x->regmap, slots); 832 if (ret) 833 goto exit_unlock; 834 } else if (mask == WSA885X_CHANNEL_MONO_RIGHT) { 835 wsa885x_multi_update_bits(wsa885x->regmap, mono_right_updates, 836 ARRAY_SIZE(mono_right_updates)); 837 ret = wsa885x_reg_update_sequence(wsa885x->regmap, slots); 838 if (ret) 839 goto exit_unlock; 840 } 841 842 regmap_update_bits(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_CTL0, 843 WSA885X_I2S_CTL0_ENABLE_MASK, 844 WSA885X_I2S_CTL0_ENABLE_MASK); 845 regmap_update_bits(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_RESET_CTL, 846 WSA885X_I2S_RESET_CTL_RESET_MASK, 0); 847 848 ret = 0; 849 850 exit_unlock: 851 mutex_unlock(&wsa885x->state_lock); 852 853 return ret; 854 } 855 856 static int wsa885x_codec_set_sysclk(struct snd_soc_dai *dai, int clk_id, 857 unsigned int freq, int dir) 858 { 859 static const struct reg_sequence pll_prep[] = { 860 { WSA885X_ANA_TOP_BG_TVP_OVRD_CTL, 0x03 }, 861 { WSA885X_DIG_CTRL0_SYS_CLK_SEL, 0x04 }, 862 { WSA885X_ANA_TOP_PLL_LOOPFILT_0, 0xB4 }, 863 { WSA885X_ANA_TOP_PLL_VCO_CTL, 0x00 }, 864 { WSA885X_ANA_TOP_PLL_OVRD_CTL, 0x00 }, 865 }; 866 static const struct reg_sequence pll_cleanup[] = { 867 { WSA885X_DIG_CTRL0_CLK_SOURCE_ENABLE, 0x00 }, 868 { WSA885X_DIG_CTRL0_SYS_CLK_SEL, 0x00 }, 869 { WSA885X_ANA_TOP_BG_TVP_OVRD_CTL, 0x00 }, 870 }; 871 struct wsa885x_priv *wsa885x; 872 u32 pll_div; 873 int ret = 0; 874 875 wsa885x = snd_soc_component_get_drvdata(dai->component); 876 877 if (!freq) 878 return -EINVAL; 879 if (WSA885X_CLK_RATE_FIXED % freq) 880 return -EINVAL; 881 pll_div = WSA885X_CLK_RATE_FIXED / freq; 882 if (pll_div > 0xff) 883 return -EINVAL; 884 885 regmap_multi_reg_write(wsa885x->regmap, pll_prep, ARRAY_SIZE(pll_prep)); 886 regmap_write(wsa885x->regmap, WSA885X_ANA_PLL_DIV_CTL_0, pll_div); 887 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_CLK_SOURCE_ENABLE, 0x02); 888 889 ret = wsa885x_wait_for_pll_lock(wsa885x); 890 if (ret) { 891 dev_err(wsa885x->dev, "PLL lock failed, aborting sysclk configuration\n"); 892 regmap_multi_reg_write(wsa885x->regmap, pll_cleanup, 893 ARRAY_SIZE(pll_cleanup)); 894 return ret; 895 } 896 897 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_SYS_CLK_SEL, 0x00); 898 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_POWER_FSM_CTL1, 0x01); 899 regmap_write(wsa885x->regmap, WSA885X_ANA_TOP_BG_TVP_OVRD_CTL, 0x00); 900 901 return 0; 902 } 903 904 static int wsa885x_codec_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 905 { 906 static const struct reg_sequence mute_regs[] = { 907 { WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x00 }, 908 { WSA885X_SMP_AMP_CTRL_STEREO_PDE23_REQ_PS, 0x03 }, 909 }; 910 static const struct reg_sequence mute_commit_regs[] = { 911 { WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X0, 0x01 }, 912 { WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X1, 0x01 }, 913 { WSA885X_DIG_CTRL0_SDCA_COMMIT, 0x01 }, 914 }; 915 static const struct reg_sequence unmute_prep_head_regs[] = { 916 { WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x00 }, 917 }; 918 static const struct reg_sequence unmute_prep_tail_regs[] = { 919 { WSA885X_SMP_AMP_CTRL_STEREO_IT21_CLUSERINDEX, 0x01 }, 920 { WSA885X_SMP_AMP_CTRL_STEREO_PPU21_POSTURENUMBER, 0x01 }, 921 }; 922 static const struct reg_sequence unmute_volume_regs[] = { 923 { WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X0_LSB, 0x00 }, 924 { WSA885X_SMP_AMP_CTRL_STEREO_FU21_CH_VOL_CH2X1_LSB, 0x00 }, 925 }; 926 static const struct reg_sequence unmute_commit_regs[] = { 927 { WSA885X_DIG_CTRL0_SDCA_COMMIT, 0x01 }, 928 { WSA885X_SMP_AMP_CTRL_STEREO_PDE23_REQ_PS, 0x00 }, 929 }; 930 static const struct reg_sequence unmute_finish_regs[] = { 931 { WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X0, 0x00 }, 932 { WSA885X_SMP_AMP_CTRL_STEREO_FU21_MUTE_CH2X1, 0x00 }, 933 { WSA885X_DIG_CTRL0_SDCA_COMMIT, 0x01 }, 934 }; 935 struct wsa885x_priv *wsa885x; 936 int ret = 0, ps0 = 0, ps3 = 3; 937 938 wsa885x = snd_soc_component_get_drvdata(dai->component); 939 940 if (stream != SNDRV_PCM_STREAM_PLAYBACK) 941 return 0; 942 943 mutex_lock(&wsa885x->state_lock); 944 945 if (wsa885x->usage_mode > WSA885X_USAGE_MODE_MAX) { 946 ret = -EINVAL; 947 goto exit_unlock; 948 } 949 950 if (!wsa885x_is_valid_rx_slot_mask(wsa885x->rx_slot_mask)) 951 wsa885x->rx_slot_mask = WSA885X_CHANNEL_STEREO; 952 953 if (mute) { 954 regmap_multi_reg_write(wsa885x->regmap, mute_regs, 955 ARRAY_SIZE(mute_regs)); 956 ret = wsa885x_wait_for_pde_state(wsa885x, ps3); 957 if (ret) { 958 dev_err(wsa885x->dev, 959 "PS3 transition failed: %d\n", ret); 960 } else { 961 regmap_multi_reg_write(wsa885x->regmap, mute_commit_regs, 962 ARRAY_SIZE(mute_commit_regs)); 963 } 964 } else { 965 regmap_multi_reg_write(wsa885x->regmap, unmute_prep_head_regs, 966 ARRAY_SIZE(unmute_prep_head_regs)); 967 regmap_write(wsa885x->regmap, WSA885X_SMP_AMP_CTRL_STEREO_OT23_USAGE, 968 wsa885x->usage_mode); 969 regmap_multi_reg_write(wsa885x->regmap, unmute_prep_tail_regs, 970 ARRAY_SIZE(unmute_prep_tail_regs)); 971 wsa885x_program_stereo_volume(wsa885x, wsa885x->stereo_vol_db, false); 972 regmap_multi_reg_write(wsa885x->regmap, unmute_volume_regs, 973 ARRAY_SIZE(unmute_volume_regs)); 974 regmap_multi_reg_write(wsa885x->regmap, unmute_commit_regs, 975 ARRAY_SIZE(unmute_commit_regs)); 976 ret = wsa885x_wait_for_pde_state(wsa885x, ps0); 977 if (ret) 978 goto exit_unlock; 979 980 if (wsa885x->rx_slot_mask == WSA885X_CHANNEL_STEREO) { 981 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_TDM_CH_RX, 982 WSA885X_I2S_TDM_CH_RX_CH0_EN | 983 WSA885X_I2S_TDM_CH_RX_CH3_EN); 984 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x03); 985 } else if (wsa885x->rx_slot_mask == WSA885X_CHANNEL_MONO_LEFT) { 986 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_TDM_CH_RX, 987 WSA885X_I2S_TDM_CH_RX_CH3_EN); 988 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x01); 989 } else if (wsa885x->rx_slot_mask == WSA885X_CHANNEL_MONO_RIGHT) { 990 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL1_I2S_TDM_CH_RX, 991 WSA885X_I2S_TDM_CH_RX_CH0_EN); 992 regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x02); 993 } 994 995 regmap_multi_reg_write(wsa885x->regmap, unmute_finish_regs, 996 ARRAY_SIZE(unmute_finish_regs)); 997 } 998 999 exit_unlock: 1000 mutex_unlock(&wsa885x->state_lock); 1001 1002 return ret; 1003 } 1004 1005 static int wsa885x_codec_hw_free(struct snd_pcm_substream *substream, 1006 struct snd_soc_dai *dai) 1007 { 1008 static const struct reg_sequence regs[] = { 1009 { WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x00 }, 1010 }; 1011 struct wsa885x_priv *wsa885x; 1012 1013 wsa885x = snd_soc_component_get_drvdata(dai->component); 1014 1015 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 1016 return 0; 1017 1018 mutex_lock(&wsa885x->state_lock); 1019 regmap_multi_reg_write(wsa885x->regmap, regs, ARRAY_SIZE(regs)); 1020 mutex_unlock(&wsa885x->state_lock); 1021 1022 return 0; 1023 } 1024 1025 static const struct snd_soc_dai_ops wsa885x_dai_ops = { 1026 .hw_params = wsa885x_codec_hw_params, 1027 .set_tdm_slot = wsa885x_codec_set_tdm_slot, 1028 .set_sysclk = wsa885x_codec_set_sysclk, 1029 .mute_stream = wsa885x_codec_mute_stream, 1030 .hw_free = wsa885x_codec_hw_free, 1031 }; 1032 1033 static struct snd_soc_dai_driver wsa885x_dai[] = { 1034 { 1035 .name = "wsa885x_dai_drv", 1036 .playback = { 1037 .stream_name = "WSA885X TDM Playback", 1038 .channels_min = 1, 1039 .channels_max = 2, 1040 .rates = WSA885X_RATES, 1041 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | 1042 SNDRV_PCM_FMTBIT_S32_LE, 1043 }, 1044 .ops = &wsa885x_dai_ops, 1045 }, 1046 }; 1047 1048 static void wsa885x_reset_assert(void *data) 1049 { 1050 struct wsa885x_priv *wsa885x = data; 1051 1052 if (wsa885x->sd_reset) 1053 reset_control_assert(wsa885x->sd_reset); 1054 else 1055 gpiod_direction_output(wsa885x->sd_n, 1); 1056 } 1057 1058 static void wsa885x_reset_deassert(struct wsa885x_priv *wsa885x) 1059 { 1060 if (wsa885x->sd_reset) 1061 reset_control_deassert(wsa885x->sd_reset); 1062 else 1063 gpiod_direction_output(wsa885x->sd_n, 0); 1064 } 1065 1066 static int wsa885x_get_reset(struct device *dev, struct wsa885x_priv *wsa885x) 1067 { 1068 wsa885x->sd_reset = devm_reset_control_get_optional_shared(dev, NULL); 1069 if (IS_ERR(wsa885x->sd_reset)) 1070 return dev_err_probe(dev, PTR_ERR(wsa885x->sd_reset), 1071 "Failed to get reset\n"); 1072 else if (wsa885x->sd_reset) 1073 return 0; 1074 1075 wsa885x->sd_n = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH); 1076 if (IS_ERR(wsa885x->sd_n)) 1077 return dev_err_probe(dev, PTR_ERR(wsa885x->sd_n), 1078 "Shutdown Control GPIO not found\n"); 1079 1080 return 0; 1081 } 1082 1083 static bool wsa885x_volatile_register(struct device *dev, unsigned int reg) 1084 { 1085 switch (reg) { 1086 case WSA885X_ANA_TOP_PLL_STATUS_0: 1087 case WSA885X_ANA_TOP_PLL_STATUS_1: 1088 case WSA885X_DIG_CTRL0_SDCA_COMMIT: 1089 case WSA885X_SMP_AMP_CTRL_STEREO_PDE23_ACT_PS: 1090 case WSA885X_SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID: 1091 case WSA885X_INTR_STATUS0: 1092 case WSA885X_INTR_STATUS0 + 1: 1093 case WSA885X_INTR_STATUS0 + 2: 1094 case WSA885X_INTR_CLEAR0: 1095 case WSA885X_INTR_CLEAR0 + 1: 1096 case WSA885X_INTR_CLEAR0 + 2: 1097 return true; 1098 default: 1099 return false; 1100 } 1101 } 1102 1103 static bool wsa885x_readable_register(struct device *dev, unsigned int reg) 1104 { 1105 if (reg == WSA885X_INTR_CLEAR0 || 1106 reg == WSA885X_INTR_CLEAR0 + 1 || 1107 reg == WSA885X_INTR_CLEAR0 + 2) 1108 return false; 1109 return reg <= 0x88ff; 1110 } 1111 1112 static bool wsa885x_writeable_register(struct device *dev, unsigned int reg) 1113 { 1114 if (reg > 0x88ff) 1115 return false; 1116 1117 switch (reg) { 1118 case WSA885X_ANA_TOP_PLL_STATUS_0: 1119 case WSA885X_ANA_TOP_PLL_STATUS_1: 1120 case WSA885X_INTR_STATUS0: 1121 case WSA885X_INTR_STATUS0 + 1: 1122 case WSA885X_INTR_STATUS0 + 2: 1123 case WSA885X_SMP_AMP_CTRL_STEREO_PDE23_ACT_PS: 1124 case WSA885X_SMP_AMP_CTRL_STEREO_CS21_CLOCK_VALID: 1125 return false; 1126 default: 1127 return true; 1128 } 1129 } 1130 1131 static const struct regmap_config wsa885x_regmap_cfg = { 1132 .reg_bits = 8, 1133 .val_bits = 8, 1134 .max_register = 0x88FF, 1135 .ranges = wsa885x_regmap_ranges, 1136 .num_ranges = ARRAY_SIZE(wsa885x_regmap_ranges), 1137 .reg_defaults = wsa885x_codec_reg_defaults, 1138 .num_reg_defaults = ARRAY_SIZE(wsa885x_codec_reg_defaults), 1139 .volatile_reg = wsa885x_volatile_register, 1140 .writeable_reg = wsa885x_writeable_register, 1141 .readable_reg = wsa885x_readable_register, 1142 .cache_type = REGCACHE_MAPLE, 1143 .use_single_read = true, 1144 .use_single_write = true, 1145 }; 1146 1147 static int wsa885x_component_probe(struct snd_soc_component *component) 1148 { 1149 struct wsa885x_priv *wsa885x = 1150 snd_soc_component_get_drvdata(component); 1151 int ret; 1152 1153 wsa885x->component = component; 1154 snd_soc_component_init_regmap(component, wsa885x->regmap); 1155 1156 ret = wsa885x_hw_init(wsa885x); 1157 if (ret) 1158 return ret; 1159 1160 return wsa885x_unmask_interrupts(wsa885x); 1161 } 1162 1163 static int wsa885x_stereo_gain_offset_get(struct snd_kcontrol *kcontrol, 1164 struct snd_ctl_elem_value *ucontrol) 1165 { 1166 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1167 struct wsa885x_priv *wsa885x = snd_soc_component_get_drvdata(component); 1168 int val; 1169 1170 mutex_lock(&wsa885x->state_lock); 1171 val = wsa885x->stereo_vol_db + 84; 1172 mutex_unlock(&wsa885x->state_lock); 1173 if (val < 0 || val > WSA885X_FU21_VOL_STEPS) 1174 return -ERANGE; 1175 1176 ucontrol->value.integer.value[0] = val; 1177 return 0; 1178 } 1179 1180 static int wsa885x_stereo_gain_offset_put(struct snd_kcontrol *kcontrol, 1181 struct snd_ctl_elem_value *ucontrol) 1182 { 1183 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1184 struct wsa885x_priv *wsa885x = snd_soc_component_get_drvdata(component); 1185 long val; 1186 int stereo_vol_db; 1187 1188 val = ucontrol->value.integer.value[0]; 1189 1190 if (val < 0 || val > WSA885X_FU21_VOL_STEPS) { 1191 dev_err(component->dev, "%s: Invalid range, Val: %ld\n", __func__, val); 1192 return -EINVAL; 1193 } 1194 1195 stereo_vol_db = (int)val - 84; 1196 1197 mutex_lock(&wsa885x->state_lock); 1198 if (wsa885x->stereo_vol_db == stereo_vol_db) { 1199 mutex_unlock(&wsa885x->state_lock); 1200 return 0; 1201 } 1202 1203 wsa885x_program_stereo_volume(wsa885x, stereo_vol_db, true); 1204 wsa885x->stereo_vol_db = stereo_vol_db; 1205 mutex_unlock(&wsa885x->state_lock); 1206 1207 return 1; 1208 } 1209 1210 static int wsa885x_usage_modes_get(struct snd_kcontrol *kcontrol, 1211 struct snd_ctl_elem_value *ucontrol) 1212 { 1213 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1214 struct wsa885x_priv *wsa885x = snd_soc_component_get_drvdata(component); 1215 1216 mutex_lock(&wsa885x->state_lock); 1217 if (wsa885x->usage_mode > WSA885X_USAGE_MODE_MAX) { 1218 mutex_unlock(&wsa885x->state_lock); 1219 return -ERANGE; 1220 } 1221 1222 ucontrol->value.integer.value[0] = wsa885x->usage_mode; 1223 mutex_unlock(&wsa885x->state_lock); 1224 1225 return 0; 1226 } 1227 1228 static int wsa885x_usage_modes_put(struct snd_kcontrol *kcontrol, 1229 struct snd_ctl_elem_value *ucontrol) 1230 { 1231 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1232 struct wsa885x_priv *wsa885x = snd_soc_component_get_drvdata(component); 1233 u32 val = ucontrol->value.integer.value[0]; 1234 1235 if (val > WSA885X_USAGE_MODE_MAX) 1236 return -EINVAL; 1237 1238 mutex_lock(&wsa885x->state_lock); 1239 if (wsa885x->usage_mode == val) { 1240 mutex_unlock(&wsa885x->state_lock); 1241 return 0; 1242 } 1243 1244 wsa885x->usage_mode = val; 1245 mutex_unlock(&wsa885x->state_lock); 1246 1247 return 1; 1248 } 1249 1250 static int wsa885x_rx_slot_mask_get(struct snd_kcontrol *kcontrol, 1251 struct snd_ctl_elem_value *ucontrol) 1252 { 1253 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1254 struct wsa885x_priv *wsa885x = snd_soc_component_get_drvdata(component); 1255 u32 mask; 1256 1257 mutex_lock(&wsa885x->state_lock); 1258 mask = wsa885x->rx_slot_mask; 1259 mutex_unlock(&wsa885x->state_lock); 1260 if (!wsa885x_is_valid_rx_slot_mask(mask)) 1261 return -ERANGE; 1262 1263 ucontrol->value.integer.value[0] = mask; 1264 1265 return 0; 1266 } 1267 1268 static int wsa885x_rx_slot_mask_put(struct snd_kcontrol *kcontrol, 1269 struct snd_ctl_elem_value *ucontrol) 1270 { 1271 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1272 struct wsa885x_priv *wsa885x = snd_soc_component_get_drvdata(component); 1273 u32 mask = ucontrol->value.integer.value[0]; 1274 1275 if (!wsa885x_is_valid_rx_slot_mask(mask)) 1276 return -EINVAL; 1277 1278 mutex_lock(&wsa885x->state_lock); 1279 if (wsa885x->rx_slot_mask == mask) { 1280 mutex_unlock(&wsa885x->state_lock); 1281 return 0; 1282 } 1283 1284 wsa885x->rx_slot_mask = mask; 1285 mutex_unlock(&wsa885x->state_lock); 1286 1287 return 1; 1288 } 1289 1290 static const struct snd_kcontrol_new wsa885x_snd_controls[] = { 1291 SOC_SINGLE_EXT("Usage Mode", SND_SOC_NOPM, 0, WSA885X_USAGE_MODE_MAX, 0, 1292 wsa885x_usage_modes_get, 1293 wsa885x_usage_modes_put), 1294 1295 SOC_SINGLE_EXT_TLV("Speaker Volume", SND_SOC_NOPM, 1296 0, WSA885X_FU21_VOL_STEPS, 0, 1297 wsa885x_stereo_gain_offset_get, 1298 wsa885x_stereo_gain_offset_put, 1299 wsa885x_fu21_digital_gain), 1300 1301 SOC_SINGLE_EXT("Rx Slot Mask", SND_SOC_NOPM, 0, 3, 0, 1302 wsa885x_rx_slot_mask_get, 1303 wsa885x_rx_slot_mask_put), 1304 }; 1305 1306 static const struct snd_soc_component_driver wsa885x_component = { 1307 .name = "wsa885x", 1308 .probe = wsa885x_component_probe, 1309 .controls = wsa885x_snd_controls, 1310 .num_controls = ARRAY_SIZE(wsa885x_snd_controls), 1311 }; 1312 1313 static irqreturn_t wsa885x_handle_irq(int irq_idx, void *data) 1314 { 1315 struct wsa885x_priv *wsa885x = data; 1316 1317 if (irq_idx < 0 || irq_idx >= WSA885X_IRQ_MAX) 1318 return IRQ_NONE; 1319 1320 switch (irq_idx) { 1321 case WSA885X_IRQ_INT_SAF2WAR: 1322 case WSA885X_IRQ_INT_WAR2SAF: 1323 case WSA885X_IRQ_INT_DISABLE: 1324 case WSA885X_IRQ_INT_INTR_GPIO1_PIN: 1325 case WSA885X_IRQ_INT_INTR_GPIO2_PIN: 1326 case WSA885X_IRQ_INT_PA0_OCP: 1327 case WSA885X_IRQ_INT_PA1_OCP: 1328 case WSA885X_IRQ_INT_CLIP0: 1329 case WSA885X_IRQ_INT_CLIP1: 1330 case WSA885X_IRQ_INT_CLK_WD: 1331 case WSA885X_IRQ_INT_BOP: 1332 case WSA885X_IRQ_INT_UVLO: 1333 case WSA885X_IRQ_INT_PCM_DATA0_DC: 1334 case WSA885X_IRQ_INT_PCM_DATA1_DC: 1335 case WSA885X_IRQ_INT_PLL_UNLOCKED: 1336 case WSA885X_IRQ_INT_PROT_MODE_CHANGE: 1337 case WSA885X_IRQ_INT_PB_CLOCK_VALID: 1338 case WSA885X_IRQ_INT_SENSE_CLOCK_VALID: 1339 break; 1340 case WSA885X_IRQ_INT_PCM_DATA0_WD: 1341 case WSA885X_IRQ_INT_PCM_DATA1_WD: 1342 if (irq_idx == WSA885X_IRQ_INT_PCM_DATA0_WD) 1343 wsa885x_toggle_irq_bit(wsa885x, WSA885X_DIG_CTRL0_PCM_DATA_WD0_CTL1, 1344 WSA885X_PCM_DATA_WD_CTL1_PCM_DATA_WD_EN_MASK); 1345 else 1346 wsa885x_toggle_irq_bit(wsa885x, WSA885X_DIG_CTRL0_PCM_DATA_WD1_CTL1, 1347 WSA885X_PCM_DATA_WD_CTL1_PCM_DATA_WD_EN_MASK); 1348 break; 1349 case WSA885X_IRQ_INT_PA0_FSM_ERR: 1350 case WSA885X_IRQ_INT_PA1_FSM_ERR: 1351 case WSA885X_IRQ_INT_MAIN_FSM_ERR: 1352 if (irq_idx == WSA885X_IRQ_INT_MAIN_FSM_ERR) { 1353 wsa885x_pulse_irq_bit(wsa885x, WSA885X_DIG_CTRL0_POWER_FSM_CTL0, 1354 WSA885X_POWER_FSM_CTL0_CLEAR_ERROR_MASK); 1355 } else if (irq_idx == WSA885X_IRQ_INT_PA0_FSM_ERR) { 1356 wsa885x_pulse_irq_bit(wsa885x, WSA885X_PA0_FSM_CTL0, 1357 WSA885X_PA_FSM_CTL0_CLEAR_ERROR_MASK); 1358 } else if (irq_idx == WSA885X_IRQ_INT_PA1_FSM_ERR) { 1359 wsa885x_pulse_irq_bit(wsa885x, WSA885X_PA1_FSM_CTL0, 1360 WSA885X_PA_FSM_CTL0_CLEAR_ERROR_MASK); 1361 } 1362 break; 1363 default: 1364 break; 1365 } 1366 1367 return IRQ_HANDLED; 1368 } 1369 1370 static irqreturn_t wsa885x_interrupt_handler(int irq, void *data) 1371 { 1372 static const unsigned int status_reg[WSA885X_NUM_REGS] = { 1373 WSA885X_INTR_STATUS0, 1374 WSA885X_INTR_STATUS0 + 1, 1375 WSA885X_INTR_STATUS0 + 2, 1376 }; 1377 static const unsigned int clear_reg[WSA885X_NUM_REGS] = { 1378 WSA885X_INTR_CLEAR0, 1379 WSA885X_INTR_CLEAR0 + 1, 1380 WSA885X_INTR_CLEAR0 + 2, 1381 }; 1382 unsigned int status[WSA885X_NUM_REGS] = { 0 }; 1383 struct wsa885x_priv *wsa885x = data; 1384 irqreturn_t handled = IRQ_NONE; 1385 irqreturn_t irq_ret; 1386 int i, bit, ret, irq_num; 1387 1388 for (i = 0; i < WSA885X_NUM_REGS; i++) { 1389 ret = regmap_read(wsa885x->regmap, status_reg[i], &status[i]); 1390 if (ret) { 1391 dev_err(wsa885x->dev, 1392 "Failed to read status_reg[%d] (0x%x): %d\n", 1393 i, status_reg[i], ret); 1394 status[i] = 0; 1395 continue; 1396 } 1397 } 1398 1399 for (i = 0; i < WSA885X_NUM_REGS; i++) { 1400 for (bit = 0; bit < 8; bit++) { 1401 if (status[i] & BIT(bit)) { 1402 irq_num = i * 8 + bit; 1403 regmap_write(wsa885x->regmap, clear_reg[i], BIT(bit)); 1404 regmap_write(wsa885x->regmap, clear_reg[i], 0); 1405 if (irq_num >= WSA885X_IRQ_MAX) { 1406 dev_warn_ratelimited(wsa885x->dev, 1407 "Unexpected IRQ bit %d (reg %d)\n", 1408 bit, i); 1409 handled = IRQ_HANDLED; 1410 continue; 1411 } 1412 irq_ret = wsa885x_handle_irq(irq_num, wsa885x); 1413 if (irq_ret == IRQ_HANDLED) 1414 handled = IRQ_HANDLED; 1415 } 1416 } 1417 } 1418 return handled; 1419 } 1420 1421 static int wsa885x_register_irq(struct wsa885x_priv *wsa885x) 1422 { 1423 if (!wsa885x->client->irq) 1424 return dev_err_probe(wsa885x->dev, -EINVAL, 1425 "IRQ is not configured\n"); 1426 1427 return devm_request_threaded_irq(wsa885x->dev, wsa885x->client->irq, NULL, 1428 wsa885x_interrupt_handler, 1429 IRQF_ONESHOT, 1430 dev_name(wsa885x->dev), wsa885x); 1431 } 1432 1433 static int wsa885x_probe(struct i2c_client *client) 1434 { 1435 struct wsa885x_priv *wsa885x; 1436 const struct snd_soc_component_driver *component_driver = &wsa885x_component; 1437 const char *battery_config; 1438 unsigned int i; 1439 int ret; 1440 struct device *dev = &client->dev; 1441 1442 wsa885x = devm_kzalloc(dev, sizeof(*wsa885x), GFP_KERNEL); 1443 if (!wsa885x) 1444 return -ENOMEM; 1445 1446 wsa885x->client = client; 1447 wsa885x->dev = dev; 1448 wsa885x->stereo_vol_db = -84; 1449 wsa885x->rx_slot_mask = WSA885X_CHANNEL_STEREO; 1450 mutex_init(&wsa885x->state_lock); 1451 wsa885x->regmap = devm_regmap_init_i2c(client, &wsa885x_regmap_cfg); 1452 1453 if (IS_ERR(wsa885x->regmap)) 1454 return PTR_ERR(wsa885x->regmap); 1455 1456 ret = device_property_read_string(dev, "qcom,battery-config", 1457 &battery_config); 1458 if (ret) { 1459 wsa885x->batt_conf = WSA885X_BATT_1S; 1460 } else if (!strcmp(battery_config, "1s")) { 1461 wsa885x->batt_conf = WSA885X_BATT_1S; 1462 } else if (!strcmp(battery_config, "2s")) { 1463 wsa885x->batt_conf = WSA885X_BATT_2S; 1464 } else { 1465 return dev_err_probe(dev, -EINVAL, 1466 "Invalid battery config %s (expected 1s or 2s)\n", 1467 battery_config); 1468 } 1469 1470 for (i = 0; i < ARRAY_SIZE(wsa885x_supply_name); i++) { 1471 ret = devm_regulator_get_enable(dev, wsa885x_supply_name[i]); 1472 if (ret) 1473 return dev_err_probe(dev, ret, 1474 "Failed to enable regulator %s\n", 1475 wsa885x_supply_name[i]); 1476 } 1477 1478 ret = wsa885x_get_reset(dev, wsa885x); 1479 if (ret) 1480 return ret; 1481 1482 wsa885x_reset_deassert(wsa885x); 1483 usleep_range(5000, 5500); 1484 1485 ret = devm_add_action_or_reset(dev, wsa885x_reset_assert, wsa885x); 1486 if (ret) 1487 return dev_err_probe(dev, ret, "devm_add_action_or_reset failed\n"); 1488 1489 i2c_set_clientdata(client, wsa885x); 1490 1491 ret = wsa885x_register_irq(wsa885x); 1492 if (ret) 1493 return dev_err_probe(dev, ret, "wsa885x irq registration failed\n"); 1494 1495 ret = devm_snd_soc_register_component(dev, component_driver, 1496 wsa885x_dai, 1497 ARRAY_SIZE(wsa885x_dai)); 1498 if (ret) 1499 return dev_err_probe(dev, ret, "Codec component registration failed\n"); 1500 1501 return 0; 1502 } 1503 1504 static const struct of_device_id wsa885x_dt_match[] = { 1505 { 1506 .compatible = "qcom,wsa8855", 1507 }, 1508 {} 1509 }; 1510 MODULE_DEVICE_TABLE(of, wsa885x_dt_match); 1511 1512 static const struct i2c_device_id wsa885x_id[] = { 1513 { 1514 .name = "wsa885x", 1515 .driver_data = 0, 1516 }, 1517 {} 1518 }; 1519 MODULE_DEVICE_TABLE(i2c, wsa885x_id); 1520 1521 static struct i2c_driver wsa885x_driver = { 1522 .driver = { 1523 .name = "wsa885x", 1524 .of_match_table = wsa885x_dt_match, 1525 }, 1526 .probe = wsa885x_probe, 1527 .id_table = wsa885x_id, 1528 }; 1529 1530 module_i2c_driver(wsa885x_driver); 1531 1532 MODULE_DESCRIPTION("ASoC WSA885X Stereo Smart PA Codec Driver"); 1533 MODULE_LICENSE("GPL"); 1534