1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2017, The Linux Foundation. 3 // Copyright (c) 2019, Linaro Limited 4 5 #include <linux/bitops.h> 6 #include <linux/gpio.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/module.h> 9 #include <linux/regmap.h> 10 #include <linux/slab.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_registers.h> 14 #include <linux/soundwire/sdw_type.h> 15 #include <sound/soc.h> 16 #include <sound/tlv.h> 17 18 #define WSA881X_DIGITAL_BASE 0x3000 19 #define WSA881X_ANALOG_BASE 0x3100 20 21 /* Digital register address space */ 22 #define WSA881X_CHIP_ID0 (WSA881X_DIGITAL_BASE + 0x0000) 23 #define WSA881X_CHIP_ID1 (WSA881X_DIGITAL_BASE + 0x0001) 24 #define WSA881X_CHIP_ID2 (WSA881X_DIGITAL_BASE + 0x0002) 25 #define WSA881X_CHIP_ID3 (WSA881X_DIGITAL_BASE + 0x0003) 26 #define WSA881X_BUS_ID (WSA881X_DIGITAL_BASE + 0x0004) 27 #define WSA881X_CDC_RST_CTL (WSA881X_DIGITAL_BASE + 0x0005) 28 #define WSA881X_CDC_TOP_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0006) 29 #define WSA881X_CDC_ANA_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0007) 30 #define WSA881X_CDC_DIG_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0008) 31 #define WSA881X_CLOCK_CONFIG (WSA881X_DIGITAL_BASE + 0x0009) 32 #define WSA881X_ANA_CTL (WSA881X_DIGITAL_BASE + 0x000A) 33 #define WSA881X_SWR_RESET_EN (WSA881X_DIGITAL_BASE + 0x000B) 34 #define WSA881X_RESET_CTL (WSA881X_DIGITAL_BASE + 0x000C) 35 #define WSA881X_TADC_VALUE_CTL (WSA881X_DIGITAL_BASE + 0x000F) 36 #define WSA881X_TEMP_DETECT_CTL (WSA881X_DIGITAL_BASE + 0x0010) 37 #define WSA881X_TEMP_MSB (WSA881X_DIGITAL_BASE + 0x0011) 38 #define WSA881X_TEMP_LSB (WSA881X_DIGITAL_BASE + 0x0012) 39 #define WSA881X_TEMP_CONFIG0 (WSA881X_DIGITAL_BASE + 0x0013) 40 #define WSA881X_TEMP_CONFIG1 (WSA881X_DIGITAL_BASE + 0x0014) 41 #define WSA881X_CDC_CLIP_CTL (WSA881X_DIGITAL_BASE + 0x0015) 42 #define WSA881X_SDM_PDM9_LSB (WSA881X_DIGITAL_BASE + 0x0016) 43 #define WSA881X_SDM_PDM9_MSB (WSA881X_DIGITAL_BASE + 0x0017) 44 #define WSA881X_CDC_RX_CTL (WSA881X_DIGITAL_BASE + 0x0018) 45 #define WSA881X_DEM_BYPASS_DATA0 (WSA881X_DIGITAL_BASE + 0x0019) 46 #define WSA881X_DEM_BYPASS_DATA1 (WSA881X_DIGITAL_BASE + 0x001A) 47 #define WSA881X_DEM_BYPASS_DATA2 (WSA881X_DIGITAL_BASE + 0x001B) 48 #define WSA881X_DEM_BYPASS_DATA3 (WSA881X_DIGITAL_BASE + 0x001C) 49 #define WSA881X_OTP_CTRL0 (WSA881X_DIGITAL_BASE + 0x001D) 50 #define WSA881X_OTP_CTRL1 (WSA881X_DIGITAL_BASE + 0x001E) 51 #define WSA881X_HDRIVE_CTL_GROUP1 (WSA881X_DIGITAL_BASE + 0x001F) 52 #define WSA881X_INTR_MODE (WSA881X_DIGITAL_BASE + 0x0020) 53 #define WSA881X_INTR_MASK (WSA881X_DIGITAL_BASE + 0x0021) 54 #define WSA881X_INTR_STATUS (WSA881X_DIGITAL_BASE + 0x0022) 55 #define WSA881X_INTR_CLEAR (WSA881X_DIGITAL_BASE + 0x0023) 56 #define WSA881X_INTR_LEVEL (WSA881X_DIGITAL_BASE + 0x0024) 57 #define WSA881X_INTR_SET (WSA881X_DIGITAL_BASE + 0x0025) 58 #define WSA881X_INTR_TEST (WSA881X_DIGITAL_BASE + 0x0026) 59 #define WSA881X_PDM_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0030) 60 #define WSA881X_ATE_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0031) 61 #define WSA881X_PIN_CTL_MODE (WSA881X_DIGITAL_BASE + 0x0032) 62 #define WSA881X_PIN_CTL_OE (WSA881X_DIGITAL_BASE + 0x0033) 63 #define WSA881X_PIN_WDATA_IOPAD (WSA881X_DIGITAL_BASE + 0x0034) 64 #define WSA881X_PIN_STATUS (WSA881X_DIGITAL_BASE + 0x0035) 65 #define WSA881X_DIG_DEBUG_MODE (WSA881X_DIGITAL_BASE + 0x0037) 66 #define WSA881X_DIG_DEBUG_SEL (WSA881X_DIGITAL_BASE + 0x0038) 67 #define WSA881X_DIG_DEBUG_EN (WSA881X_DIGITAL_BASE + 0x0039) 68 #define WSA881X_SWR_HM_TEST1 (WSA881X_DIGITAL_BASE + 0x003B) 69 #define WSA881X_SWR_HM_TEST2 (WSA881X_DIGITAL_BASE + 0x003C) 70 #define WSA881X_TEMP_DETECT_DBG_CTL (WSA881X_DIGITAL_BASE + 0x003D) 71 #define WSA881X_TEMP_DEBUG_MSB (WSA881X_DIGITAL_BASE + 0x003E) 72 #define WSA881X_TEMP_DEBUG_LSB (WSA881X_DIGITAL_BASE + 0x003F) 73 #define WSA881X_SAMPLE_EDGE_SEL (WSA881X_DIGITAL_BASE + 0x0044) 74 #define WSA881X_IOPAD_CTL (WSA881X_DIGITAL_BASE + 0x0045) 75 #define WSA881X_SPARE_0 (WSA881X_DIGITAL_BASE + 0x0050) 76 #define WSA881X_SPARE_1 (WSA881X_DIGITAL_BASE + 0x0051) 77 #define WSA881X_SPARE_2 (WSA881X_DIGITAL_BASE + 0x0052) 78 #define WSA881X_OTP_REG_0 (WSA881X_DIGITAL_BASE + 0x0080) 79 #define WSA881X_OTP_REG_1 (WSA881X_DIGITAL_BASE + 0x0081) 80 #define WSA881X_OTP_REG_2 (WSA881X_DIGITAL_BASE + 0x0082) 81 #define WSA881X_OTP_REG_3 (WSA881X_DIGITAL_BASE + 0x0083) 82 #define WSA881X_OTP_REG_4 (WSA881X_DIGITAL_BASE + 0x0084) 83 #define WSA881X_OTP_REG_5 (WSA881X_DIGITAL_BASE + 0x0085) 84 #define WSA881X_OTP_REG_6 (WSA881X_DIGITAL_BASE + 0x0086) 85 #define WSA881X_OTP_REG_7 (WSA881X_DIGITAL_BASE + 0x0087) 86 #define WSA881X_OTP_REG_8 (WSA881X_DIGITAL_BASE + 0x0088) 87 #define WSA881X_OTP_REG_9 (WSA881X_DIGITAL_BASE + 0x0089) 88 #define WSA881X_OTP_REG_10 (WSA881X_DIGITAL_BASE + 0x008A) 89 #define WSA881X_OTP_REG_11 (WSA881X_DIGITAL_BASE + 0x008B) 90 #define WSA881X_OTP_REG_12 (WSA881X_DIGITAL_BASE + 0x008C) 91 #define WSA881X_OTP_REG_13 (WSA881X_DIGITAL_BASE + 0x008D) 92 #define WSA881X_OTP_REG_14 (WSA881X_DIGITAL_BASE + 0x008E) 93 #define WSA881X_OTP_REG_15 (WSA881X_DIGITAL_BASE + 0x008F) 94 #define WSA881X_OTP_REG_16 (WSA881X_DIGITAL_BASE + 0x0090) 95 #define WSA881X_OTP_REG_17 (WSA881X_DIGITAL_BASE + 0x0091) 96 #define WSA881X_OTP_REG_18 (WSA881X_DIGITAL_BASE + 0x0092) 97 #define WSA881X_OTP_REG_19 (WSA881X_DIGITAL_BASE + 0x0093) 98 #define WSA881X_OTP_REG_20 (WSA881X_DIGITAL_BASE + 0x0094) 99 #define WSA881X_OTP_REG_21 (WSA881X_DIGITAL_BASE + 0x0095) 100 #define WSA881X_OTP_REG_22 (WSA881X_DIGITAL_BASE + 0x0096) 101 #define WSA881X_OTP_REG_23 (WSA881X_DIGITAL_BASE + 0x0097) 102 #define WSA881X_OTP_REG_24 (WSA881X_DIGITAL_BASE + 0x0098) 103 #define WSA881X_OTP_REG_25 (WSA881X_DIGITAL_BASE + 0x0099) 104 #define WSA881X_OTP_REG_26 (WSA881X_DIGITAL_BASE + 0x009A) 105 #define WSA881X_OTP_REG_27 (WSA881X_DIGITAL_BASE + 0x009B) 106 #define WSA881X_OTP_REG_28 (WSA881X_DIGITAL_BASE + 0x009C) 107 #define WSA881X_OTP_REG_29 (WSA881X_DIGITAL_BASE + 0x009D) 108 #define WSA881X_OTP_REG_30 (WSA881X_DIGITAL_BASE + 0x009E) 109 #define WSA881X_OTP_REG_31 (WSA881X_DIGITAL_BASE + 0x009F) 110 #define WSA881X_OTP_REG_63 (WSA881X_DIGITAL_BASE + 0x00BF) 111 112 /* Analog Register address space */ 113 #define WSA881X_BIAS_REF_CTRL (WSA881X_ANALOG_BASE + 0x0000) 114 #define WSA881X_BIAS_TEST (WSA881X_ANALOG_BASE + 0x0001) 115 #define WSA881X_BIAS_BIAS (WSA881X_ANALOG_BASE + 0x0002) 116 #define WSA881X_TEMP_OP (WSA881X_ANALOG_BASE + 0x0003) 117 #define WSA881X_TEMP_IREF_CTRL (WSA881X_ANALOG_BASE + 0x0004) 118 #define WSA881X_TEMP_ISENS_CTRL (WSA881X_ANALOG_BASE + 0x0005) 119 #define WSA881X_TEMP_CLK_CTRL (WSA881X_ANALOG_BASE + 0x0006) 120 #define WSA881X_TEMP_TEST (WSA881X_ANALOG_BASE + 0x0007) 121 #define WSA881X_TEMP_BIAS (WSA881X_ANALOG_BASE + 0x0008) 122 #define WSA881X_TEMP_ADC_CTRL (WSA881X_ANALOG_BASE + 0x0009) 123 #define WSA881X_TEMP_DOUT_MSB (WSA881X_ANALOG_BASE + 0x000A) 124 #define WSA881X_TEMP_DOUT_LSB (WSA881X_ANALOG_BASE + 0x000B) 125 #define WSA881X_ADC_EN_MODU_V (WSA881X_ANALOG_BASE + 0x0010) 126 #define WSA881X_ADC_EN_MODU_I (WSA881X_ANALOG_BASE + 0x0011) 127 #define WSA881X_ADC_EN_DET_TEST_V (WSA881X_ANALOG_BASE + 0x0012) 128 #define WSA881X_ADC_EN_DET_TEST_I (WSA881X_ANALOG_BASE + 0x0013) 129 #define WSA881X_ADC_SEL_IBIAS (WSA881X_ANALOG_BASE + 0x0014) 130 #define WSA881X_ADC_EN_SEL_IBAIS (WSA881X_ANALOG_BASE + 0x0015) 131 #define WSA881X_SPKR_DRV_EN (WSA881X_ANALOG_BASE + 0x001A) 132 #define WSA881X_SPKR_DRV_GAIN (WSA881X_ANALOG_BASE + 0x001B) 133 #define WSA881X_PA_GAIN_SEL_MASK BIT(3) 134 #define WSA881X_PA_GAIN_SEL_REG BIT(3) 135 #define WSA881X_PA_GAIN_SEL_DRE 0 136 #define WSA881X_SPKR_PAG_GAIN_MASK GENMASK(7, 4) 137 #define WSA881X_SPKR_DAC_CTL (WSA881X_ANALOG_BASE + 0x001C) 138 #define WSA881X_SPKR_DRV_DBG (WSA881X_ANALOG_BASE + 0x001D) 139 #define WSA881X_SPKR_PWRSTG_DBG (WSA881X_ANALOG_BASE + 0x001E) 140 #define WSA881X_SPKR_OCP_CTL (WSA881X_ANALOG_BASE + 0x001F) 141 #define WSA881X_SPKR_OCP_MASK GENMASK(7, 6) 142 #define WSA881X_SPKR_OCP_EN BIT(7) 143 #define WSA881X_SPKR_OCP_HOLD BIT(6) 144 #define WSA881X_SPKR_CLIP_CTL (WSA881X_ANALOG_BASE + 0x0020) 145 #define WSA881X_SPKR_BBM_CTL (WSA881X_ANALOG_BASE + 0x0021) 146 #define WSA881X_SPKR_MISC_CTL1 (WSA881X_ANALOG_BASE + 0x0022) 147 #define WSA881X_SPKR_MISC_CTL2 (WSA881X_ANALOG_BASE + 0x0023) 148 #define WSA881X_SPKR_BIAS_INT (WSA881X_ANALOG_BASE + 0x0024) 149 #define WSA881X_SPKR_PA_INT (WSA881X_ANALOG_BASE + 0x0025) 150 #define WSA881X_SPKR_BIAS_CAL (WSA881X_ANALOG_BASE + 0x0026) 151 #define WSA881X_SPKR_BIAS_PSRR (WSA881X_ANALOG_BASE + 0x0027) 152 #define WSA881X_SPKR_STATUS1 (WSA881X_ANALOG_BASE + 0x0028) 153 #define WSA881X_SPKR_STATUS2 (WSA881X_ANALOG_BASE + 0x0029) 154 #define WSA881X_BOOST_EN_CTL (WSA881X_ANALOG_BASE + 0x002A) 155 #define WSA881X_BOOST_EN_MASK BIT(7) 156 #define WSA881X_BOOST_EN BIT(7) 157 #define WSA881X_BOOST_CURRENT_LIMIT (WSA881X_ANALOG_BASE + 0x002B) 158 #define WSA881X_BOOST_PS_CTL (WSA881X_ANALOG_BASE + 0x002C) 159 #define WSA881X_BOOST_PRESET_OUT1 (WSA881X_ANALOG_BASE + 0x002D) 160 #define WSA881X_BOOST_PRESET_OUT2 (WSA881X_ANALOG_BASE + 0x002E) 161 #define WSA881X_BOOST_FORCE_OUT (WSA881X_ANALOG_BASE + 0x002F) 162 #define WSA881X_BOOST_LDO_PROG (WSA881X_ANALOG_BASE + 0x0030) 163 #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB (WSA881X_ANALOG_BASE + 0x0031) 164 #define WSA881X_BOOST_RON_CTL (WSA881X_ANALOG_BASE + 0x0032) 165 #define WSA881X_BOOST_LOOP_STABILITY (WSA881X_ANALOG_BASE + 0x0033) 166 #define WSA881X_BOOST_ZX_CTL (WSA881X_ANALOG_BASE + 0x0034) 167 #define WSA881X_BOOST_START_CTL (WSA881X_ANALOG_BASE + 0x0035) 168 #define WSA881X_BOOST_MISC1_CTL (WSA881X_ANALOG_BASE + 0x0036) 169 #define WSA881X_BOOST_MISC2_CTL (WSA881X_ANALOG_BASE + 0x0037) 170 #define WSA881X_BOOST_MISC3_CTL (WSA881X_ANALOG_BASE + 0x0038) 171 #define WSA881X_BOOST_ATEST_CTL (WSA881X_ANALOG_BASE + 0x0039) 172 #define WSA881X_SPKR_PROT_FE_GAIN (WSA881X_ANALOG_BASE + 0x003A) 173 #define WSA881X_SPKR_PROT_FE_CM_LDO_SET (WSA881X_ANALOG_BASE + 0x003B) 174 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x003C) 175 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2 (WSA881X_ANALOG_BASE + 0x003D) 176 #define WSA881X_SPKR_PROT_ATEST1 (WSA881X_ANALOG_BASE + 0x003E) 177 #define WSA881X_SPKR_PROT_ATEST2 (WSA881X_ANALOG_BASE + 0x003F) 178 #define WSA881X_SPKR_PROT_FE_VSENSE_VCM (WSA881X_ANALOG_BASE + 0x0040) 179 #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x0041) 180 #define WSA881X_BONGO_RESRV_REG1 (WSA881X_ANALOG_BASE + 0x0042) 181 #define WSA881X_BONGO_RESRV_REG2 (WSA881X_ANALOG_BASE + 0x0043) 182 #define WSA881X_SPKR_PROT_SAR (WSA881X_ANALOG_BASE + 0x0044) 183 #define WSA881X_SPKR_STATUS3 (WSA881X_ANALOG_BASE + 0x0045) 184 185 #define SWRS_SCP_FRAME_CTRL_BANK(m) (0x60 + 0x10 * (m)) 186 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m)) 187 #define SWR_SLV_MAX_REG_ADDR 0x390 188 #define SWR_SLV_START_REG_ADDR 0x40 189 #define SWR_SLV_MAX_BUF_LEN 20 190 #define BYTES_PER_LINE 12 191 #define SWR_SLV_RD_BUF_LEN 8 192 #define SWR_SLV_WR_BUF_LEN 32 193 #define SWR_SLV_MAX_DEVICES 2 194 #define WSA881X_MAX_SWR_PORTS 4 195 #define WSA881X_VERSION_ENTRY_SIZE 27 196 #define WSA881X_OCP_CTL_TIMER_SEC 2 197 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25 198 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60 199 #define WSA881X_PROBE_TIMEOUT 1000 200 201 #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 202 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 203 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 204 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 205 .tlv.p = (tlv_array), \ 206 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 207 .put = wsa881x_put_pa_gain, \ 208 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } 209 210 static struct reg_default wsa881x_defaults[] = { 211 { WSA881X_CHIP_ID0, 0x00 }, 212 { WSA881X_CHIP_ID1, 0x00 }, 213 { WSA881X_CHIP_ID2, 0x00 }, 214 { WSA881X_CHIP_ID3, 0x02 }, 215 { WSA881X_BUS_ID, 0x00 }, 216 { WSA881X_CDC_RST_CTL, 0x00 }, 217 { WSA881X_CDC_TOP_CLK_CTL, 0x03 }, 218 { WSA881X_CDC_ANA_CLK_CTL, 0x00 }, 219 { WSA881X_CDC_DIG_CLK_CTL, 0x00 }, 220 { WSA881X_CLOCK_CONFIG, 0x00 }, 221 { WSA881X_ANA_CTL, 0x08 }, 222 { WSA881X_SWR_RESET_EN, 0x00 }, 223 { WSA881X_TEMP_DETECT_CTL, 0x01 }, 224 { WSA881X_TEMP_MSB, 0x00 }, 225 { WSA881X_TEMP_LSB, 0x00 }, 226 { WSA881X_TEMP_CONFIG0, 0x00 }, 227 { WSA881X_TEMP_CONFIG1, 0x00 }, 228 { WSA881X_CDC_CLIP_CTL, 0x03 }, 229 { WSA881X_SDM_PDM9_LSB, 0x00 }, 230 { WSA881X_SDM_PDM9_MSB, 0x00 }, 231 { WSA881X_CDC_RX_CTL, 0x7E }, 232 { WSA881X_DEM_BYPASS_DATA0, 0x00 }, 233 { WSA881X_DEM_BYPASS_DATA1, 0x00 }, 234 { WSA881X_DEM_BYPASS_DATA2, 0x00 }, 235 { WSA881X_DEM_BYPASS_DATA3, 0x00 }, 236 { WSA881X_OTP_CTRL0, 0x00 }, 237 { WSA881X_OTP_CTRL1, 0x00 }, 238 { WSA881X_HDRIVE_CTL_GROUP1, 0x00 }, 239 { WSA881X_INTR_MODE, 0x00 }, 240 { WSA881X_INTR_STATUS, 0x00 }, 241 { WSA881X_INTR_CLEAR, 0x00 }, 242 { WSA881X_INTR_LEVEL, 0x00 }, 243 { WSA881X_INTR_SET, 0x00 }, 244 { WSA881X_INTR_TEST, 0x00 }, 245 { WSA881X_PDM_TEST_MODE, 0x00 }, 246 { WSA881X_ATE_TEST_MODE, 0x00 }, 247 { WSA881X_PIN_CTL_MODE, 0x00 }, 248 { WSA881X_PIN_CTL_OE, 0x00 }, 249 { WSA881X_PIN_WDATA_IOPAD, 0x00 }, 250 { WSA881X_PIN_STATUS, 0x00 }, 251 { WSA881X_DIG_DEBUG_MODE, 0x00 }, 252 { WSA881X_DIG_DEBUG_SEL, 0x00 }, 253 { WSA881X_DIG_DEBUG_EN, 0x00 }, 254 { WSA881X_SWR_HM_TEST1, 0x08 }, 255 { WSA881X_SWR_HM_TEST2, 0x00 }, 256 { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 }, 257 { WSA881X_TEMP_DEBUG_MSB, 0x00 }, 258 { WSA881X_TEMP_DEBUG_LSB, 0x00 }, 259 { WSA881X_SAMPLE_EDGE_SEL, 0x0C }, 260 { WSA881X_SPARE_0, 0x00 }, 261 { WSA881X_SPARE_1, 0x00 }, 262 { WSA881X_SPARE_2, 0x00 }, 263 { WSA881X_OTP_REG_0, 0x01 }, 264 { WSA881X_OTP_REG_1, 0xFF }, 265 { WSA881X_OTP_REG_2, 0xC0 }, 266 { WSA881X_OTP_REG_3, 0xFF }, 267 { WSA881X_OTP_REG_4, 0xC0 }, 268 { WSA881X_OTP_REG_5, 0xFF }, 269 { WSA881X_OTP_REG_6, 0xFF }, 270 { WSA881X_OTP_REG_7, 0xFF }, 271 { WSA881X_OTP_REG_8, 0xFF }, 272 { WSA881X_OTP_REG_9, 0xFF }, 273 { WSA881X_OTP_REG_10, 0xFF }, 274 { WSA881X_OTP_REG_11, 0xFF }, 275 { WSA881X_OTP_REG_12, 0xFF }, 276 { WSA881X_OTP_REG_13, 0xFF }, 277 { WSA881X_OTP_REG_14, 0xFF }, 278 { WSA881X_OTP_REG_15, 0xFF }, 279 { WSA881X_OTP_REG_16, 0xFF }, 280 { WSA881X_OTP_REG_17, 0xFF }, 281 { WSA881X_OTP_REG_18, 0xFF }, 282 { WSA881X_OTP_REG_19, 0xFF }, 283 { WSA881X_OTP_REG_20, 0xFF }, 284 { WSA881X_OTP_REG_21, 0xFF }, 285 { WSA881X_OTP_REG_22, 0xFF }, 286 { WSA881X_OTP_REG_23, 0xFF }, 287 { WSA881X_OTP_REG_24, 0x03 }, 288 { WSA881X_OTP_REG_25, 0x01 }, 289 { WSA881X_OTP_REG_26, 0x03 }, 290 { WSA881X_OTP_REG_27, 0x11 }, 291 { WSA881X_OTP_REG_63, 0x40 }, 292 /* WSA881x Analog registers */ 293 { WSA881X_BIAS_REF_CTRL, 0x6C }, 294 { WSA881X_BIAS_TEST, 0x16 }, 295 { WSA881X_BIAS_BIAS, 0xF0 }, 296 { WSA881X_TEMP_OP, 0x00 }, 297 { WSA881X_TEMP_IREF_CTRL, 0x56 }, 298 { WSA881X_TEMP_ISENS_CTRL, 0x47 }, 299 { WSA881X_TEMP_CLK_CTRL, 0x87 }, 300 { WSA881X_TEMP_TEST, 0x00 }, 301 { WSA881X_TEMP_BIAS, 0x51 }, 302 { WSA881X_TEMP_DOUT_MSB, 0x00 }, 303 { WSA881X_TEMP_DOUT_LSB, 0x00 }, 304 { WSA881X_ADC_EN_MODU_V, 0x00 }, 305 { WSA881X_ADC_EN_MODU_I, 0x00 }, 306 { WSA881X_ADC_EN_DET_TEST_V, 0x00 }, 307 { WSA881X_ADC_EN_DET_TEST_I, 0x00 }, 308 { WSA881X_ADC_EN_SEL_IBAIS, 0x10 }, 309 { WSA881X_SPKR_DRV_EN, 0x74 }, 310 { WSA881X_SPKR_DRV_DBG, 0x15 }, 311 { WSA881X_SPKR_PWRSTG_DBG, 0x00 }, 312 { WSA881X_SPKR_OCP_CTL, 0xD4 }, 313 { WSA881X_SPKR_CLIP_CTL, 0x90 }, 314 { WSA881X_SPKR_PA_INT, 0x54 }, 315 { WSA881X_SPKR_BIAS_CAL, 0xAC }, 316 { WSA881X_SPKR_STATUS1, 0x00 }, 317 { WSA881X_SPKR_STATUS2, 0x00 }, 318 { WSA881X_BOOST_EN_CTL, 0x18 }, 319 { WSA881X_BOOST_CURRENT_LIMIT, 0x7A }, 320 { WSA881X_BOOST_PRESET_OUT2, 0x70 }, 321 { WSA881X_BOOST_FORCE_OUT, 0x0E }, 322 { WSA881X_BOOST_LDO_PROG, 0x16 }, 323 { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 }, 324 { WSA881X_BOOST_RON_CTL, 0x0F }, 325 { WSA881X_BOOST_ZX_CTL, 0x34 }, 326 { WSA881X_BOOST_START_CTL, 0x23 }, 327 { WSA881X_BOOST_MISC1_CTL, 0x80 }, 328 { WSA881X_BOOST_MISC2_CTL, 0x00 }, 329 { WSA881X_BOOST_MISC3_CTL, 0x00 }, 330 { WSA881X_BOOST_ATEST_CTL, 0x00 }, 331 { WSA881X_SPKR_PROT_FE_GAIN, 0x46 }, 332 { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B }, 333 { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D }, 334 { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D }, 335 { WSA881X_SPKR_PROT_ATEST1, 0x01 }, 336 { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D }, 337 { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D }, 338 { WSA881X_SPKR_PROT_SAR, 0x00 }, 339 { WSA881X_SPKR_STATUS3, 0x00 }, 340 }; 341 342 static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = { 343 { WSA881X_SPKR_DRV_GAIN, 0x41, 0 }, 344 { WSA881X_SPKR_MISC_CTL1, 0x87, 0 }, 345 }; 346 347 static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = { 348 { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 }, 349 { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 }, 350 { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 }, 351 }; 352 353 /* Default register reset values for WSA881x rev 2.0 */ 354 static struct reg_sequence wsa881x_rev_2_0[] = { 355 { WSA881X_RESET_CTL, 0x00, 0x00 }, 356 { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 }, 357 { WSA881X_INTR_MASK, 0x1B, 0x00 }, 358 { WSA881X_IOPAD_CTL, 0x00, 0x00 }, 359 { WSA881X_OTP_REG_28, 0x3F, 0x00 }, 360 { WSA881X_OTP_REG_29, 0x3F, 0x00 }, 361 { WSA881X_OTP_REG_30, 0x01, 0x00 }, 362 { WSA881X_OTP_REG_31, 0x01, 0x00 }, 363 { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 }, 364 { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 }, 365 { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 }, 366 { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 }, 367 { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 }, 368 { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 }, 369 { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 }, 370 { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 }, 371 { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 }, 372 { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 }, 373 { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 }, 374 { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 }, 375 { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 }, 376 { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 }, 377 { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 }, 378 }; 379 380 enum wsa_port_ids { 381 WSA881X_PORT_DAC, 382 WSA881X_PORT_COMP, 383 WSA881X_PORT_BOOST, 384 WSA881X_PORT_VISENSE, 385 }; 386 387 /* 4 ports */ 388 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = { 389 { 390 /* DAC */ 391 .num = 1, 392 .type = SDW_DPN_SIMPLE, 393 .min_ch = 1, 394 .max_ch = 1, 395 .simple_ch_prep_sm = true, 396 .read_only_wordlength = true, 397 }, { 398 /* COMP */ 399 .num = 2, 400 .type = SDW_DPN_SIMPLE, 401 .min_ch = 1, 402 .max_ch = 1, 403 .simple_ch_prep_sm = true, 404 .read_only_wordlength = true, 405 }, { 406 /* BOOST */ 407 .num = 3, 408 .type = SDW_DPN_SIMPLE, 409 .min_ch = 1, 410 .max_ch = 1, 411 .simple_ch_prep_sm = true, 412 .read_only_wordlength = true, 413 }, { 414 /* VISENSE */ 415 .num = 4, 416 .type = SDW_DPN_SIMPLE, 417 .min_ch = 1, 418 .max_ch = 1, 419 .simple_ch_prep_sm = true, 420 .read_only_wordlength = true, 421 } 422 }; 423 424 static const struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = { 425 { 426 .num = 1, 427 .ch_mask = 0x1, 428 }, { 429 .num = 2, 430 .ch_mask = 0xf, 431 }, { 432 .num = 3, 433 .ch_mask = 0x3, 434 }, { /* IV feedback */ 435 .num = 4, 436 .ch_mask = 0x3, 437 }, 438 }; 439 440 static bool wsa881x_readable_register(struct device *dev, unsigned int reg) 441 { 442 switch (reg) { 443 case WSA881X_CHIP_ID0: 444 case WSA881X_CHIP_ID1: 445 case WSA881X_CHIP_ID2: 446 case WSA881X_CHIP_ID3: 447 case WSA881X_BUS_ID: 448 case WSA881X_CDC_RST_CTL: 449 case WSA881X_CDC_TOP_CLK_CTL: 450 case WSA881X_CDC_ANA_CLK_CTL: 451 case WSA881X_CDC_DIG_CLK_CTL: 452 case WSA881X_CLOCK_CONFIG: 453 case WSA881X_ANA_CTL: 454 case WSA881X_SWR_RESET_EN: 455 case WSA881X_RESET_CTL: 456 case WSA881X_TADC_VALUE_CTL: 457 case WSA881X_TEMP_DETECT_CTL: 458 case WSA881X_TEMP_MSB: 459 case WSA881X_TEMP_LSB: 460 case WSA881X_TEMP_CONFIG0: 461 case WSA881X_TEMP_CONFIG1: 462 case WSA881X_CDC_CLIP_CTL: 463 case WSA881X_SDM_PDM9_LSB: 464 case WSA881X_SDM_PDM9_MSB: 465 case WSA881X_CDC_RX_CTL: 466 case WSA881X_DEM_BYPASS_DATA0: 467 case WSA881X_DEM_BYPASS_DATA1: 468 case WSA881X_DEM_BYPASS_DATA2: 469 case WSA881X_DEM_BYPASS_DATA3: 470 case WSA881X_OTP_CTRL0: 471 case WSA881X_OTP_CTRL1: 472 case WSA881X_HDRIVE_CTL_GROUP1: 473 case WSA881X_INTR_MODE: 474 case WSA881X_INTR_MASK: 475 case WSA881X_INTR_STATUS: 476 case WSA881X_INTR_CLEAR: 477 case WSA881X_INTR_LEVEL: 478 case WSA881X_INTR_SET: 479 case WSA881X_INTR_TEST: 480 case WSA881X_PDM_TEST_MODE: 481 case WSA881X_ATE_TEST_MODE: 482 case WSA881X_PIN_CTL_MODE: 483 case WSA881X_PIN_CTL_OE: 484 case WSA881X_PIN_WDATA_IOPAD: 485 case WSA881X_PIN_STATUS: 486 case WSA881X_DIG_DEBUG_MODE: 487 case WSA881X_DIG_DEBUG_SEL: 488 case WSA881X_DIG_DEBUG_EN: 489 case WSA881X_SWR_HM_TEST1: 490 case WSA881X_SWR_HM_TEST2: 491 case WSA881X_TEMP_DETECT_DBG_CTL: 492 case WSA881X_TEMP_DEBUG_MSB: 493 case WSA881X_TEMP_DEBUG_LSB: 494 case WSA881X_SAMPLE_EDGE_SEL: 495 case WSA881X_IOPAD_CTL: 496 case WSA881X_SPARE_0: 497 case WSA881X_SPARE_1: 498 case WSA881X_SPARE_2: 499 case WSA881X_OTP_REG_0: 500 case WSA881X_OTP_REG_1: 501 case WSA881X_OTP_REG_2: 502 case WSA881X_OTP_REG_3: 503 case WSA881X_OTP_REG_4: 504 case WSA881X_OTP_REG_5: 505 case WSA881X_OTP_REG_6: 506 case WSA881X_OTP_REG_7: 507 case WSA881X_OTP_REG_8: 508 case WSA881X_OTP_REG_9: 509 case WSA881X_OTP_REG_10: 510 case WSA881X_OTP_REG_11: 511 case WSA881X_OTP_REG_12: 512 case WSA881X_OTP_REG_13: 513 case WSA881X_OTP_REG_14: 514 case WSA881X_OTP_REG_15: 515 case WSA881X_OTP_REG_16: 516 case WSA881X_OTP_REG_17: 517 case WSA881X_OTP_REG_18: 518 case WSA881X_OTP_REG_19: 519 case WSA881X_OTP_REG_20: 520 case WSA881X_OTP_REG_21: 521 case WSA881X_OTP_REG_22: 522 case WSA881X_OTP_REG_23: 523 case WSA881X_OTP_REG_24: 524 case WSA881X_OTP_REG_25: 525 case WSA881X_OTP_REG_26: 526 case WSA881X_OTP_REG_27: 527 case WSA881X_OTP_REG_28: 528 case WSA881X_OTP_REG_29: 529 case WSA881X_OTP_REG_30: 530 case WSA881X_OTP_REG_31: 531 case WSA881X_OTP_REG_63: 532 case WSA881X_BIAS_REF_CTRL: 533 case WSA881X_BIAS_TEST: 534 case WSA881X_BIAS_BIAS: 535 case WSA881X_TEMP_OP: 536 case WSA881X_TEMP_IREF_CTRL: 537 case WSA881X_TEMP_ISENS_CTRL: 538 case WSA881X_TEMP_CLK_CTRL: 539 case WSA881X_TEMP_TEST: 540 case WSA881X_TEMP_BIAS: 541 case WSA881X_TEMP_ADC_CTRL: 542 case WSA881X_TEMP_DOUT_MSB: 543 case WSA881X_TEMP_DOUT_LSB: 544 case WSA881X_ADC_EN_MODU_V: 545 case WSA881X_ADC_EN_MODU_I: 546 case WSA881X_ADC_EN_DET_TEST_V: 547 case WSA881X_ADC_EN_DET_TEST_I: 548 case WSA881X_ADC_SEL_IBIAS: 549 case WSA881X_ADC_EN_SEL_IBAIS: 550 case WSA881X_SPKR_DRV_EN: 551 case WSA881X_SPKR_DRV_GAIN: 552 case WSA881X_SPKR_DAC_CTL: 553 case WSA881X_SPKR_DRV_DBG: 554 case WSA881X_SPKR_PWRSTG_DBG: 555 case WSA881X_SPKR_OCP_CTL: 556 case WSA881X_SPKR_CLIP_CTL: 557 case WSA881X_SPKR_BBM_CTL: 558 case WSA881X_SPKR_MISC_CTL1: 559 case WSA881X_SPKR_MISC_CTL2: 560 case WSA881X_SPKR_BIAS_INT: 561 case WSA881X_SPKR_PA_INT: 562 case WSA881X_SPKR_BIAS_CAL: 563 case WSA881X_SPKR_BIAS_PSRR: 564 case WSA881X_SPKR_STATUS1: 565 case WSA881X_SPKR_STATUS2: 566 case WSA881X_BOOST_EN_CTL: 567 case WSA881X_BOOST_CURRENT_LIMIT: 568 case WSA881X_BOOST_PS_CTL: 569 case WSA881X_BOOST_PRESET_OUT1: 570 case WSA881X_BOOST_PRESET_OUT2: 571 case WSA881X_BOOST_FORCE_OUT: 572 case WSA881X_BOOST_LDO_PROG: 573 case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB: 574 case WSA881X_BOOST_RON_CTL: 575 case WSA881X_BOOST_LOOP_STABILITY: 576 case WSA881X_BOOST_ZX_CTL: 577 case WSA881X_BOOST_START_CTL: 578 case WSA881X_BOOST_MISC1_CTL: 579 case WSA881X_BOOST_MISC2_CTL: 580 case WSA881X_BOOST_MISC3_CTL: 581 case WSA881X_BOOST_ATEST_CTL: 582 case WSA881X_SPKR_PROT_FE_GAIN: 583 case WSA881X_SPKR_PROT_FE_CM_LDO_SET: 584 case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1: 585 case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2: 586 case WSA881X_SPKR_PROT_ATEST1: 587 case WSA881X_SPKR_PROT_ATEST2: 588 case WSA881X_SPKR_PROT_FE_VSENSE_VCM: 589 case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1: 590 case WSA881X_BONGO_RESRV_REG1: 591 case WSA881X_BONGO_RESRV_REG2: 592 case WSA881X_SPKR_PROT_SAR: 593 case WSA881X_SPKR_STATUS3: 594 return true; 595 default: 596 return false; 597 } 598 } 599 600 static bool wsa881x_volatile_register(struct device *dev, unsigned int reg) 601 { 602 switch (reg) { 603 case WSA881X_CHIP_ID0: 604 case WSA881X_CHIP_ID1: 605 case WSA881X_CHIP_ID2: 606 case WSA881X_CHIP_ID3: 607 case WSA881X_BUS_ID: 608 case WSA881X_TEMP_MSB: 609 case WSA881X_TEMP_LSB: 610 case WSA881X_SDM_PDM9_LSB: 611 case WSA881X_SDM_PDM9_MSB: 612 case WSA881X_OTP_CTRL1: 613 case WSA881X_INTR_STATUS: 614 case WSA881X_ATE_TEST_MODE: 615 case WSA881X_PIN_STATUS: 616 case WSA881X_SWR_HM_TEST2: 617 case WSA881X_SPKR_STATUS1: 618 case WSA881X_SPKR_STATUS2: 619 case WSA881X_SPKR_STATUS3: 620 case WSA881X_OTP_REG_0: 621 case WSA881X_OTP_REG_1: 622 case WSA881X_OTP_REG_2: 623 case WSA881X_OTP_REG_3: 624 case WSA881X_OTP_REG_4: 625 case WSA881X_OTP_REG_5: 626 case WSA881X_OTP_REG_31: 627 case WSA881X_TEMP_DOUT_MSB: 628 case WSA881X_TEMP_DOUT_LSB: 629 case WSA881X_TEMP_OP: 630 case WSA881X_SPKR_PROT_SAR: 631 return true; 632 default: 633 return false; 634 } 635 } 636 637 static struct regmap_config wsa881x_regmap_config = { 638 .reg_bits = 32, 639 .val_bits = 8, 640 .cache_type = REGCACHE_RBTREE, 641 .reg_defaults = wsa881x_defaults, 642 .max_register = WSA881X_SPKR_STATUS3, 643 .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults), 644 .volatile_reg = wsa881x_volatile_register, 645 .readable_reg = wsa881x_readable_register, 646 .reg_format_endian = REGMAP_ENDIAN_NATIVE, 647 .val_format_endian = REGMAP_ENDIAN_NATIVE, 648 .can_multi_write = true, 649 }; 650 651 enum { 652 G_18DB = 0, 653 G_16P5DB, 654 G_15DB, 655 G_13P5DB, 656 G_12DB, 657 G_10P5DB, 658 G_9DB, 659 G_7P5DB, 660 G_6DB, 661 G_4P5DB, 662 G_3DB, 663 G_1P5DB, 664 G_0DB, 665 }; 666 667 /* 668 * Private data Structure for wsa881x. All parameters related to 669 * WSA881X codec needs to be defined here. 670 */ 671 struct wsa881x_priv { 672 struct regmap *regmap; 673 struct device *dev; 674 struct sdw_slave *slave; 675 struct sdw_stream_config sconfig; 676 struct sdw_stream_runtime *sruntime; 677 struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS]; 678 struct gpio_desc *sd_n; 679 /* 680 * Logical state for SD_N GPIO: high for shutdown, low for enable. 681 * For backwards compatibility. 682 */ 683 unsigned int sd_n_val; 684 int version; 685 int active_ports; 686 bool port_prepared[WSA881X_MAX_SWR_PORTS]; 687 bool port_enable[WSA881X_MAX_SWR_PORTS]; 688 }; 689 690 static void wsa881x_init(struct wsa881x_priv *wsa881x) 691 { 692 struct regmap *rm = wsa881x->regmap; 693 unsigned int val = 0; 694 695 regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version); 696 regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0, 697 ARRAY_SIZE(wsa881x_rev_2_0)); 698 699 /* Enable software reset output from soundwire slave */ 700 regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07); 701 702 /* Bring out of analog reset */ 703 regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02); 704 705 /* Bring out of digital reset */ 706 regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01); 707 regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10); 708 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02); 709 regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80); 710 regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06); 711 regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00); 712 regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40); 713 regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E); 714 regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03); 715 regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14); 716 regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80); 717 regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00); 718 regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04); 719 regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00); 720 721 regmap_read(rm, WSA881X_OTP_REG_0, &val); 722 if (val) 723 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70); 724 725 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30); 726 regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08); 727 regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08); 728 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30); 729 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00); 730 regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A); 731 regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2); 732 regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05); 733 } 734 735 static int wsa881x_component_probe(struct snd_soc_component *comp) 736 { 737 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp); 738 739 snd_soc_component_init_regmap(comp, wsa881x->regmap); 740 741 return 0; 742 } 743 744 static int wsa881x_put_pa_gain(struct snd_kcontrol *kc, 745 struct snd_ctl_elem_value *ucontrol) 746 { 747 struct snd_soc_component *comp = snd_soc_kcontrol_component(kc); 748 struct soc_mixer_control *mc = 749 (struct soc_mixer_control *)kc->private_value; 750 int max = mc->max; 751 unsigned int mask = (1 << fls(max)) - 1; 752 int val, ret, min_gain, max_gain; 753 754 ret = pm_runtime_resume_and_get(comp->dev); 755 if (ret < 0 && ret != -EACCES) 756 return ret; 757 758 max_gain = (max - ucontrol->value.integer.value[0]) & mask; 759 /* 760 * Gain has to set incrementally in 4 steps 761 * as per HW sequence 762 */ 763 if (max_gain > G_4P5DB) 764 min_gain = G_0DB; 765 else 766 min_gain = max_gain + 3; 767 /* 768 * 1ms delay is needed before change in gain 769 * as per HW requirement. 770 */ 771 usleep_range(1000, 1010); 772 773 for (val = min_gain; max_gain <= val; val--) { 774 ret = snd_soc_component_update_bits(comp, 775 WSA881X_SPKR_DRV_GAIN, 776 WSA881X_SPKR_PAG_GAIN_MASK, 777 val << 4); 778 if (ret < 0) 779 dev_err(comp->dev, "Failed to change PA gain"); 780 781 usleep_range(1000, 1010); 782 } 783 784 pm_runtime_mark_last_busy(comp->dev); 785 pm_runtime_put_autosuspend(comp->dev); 786 787 return 1; 788 } 789 790 static int wsa881x_get_port(struct snd_kcontrol *kcontrol, 791 struct snd_ctl_elem_value *ucontrol) 792 { 793 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 794 struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp); 795 struct soc_mixer_control *mixer = 796 (struct soc_mixer_control *)kcontrol->private_value; 797 int portidx = mixer->reg; 798 799 ucontrol->value.integer.value[0] = data->port_enable[portidx]; 800 801 802 return 0; 803 } 804 805 static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable) 806 { 807 if (enable) 808 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL, 809 WSA881X_BOOST_EN_MASK, 810 WSA881X_BOOST_EN); 811 else 812 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL, 813 WSA881X_BOOST_EN_MASK, 0); 814 /* 815 * 1.5ms sleep is needed after boost enable/disable as per 816 * HW requirement 817 */ 818 usleep_range(1500, 1510); 819 return 0; 820 } 821 822 static int wsa881x_set_port(struct snd_kcontrol *kcontrol, 823 struct snd_ctl_elem_value *ucontrol) 824 { 825 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 826 struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp); 827 struct soc_mixer_control *mixer = 828 (struct soc_mixer_control *)kcontrol->private_value; 829 int portidx = mixer->reg; 830 831 if (ucontrol->value.integer.value[0]) { 832 if (data->port_enable[portidx]) 833 return 0; 834 835 data->port_enable[portidx] = true; 836 } else { 837 if (!data->port_enable[portidx]) 838 return 0; 839 840 data->port_enable[portidx] = false; 841 } 842 843 if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */ 844 wsa881x_boost_ctrl(comp, data->port_enable[portidx]); 845 846 return 1; 847 } 848 849 static const char * const smart_boost_lvl_text[] = { 850 "6.625 V", "6.750 V", "6.875 V", "7.000 V", 851 "7.125 V", "7.250 V", "7.375 V", "7.500 V", 852 "7.625 V", "7.750 V", "7.875 V", "8.000 V", 853 "8.125 V", "8.250 V", "8.375 V", "8.500 V" 854 }; 855 856 static const struct soc_enum smart_boost_lvl_enum = 857 SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0, 858 ARRAY_SIZE(smart_boost_lvl_text), 859 smart_boost_lvl_text); 860 861 static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0); 862 863 static const struct snd_kcontrol_new wsa881x_snd_controls[] = { 864 SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum), 865 WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN, 866 4, 0xC, 1, pa_gain), 867 SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0, 868 wsa881x_get_port, wsa881x_set_port), 869 SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0, 870 wsa881x_get_port, wsa881x_set_port), 871 SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0, 872 wsa881x_get_port, wsa881x_set_port), 873 SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0, 874 wsa881x_get_port, wsa881x_set_port), 875 }; 876 877 static const struct snd_soc_dapm_route wsa881x_audio_map[] = { 878 { "RDAC", NULL, "IN" }, 879 { "RDAC", NULL, "DCLK" }, 880 { "RDAC", NULL, "ACLK" }, 881 { "RDAC", NULL, "Bandgap" }, 882 { "SPKR PGA", NULL, "RDAC" }, 883 { "SPKR", NULL, "SPKR PGA" }, 884 }; 885 886 static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp, 887 bool enable) 888 { 889 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp); 890 891 if (enable) { 892 regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0, 893 ARRAY_SIZE(wsa881x_vi_txfe_en_2_0)); 894 } else { 895 snd_soc_component_update_bits(comp, 896 WSA881X_SPKR_PROT_FE_VSENSE_VCM, 897 0x08, 0x08); 898 /* 899 * 200us sleep is needed after visense txfe disable as per 900 * HW requirement. 901 */ 902 usleep_range(200, 210); 903 snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN, 904 0x01, 0x00); 905 } 906 return 0; 907 } 908 909 static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp, 910 bool enable) 911 { 912 snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7), 913 (enable << 7)); 914 snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7), 915 (enable << 7)); 916 return 0; 917 } 918 919 static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w, 920 struct snd_kcontrol *kcontrol, int event) 921 { 922 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 923 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp); 924 925 switch (event) { 926 case SND_SOC_DAPM_PRE_PMU: 927 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL, 928 WSA881X_SPKR_OCP_MASK, 929 WSA881X_SPKR_OCP_EN); 930 regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0, 931 ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0)); 932 933 snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN, 934 WSA881X_PA_GAIN_SEL_MASK, 935 WSA881X_PA_GAIN_SEL_REG); 936 break; 937 case SND_SOC_DAPM_POST_PMU: 938 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) { 939 wsa881x_visense_txfe_ctrl(comp, true); 940 snd_soc_component_update_bits(comp, 941 WSA881X_ADC_EN_SEL_IBAIS, 942 0x07, 0x01); 943 wsa881x_visense_adc_ctrl(comp, true); 944 } 945 946 break; 947 case SND_SOC_DAPM_POST_PMD: 948 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) { 949 wsa881x_visense_adc_ctrl(comp, false); 950 wsa881x_visense_txfe_ctrl(comp, false); 951 } 952 953 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL, 954 WSA881X_SPKR_OCP_MASK, 955 WSA881X_SPKR_OCP_EN | 956 WSA881X_SPKR_OCP_HOLD); 957 break; 958 } 959 return 0; 960 } 961 962 static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = { 963 SND_SOC_DAPM_INPUT("IN"), 964 SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0, 965 NULL, 966 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 967 SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 968 wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU | 969 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 970 SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL, 971 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 972 SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL, 973 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 974 SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0, 975 NULL, 976 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 977 SND_SOC_DAPM_OUTPUT("SPKR"), 978 }; 979 980 static int wsa881x_hw_params(struct snd_pcm_substream *substream, 981 struct snd_pcm_hw_params *params, 982 struct snd_soc_dai *dai) 983 { 984 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 985 int i; 986 987 wsa881x->active_ports = 0; 988 for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) { 989 if (!wsa881x->port_enable[i]) 990 continue; 991 992 wsa881x->port_config[wsa881x->active_ports] = 993 wsa881x_pconfig[i]; 994 wsa881x->active_ports++; 995 } 996 997 return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig, 998 wsa881x->port_config, wsa881x->active_ports, 999 wsa881x->sruntime); 1000 } 1001 1002 static int wsa881x_hw_free(struct snd_pcm_substream *substream, 1003 struct snd_soc_dai *dai) 1004 { 1005 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 1006 1007 sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime); 1008 1009 return 0; 1010 } 1011 1012 static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai, 1013 void *stream, int direction) 1014 { 1015 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 1016 1017 wsa881x->sruntime = stream; 1018 1019 return 0; 1020 } 1021 1022 static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1023 { 1024 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 1025 1026 if (mute) 1027 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80, 1028 0x00); 1029 else 1030 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80, 1031 0x80); 1032 1033 return 0; 1034 } 1035 1036 static const struct snd_soc_dai_ops wsa881x_dai_ops = { 1037 .hw_params = wsa881x_hw_params, 1038 .hw_free = wsa881x_hw_free, 1039 .mute_stream = wsa881x_digital_mute, 1040 .set_stream = wsa881x_set_sdw_stream, 1041 }; 1042 1043 static struct snd_soc_dai_driver wsa881x_dais[] = { 1044 { 1045 .name = "SPKR", 1046 .id = 0, 1047 .playback = { 1048 .stream_name = "SPKR Playback", 1049 .rates = SNDRV_PCM_RATE_48000, 1050 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1051 .rate_max = 48000, 1052 .rate_min = 48000, 1053 .channels_min = 1, 1054 .channels_max = 1, 1055 }, 1056 .ops = &wsa881x_dai_ops, 1057 }, 1058 }; 1059 1060 static const struct snd_soc_component_driver wsa881x_component_drv = { 1061 .name = "WSA881x", 1062 .probe = wsa881x_component_probe, 1063 .controls = wsa881x_snd_controls, 1064 .num_controls = ARRAY_SIZE(wsa881x_snd_controls), 1065 .dapm_widgets = wsa881x_dapm_widgets, 1066 .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets), 1067 .dapm_routes = wsa881x_audio_map, 1068 .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map), 1069 .endianness = 1, 1070 }; 1071 1072 static int wsa881x_update_status(struct sdw_slave *slave, 1073 enum sdw_slave_status status) 1074 { 1075 struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev); 1076 1077 if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0) 1078 wsa881x_init(wsa881x); 1079 1080 return 0; 1081 } 1082 1083 static int wsa881x_port_prep(struct sdw_slave *slave, 1084 struct sdw_prepare_ch *prepare_ch, 1085 enum sdw_port_prep_ops state) 1086 { 1087 struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev); 1088 1089 if (state == SDW_OPS_PORT_POST_PREP) 1090 wsa881x->port_prepared[prepare_ch->num - 1] = true; 1091 else 1092 wsa881x->port_prepared[prepare_ch->num - 1] = false; 1093 1094 return 0; 1095 } 1096 1097 static int wsa881x_bus_config(struct sdw_slave *slave, 1098 struct sdw_bus_params *params) 1099 { 1100 sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank), 1101 0x01); 1102 1103 return 0; 1104 } 1105 1106 static const struct sdw_slave_ops wsa881x_slave_ops = { 1107 .update_status = wsa881x_update_status, 1108 .bus_config = wsa881x_bus_config, 1109 .port_prep = wsa881x_port_prep, 1110 }; 1111 1112 static int wsa881x_probe(struct sdw_slave *pdev, 1113 const struct sdw_device_id *id) 1114 { 1115 struct wsa881x_priv *wsa881x; 1116 struct device *dev = &pdev->dev; 1117 1118 wsa881x = devm_kzalloc(dev, sizeof(*wsa881x), GFP_KERNEL); 1119 if (!wsa881x) 1120 return -ENOMEM; 1121 1122 wsa881x->sd_n = devm_gpiod_get_optional(dev, "powerdown", 1123 GPIOD_FLAGS_BIT_NONEXCLUSIVE); 1124 if (IS_ERR(wsa881x->sd_n)) 1125 return dev_err_probe(dev, PTR_ERR(wsa881x->sd_n), 1126 "Shutdown Control GPIO not found\n"); 1127 1128 /* 1129 * Backwards compatibility work-around. 1130 * 1131 * The SD_N GPIO is active low, however upstream DTS used always active 1132 * high. Changing the flag in driver and DTS will break backwards 1133 * compatibility, so add a simple value inversion to work with both old 1134 * and new DTS. 1135 * 1136 * This won't work properly with DTS using the flags properly in cases: 1137 * 1. Old DTS with proper ACTIVE_LOW, however such case was broken 1138 * before as the driver required the active high. 1139 * 2. New DTS with proper ACTIVE_HIGH (intended), which is rare case 1140 * (not existing upstream) but possible. This is the price of 1141 * backwards compatibility, therefore this hack should be removed at 1142 * some point. 1143 */ 1144 wsa881x->sd_n_val = gpiod_is_active_low(wsa881x->sd_n); 1145 if (!wsa881x->sd_n_val) 1146 dev_warn(dev, "Using ACTIVE_HIGH for shutdown GPIO. Your DTB might be outdated or you use unsupported configuration for the GPIO."); 1147 1148 dev_set_drvdata(dev, wsa881x); 1149 wsa881x->slave = pdev; 1150 wsa881x->dev = dev; 1151 wsa881x->sconfig.ch_count = 1; 1152 wsa881x->sconfig.bps = 1; 1153 wsa881x->sconfig.frame_rate = 48000; 1154 wsa881x->sconfig.direction = SDW_DATA_DIR_RX; 1155 wsa881x->sconfig.type = SDW_STREAM_PDM; 1156 pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0); 1157 pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; 1158 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 1159 gpiod_direction_output(wsa881x->sd_n, !wsa881x->sd_n_val); 1160 1161 wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config); 1162 if (IS_ERR(wsa881x->regmap)) 1163 return dev_err_probe(dev, PTR_ERR(wsa881x->regmap), "regmap_init failed\n"); 1164 1165 pm_runtime_set_autosuspend_delay(dev, 3000); 1166 pm_runtime_use_autosuspend(dev); 1167 pm_runtime_mark_last_busy(dev); 1168 pm_runtime_set_active(dev); 1169 pm_runtime_enable(dev); 1170 1171 return devm_snd_soc_register_component(dev, 1172 &wsa881x_component_drv, 1173 wsa881x_dais, 1174 ARRAY_SIZE(wsa881x_dais)); 1175 } 1176 1177 static int __maybe_unused wsa881x_runtime_suspend(struct device *dev) 1178 { 1179 struct regmap *regmap = dev_get_regmap(dev, NULL); 1180 struct wsa881x_priv *wsa881x = dev_get_drvdata(dev); 1181 1182 gpiod_direction_output(wsa881x->sd_n, wsa881x->sd_n_val); 1183 1184 regcache_cache_only(regmap, true); 1185 regcache_mark_dirty(regmap); 1186 1187 return 0; 1188 } 1189 1190 static int __maybe_unused wsa881x_runtime_resume(struct device *dev) 1191 { 1192 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1193 struct regmap *regmap = dev_get_regmap(dev, NULL); 1194 struct wsa881x_priv *wsa881x = dev_get_drvdata(dev); 1195 unsigned long time; 1196 1197 gpiod_direction_output(wsa881x->sd_n, !wsa881x->sd_n_val); 1198 1199 time = wait_for_completion_timeout(&slave->initialization_complete, 1200 msecs_to_jiffies(WSA881X_PROBE_TIMEOUT)); 1201 if (!time) { 1202 dev_err(dev, "Initialization not complete, timed out\n"); 1203 gpiod_direction_output(wsa881x->sd_n, wsa881x->sd_n_val); 1204 return -ETIMEDOUT; 1205 } 1206 1207 regcache_cache_only(regmap, false); 1208 regcache_sync(regmap); 1209 1210 return 0; 1211 } 1212 1213 static const struct dev_pm_ops wsa881x_pm_ops = { 1214 SET_RUNTIME_PM_OPS(wsa881x_runtime_suspend, wsa881x_runtime_resume, NULL) 1215 }; 1216 1217 static const struct sdw_device_id wsa881x_slave_id[] = { 1218 SDW_SLAVE_ENTRY(0x0217, 0x2010, 0), 1219 SDW_SLAVE_ENTRY(0x0217, 0x2110, 0), 1220 {}, 1221 }; 1222 MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id); 1223 1224 static struct sdw_driver wsa881x_codec_driver = { 1225 .probe = wsa881x_probe, 1226 .ops = &wsa881x_slave_ops, 1227 .id_table = wsa881x_slave_id, 1228 .driver = { 1229 .name = "wsa881x-codec", 1230 .pm = &wsa881x_pm_ops, 1231 } 1232 }; 1233 module_sdw_driver(wsa881x_codec_driver); 1234 1235 MODULE_DESCRIPTION("WSA881x codec driver"); 1236 MODULE_LICENSE("GPL v2"); 1237