1 /* 2 * wm9081.c -- WM9081 ALSA SoC Audio driver 3 * 4 * Author: Mark Brown 5 * 6 * Copyright 2009-12 Wolfson Microelectronics plc 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 30 #include <sound/wm9081.h> 31 #include "wm9081.h" 32 33 static const struct reg_default wm9081_reg[] = { 34 { 2, 0x00B9 }, /* R2 - Analogue Lineout */ 35 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */ 36 { 4, 0x0001 }, /* R4 - VMID Control */ 37 { 5, 0x0068 }, /* R5 - Bias Control 1 */ 38 { 7, 0x0000 }, /* R7 - Analogue Mixer */ 39 { 8, 0x0000 }, /* R8 - Anti Pop Control */ 40 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */ 41 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */ 42 { 11, 0x0180 }, /* R11 - Power Management */ 43 { 12, 0x0000 }, /* R12 - Clock Control 1 */ 44 { 13, 0x0038 }, /* R13 - Clock Control 2 */ 45 { 14, 0x4000 }, /* R14 - Clock Control 3 */ 46 { 16, 0x0000 }, /* R16 - FLL Control 1 */ 47 { 17, 0x0200 }, /* R17 - FLL Control 2 */ 48 { 18, 0x0000 }, /* R18 - FLL Control 3 */ 49 { 19, 0x0204 }, /* R19 - FLL Control 4 */ 50 { 20, 0x0000 }, /* R20 - FLL Control 5 */ 51 { 22, 0x0000 }, /* R22 - Audio Interface 1 */ 52 { 23, 0x0002 }, /* R23 - Audio Interface 2 */ 53 { 24, 0x0008 }, /* R24 - Audio Interface 3 */ 54 { 25, 0x0022 }, /* R25 - Audio Interface 4 */ 55 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */ 56 { 28, 0x0000 }, /* R28 - Interrupt Polarity */ 57 { 29, 0x0000 }, /* R29 - Interrupt Control */ 58 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */ 59 { 31, 0x0008 }, /* R31 - DAC Digital 2 */ 60 { 32, 0x09AF }, /* R32 - DRC 1 */ 61 { 33, 0x4201 }, /* R33 - DRC 2 */ 62 { 34, 0x0000 }, /* R34 - DRC 3 */ 63 { 35, 0x0000 }, /* R35 - DRC 4 */ 64 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */ 65 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */ 66 { 40, 0x0002 }, /* R40 - MW Slave 1 */ 67 { 42, 0x0000 }, /* R42 - EQ 1 */ 68 { 43, 0x0000 }, /* R43 - EQ 2 */ 69 { 44, 0x0FCA }, /* R44 - EQ 3 */ 70 { 45, 0x0400 }, /* R45 - EQ 4 */ 71 { 46, 0x00B8 }, /* R46 - EQ 5 */ 72 { 47, 0x1EB5 }, /* R47 - EQ 6 */ 73 { 48, 0xF145 }, /* R48 - EQ 7 */ 74 { 49, 0x0B75 }, /* R49 - EQ 8 */ 75 { 50, 0x01C5 }, /* R50 - EQ 9 */ 76 { 51, 0x169E }, /* R51 - EQ 10 */ 77 { 52, 0xF829 }, /* R52 - EQ 11 */ 78 { 53, 0x07AD }, /* R53 - EQ 12 */ 79 { 54, 0x1103 }, /* R54 - EQ 13 */ 80 { 55, 0x1C58 }, /* R55 - EQ 14 */ 81 { 56, 0xF373 }, /* R56 - EQ 15 */ 82 { 57, 0x0A54 }, /* R57 - EQ 16 */ 83 { 58, 0x0558 }, /* R58 - EQ 17 */ 84 { 59, 0x0564 }, /* R59 - EQ 18 */ 85 { 60, 0x0559 }, /* R60 - EQ 19 */ 86 { 61, 0x4000 }, /* R61 - EQ 20 */ 87 }; 88 89 static struct { 90 int ratio; 91 int clk_sys_rate; 92 } clk_sys_rates[] = { 93 { 64, 0 }, 94 { 128, 1 }, 95 { 192, 2 }, 96 { 256, 3 }, 97 { 384, 4 }, 98 { 512, 5 }, 99 { 768, 6 }, 100 { 1024, 7 }, 101 { 1408, 8 }, 102 { 1536, 9 }, 103 }; 104 105 static struct { 106 int rate; 107 int sample_rate; 108 } sample_rates[] = { 109 { 8000, 0 }, 110 { 11025, 1 }, 111 { 12000, 2 }, 112 { 16000, 3 }, 113 { 22050, 4 }, 114 { 24000, 5 }, 115 { 32000, 6 }, 116 { 44100, 7 }, 117 { 48000, 8 }, 118 { 88200, 9 }, 119 { 96000, 10 }, 120 }; 121 122 static struct { 123 int div; /* *10 due to .5s */ 124 int bclk_div; 125 } bclk_divs[] = { 126 { 10, 0 }, 127 { 15, 1 }, 128 { 20, 2 }, 129 { 30, 3 }, 130 { 40, 4 }, 131 { 50, 5 }, 132 { 55, 6 }, 133 { 60, 7 }, 134 { 80, 8 }, 135 { 100, 9 }, 136 { 110, 10 }, 137 { 120, 11 }, 138 { 160, 12 }, 139 { 200, 13 }, 140 { 220, 14 }, 141 { 240, 15 }, 142 { 250, 16 }, 143 { 300, 17 }, 144 { 320, 18 }, 145 { 440, 19 }, 146 { 480, 20 }, 147 }; 148 149 struct wm9081_priv { 150 struct regmap *regmap; 151 int sysclk_source; 152 int mclk_rate; 153 int sysclk_rate; 154 int fs; 155 int bclk; 156 int master; 157 int fll_fref; 158 int fll_fout; 159 int tdm_width; 160 struct wm9081_pdata pdata; 161 }; 162 163 static bool wm9081_volatile_register(struct device *dev, unsigned int reg) 164 { 165 switch (reg) { 166 case WM9081_SOFTWARE_RESET: 167 case WM9081_INTERRUPT_STATUS: 168 return true; 169 default: 170 return false; 171 } 172 } 173 174 static bool wm9081_readable_register(struct device *dev, unsigned int reg) 175 { 176 switch (reg) { 177 case WM9081_SOFTWARE_RESET: 178 case WM9081_ANALOGUE_LINEOUT: 179 case WM9081_ANALOGUE_SPEAKER_PGA: 180 case WM9081_VMID_CONTROL: 181 case WM9081_BIAS_CONTROL_1: 182 case WM9081_ANALOGUE_MIXER: 183 case WM9081_ANTI_POP_CONTROL: 184 case WM9081_ANALOGUE_SPEAKER_1: 185 case WM9081_ANALOGUE_SPEAKER_2: 186 case WM9081_POWER_MANAGEMENT: 187 case WM9081_CLOCK_CONTROL_1: 188 case WM9081_CLOCK_CONTROL_2: 189 case WM9081_CLOCK_CONTROL_3: 190 case WM9081_FLL_CONTROL_1: 191 case WM9081_FLL_CONTROL_2: 192 case WM9081_FLL_CONTROL_3: 193 case WM9081_FLL_CONTROL_4: 194 case WM9081_FLL_CONTROL_5: 195 case WM9081_AUDIO_INTERFACE_1: 196 case WM9081_AUDIO_INTERFACE_2: 197 case WM9081_AUDIO_INTERFACE_3: 198 case WM9081_AUDIO_INTERFACE_4: 199 case WM9081_INTERRUPT_STATUS: 200 case WM9081_INTERRUPT_STATUS_MASK: 201 case WM9081_INTERRUPT_POLARITY: 202 case WM9081_INTERRUPT_CONTROL: 203 case WM9081_DAC_DIGITAL_1: 204 case WM9081_DAC_DIGITAL_2: 205 case WM9081_DRC_1: 206 case WM9081_DRC_2: 207 case WM9081_DRC_3: 208 case WM9081_DRC_4: 209 case WM9081_WRITE_SEQUENCER_1: 210 case WM9081_WRITE_SEQUENCER_2: 211 case WM9081_MW_SLAVE_1: 212 case WM9081_EQ_1: 213 case WM9081_EQ_2: 214 case WM9081_EQ_3: 215 case WM9081_EQ_4: 216 case WM9081_EQ_5: 217 case WM9081_EQ_6: 218 case WM9081_EQ_7: 219 case WM9081_EQ_8: 220 case WM9081_EQ_9: 221 case WM9081_EQ_10: 222 case WM9081_EQ_11: 223 case WM9081_EQ_12: 224 case WM9081_EQ_13: 225 case WM9081_EQ_14: 226 case WM9081_EQ_15: 227 case WM9081_EQ_16: 228 case WM9081_EQ_17: 229 case WM9081_EQ_18: 230 case WM9081_EQ_19: 231 case WM9081_EQ_20: 232 return true; 233 default: 234 return false; 235 } 236 } 237 238 static int wm9081_reset(struct regmap *map) 239 { 240 return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081); 241 } 242 243 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0); 244 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0); 245 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); 246 static const DECLARE_TLV_DB_RANGE(drc_max_tlv, 247 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0), 248 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0), 249 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), 250 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0) 251 ); 252 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); 253 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0); 254 255 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 256 257 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0); 258 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1); 259 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 260 261 static const char *drc_high_text[] = { 262 "1", 263 "1/2", 264 "1/4", 265 "1/8", 266 "1/16", 267 "0", 268 }; 269 270 static SOC_ENUM_SINGLE_DECL(drc_high, WM9081_DRC_3, 3, drc_high_text); 271 272 static const char *drc_low_text[] = { 273 "1", 274 "1/2", 275 "1/4", 276 "1/8", 277 "0", 278 }; 279 280 static SOC_ENUM_SINGLE_DECL(drc_low, WM9081_DRC_3, 0, drc_low_text); 281 282 static const char *drc_atk_text[] = { 283 "181us", 284 "181us", 285 "363us", 286 "726us", 287 "1.45ms", 288 "2.9ms", 289 "5.8ms", 290 "11.6ms", 291 "23.2ms", 292 "46.4ms", 293 "92.8ms", 294 "185.6ms", 295 }; 296 297 static SOC_ENUM_SINGLE_DECL(drc_atk, WM9081_DRC_2, 12, drc_atk_text); 298 299 static const char *drc_dcy_text[] = { 300 "186ms", 301 "372ms", 302 "743ms", 303 "1.49s", 304 "2.97s", 305 "5.94s", 306 "11.89s", 307 "23.78s", 308 "47.56s", 309 }; 310 311 static SOC_ENUM_SINGLE_DECL(drc_dcy, WM9081_DRC_2, 8, drc_dcy_text); 312 313 static const char *drc_qr_dcy_text[] = { 314 "0.725ms", 315 "1.45ms", 316 "5.8ms", 317 }; 318 319 static SOC_ENUM_SINGLE_DECL(drc_qr_dcy, WM9081_DRC_2, 4, drc_qr_dcy_text); 320 321 static const char *dac_deemph_text[] = { 322 "None", 323 "32kHz", 324 "44.1kHz", 325 "48kHz", 326 }; 327 328 static SOC_ENUM_SINGLE_DECL(dac_deemph, WM9081_DAC_DIGITAL_2, 1, 329 dac_deemph_text); 330 331 static const char *speaker_mode_text[] = { 332 "Class D", 333 "Class AB", 334 }; 335 336 static SOC_ENUM_SINGLE_DECL(speaker_mode, WM9081_ANALOGUE_SPEAKER_2, 6, 337 speaker_mode_text); 338 339 static int speaker_mode_get(struct snd_kcontrol *kcontrol, 340 struct snd_ctl_elem_value *ucontrol) 341 { 342 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 343 unsigned int reg; 344 345 reg = snd_soc_component_read32(component, WM9081_ANALOGUE_SPEAKER_2); 346 if (reg & WM9081_SPK_MODE) 347 ucontrol->value.enumerated.item[0] = 1; 348 else 349 ucontrol->value.enumerated.item[0] = 0; 350 351 return 0; 352 } 353 354 /* 355 * Stop any attempts to change speaker mode while the speaker is enabled. 356 * 357 * We also have some special anti-pop controls dependent on speaker 358 * mode which must be changed along with the mode. 359 */ 360 static int speaker_mode_put(struct snd_kcontrol *kcontrol, 361 struct snd_ctl_elem_value *ucontrol) 362 { 363 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 364 unsigned int reg_pwr = snd_soc_component_read32(component, WM9081_POWER_MANAGEMENT); 365 unsigned int reg2 = snd_soc_component_read32(component, WM9081_ANALOGUE_SPEAKER_2); 366 367 /* Are we changing anything? */ 368 if (ucontrol->value.enumerated.item[0] == 369 ((reg2 & WM9081_SPK_MODE) != 0)) 370 return 0; 371 372 /* Don't try to change modes while enabled */ 373 if (reg_pwr & WM9081_SPK_ENA) 374 return -EINVAL; 375 376 if (ucontrol->value.enumerated.item[0]) { 377 /* Class AB */ 378 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL); 379 reg2 |= WM9081_SPK_MODE; 380 } else { 381 /* Class D */ 382 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL; 383 reg2 &= ~WM9081_SPK_MODE; 384 } 385 386 snd_soc_component_write(component, WM9081_ANALOGUE_SPEAKER_2, reg2); 387 388 return 0; 389 } 390 391 static const struct snd_kcontrol_new wm9081_snd_controls[] = { 392 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv), 393 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv), 394 395 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv), 396 397 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1), 398 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0), 399 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv), 400 401 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0), 402 SOC_ENUM("DRC High Slope", drc_high), 403 SOC_ENUM("DRC Low Slope", drc_low), 404 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv), 405 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv), 406 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv), 407 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv), 408 SOC_ENUM("DRC Attack", drc_atk), 409 SOC_ENUM("DRC Decay", drc_dcy), 410 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0), 411 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv), 412 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy), 413 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv), 414 415 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0), 416 417 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0), 418 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0), 419 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1), 420 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0), 421 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0, 422 out_tlv), 423 SOC_ENUM("DAC Deemphasis", dac_deemph), 424 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put), 425 }; 426 427 static const struct snd_kcontrol_new wm9081_eq_controls[] = { 428 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv), 429 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv), 430 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv), 431 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv), 432 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv), 433 }; 434 435 static const struct snd_kcontrol_new mixer[] = { 436 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0), 437 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0), 438 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0), 439 }; 440 441 struct _fll_div { 442 u16 fll_fratio; 443 u16 fll_outdiv; 444 u16 fll_clk_ref_div; 445 u16 n; 446 u16 k; 447 }; 448 449 /* The size in bits of the FLL divide multiplied by 10 450 * to allow rounding later */ 451 #define FIXED_FLL_SIZE ((1 << 16) * 10) 452 453 static struct { 454 unsigned int min; 455 unsigned int max; 456 u16 fll_fratio; 457 int ratio; 458 } fll_fratios[] = { 459 { 0, 64000, 4, 16 }, 460 { 64000, 128000, 3, 8 }, 461 { 128000, 256000, 2, 4 }, 462 { 256000, 1000000, 1, 2 }, 463 { 1000000, 13500000, 0, 1 }, 464 }; 465 466 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 467 unsigned int Fout) 468 { 469 u64 Kpart; 470 unsigned int K, Ndiv, Nmod, target; 471 unsigned int div; 472 int i; 473 474 /* Fref must be <=13.5MHz */ 475 div = 1; 476 while ((Fref / div) > 13500000) { 477 div *= 2; 478 479 if (div > 8) { 480 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 481 Fref); 482 return -EINVAL; 483 } 484 } 485 fll_div->fll_clk_ref_div = div / 2; 486 487 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 488 489 /* Apply the division for our remaining calculations */ 490 Fref /= div; 491 492 /* Fvco should be 90-100MHz; don't check the upper bound */ 493 div = 0; 494 target = Fout * 2; 495 while (target < 90000000) { 496 div++; 497 target *= 2; 498 if (div > 7) { 499 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 500 Fout); 501 return -EINVAL; 502 } 503 } 504 fll_div->fll_outdiv = div; 505 506 pr_debug("Fvco=%dHz\n", target); 507 508 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 509 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 510 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 511 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 512 target /= fll_fratios[i].ratio; 513 break; 514 } 515 } 516 if (i == ARRAY_SIZE(fll_fratios)) { 517 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 518 return -EINVAL; 519 } 520 521 /* Now, calculate N.K */ 522 Ndiv = target / Fref; 523 524 fll_div->n = Ndiv; 525 Nmod = target % Fref; 526 pr_debug("Nmod=%d\n", Nmod); 527 528 /* Calculate fractional part - scale up so we can round. */ 529 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 530 531 do_div(Kpart, Fref); 532 533 K = Kpart & 0xFFFFFFFF; 534 535 if ((K % 10) >= 5) 536 K += 5; 537 538 /* Move down to proper range now rounding is done */ 539 fll_div->k = K / 10; 540 541 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 542 fll_div->n, fll_div->k, 543 fll_div->fll_fratio, fll_div->fll_outdiv, 544 fll_div->fll_clk_ref_div); 545 546 return 0; 547 } 548 549 static int wm9081_set_fll(struct snd_soc_component *component, int fll_id, 550 unsigned int Fref, unsigned int Fout) 551 { 552 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 553 u16 reg1, reg4, reg5; 554 struct _fll_div fll_div; 555 int ret; 556 int clk_sys_reg; 557 558 /* Any change? */ 559 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout) 560 return 0; 561 562 /* Disable the FLL */ 563 if (Fout == 0) { 564 dev_dbg(component->dev, "FLL disabled\n"); 565 wm9081->fll_fref = 0; 566 wm9081->fll_fout = 0; 567 568 return 0; 569 } 570 571 ret = fll_factors(&fll_div, Fref, Fout); 572 if (ret != 0) 573 return ret; 574 575 reg5 = snd_soc_component_read32(component, WM9081_FLL_CONTROL_5); 576 reg5 &= ~WM9081_FLL_CLK_SRC_MASK; 577 578 switch (fll_id) { 579 case WM9081_SYSCLK_FLL_MCLK: 580 reg5 |= 0x1; 581 break; 582 583 default: 584 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id); 585 return -EINVAL; 586 } 587 588 /* Disable CLK_SYS while we reconfigure */ 589 clk_sys_reg = snd_soc_component_read32(component, WM9081_CLOCK_CONTROL_3); 590 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 591 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, 592 clk_sys_reg & ~WM9081_CLK_SYS_ENA); 593 594 /* Any FLL configuration change requires that the FLL be 595 * disabled first. */ 596 reg1 = snd_soc_component_read32(component, WM9081_FLL_CONTROL_1); 597 reg1 &= ~WM9081_FLL_ENA; 598 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1); 599 600 /* Apply the configuration */ 601 if (fll_div.k) 602 reg1 |= WM9081_FLL_FRAC_MASK; 603 else 604 reg1 &= ~WM9081_FLL_FRAC_MASK; 605 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1); 606 607 snd_soc_component_write(component, WM9081_FLL_CONTROL_2, 608 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) | 609 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT)); 610 snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k); 611 612 reg4 = snd_soc_component_read32(component, WM9081_FLL_CONTROL_4); 613 reg4 &= ~WM9081_FLL_N_MASK; 614 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT; 615 snd_soc_component_write(component, WM9081_FLL_CONTROL_4, reg4); 616 617 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; 618 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; 619 snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5); 620 621 /* Set gain to the recommended value */ 622 snd_soc_component_update_bits(component, WM9081_FLL_CONTROL_4, 623 WM9081_FLL_GAIN_MASK, 0); 624 625 /* Enable the FLL */ 626 snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); 627 628 /* Then bring CLK_SYS up again if it was disabled */ 629 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 630 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, clk_sys_reg); 631 632 dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 633 634 wm9081->fll_fref = Fref; 635 wm9081->fll_fout = Fout; 636 637 return 0; 638 } 639 640 static int configure_clock(struct snd_soc_component *component) 641 { 642 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 643 int new_sysclk, i, target; 644 unsigned int reg; 645 int ret = 0; 646 int mclkdiv = 0; 647 int fll = 0; 648 649 switch (wm9081->sysclk_source) { 650 case WM9081_SYSCLK_MCLK: 651 if (wm9081->mclk_rate > 12225000) { 652 mclkdiv = 1; 653 wm9081->sysclk_rate = wm9081->mclk_rate / 2; 654 } else { 655 wm9081->sysclk_rate = wm9081->mclk_rate; 656 } 657 wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK, 0, 0); 658 break; 659 660 case WM9081_SYSCLK_FLL_MCLK: 661 /* If we have a sample rate calculate a CLK_SYS that 662 * gives us a suitable DAC configuration, plus BCLK. 663 * Ideally we would check to see if we can clock 664 * directly from MCLK and only use the FLL if this is 665 * not the case, though care must be taken with free 666 * running mode. 667 */ 668 if (wm9081->master && wm9081->bclk) { 669 /* Make sure we can generate CLK_SYS and BCLK 670 * and that we've got 3MHz for optimal 671 * performance. */ 672 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { 673 target = wm9081->fs * clk_sys_rates[i].ratio; 674 new_sysclk = target; 675 if (target >= wm9081->bclk && 676 target > 3000000) 677 break; 678 } 679 680 if (i == ARRAY_SIZE(clk_sys_rates)) 681 return -EINVAL; 682 683 } else if (wm9081->fs) { 684 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { 685 new_sysclk = clk_sys_rates[i].ratio 686 * wm9081->fs; 687 if (new_sysclk > 3000000) 688 break; 689 } 690 691 if (i == ARRAY_SIZE(clk_sys_rates)) 692 return -EINVAL; 693 694 } else { 695 new_sysclk = 12288000; 696 } 697 698 ret = wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK, 699 wm9081->mclk_rate, new_sysclk); 700 if (ret == 0) { 701 wm9081->sysclk_rate = new_sysclk; 702 703 /* Switch SYSCLK over to FLL */ 704 fll = 1; 705 } else { 706 wm9081->sysclk_rate = wm9081->mclk_rate; 707 } 708 break; 709 710 default: 711 return -EINVAL; 712 } 713 714 reg = snd_soc_component_read32(component, WM9081_CLOCK_CONTROL_1); 715 if (mclkdiv) 716 reg |= WM9081_MCLKDIV2; 717 else 718 reg &= ~WM9081_MCLKDIV2; 719 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_1, reg); 720 721 reg = snd_soc_component_read32(component, WM9081_CLOCK_CONTROL_3); 722 if (fll) 723 reg |= WM9081_CLK_SRC_SEL; 724 else 725 reg &= ~WM9081_CLK_SRC_SEL; 726 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, reg); 727 728 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); 729 730 return ret; 731 } 732 733 static int clk_sys_event(struct snd_soc_dapm_widget *w, 734 struct snd_kcontrol *kcontrol, int event) 735 { 736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 737 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 738 739 /* This should be done on init() for bypass paths */ 740 switch (wm9081->sysclk_source) { 741 case WM9081_SYSCLK_MCLK: 742 dev_dbg(component->dev, "Using %dHz MCLK\n", wm9081->mclk_rate); 743 break; 744 case WM9081_SYSCLK_FLL_MCLK: 745 dev_dbg(component->dev, "Using %dHz MCLK with FLL\n", 746 wm9081->mclk_rate); 747 break; 748 default: 749 dev_err(component->dev, "System clock not configured\n"); 750 return -EINVAL; 751 } 752 753 switch (event) { 754 case SND_SOC_DAPM_PRE_PMU: 755 configure_clock(component); 756 break; 757 758 case SND_SOC_DAPM_POST_PMD: 759 /* Disable the FLL if it's running */ 760 wm9081_set_fll(component, 0, 0, 0); 761 break; 762 } 763 764 return 0; 765 } 766 767 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = { 768 SND_SOC_DAPM_INPUT("IN1"), 769 SND_SOC_DAPM_INPUT("IN2"), 770 771 SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0), 772 773 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0, 774 mixer, ARRAY_SIZE(mixer)), 775 776 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0), 777 778 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0), 779 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0), 780 781 SND_SOC_DAPM_OUTPUT("LINEOUT"), 782 SND_SOC_DAPM_OUTPUT("SPKN"), 783 SND_SOC_DAPM_OUTPUT("SPKP"), 784 785 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event, 786 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 787 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0), 788 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0), 789 SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0), 790 }; 791 792 793 static const struct snd_soc_dapm_route wm9081_audio_paths[] = { 794 { "DAC", NULL, "CLK_SYS" }, 795 { "DAC", NULL, "CLK_DSP" }, 796 { "DAC", NULL, "AIF" }, 797 798 { "Mixer", "IN1 Switch", "IN1" }, 799 { "Mixer", "IN2 Switch", "IN2" }, 800 { "Mixer", "Playback Switch", "DAC" }, 801 802 { "LINEOUT PGA", NULL, "Mixer" }, 803 { "LINEOUT PGA", NULL, "TOCLK" }, 804 { "LINEOUT PGA", NULL, "CLK_SYS" }, 805 806 { "LINEOUT", NULL, "LINEOUT PGA" }, 807 808 { "Speaker PGA", NULL, "Mixer" }, 809 { "Speaker PGA", NULL, "TOCLK" }, 810 { "Speaker PGA", NULL, "CLK_SYS" }, 811 812 { "Speaker", NULL, "Speaker PGA" }, 813 { "Speaker", NULL, "TSENSE" }, 814 815 { "SPKN", NULL, "Speaker" }, 816 { "SPKP", NULL, "Speaker" }, 817 }; 818 819 static int wm9081_set_bias_level(struct snd_soc_component *component, 820 enum snd_soc_bias_level level) 821 { 822 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 823 824 switch (level) { 825 case SND_SOC_BIAS_ON: 826 break; 827 828 case SND_SOC_BIAS_PREPARE: 829 /* VMID=2*40k */ 830 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL, 831 WM9081_VMID_SEL_MASK, 0x2); 832 833 /* Normal bias current */ 834 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1, 835 WM9081_STBY_BIAS_ENA, 0); 836 break; 837 838 case SND_SOC_BIAS_STANDBY: 839 /* Initial cold start */ 840 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 841 regcache_cache_only(wm9081->regmap, false); 842 regcache_sync(wm9081->regmap); 843 844 /* Disable LINEOUT discharge */ 845 snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL, 846 WM9081_LINEOUT_DISCH, 0); 847 848 /* Select startup bias source */ 849 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1, 850 WM9081_BIAS_SRC | WM9081_BIAS_ENA, 851 WM9081_BIAS_SRC | WM9081_BIAS_ENA); 852 853 /* VMID 2*4k; Soft VMID ramp enable */ 854 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL, 855 WM9081_VMID_RAMP | 856 WM9081_VMID_SEL_MASK, 857 WM9081_VMID_RAMP | 0x6); 858 859 mdelay(100); 860 861 /* Normal bias enable & soft start off */ 862 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL, 863 WM9081_VMID_RAMP, 0); 864 865 /* Standard bias source */ 866 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1, 867 WM9081_BIAS_SRC, 0); 868 } 869 870 /* VMID 2*240k */ 871 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL, 872 WM9081_VMID_SEL_MASK, 0x04); 873 874 /* Standby bias current on */ 875 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1, 876 WM9081_STBY_BIAS_ENA, 877 WM9081_STBY_BIAS_ENA); 878 break; 879 880 case SND_SOC_BIAS_OFF: 881 /* Startup bias source and disable bias */ 882 snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1, 883 WM9081_BIAS_SRC | WM9081_BIAS_ENA, 884 WM9081_BIAS_SRC); 885 886 /* Disable VMID with soft ramping */ 887 snd_soc_component_update_bits(component, WM9081_VMID_CONTROL, 888 WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK, 889 WM9081_VMID_RAMP); 890 891 /* Actively discharge LINEOUT */ 892 snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL, 893 WM9081_LINEOUT_DISCH, 894 WM9081_LINEOUT_DISCH); 895 896 regcache_cache_only(wm9081->regmap, true); 897 break; 898 } 899 900 return 0; 901 } 902 903 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai, 904 unsigned int fmt) 905 { 906 struct snd_soc_component *component = dai->component; 907 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 908 unsigned int aif2 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_2); 909 910 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | 911 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK); 912 913 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 914 case SND_SOC_DAIFMT_CBS_CFS: 915 wm9081->master = 0; 916 break; 917 case SND_SOC_DAIFMT_CBS_CFM: 918 aif2 |= WM9081_LRCLK_DIR; 919 wm9081->master = 1; 920 break; 921 case SND_SOC_DAIFMT_CBM_CFS: 922 aif2 |= WM9081_BCLK_DIR; 923 wm9081->master = 1; 924 break; 925 case SND_SOC_DAIFMT_CBM_CFM: 926 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR; 927 wm9081->master = 1; 928 break; 929 default: 930 return -EINVAL; 931 } 932 933 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 934 case SND_SOC_DAIFMT_DSP_B: 935 aif2 |= WM9081_AIF_LRCLK_INV; 936 case SND_SOC_DAIFMT_DSP_A: 937 aif2 |= 0x3; 938 break; 939 case SND_SOC_DAIFMT_I2S: 940 aif2 |= 0x2; 941 break; 942 case SND_SOC_DAIFMT_RIGHT_J: 943 break; 944 case SND_SOC_DAIFMT_LEFT_J: 945 aif2 |= 0x1; 946 break; 947 default: 948 return -EINVAL; 949 } 950 951 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 952 case SND_SOC_DAIFMT_DSP_A: 953 case SND_SOC_DAIFMT_DSP_B: 954 /* frame inversion not valid for DSP modes */ 955 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 956 case SND_SOC_DAIFMT_NB_NF: 957 break; 958 case SND_SOC_DAIFMT_IB_NF: 959 aif2 |= WM9081_AIF_BCLK_INV; 960 break; 961 default: 962 return -EINVAL; 963 } 964 break; 965 966 case SND_SOC_DAIFMT_I2S: 967 case SND_SOC_DAIFMT_RIGHT_J: 968 case SND_SOC_DAIFMT_LEFT_J: 969 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 970 case SND_SOC_DAIFMT_NB_NF: 971 break; 972 case SND_SOC_DAIFMT_IB_IF: 973 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV; 974 break; 975 case SND_SOC_DAIFMT_IB_NF: 976 aif2 |= WM9081_AIF_BCLK_INV; 977 break; 978 case SND_SOC_DAIFMT_NB_IF: 979 aif2 |= WM9081_AIF_LRCLK_INV; 980 break; 981 default: 982 return -EINVAL; 983 } 984 break; 985 default: 986 return -EINVAL; 987 } 988 989 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2); 990 991 return 0; 992 } 993 994 static int wm9081_hw_params(struct snd_pcm_substream *substream, 995 struct snd_pcm_hw_params *params, 996 struct snd_soc_dai *dai) 997 { 998 struct snd_soc_component *component = dai->component; 999 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 1000 int ret, i, best, best_val, cur_val; 1001 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; 1002 1003 clk_ctrl2 = snd_soc_component_read32(component, WM9081_CLOCK_CONTROL_2); 1004 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK); 1005 1006 aif1 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_1); 1007 1008 aif2 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_2); 1009 aif2 &= ~WM9081_AIF_WL_MASK; 1010 1011 aif3 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_3); 1012 aif3 &= ~WM9081_BCLK_DIV_MASK; 1013 1014 aif4 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_4); 1015 aif4 &= ~WM9081_LRCLK_RATE_MASK; 1016 1017 wm9081->fs = params_rate(params); 1018 1019 if (wm9081->tdm_width) { 1020 /* If TDM is set up then that fixes our BCLK. */ 1021 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >> 1022 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1; 1023 1024 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots; 1025 } else { 1026 /* Otherwise work out a BCLK from the sample size */ 1027 wm9081->bclk = 2 * wm9081->fs; 1028 1029 switch (params_width(params)) { 1030 case 16: 1031 wm9081->bclk *= 16; 1032 break; 1033 case 20: 1034 wm9081->bclk *= 20; 1035 aif2 |= 0x4; 1036 break; 1037 case 24: 1038 wm9081->bclk *= 24; 1039 aif2 |= 0x8; 1040 break; 1041 case 32: 1042 wm9081->bclk *= 32; 1043 aif2 |= 0xc; 1044 break; 1045 default: 1046 return -EINVAL; 1047 } 1048 } 1049 1050 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk); 1051 1052 ret = configure_clock(component); 1053 if (ret != 0) 1054 return ret; 1055 1056 /* Select nearest CLK_SYS_RATE */ 1057 best = 0; 1058 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio) 1059 - wm9081->fs); 1060 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1061 cur_val = abs((wm9081->sysclk_rate / 1062 clk_sys_rates[i].ratio) - wm9081->fs); 1063 if (cur_val < best_val) { 1064 best = i; 1065 best_val = cur_val; 1066 } 1067 } 1068 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n", 1069 clk_sys_rates[best].ratio); 1070 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate 1071 << WM9081_CLK_SYS_RATE_SHIFT); 1072 1073 /* SAMPLE_RATE */ 1074 best = 0; 1075 best_val = abs(wm9081->fs - sample_rates[0].rate); 1076 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1077 /* Closest match */ 1078 cur_val = abs(wm9081->fs - sample_rates[i].rate); 1079 if (cur_val < best_val) { 1080 best = i; 1081 best_val = cur_val; 1082 } 1083 } 1084 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n", 1085 sample_rates[best].rate); 1086 clk_ctrl2 |= (sample_rates[best].sample_rate 1087 << WM9081_SAMPLE_RATE_SHIFT); 1088 1089 /* BCLK_DIV */ 1090 best = 0; 1091 best_val = INT_MAX; 1092 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1093 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div) 1094 - wm9081->bclk; 1095 if (cur_val < 0) /* Table is sorted */ 1096 break; 1097 if (cur_val < best_val) { 1098 best = i; 1099 best_val = cur_val; 1100 } 1101 } 1102 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div; 1103 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1104 bclk_divs[best].div, wm9081->bclk); 1105 aif3 |= bclk_divs[best].bclk_div; 1106 1107 /* LRCLK is a simple fraction of BCLK */ 1108 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs); 1109 aif4 |= wm9081->bclk / wm9081->fs; 1110 1111 /* Apply a ReTune Mobile configuration if it's in use */ 1112 if (wm9081->pdata.num_retune_configs) { 1113 struct wm9081_pdata *pdata = &wm9081->pdata; 1114 struct wm9081_retune_mobile_setting *s; 1115 int eq1; 1116 1117 best = 0; 1118 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs); 1119 for (i = 0; i < pdata->num_retune_configs; i++) { 1120 cur_val = abs(pdata->retune_configs[i].rate - 1121 wm9081->fs); 1122 if (cur_val < best_val) { 1123 best_val = cur_val; 1124 best = i; 1125 } 1126 } 1127 s = &pdata->retune_configs[best]; 1128 1129 dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n", 1130 s->name, s->rate); 1131 1132 /* If the EQ is enabled then disable it while we write out */ 1133 eq1 = snd_soc_component_read32(component, WM9081_EQ_1) & WM9081_EQ_ENA; 1134 if (eq1 & WM9081_EQ_ENA) 1135 snd_soc_component_write(component, WM9081_EQ_1, 0); 1136 1137 /* Write out the other values */ 1138 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1139 snd_soc_component_write(component, WM9081_EQ_1 + i, s->config[i]); 1140 1141 eq1 |= (s->config[0] & ~WM9081_EQ_ENA); 1142 snd_soc_component_write(component, WM9081_EQ_1, eq1); 1143 } 1144 1145 snd_soc_component_write(component, WM9081_CLOCK_CONTROL_2, clk_ctrl2); 1146 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2); 1147 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_3, aif3); 1148 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_4, aif4); 1149 1150 return 0; 1151 } 1152 1153 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1154 { 1155 struct snd_soc_component *component = codec_dai->component; 1156 unsigned int reg; 1157 1158 reg = snd_soc_component_read32(component, WM9081_DAC_DIGITAL_2); 1159 1160 if (mute) 1161 reg |= WM9081_DAC_MUTE; 1162 else 1163 reg &= ~WM9081_DAC_MUTE; 1164 1165 snd_soc_component_write(component, WM9081_DAC_DIGITAL_2, reg); 1166 1167 return 0; 1168 } 1169 1170 static int wm9081_set_sysclk(struct snd_soc_component *component, int clk_id, 1171 int source, unsigned int freq, int dir) 1172 { 1173 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 1174 1175 switch (clk_id) { 1176 case WM9081_SYSCLK_MCLK: 1177 case WM9081_SYSCLK_FLL_MCLK: 1178 wm9081->sysclk_source = clk_id; 1179 wm9081->mclk_rate = freq; 1180 break; 1181 1182 default: 1183 return -EINVAL; 1184 } 1185 1186 return 0; 1187 } 1188 1189 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai, 1190 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1191 { 1192 struct snd_soc_component *component = dai->component; 1193 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 1194 unsigned int aif1 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_1); 1195 1196 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK); 1197 1198 if (slots < 0 || slots > 4) 1199 return -EINVAL; 1200 1201 wm9081->tdm_width = slot_width; 1202 1203 if (slots == 0) 1204 slots = 1; 1205 1206 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT; 1207 1208 switch (rx_mask) { 1209 case 1: 1210 break; 1211 case 2: 1212 aif1 |= 0x10; 1213 break; 1214 case 4: 1215 aif1 |= 0x20; 1216 break; 1217 case 8: 1218 aif1 |= 0x30; 1219 break; 1220 default: 1221 return -EINVAL; 1222 } 1223 1224 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_1, aif1); 1225 1226 return 0; 1227 } 1228 1229 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000 1230 1231 #define WM9081_FORMATS \ 1232 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1233 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1234 1235 static const struct snd_soc_dai_ops wm9081_dai_ops = { 1236 .hw_params = wm9081_hw_params, 1237 .set_fmt = wm9081_set_dai_fmt, 1238 .digital_mute = wm9081_digital_mute, 1239 .set_tdm_slot = wm9081_set_tdm_slot, 1240 }; 1241 1242 /* We report two channels because the CODEC processes a stereo signal, even 1243 * though it is only capable of handling a mono output. 1244 */ 1245 static struct snd_soc_dai_driver wm9081_dai = { 1246 .name = "wm9081-hifi", 1247 .playback = { 1248 .stream_name = "AIF", 1249 .channels_min = 1, 1250 .channels_max = 2, 1251 .rates = WM9081_RATES, 1252 .formats = WM9081_FORMATS, 1253 }, 1254 .ops = &wm9081_dai_ops, 1255 }; 1256 1257 static int wm9081_probe(struct snd_soc_component *component) 1258 { 1259 struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component); 1260 1261 /* Enable zero cross by default */ 1262 snd_soc_component_update_bits(component, WM9081_ANALOGUE_LINEOUT, 1263 WM9081_LINEOUTZC, WM9081_LINEOUTZC); 1264 snd_soc_component_update_bits(component, WM9081_ANALOGUE_SPEAKER_PGA, 1265 WM9081_SPKPGAZC, WM9081_SPKPGAZC); 1266 1267 if (!wm9081->pdata.num_retune_configs) { 1268 dev_dbg(component->dev, 1269 "No ReTune Mobile data, using normal EQ\n"); 1270 snd_soc_add_component_controls(component, wm9081_eq_controls, 1271 ARRAY_SIZE(wm9081_eq_controls)); 1272 } 1273 1274 return 0; 1275 } 1276 1277 static const struct snd_soc_component_driver soc_component_dev_wm9081 = { 1278 .probe = wm9081_probe, 1279 .set_sysclk = wm9081_set_sysclk, 1280 .set_bias_level = wm9081_set_bias_level, 1281 .controls = wm9081_snd_controls, 1282 .num_controls = ARRAY_SIZE(wm9081_snd_controls), 1283 .dapm_widgets = wm9081_dapm_widgets, 1284 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets), 1285 .dapm_routes = wm9081_audio_paths, 1286 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths), 1287 .use_pmdown_time = 1, 1288 .endianness = 1, 1289 .non_legacy_dai_naming = 1, 1290 }; 1291 1292 static const struct regmap_config wm9081_regmap = { 1293 .reg_bits = 8, 1294 .val_bits = 16, 1295 1296 .max_register = WM9081_MAX_REGISTER, 1297 .reg_defaults = wm9081_reg, 1298 .num_reg_defaults = ARRAY_SIZE(wm9081_reg), 1299 .volatile_reg = wm9081_volatile_register, 1300 .readable_reg = wm9081_readable_register, 1301 .cache_type = REGCACHE_RBTREE, 1302 }; 1303 1304 static int wm9081_i2c_probe(struct i2c_client *i2c, 1305 const struct i2c_device_id *id) 1306 { 1307 struct wm9081_priv *wm9081; 1308 unsigned int reg; 1309 int ret; 1310 1311 wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv), 1312 GFP_KERNEL); 1313 if (wm9081 == NULL) 1314 return -ENOMEM; 1315 1316 i2c_set_clientdata(i2c, wm9081); 1317 1318 wm9081->regmap = devm_regmap_init_i2c(i2c, &wm9081_regmap); 1319 if (IS_ERR(wm9081->regmap)) { 1320 ret = PTR_ERR(wm9081->regmap); 1321 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 1322 return ret; 1323 } 1324 1325 ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, ®); 1326 if (ret != 0) { 1327 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 1328 return ret; 1329 } 1330 if (reg != 0x9081) { 1331 dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg); 1332 return -EINVAL; 1333 } 1334 1335 ret = wm9081_reset(wm9081->regmap); 1336 if (ret < 0) { 1337 dev_err(&i2c->dev, "Failed to issue reset\n"); 1338 return ret; 1339 } 1340 1341 if (dev_get_platdata(&i2c->dev)) 1342 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev), 1343 sizeof(wm9081->pdata)); 1344 1345 reg = 0; 1346 if (wm9081->pdata.irq_high) 1347 reg |= WM9081_IRQ_POL; 1348 if (!wm9081->pdata.irq_cmos) 1349 reg |= WM9081_IRQ_OP_CTRL; 1350 regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL, 1351 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg); 1352 1353 regcache_cache_only(wm9081->regmap, true); 1354 1355 ret = devm_snd_soc_register_component(&i2c->dev, 1356 &soc_component_dev_wm9081, &wm9081_dai, 1); 1357 if (ret < 0) 1358 return ret; 1359 1360 return 0; 1361 } 1362 1363 static int wm9081_i2c_remove(struct i2c_client *client) 1364 { 1365 return 0; 1366 } 1367 1368 static const struct i2c_device_id wm9081_i2c_id[] = { 1369 { "wm9081", 0 }, 1370 { } 1371 }; 1372 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id); 1373 1374 static struct i2c_driver wm9081_i2c_driver = { 1375 .driver = { 1376 .name = "wm9081", 1377 }, 1378 .probe = wm9081_i2c_probe, 1379 .remove = wm9081_i2c_remove, 1380 .id_table = wm9081_i2c_id, 1381 }; 1382 1383 module_i2c_driver(wm9081_i2c_driver); 1384 1385 MODULE_DESCRIPTION("ASoC WM9081 driver"); 1386 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1387 MODULE_LICENSE("GPL"); 1388