1 /* 2 * wm8996.c - WM8996 audio codec interface 3 * 4 * Copyright 2011 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/gpio.h> 21 #include <linux/i2c.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/workqueue.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 #include <trace/events/asoc.h> 33 34 #include <sound/wm8996.h> 35 #include "wm8996.h" 36 37 #define WM8996_AIFS 2 38 39 #define HPOUT1L 1 40 #define HPOUT1R 2 41 #define HPOUT2L 4 42 #define HPOUT2R 8 43 44 #define WM8996_NUM_SUPPLIES 3 45 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = { 46 "DBVDD", 47 "AVDD1", 48 "AVDD2", 49 }; 50 51 struct wm8996_priv { 52 struct snd_soc_codec *codec; 53 54 int ldo1ena; 55 56 int sysclk; 57 int sysclk_src; 58 59 int fll_src; 60 int fll_fref; 61 int fll_fout; 62 63 struct completion fll_lock; 64 65 u16 dcs_pending; 66 struct completion dcs_done; 67 68 u16 hpout_ena; 69 u16 hpout_pending; 70 71 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES]; 72 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES]; 73 struct regulator *cpvdd; 74 int bg_ena; 75 76 struct wm8996_pdata pdata; 77 78 int rx_rate[WM8996_AIFS]; 79 int bclk_rate[WM8996_AIFS]; 80 81 /* Platform dependant ReTune mobile configuration */ 82 int num_retune_mobile_texts; 83 const char **retune_mobile_texts; 84 int retune_mobile_cfg[2]; 85 struct soc_enum retune_mobile_enum; 86 87 struct snd_soc_jack *jack; 88 bool detecting; 89 bool jack_mic; 90 wm8996_polarity_fn polarity_cb; 91 92 #ifdef CONFIG_GPIOLIB 93 struct gpio_chip gpio_chip; 94 #endif 95 }; 96 97 /* We can't use the same notifier block for more than one supply and 98 * there's no way I can see to get from a callback to the caller 99 * except container_of(). 100 */ 101 #define WM8996_REGULATOR_EVENT(n) \ 102 static int wm8996_regulator_event_##n(struct notifier_block *nb, \ 103 unsigned long event, void *data) \ 104 { \ 105 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \ 106 disable_nb[n]); \ 107 if (event & REGULATOR_EVENT_DISABLE) { \ 108 wm8996->codec->cache_sync = 1; \ 109 } \ 110 return 0; \ 111 } 112 113 WM8996_REGULATOR_EVENT(0) 114 WM8996_REGULATOR_EVENT(1) 115 WM8996_REGULATOR_EVENT(2) 116 117 static const u16 wm8996_reg[WM8996_MAX_REGISTER] = { 118 [WM8996_SOFTWARE_RESET] = 0x8996, 119 [WM8996_POWER_MANAGEMENT_7] = 0x10, 120 [WM8996_DAC1_HPOUT1_VOLUME] = 0x88, 121 [WM8996_DAC2_HPOUT2_VOLUME] = 0x88, 122 [WM8996_DAC1_LEFT_VOLUME] = 0x2c0, 123 [WM8996_DAC1_RIGHT_VOLUME] = 0x2c0, 124 [WM8996_DAC2_LEFT_VOLUME] = 0x2c0, 125 [WM8996_DAC2_RIGHT_VOLUME] = 0x2c0, 126 [WM8996_OUTPUT1_LEFT_VOLUME] = 0x80, 127 [WM8996_OUTPUT1_RIGHT_VOLUME] = 0x80, 128 [WM8996_OUTPUT2_LEFT_VOLUME] = 0x80, 129 [WM8996_OUTPUT2_RIGHT_VOLUME] = 0x80, 130 [WM8996_MICBIAS_1] = 0x39, 131 [WM8996_MICBIAS_2] = 0x39, 132 [WM8996_LDO_1] = 0x3, 133 [WM8996_LDO_2] = 0x13, 134 [WM8996_ACCESSORY_DETECT_MODE_1] = 0x4, 135 [WM8996_HEADPHONE_DETECT_1] = 0x20, 136 [WM8996_MIC_DETECT_1] = 0x7600, 137 [WM8996_MIC_DETECT_2] = 0xbf, 138 [WM8996_CHARGE_PUMP_1] = 0x1f25, 139 [WM8996_CHARGE_PUMP_2] = 0xab19, 140 [WM8996_DC_SERVO_5] = 0x2a2a, 141 [WM8996_CONTROL_INTERFACE_1] = 0x8004, 142 [WM8996_CLOCKING_1] = 0x10, 143 [WM8996_AIF_RATE] = 0x83, 144 [WM8996_FLL_CONTROL_4] = 0x5dc0, 145 [WM8996_FLL_CONTROL_5] = 0xc84, 146 [WM8996_FLL_EFS_2] = 0x2, 147 [WM8996_AIF1_TX_LRCLK_1] = 0x80, 148 [WM8996_AIF1_TX_LRCLK_2] = 0x8, 149 [WM8996_AIF1_RX_LRCLK_1] = 0x80, 150 [WM8996_AIF1TX_DATA_CONFIGURATION_1] = 0x1818, 151 [WM8996_AIF1RX_DATA_CONFIGURATION] = 0x1818, 152 [WM8996_AIF1TX_TEST] = 0x7, 153 [WM8996_AIF2_TX_LRCLK_1] = 0x80, 154 [WM8996_AIF2_TX_LRCLK_2] = 0x8, 155 [WM8996_AIF2_RX_LRCLK_1] = 0x80, 156 [WM8996_AIF2TX_DATA_CONFIGURATION_1] = 0x1818, 157 [WM8996_AIF2RX_DATA_CONFIGURATION] = 0x1818, 158 [WM8996_AIF2TX_TEST] = 0x1, 159 [WM8996_DSP1_TX_LEFT_VOLUME] = 0xc0, 160 [WM8996_DSP1_TX_RIGHT_VOLUME] = 0xc0, 161 [WM8996_DSP1_RX_LEFT_VOLUME] = 0xc0, 162 [WM8996_DSP1_RX_RIGHT_VOLUME] = 0xc0, 163 [WM8996_DSP1_TX_FILTERS] = 0x2000, 164 [WM8996_DSP1_RX_FILTERS_1] = 0x200, 165 [WM8996_DSP1_RX_FILTERS_2] = 0x10, 166 [WM8996_DSP1_DRC_1] = 0x98, 167 [WM8996_DSP1_DRC_2] = 0x845, 168 [WM8996_DSP1_RX_EQ_GAINS_1] = 0x6318, 169 [WM8996_DSP1_RX_EQ_GAINS_2] = 0x6300, 170 [WM8996_DSP1_RX_EQ_BAND_1_A] = 0xfca, 171 [WM8996_DSP1_RX_EQ_BAND_1_B] = 0x400, 172 [WM8996_DSP1_RX_EQ_BAND_1_PG] = 0xd8, 173 [WM8996_DSP1_RX_EQ_BAND_2_A] = 0x1eb5, 174 [WM8996_DSP1_RX_EQ_BAND_2_B] = 0xf145, 175 [WM8996_DSP1_RX_EQ_BAND_2_C] = 0xb75, 176 [WM8996_DSP1_RX_EQ_BAND_2_PG] = 0x1c5, 177 [WM8996_DSP1_RX_EQ_BAND_3_A] = 0x1c58, 178 [WM8996_DSP1_RX_EQ_BAND_3_B] = 0xf373, 179 [WM8996_DSP1_RX_EQ_BAND_3_C] = 0xa54, 180 [WM8996_DSP1_RX_EQ_BAND_3_PG] = 0x558, 181 [WM8996_DSP1_RX_EQ_BAND_4_A] = 0x168e, 182 [WM8996_DSP1_RX_EQ_BAND_4_B] = 0xf829, 183 [WM8996_DSP1_RX_EQ_BAND_4_C] = 0x7ad, 184 [WM8996_DSP1_RX_EQ_BAND_4_PG] = 0x1103, 185 [WM8996_DSP1_RX_EQ_BAND_5_A] = 0x564, 186 [WM8996_DSP1_RX_EQ_BAND_5_B] = 0x559, 187 [WM8996_DSP1_RX_EQ_BAND_5_PG] = 0x4000, 188 [WM8996_DSP2_TX_LEFT_VOLUME] = 0xc0, 189 [WM8996_DSP2_TX_RIGHT_VOLUME] = 0xc0, 190 [WM8996_DSP2_RX_LEFT_VOLUME] = 0xc0, 191 [WM8996_DSP2_RX_RIGHT_VOLUME] = 0xc0, 192 [WM8996_DSP2_TX_FILTERS] = 0x2000, 193 [WM8996_DSP2_RX_FILTERS_1] = 0x200, 194 [WM8996_DSP2_RX_FILTERS_2] = 0x10, 195 [WM8996_DSP2_DRC_1] = 0x98, 196 [WM8996_DSP2_DRC_2] = 0x845, 197 [WM8996_DSP2_RX_EQ_GAINS_1] = 0x6318, 198 [WM8996_DSP2_RX_EQ_GAINS_2] = 0x6300, 199 [WM8996_DSP2_RX_EQ_BAND_1_A] = 0xfca, 200 [WM8996_DSP2_RX_EQ_BAND_1_B] = 0x400, 201 [WM8996_DSP2_RX_EQ_BAND_1_PG] = 0xd8, 202 [WM8996_DSP2_RX_EQ_BAND_2_A] = 0x1eb5, 203 [WM8996_DSP2_RX_EQ_BAND_2_B] = 0xf145, 204 [WM8996_DSP2_RX_EQ_BAND_2_C] = 0xb75, 205 [WM8996_DSP2_RX_EQ_BAND_2_PG] = 0x1c5, 206 [WM8996_DSP2_RX_EQ_BAND_3_A] = 0x1c58, 207 [WM8996_DSP2_RX_EQ_BAND_3_B] = 0xf373, 208 [WM8996_DSP2_RX_EQ_BAND_3_C] = 0xa54, 209 [WM8996_DSP2_RX_EQ_BAND_3_PG] = 0x558, 210 [WM8996_DSP2_RX_EQ_BAND_4_A] = 0x168e, 211 [WM8996_DSP2_RX_EQ_BAND_4_B] = 0xf829, 212 [WM8996_DSP2_RX_EQ_BAND_4_C] = 0x7ad, 213 [WM8996_DSP2_RX_EQ_BAND_4_PG] = 0x1103, 214 [WM8996_DSP2_RX_EQ_BAND_5_A] = 0x564, 215 [WM8996_DSP2_RX_EQ_BAND_5_B] = 0x559, 216 [WM8996_DSP2_RX_EQ_BAND_5_PG] = 0x4000, 217 [WM8996_OVERSAMPLING] = 0xd, 218 [WM8996_SIDETONE] = 0x1040, 219 [WM8996_GPIO_1] = 0xa101, 220 [WM8996_GPIO_2] = 0xa101, 221 [WM8996_GPIO_3] = 0xa101, 222 [WM8996_GPIO_4] = 0xa101, 223 [WM8996_GPIO_5] = 0xa101, 224 [WM8996_PULL_CONTROL_2] = 0x140, 225 [WM8996_INTERRUPT_STATUS_1_MASK] = 0x1f, 226 [WM8996_INTERRUPT_STATUS_2_MASK] = 0x1ecf, 227 [WM8996_RIGHT_PDM_SPEAKER] = 0x1, 228 [WM8996_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69, 229 [WM8996_PDM_SPEAKER_VOLUME] = 0x66, 230 [WM8996_WRITE_SEQUENCER_0] = 0x1, 231 [WM8996_WRITE_SEQUENCER_1] = 0x1, 232 [WM8996_WRITE_SEQUENCER_3] = 0x6, 233 [WM8996_WRITE_SEQUENCER_4] = 0x40, 234 [WM8996_WRITE_SEQUENCER_5] = 0x1, 235 [WM8996_WRITE_SEQUENCER_6] = 0xf, 236 [WM8996_WRITE_SEQUENCER_7] = 0x6, 237 [WM8996_WRITE_SEQUENCER_8] = 0x1, 238 [WM8996_WRITE_SEQUENCER_9] = 0x3, 239 [WM8996_WRITE_SEQUENCER_10] = 0x104, 240 [WM8996_WRITE_SEQUENCER_12] = 0x60, 241 [WM8996_WRITE_SEQUENCER_13] = 0x11, 242 [WM8996_WRITE_SEQUENCER_14] = 0x401, 243 [WM8996_WRITE_SEQUENCER_16] = 0x50, 244 [WM8996_WRITE_SEQUENCER_17] = 0x3, 245 [WM8996_WRITE_SEQUENCER_18] = 0x100, 246 [WM8996_WRITE_SEQUENCER_20] = 0x51, 247 [WM8996_WRITE_SEQUENCER_21] = 0x3, 248 [WM8996_WRITE_SEQUENCER_22] = 0x104, 249 [WM8996_WRITE_SEQUENCER_23] = 0xa, 250 [WM8996_WRITE_SEQUENCER_24] = 0x60, 251 [WM8996_WRITE_SEQUENCER_25] = 0x3b, 252 [WM8996_WRITE_SEQUENCER_26] = 0x502, 253 [WM8996_WRITE_SEQUENCER_27] = 0x100, 254 [WM8996_WRITE_SEQUENCER_28] = 0x2fff, 255 [WM8996_WRITE_SEQUENCER_32] = 0x2fff, 256 [WM8996_WRITE_SEQUENCER_36] = 0x2fff, 257 [WM8996_WRITE_SEQUENCER_40] = 0x2fff, 258 [WM8996_WRITE_SEQUENCER_44] = 0x2fff, 259 [WM8996_WRITE_SEQUENCER_48] = 0x2fff, 260 [WM8996_WRITE_SEQUENCER_52] = 0x2fff, 261 [WM8996_WRITE_SEQUENCER_56] = 0x2fff, 262 [WM8996_WRITE_SEQUENCER_60] = 0x2fff, 263 [WM8996_WRITE_SEQUENCER_64] = 0x1, 264 [WM8996_WRITE_SEQUENCER_65] = 0x1, 265 [WM8996_WRITE_SEQUENCER_67] = 0x6, 266 [WM8996_WRITE_SEQUENCER_68] = 0x40, 267 [WM8996_WRITE_SEQUENCER_69] = 0x1, 268 [WM8996_WRITE_SEQUENCER_70] = 0xf, 269 [WM8996_WRITE_SEQUENCER_71] = 0x6, 270 [WM8996_WRITE_SEQUENCER_72] = 0x1, 271 [WM8996_WRITE_SEQUENCER_73] = 0x3, 272 [WM8996_WRITE_SEQUENCER_74] = 0x104, 273 [WM8996_WRITE_SEQUENCER_76] = 0x60, 274 [WM8996_WRITE_SEQUENCER_77] = 0x11, 275 [WM8996_WRITE_SEQUENCER_78] = 0x401, 276 [WM8996_WRITE_SEQUENCER_80] = 0x50, 277 [WM8996_WRITE_SEQUENCER_81] = 0x3, 278 [WM8996_WRITE_SEQUENCER_82] = 0x100, 279 [WM8996_WRITE_SEQUENCER_84] = 0x60, 280 [WM8996_WRITE_SEQUENCER_85] = 0x3b, 281 [WM8996_WRITE_SEQUENCER_86] = 0x502, 282 [WM8996_WRITE_SEQUENCER_87] = 0x100, 283 [WM8996_WRITE_SEQUENCER_88] = 0x2fff, 284 [WM8996_WRITE_SEQUENCER_92] = 0x2fff, 285 [WM8996_WRITE_SEQUENCER_96] = 0x2fff, 286 [WM8996_WRITE_SEQUENCER_100] = 0x2fff, 287 [WM8996_WRITE_SEQUENCER_104] = 0x2fff, 288 [WM8996_WRITE_SEQUENCER_108] = 0x2fff, 289 [WM8996_WRITE_SEQUENCER_112] = 0x2fff, 290 [WM8996_WRITE_SEQUENCER_116] = 0x2fff, 291 [WM8996_WRITE_SEQUENCER_120] = 0x2fff, 292 [WM8996_WRITE_SEQUENCER_124] = 0x2fff, 293 [WM8996_WRITE_SEQUENCER_128] = 0x1, 294 [WM8996_WRITE_SEQUENCER_129] = 0x1, 295 [WM8996_WRITE_SEQUENCER_131] = 0x6, 296 [WM8996_WRITE_SEQUENCER_132] = 0x40, 297 [WM8996_WRITE_SEQUENCER_133] = 0x1, 298 [WM8996_WRITE_SEQUENCER_134] = 0xf, 299 [WM8996_WRITE_SEQUENCER_135] = 0x6, 300 [WM8996_WRITE_SEQUENCER_136] = 0x1, 301 [WM8996_WRITE_SEQUENCER_137] = 0x3, 302 [WM8996_WRITE_SEQUENCER_138] = 0x106, 303 [WM8996_WRITE_SEQUENCER_140] = 0x61, 304 [WM8996_WRITE_SEQUENCER_141] = 0x11, 305 [WM8996_WRITE_SEQUENCER_142] = 0x401, 306 [WM8996_WRITE_SEQUENCER_144] = 0x50, 307 [WM8996_WRITE_SEQUENCER_145] = 0x3, 308 [WM8996_WRITE_SEQUENCER_146] = 0x102, 309 [WM8996_WRITE_SEQUENCER_148] = 0x51, 310 [WM8996_WRITE_SEQUENCER_149] = 0x3, 311 [WM8996_WRITE_SEQUENCER_150] = 0x106, 312 [WM8996_WRITE_SEQUENCER_151] = 0xa, 313 [WM8996_WRITE_SEQUENCER_152] = 0x61, 314 [WM8996_WRITE_SEQUENCER_153] = 0x3b, 315 [WM8996_WRITE_SEQUENCER_154] = 0x502, 316 [WM8996_WRITE_SEQUENCER_155] = 0x100, 317 [WM8996_WRITE_SEQUENCER_156] = 0x2fff, 318 [WM8996_WRITE_SEQUENCER_160] = 0x2fff, 319 [WM8996_WRITE_SEQUENCER_164] = 0x2fff, 320 [WM8996_WRITE_SEQUENCER_168] = 0x2fff, 321 [WM8996_WRITE_SEQUENCER_172] = 0x2fff, 322 [WM8996_WRITE_SEQUENCER_176] = 0x2fff, 323 [WM8996_WRITE_SEQUENCER_180] = 0x2fff, 324 [WM8996_WRITE_SEQUENCER_184] = 0x2fff, 325 [WM8996_WRITE_SEQUENCER_188] = 0x2fff, 326 [WM8996_WRITE_SEQUENCER_192] = 0x1, 327 [WM8996_WRITE_SEQUENCER_193] = 0x1, 328 [WM8996_WRITE_SEQUENCER_195] = 0x6, 329 [WM8996_WRITE_SEQUENCER_196] = 0x40, 330 [WM8996_WRITE_SEQUENCER_197] = 0x1, 331 [WM8996_WRITE_SEQUENCER_198] = 0xf, 332 [WM8996_WRITE_SEQUENCER_199] = 0x6, 333 [WM8996_WRITE_SEQUENCER_200] = 0x1, 334 [WM8996_WRITE_SEQUENCER_201] = 0x3, 335 [WM8996_WRITE_SEQUENCER_202] = 0x106, 336 [WM8996_WRITE_SEQUENCER_204] = 0x61, 337 [WM8996_WRITE_SEQUENCER_205] = 0x11, 338 [WM8996_WRITE_SEQUENCER_206] = 0x401, 339 [WM8996_WRITE_SEQUENCER_208] = 0x50, 340 [WM8996_WRITE_SEQUENCER_209] = 0x3, 341 [WM8996_WRITE_SEQUENCER_210] = 0x102, 342 [WM8996_WRITE_SEQUENCER_212] = 0x61, 343 [WM8996_WRITE_SEQUENCER_213] = 0x3b, 344 [WM8996_WRITE_SEQUENCER_214] = 0x502, 345 [WM8996_WRITE_SEQUENCER_215] = 0x100, 346 [WM8996_WRITE_SEQUENCER_216] = 0x2fff, 347 [WM8996_WRITE_SEQUENCER_220] = 0x2fff, 348 [WM8996_WRITE_SEQUENCER_224] = 0x2fff, 349 [WM8996_WRITE_SEQUENCER_228] = 0x2fff, 350 [WM8996_WRITE_SEQUENCER_232] = 0x2fff, 351 [WM8996_WRITE_SEQUENCER_236] = 0x2fff, 352 [WM8996_WRITE_SEQUENCER_240] = 0x2fff, 353 [WM8996_WRITE_SEQUENCER_244] = 0x2fff, 354 [WM8996_WRITE_SEQUENCER_248] = 0x2fff, 355 [WM8996_WRITE_SEQUENCER_252] = 0x2fff, 356 [WM8996_WRITE_SEQUENCER_256] = 0x60, 357 [WM8996_WRITE_SEQUENCER_258] = 0x601, 358 [WM8996_WRITE_SEQUENCER_260] = 0x50, 359 [WM8996_WRITE_SEQUENCER_262] = 0x100, 360 [WM8996_WRITE_SEQUENCER_264] = 0x1, 361 [WM8996_WRITE_SEQUENCER_266] = 0x104, 362 [WM8996_WRITE_SEQUENCER_267] = 0x100, 363 [WM8996_WRITE_SEQUENCER_268] = 0x2fff, 364 [WM8996_WRITE_SEQUENCER_272] = 0x2fff, 365 [WM8996_WRITE_SEQUENCER_276] = 0x2fff, 366 [WM8996_WRITE_SEQUENCER_280] = 0x2fff, 367 [WM8996_WRITE_SEQUENCER_284] = 0x2fff, 368 [WM8996_WRITE_SEQUENCER_288] = 0x2fff, 369 [WM8996_WRITE_SEQUENCER_292] = 0x2fff, 370 [WM8996_WRITE_SEQUENCER_296] = 0x2fff, 371 [WM8996_WRITE_SEQUENCER_300] = 0x2fff, 372 [WM8996_WRITE_SEQUENCER_304] = 0x2fff, 373 [WM8996_WRITE_SEQUENCER_308] = 0x2fff, 374 [WM8996_WRITE_SEQUENCER_312] = 0x2fff, 375 [WM8996_WRITE_SEQUENCER_316] = 0x2fff, 376 [WM8996_WRITE_SEQUENCER_320] = 0x61, 377 [WM8996_WRITE_SEQUENCER_322] = 0x601, 378 [WM8996_WRITE_SEQUENCER_324] = 0x50, 379 [WM8996_WRITE_SEQUENCER_326] = 0x102, 380 [WM8996_WRITE_SEQUENCER_328] = 0x1, 381 [WM8996_WRITE_SEQUENCER_330] = 0x106, 382 [WM8996_WRITE_SEQUENCER_331] = 0x100, 383 [WM8996_WRITE_SEQUENCER_332] = 0x2fff, 384 [WM8996_WRITE_SEQUENCER_336] = 0x2fff, 385 [WM8996_WRITE_SEQUENCER_340] = 0x2fff, 386 [WM8996_WRITE_SEQUENCER_344] = 0x2fff, 387 [WM8996_WRITE_SEQUENCER_348] = 0x2fff, 388 [WM8996_WRITE_SEQUENCER_352] = 0x2fff, 389 [WM8996_WRITE_SEQUENCER_356] = 0x2fff, 390 [WM8996_WRITE_SEQUENCER_360] = 0x2fff, 391 [WM8996_WRITE_SEQUENCER_364] = 0x2fff, 392 [WM8996_WRITE_SEQUENCER_368] = 0x2fff, 393 [WM8996_WRITE_SEQUENCER_372] = 0x2fff, 394 [WM8996_WRITE_SEQUENCER_376] = 0x2fff, 395 [WM8996_WRITE_SEQUENCER_380] = 0x2fff, 396 [WM8996_WRITE_SEQUENCER_384] = 0x60, 397 [WM8996_WRITE_SEQUENCER_386] = 0x601, 398 [WM8996_WRITE_SEQUENCER_388] = 0x61, 399 [WM8996_WRITE_SEQUENCER_390] = 0x601, 400 [WM8996_WRITE_SEQUENCER_392] = 0x50, 401 [WM8996_WRITE_SEQUENCER_394] = 0x300, 402 [WM8996_WRITE_SEQUENCER_396] = 0x1, 403 [WM8996_WRITE_SEQUENCER_398] = 0x304, 404 [WM8996_WRITE_SEQUENCER_400] = 0x40, 405 [WM8996_WRITE_SEQUENCER_402] = 0xf, 406 [WM8996_WRITE_SEQUENCER_404] = 0x1, 407 [WM8996_WRITE_SEQUENCER_407] = 0x100, 408 }; 409 410 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); 411 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 412 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 413 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); 414 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); 415 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); 416 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 417 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1); 418 419 static const char *sidetone_hpf_text[] = { 420 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" 421 }; 422 423 static const struct soc_enum sidetone_hpf = 424 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text); 425 426 static const char *hpf_mode_text[] = { 427 "HiFi", "Custom", "Voice" 428 }; 429 430 static const struct soc_enum dsp1tx_hpf_mode = 431 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text); 432 433 static const struct soc_enum dsp2tx_hpf_mode = 434 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text); 435 436 static const char *hpf_cutoff_text[] = { 437 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" 438 }; 439 440 static const struct soc_enum dsp1tx_hpf_cutoff = 441 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text); 442 443 static const struct soc_enum dsp2tx_hpf_cutoff = 444 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text); 445 446 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block) 447 { 448 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 449 struct wm8996_pdata *pdata = &wm8996->pdata; 450 int base, best, best_val, save, i, cfg, iface; 451 452 if (!wm8996->num_retune_mobile_texts) 453 return; 454 455 switch (block) { 456 case 0: 457 base = WM8996_DSP1_RX_EQ_GAINS_1; 458 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 459 WM8996_DSP1RX_SRC) 460 iface = 1; 461 else 462 iface = 0; 463 break; 464 case 1: 465 base = WM8996_DSP1_RX_EQ_GAINS_2; 466 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 467 WM8996_DSP2RX_SRC) 468 iface = 1; 469 else 470 iface = 0; 471 break; 472 default: 473 return; 474 } 475 476 /* Find the version of the currently selected configuration 477 * with the nearest sample rate. */ 478 cfg = wm8996->retune_mobile_cfg[block]; 479 best = 0; 480 best_val = INT_MAX; 481 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 482 if (strcmp(pdata->retune_mobile_cfgs[i].name, 483 wm8996->retune_mobile_texts[cfg]) == 0 && 484 abs(pdata->retune_mobile_cfgs[i].rate 485 - wm8996->rx_rate[iface]) < best_val) { 486 best = i; 487 best_val = abs(pdata->retune_mobile_cfgs[i].rate 488 - wm8996->rx_rate[iface]); 489 } 490 } 491 492 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 493 block, 494 pdata->retune_mobile_cfgs[best].name, 495 pdata->retune_mobile_cfgs[best].rate, 496 wm8996->rx_rate[iface]); 497 498 /* The EQ will be disabled while reconfiguring it, remember the 499 * current configuration. 500 */ 501 save = snd_soc_read(codec, base); 502 save &= WM8996_DSP1RX_EQ_ENA; 503 504 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) 505 snd_soc_update_bits(codec, base + i, 0xffff, 506 pdata->retune_mobile_cfgs[best].regs[i]); 507 508 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save); 509 } 510 511 /* Icky as hell but saves code duplication */ 512 static int wm8996_get_retune_mobile_block(const char *name) 513 { 514 if (strcmp(name, "DSP1 EQ Mode") == 0) 515 return 0; 516 if (strcmp(name, "DSP2 EQ Mode") == 0) 517 return 1; 518 return -EINVAL; 519 } 520 521 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 522 struct snd_ctl_elem_value *ucontrol) 523 { 524 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 525 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 526 struct wm8996_pdata *pdata = &wm8996->pdata; 527 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 528 int value = ucontrol->value.integer.value[0]; 529 530 if (block < 0) 531 return block; 532 533 if (value >= pdata->num_retune_mobile_cfgs) 534 return -EINVAL; 535 536 wm8996->retune_mobile_cfg[block] = value; 537 538 wm8996_set_retune_mobile(codec, block); 539 540 return 0; 541 } 542 543 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 544 struct snd_ctl_elem_value *ucontrol) 545 { 546 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 547 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 548 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 549 550 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block]; 551 552 return 0; 553 } 554 555 static const struct snd_kcontrol_new wm8996_snd_controls[] = { 556 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME, 557 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), 558 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME, 559 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), 560 561 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES, 562 0, 5, 24, 0, sidetone_tlv), 563 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES, 564 0, 5, 24, 0, sidetone_tlv), 565 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0), 566 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), 567 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0), 568 569 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME, 570 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 571 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME, 572 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 573 574 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS, 575 13, 1, 0), 576 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0), 577 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), 578 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), 579 580 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS, 581 13, 1, 0), 582 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0), 583 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), 584 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), 585 586 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME, 587 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 588 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1), 589 590 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME, 591 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 592 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1), 593 594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME, 595 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 596 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME, 597 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1), 598 599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME, 600 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 601 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME, 602 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1), 603 604 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0), 605 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0), 606 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0), 607 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0), 608 609 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0), 610 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0), 611 612 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0), 613 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0), 614 615 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15, 616 0, threedstereo_tlv), 617 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15, 618 0, threedstereo_tlv), 619 620 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4, 621 8, 0, out_digital_tlv), 622 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4, 623 8, 0, out_digital_tlv), 624 625 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME, 626 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), 627 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME, 628 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), 629 630 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME, 631 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), 632 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME, 633 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), 634 635 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, 636 spk_tlv), 637 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER, 638 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1), 639 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER, 640 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0), 641 642 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0), 643 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0), 644 645 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0), 646 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0), 647 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0), 648 649 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0), 650 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0), 651 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0), 652 }; 653 654 static const struct snd_kcontrol_new wm8996_eq_controls[] = { 655 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0, 656 eq_tlv), 657 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0, 658 eq_tlv), 659 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0, 660 eq_tlv), 661 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0, 662 eq_tlv), 663 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0, 664 eq_tlv), 665 666 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0, 667 eq_tlv), 668 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0, 669 eq_tlv), 670 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0, 671 eq_tlv), 672 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0, 673 eq_tlv), 674 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0, 675 eq_tlv), 676 }; 677 678 static void wm8996_bg_enable(struct snd_soc_codec *codec) 679 { 680 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 681 682 wm8996->bg_ena++; 683 if (wm8996->bg_ena == 1) { 684 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 685 WM8996_BG_ENA, WM8996_BG_ENA); 686 msleep(2); 687 } 688 } 689 690 static void wm8996_bg_disable(struct snd_soc_codec *codec) 691 { 692 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 693 694 wm8996->bg_ena--; 695 if (!wm8996->bg_ena) 696 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 697 WM8996_BG_ENA, 0); 698 } 699 700 static int bg_event(struct snd_soc_dapm_widget *w, 701 struct snd_kcontrol *kcontrol, int event) 702 { 703 struct snd_soc_codec *codec = w->codec; 704 int ret = 0; 705 706 switch (event) { 707 case SND_SOC_DAPM_PRE_PMU: 708 wm8996_bg_enable(codec); 709 break; 710 case SND_SOC_DAPM_POST_PMD: 711 wm8996_bg_disable(codec); 712 break; 713 default: 714 BUG(); 715 ret = -EINVAL; 716 } 717 718 return ret; 719 } 720 721 static int cp_event(struct snd_soc_dapm_widget *w, 722 struct snd_kcontrol *kcontrol, int event) 723 { 724 struct snd_soc_codec *codec = w->codec; 725 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 726 int ret = 0; 727 728 switch (event) { 729 case SND_SOC_DAPM_PRE_PMU: 730 ret = regulator_enable(wm8996->cpvdd); 731 if (ret != 0) 732 dev_err(codec->dev, "Failed to enable CPVDD: %d\n", 733 ret); 734 break; 735 case SND_SOC_DAPM_POST_PMU: 736 msleep(5); 737 break; 738 case SND_SOC_DAPM_POST_PMD: 739 regulator_disable_deferred(wm8996->cpvdd, 20); 740 break; 741 default: 742 BUG(); 743 ret = -EINVAL; 744 } 745 746 return ret; 747 } 748 749 static int rmv_short_event(struct snd_soc_dapm_widget *w, 750 struct snd_kcontrol *kcontrol, int event) 751 { 752 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 753 754 /* Record which outputs we enabled */ 755 switch (event) { 756 case SND_SOC_DAPM_PRE_PMD: 757 wm8996->hpout_pending &= ~w->shift; 758 break; 759 case SND_SOC_DAPM_PRE_PMU: 760 wm8996->hpout_pending |= w->shift; 761 break; 762 default: 763 BUG(); 764 return -EINVAL; 765 } 766 767 return 0; 768 } 769 770 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) 771 { 772 struct i2c_client *i2c = to_i2c_client(codec->dev); 773 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 774 int ret; 775 unsigned long timeout = 200; 776 777 snd_soc_write(codec, WM8996_DC_SERVO_2, mask); 778 779 /* Use the interrupt if possible */ 780 do { 781 if (i2c->irq) { 782 timeout = wait_for_completion_timeout(&wm8996->dcs_done, 783 msecs_to_jiffies(200)); 784 if (timeout == 0) 785 dev_err(codec->dev, "DC servo timed out\n"); 786 787 } else { 788 msleep(1); 789 timeout--; 790 } 791 792 ret = snd_soc_read(codec, WM8996_DC_SERVO_2); 793 dev_dbg(codec->dev, "DC servo state: %x\n", ret); 794 } while (timeout && ret & mask); 795 796 if (timeout == 0) 797 dev_err(codec->dev, "DC servo timed out for %x\n", mask); 798 else 799 dev_dbg(codec->dev, "DC servo complete for %x\n", mask); 800 } 801 802 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm, 803 enum snd_soc_dapm_type event, int subseq) 804 { 805 struct snd_soc_codec *codec = container_of(dapm, 806 struct snd_soc_codec, dapm); 807 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 808 u16 val, mask; 809 810 /* Complete any pending DC servo starts */ 811 if (wm8996->dcs_pending) { 812 dev_dbg(codec->dev, "Starting DC servo for %x\n", 813 wm8996->dcs_pending); 814 815 /* Trigger a startup sequence */ 816 wait_for_dc_servo(codec, wm8996->dcs_pending 817 << WM8996_DCS_TRIG_STARTUP_0_SHIFT); 818 819 wm8996->dcs_pending = 0; 820 } 821 822 if (wm8996->hpout_pending != wm8996->hpout_ena) { 823 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", 824 wm8996->hpout_ena, wm8996->hpout_pending); 825 826 val = 0; 827 mask = 0; 828 if (wm8996->hpout_pending & HPOUT1L) { 829 val |= WM8996_HPOUT1L_RMV_SHORT; 830 mask |= WM8996_HPOUT1L_RMV_SHORT; 831 } else { 832 mask |= WM8996_HPOUT1L_RMV_SHORT | 833 WM8996_HPOUT1L_OUTP | 834 WM8996_HPOUT1L_DLY; 835 } 836 837 if (wm8996->hpout_pending & HPOUT1R) { 838 val |= WM8996_HPOUT1R_RMV_SHORT; 839 mask |= WM8996_HPOUT1R_RMV_SHORT; 840 } else { 841 mask |= WM8996_HPOUT1R_RMV_SHORT | 842 WM8996_HPOUT1R_OUTP | 843 WM8996_HPOUT1R_DLY; 844 } 845 846 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val); 847 848 val = 0; 849 mask = 0; 850 if (wm8996->hpout_pending & HPOUT2L) { 851 val |= WM8996_HPOUT2L_RMV_SHORT; 852 mask |= WM8996_HPOUT2L_RMV_SHORT; 853 } else { 854 mask |= WM8996_HPOUT2L_RMV_SHORT | 855 WM8996_HPOUT2L_OUTP | 856 WM8996_HPOUT2L_DLY; 857 } 858 859 if (wm8996->hpout_pending & HPOUT2R) { 860 val |= WM8996_HPOUT2R_RMV_SHORT; 861 mask |= WM8996_HPOUT2R_RMV_SHORT; 862 } else { 863 mask |= WM8996_HPOUT2R_RMV_SHORT | 864 WM8996_HPOUT2R_OUTP | 865 WM8996_HPOUT2R_DLY; 866 } 867 868 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val); 869 870 wm8996->hpout_ena = wm8996->hpout_pending; 871 } 872 } 873 874 static int dcs_start(struct snd_soc_dapm_widget *w, 875 struct snd_kcontrol *kcontrol, int event) 876 { 877 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 878 879 switch (event) { 880 case SND_SOC_DAPM_POST_PMU: 881 wm8996->dcs_pending |= 1 << w->shift; 882 break; 883 default: 884 BUG(); 885 return -EINVAL; 886 } 887 888 return 0; 889 } 890 891 static const char *sidetone_text[] = { 892 "IN1", "IN2", 893 }; 894 895 static const struct soc_enum left_sidetone_enum = 896 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text); 897 898 static const struct snd_kcontrol_new left_sidetone = 899 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); 900 901 static const struct soc_enum right_sidetone_enum = 902 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text); 903 904 static const struct snd_kcontrol_new right_sidetone = 905 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); 906 907 static const char *spk_text[] = { 908 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 909 }; 910 911 static const struct soc_enum spkl_enum = 912 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text); 913 914 static const struct snd_kcontrol_new spkl_mux = 915 SOC_DAPM_ENUM("SPKL", spkl_enum); 916 917 static const struct soc_enum spkr_enum = 918 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text); 919 920 static const struct snd_kcontrol_new spkr_mux = 921 SOC_DAPM_ENUM("SPKR", spkr_enum); 922 923 static const char *dsp1rx_text[] = { 924 "AIF1", "AIF2" 925 }; 926 927 static const struct soc_enum dsp1rx_enum = 928 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text); 929 930 static const struct snd_kcontrol_new dsp1rx = 931 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); 932 933 static const char *dsp2rx_text[] = { 934 "AIF2", "AIF1" 935 }; 936 937 static const struct soc_enum dsp2rx_enum = 938 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text); 939 940 static const struct snd_kcontrol_new dsp2rx = 941 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); 942 943 static const char *aif2tx_text[] = { 944 "DSP2", "DSP1", "AIF1" 945 }; 946 947 static const struct soc_enum aif2tx_enum = 948 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text); 949 950 static const struct snd_kcontrol_new aif2tx = 951 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); 952 953 static const char *inmux_text[] = { 954 "ADC", "DMIC1", "DMIC2" 955 }; 956 957 static const struct soc_enum in1_enum = 958 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text); 959 960 static const struct snd_kcontrol_new in1_mux = 961 SOC_DAPM_ENUM("IN1 Mux", in1_enum); 962 963 static const struct soc_enum in2_enum = 964 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text); 965 966 static const struct snd_kcontrol_new in2_mux = 967 SOC_DAPM_ENUM("IN2 Mux", in2_enum); 968 969 static const struct snd_kcontrol_new dac2r_mix[] = { 970 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 971 5, 1, 0), 972 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 973 4, 1, 0), 974 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), 975 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), 976 }; 977 978 static const struct snd_kcontrol_new dac2l_mix[] = { 979 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 980 5, 1, 0), 981 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 982 4, 1, 0), 983 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), 984 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), 985 }; 986 987 static const struct snd_kcontrol_new dac1r_mix[] = { 988 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 989 5, 1, 0), 990 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 991 4, 1, 0), 992 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), 993 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), 994 }; 995 996 static const struct snd_kcontrol_new dac1l_mix[] = { 997 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 998 5, 1, 0), 999 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1000 4, 1, 0), 1001 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), 1002 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), 1003 }; 1004 1005 static const struct snd_kcontrol_new dsp1txl[] = { 1006 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 1007 1, 1, 0), 1008 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 1009 0, 1, 0), 1010 }; 1011 1012 static const struct snd_kcontrol_new dsp1txr[] = { 1013 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 1014 1, 1, 0), 1015 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 1016 0, 1, 0), 1017 }; 1018 1019 static const struct snd_kcontrol_new dsp2txl[] = { 1020 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 1021 1, 1, 0), 1022 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 1023 0, 1, 0), 1024 }; 1025 1026 static const struct snd_kcontrol_new dsp2txr[] = { 1027 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 1028 1, 1, 0), 1029 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 1030 0, 1, 0), 1031 }; 1032 1033 1034 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = { 1035 SND_SOC_DAPM_INPUT("IN1LN"), 1036 SND_SOC_DAPM_INPUT("IN1LP"), 1037 SND_SOC_DAPM_INPUT("IN1RN"), 1038 SND_SOC_DAPM_INPUT("IN1RP"), 1039 1040 SND_SOC_DAPM_INPUT("IN2LN"), 1041 SND_SOC_DAPM_INPUT("IN2LP"), 1042 SND_SOC_DAPM_INPUT("IN2RN"), 1043 SND_SOC_DAPM_INPUT("IN2RP"), 1044 1045 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1046 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1047 1048 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0), 1049 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0), 1050 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0), 1051 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event, 1052 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1053 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event, 1054 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1055 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 1056 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0), 1057 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0), 1058 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0), 1059 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0), 1060 1061 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0), 1062 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0), 1063 1064 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux), 1065 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux), 1066 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux), 1067 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux), 1068 1069 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0), 1070 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0), 1071 1072 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0), 1073 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0), 1074 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0), 1075 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0), 1076 1077 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0), 1078 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0), 1079 1080 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), 1081 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), 1082 1083 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0), 1084 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0), 1085 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0), 1086 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0), 1087 1088 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0, 1089 dsp2txl, ARRAY_SIZE(dsp2txl)), 1090 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0, 1091 dsp2txr, ARRAY_SIZE(dsp2txr)), 1092 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0, 1093 dsp1txl, ARRAY_SIZE(dsp1txl)), 1094 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0, 1095 dsp1txr, ARRAY_SIZE(dsp1txr)), 1096 1097 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1098 dac2l_mix, ARRAY_SIZE(dac2l_mix)), 1099 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1100 dac2r_mix, ARRAY_SIZE(dac2r_mix)), 1101 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1102 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1103 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1104 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1105 1106 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0), 1107 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0), 1108 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0), 1109 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0), 1110 1111 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0, 1112 WM8996_POWER_MANAGEMENT_4, 9, 0), 1113 SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1, 1114 WM8996_POWER_MANAGEMENT_4, 8, 0), 1115 1116 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0, 1117 WM8996_POWER_MANAGEMENT_6, 9, 0), 1118 SND_SOC_DAPM_AIF_OUT("AIF2TX0", "AIF2 Capture", 1, 1119 WM8996_POWER_MANAGEMENT_6, 8, 0), 1120 1121 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5, 1122 WM8996_POWER_MANAGEMENT_4, 5, 0), 1123 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4, 1124 WM8996_POWER_MANAGEMENT_4, 4, 0), 1125 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3, 1126 WM8996_POWER_MANAGEMENT_4, 3, 0), 1127 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2, 1128 WM8996_POWER_MANAGEMENT_4, 2, 0), 1129 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1, 1130 WM8996_POWER_MANAGEMENT_4, 1, 0), 1131 SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0, 1132 WM8996_POWER_MANAGEMENT_4, 0, 0), 1133 1134 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5, 1135 WM8996_POWER_MANAGEMENT_6, 5, 0), 1136 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4, 1137 WM8996_POWER_MANAGEMENT_6, 4, 0), 1138 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3, 1139 WM8996_POWER_MANAGEMENT_6, 3, 0), 1140 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2, 1141 WM8996_POWER_MANAGEMENT_6, 2, 0), 1142 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1, 1143 WM8996_POWER_MANAGEMENT_6, 1, 0), 1144 SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0, 1145 WM8996_POWER_MANAGEMENT_6, 0, 0), 1146 1147 /* We route as stereo pairs so define some dummy widgets to squash 1148 * things down for now. RXA = 0,1, RXB = 2,3 and so on */ 1149 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), 1150 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), 1151 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), 1152 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), 1153 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), 1154 1155 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), 1156 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), 1157 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), 1158 1159 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), 1160 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), 1161 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), 1162 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), 1163 1164 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0), 1165 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0), 1166 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start, 1167 SND_SOC_DAPM_POST_PMU), 1168 SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0), 1169 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, 1170 rmv_short_event, 1171 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1172 1173 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0), 1174 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0), 1175 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start, 1176 SND_SOC_DAPM_POST_PMU), 1177 SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0), 1178 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, 1179 rmv_short_event, 1180 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1181 1182 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0), 1183 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0), 1184 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start, 1185 SND_SOC_DAPM_POST_PMU), 1186 SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0), 1187 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, 1188 rmv_short_event, 1189 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1190 1191 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0), 1192 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0), 1193 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start, 1194 SND_SOC_DAPM_POST_PMU), 1195 SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0), 1196 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, 1197 rmv_short_event, 1198 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1199 1200 SND_SOC_DAPM_OUTPUT("HPOUT1L"), 1201 SND_SOC_DAPM_OUTPUT("HPOUT1R"), 1202 SND_SOC_DAPM_OUTPUT("HPOUT2L"), 1203 SND_SOC_DAPM_OUTPUT("HPOUT2R"), 1204 SND_SOC_DAPM_OUTPUT("SPKDAT"), 1205 }; 1206 1207 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = { 1208 { "AIFCLK", NULL, "SYSCLK" }, 1209 { "SYSDSPCLK", NULL, "SYSCLK" }, 1210 { "Charge Pump", NULL, "SYSCLK" }, 1211 1212 { "MICB1", NULL, "LDO2" }, 1213 { "MICB1", NULL, "MICB1 Audio" }, 1214 { "MICB1", NULL, "Bandgap" }, 1215 { "MICB2", NULL, "LDO2" }, 1216 { "MICB2", NULL, "MICB2 Audio" }, 1217 { "MICB2", NULL, "Bandgap" }, 1218 1219 { "IN1L PGA", NULL, "IN2LN" }, 1220 { "IN1L PGA", NULL, "IN2LP" }, 1221 { "IN1L PGA", NULL, "IN1LN" }, 1222 { "IN1L PGA", NULL, "IN1LP" }, 1223 { "IN1L PGA", NULL, "Bandgap" }, 1224 1225 { "IN1R PGA", NULL, "IN2RN" }, 1226 { "IN1R PGA", NULL, "IN2RP" }, 1227 { "IN1R PGA", NULL, "IN1RN" }, 1228 { "IN1R PGA", NULL, "IN1RP" }, 1229 { "IN1R PGA", NULL, "Bandgap" }, 1230 1231 { "ADCL", NULL, "IN1L PGA" }, 1232 1233 { "ADCR", NULL, "IN1R PGA" }, 1234 1235 { "DMIC1L", NULL, "DMIC1DAT" }, 1236 { "DMIC1R", NULL, "DMIC1DAT" }, 1237 { "DMIC2L", NULL, "DMIC2DAT" }, 1238 { "DMIC2R", NULL, "DMIC2DAT" }, 1239 1240 { "DMIC2L", NULL, "DMIC2" }, 1241 { "DMIC2R", NULL, "DMIC2" }, 1242 { "DMIC1L", NULL, "DMIC1" }, 1243 { "DMIC1R", NULL, "DMIC1" }, 1244 1245 { "IN1L Mux", "ADC", "ADCL" }, 1246 { "IN1L Mux", "DMIC1", "DMIC1L" }, 1247 { "IN1L Mux", "DMIC2", "DMIC2L" }, 1248 1249 { "IN1R Mux", "ADC", "ADCR" }, 1250 { "IN1R Mux", "DMIC1", "DMIC1R" }, 1251 { "IN1R Mux", "DMIC2", "DMIC2R" }, 1252 1253 { "IN2L Mux", "ADC", "ADCL" }, 1254 { "IN2L Mux", "DMIC1", "DMIC1L" }, 1255 { "IN2L Mux", "DMIC2", "DMIC2L" }, 1256 1257 { "IN2R Mux", "ADC", "ADCR" }, 1258 { "IN2R Mux", "DMIC1", "DMIC1R" }, 1259 { "IN2R Mux", "DMIC2", "DMIC2R" }, 1260 1261 { "Left Sidetone", "IN1", "IN1L Mux" }, 1262 { "Left Sidetone", "IN2", "IN2L Mux" }, 1263 1264 { "Right Sidetone", "IN1", "IN1R Mux" }, 1265 { "Right Sidetone", "IN2", "IN2R Mux" }, 1266 1267 { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, 1268 { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, 1269 1270 { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, 1271 { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, 1272 1273 { "AIF1TX0", NULL, "DSP1TXL" }, 1274 { "AIF1TX1", NULL, "DSP1TXR" }, 1275 { "AIF1TX2", NULL, "DSP2TXL" }, 1276 { "AIF1TX3", NULL, "DSP2TXR" }, 1277 { "AIF1TX4", NULL, "AIF2RX0" }, 1278 { "AIF1TX5", NULL, "AIF2RX1" }, 1279 1280 { "AIF1RX0", NULL, "AIFCLK" }, 1281 { "AIF1RX1", NULL, "AIFCLK" }, 1282 { "AIF1RX2", NULL, "AIFCLK" }, 1283 { "AIF1RX3", NULL, "AIFCLK" }, 1284 { "AIF1RX4", NULL, "AIFCLK" }, 1285 { "AIF1RX5", NULL, "AIFCLK" }, 1286 1287 { "AIF2RX0", NULL, "AIFCLK" }, 1288 { "AIF2RX1", NULL, "AIFCLK" }, 1289 1290 { "AIF1TX0", NULL, "AIFCLK" }, 1291 { "AIF1TX1", NULL, "AIFCLK" }, 1292 { "AIF1TX2", NULL, "AIFCLK" }, 1293 { "AIF1TX3", NULL, "AIFCLK" }, 1294 { "AIF1TX4", NULL, "AIFCLK" }, 1295 { "AIF1TX5", NULL, "AIFCLK" }, 1296 1297 { "AIF2TX0", NULL, "AIFCLK" }, 1298 { "AIF2TX1", NULL, "AIFCLK" }, 1299 1300 { "DSP1RXL", NULL, "SYSDSPCLK" }, 1301 { "DSP1RXR", NULL, "SYSDSPCLK" }, 1302 { "DSP2RXL", NULL, "SYSDSPCLK" }, 1303 { "DSP2RXR", NULL, "SYSDSPCLK" }, 1304 { "DSP1TXL", NULL, "SYSDSPCLK" }, 1305 { "DSP1TXR", NULL, "SYSDSPCLK" }, 1306 { "DSP2TXL", NULL, "SYSDSPCLK" }, 1307 { "DSP2TXR", NULL, "SYSDSPCLK" }, 1308 1309 { "AIF1RXA", NULL, "AIF1RX0" }, 1310 { "AIF1RXA", NULL, "AIF1RX1" }, 1311 { "AIF1RXB", NULL, "AIF1RX2" }, 1312 { "AIF1RXB", NULL, "AIF1RX3" }, 1313 { "AIF1RXC", NULL, "AIF1RX4" }, 1314 { "AIF1RXC", NULL, "AIF1RX5" }, 1315 1316 { "AIF2RX", NULL, "AIF2RX0" }, 1317 { "AIF2RX", NULL, "AIF2RX1" }, 1318 1319 { "AIF2TX", "DSP2", "DSP2TX" }, 1320 { "AIF2TX", "DSP1", "DSP1RX" }, 1321 { "AIF2TX", "AIF1", "AIF1RXC" }, 1322 1323 { "DSP1RXL", NULL, "DSP1RX" }, 1324 { "DSP1RXR", NULL, "DSP1RX" }, 1325 { "DSP2RXL", NULL, "DSP2RX" }, 1326 { "DSP2RXR", NULL, "DSP2RX" }, 1327 1328 { "DSP2TX", NULL, "DSP2TXL" }, 1329 { "DSP2TX", NULL, "DSP2TXR" }, 1330 1331 { "DSP1RX", "AIF1", "AIF1RXA" }, 1332 { "DSP1RX", "AIF2", "AIF2RX" }, 1333 1334 { "DSP2RX", "AIF1", "AIF1RXB" }, 1335 { "DSP2RX", "AIF2", "AIF2RX" }, 1336 1337 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, 1338 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, 1339 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1340 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1341 1342 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, 1343 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, 1344 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1345 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1346 1347 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, 1348 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, 1349 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1350 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1351 1352 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, 1353 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, 1354 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1355 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1356 1357 { "DAC1L", NULL, "DAC1L Mixer" }, 1358 { "DAC1R", NULL, "DAC1R Mixer" }, 1359 { "DAC2L", NULL, "DAC2L Mixer" }, 1360 { "DAC2R", NULL, "DAC2R Mixer" }, 1361 1362 { "HPOUT2L PGA", NULL, "Charge Pump" }, 1363 { "HPOUT2L PGA", NULL, "Bandgap" }, 1364 { "HPOUT2L PGA", NULL, "DAC2L" }, 1365 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, 1366 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, 1367 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" }, 1368 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" }, 1369 1370 { "HPOUT2R PGA", NULL, "Charge Pump" }, 1371 { "HPOUT2R PGA", NULL, "Bandgap" }, 1372 { "HPOUT2R PGA", NULL, "DAC2R" }, 1373 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, 1374 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, 1375 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" }, 1376 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" }, 1377 1378 { "HPOUT1L PGA", NULL, "Charge Pump" }, 1379 { "HPOUT1L PGA", NULL, "Bandgap" }, 1380 { "HPOUT1L PGA", NULL, "DAC1L" }, 1381 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, 1382 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, 1383 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" }, 1384 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" }, 1385 1386 { "HPOUT1R PGA", NULL, "Charge Pump" }, 1387 { "HPOUT1R PGA", NULL, "Bandgap" }, 1388 { "HPOUT1R PGA", NULL, "DAC1R" }, 1389 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, 1390 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, 1391 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" }, 1392 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" }, 1393 1394 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, 1395 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, 1396 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, 1397 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, 1398 1399 { "SPKL", "DAC1L", "DAC1L" }, 1400 { "SPKL", "DAC1R", "DAC1R" }, 1401 { "SPKL", "DAC2L", "DAC2L" }, 1402 { "SPKL", "DAC2R", "DAC2R" }, 1403 1404 { "SPKR", "DAC1L", "DAC1L" }, 1405 { "SPKR", "DAC1R", "DAC1R" }, 1406 { "SPKR", "DAC2L", "DAC2L" }, 1407 { "SPKR", "DAC2R", "DAC2R" }, 1408 1409 { "SPKL PGA", NULL, "SPKL" }, 1410 { "SPKR PGA", NULL, "SPKR" }, 1411 1412 { "SPKDAT", NULL, "SPKL PGA" }, 1413 { "SPKDAT", NULL, "SPKR PGA" }, 1414 }; 1415 1416 static int wm8996_readable_register(struct snd_soc_codec *codec, 1417 unsigned int reg) 1418 { 1419 /* Due to the sparseness of the register map the compiler 1420 * output from an explicit switch statement ends up being much 1421 * more efficient than a table. 1422 */ 1423 switch (reg) { 1424 case WM8996_SOFTWARE_RESET: 1425 case WM8996_POWER_MANAGEMENT_1: 1426 case WM8996_POWER_MANAGEMENT_2: 1427 case WM8996_POWER_MANAGEMENT_3: 1428 case WM8996_POWER_MANAGEMENT_4: 1429 case WM8996_POWER_MANAGEMENT_5: 1430 case WM8996_POWER_MANAGEMENT_6: 1431 case WM8996_POWER_MANAGEMENT_7: 1432 case WM8996_POWER_MANAGEMENT_8: 1433 case WM8996_LEFT_LINE_INPUT_VOLUME: 1434 case WM8996_RIGHT_LINE_INPUT_VOLUME: 1435 case WM8996_LINE_INPUT_CONTROL: 1436 case WM8996_DAC1_HPOUT1_VOLUME: 1437 case WM8996_DAC2_HPOUT2_VOLUME: 1438 case WM8996_DAC1_LEFT_VOLUME: 1439 case WM8996_DAC1_RIGHT_VOLUME: 1440 case WM8996_DAC2_LEFT_VOLUME: 1441 case WM8996_DAC2_RIGHT_VOLUME: 1442 case WM8996_OUTPUT1_LEFT_VOLUME: 1443 case WM8996_OUTPUT1_RIGHT_VOLUME: 1444 case WM8996_OUTPUT2_LEFT_VOLUME: 1445 case WM8996_OUTPUT2_RIGHT_VOLUME: 1446 case WM8996_MICBIAS_1: 1447 case WM8996_MICBIAS_2: 1448 case WM8996_LDO_1: 1449 case WM8996_LDO_2: 1450 case WM8996_ACCESSORY_DETECT_MODE_1: 1451 case WM8996_ACCESSORY_DETECT_MODE_2: 1452 case WM8996_HEADPHONE_DETECT_1: 1453 case WM8996_HEADPHONE_DETECT_2: 1454 case WM8996_MIC_DETECT_1: 1455 case WM8996_MIC_DETECT_2: 1456 case WM8996_MIC_DETECT_3: 1457 case WM8996_CHARGE_PUMP_1: 1458 case WM8996_CHARGE_PUMP_2: 1459 case WM8996_DC_SERVO_1: 1460 case WM8996_DC_SERVO_2: 1461 case WM8996_DC_SERVO_3: 1462 case WM8996_DC_SERVO_5: 1463 case WM8996_DC_SERVO_6: 1464 case WM8996_DC_SERVO_7: 1465 case WM8996_DC_SERVO_READBACK_0: 1466 case WM8996_ANALOGUE_HP_1: 1467 case WM8996_ANALOGUE_HP_2: 1468 case WM8996_CHIP_REVISION: 1469 case WM8996_CONTROL_INTERFACE_1: 1470 case WM8996_WRITE_SEQUENCER_CTRL_1: 1471 case WM8996_WRITE_SEQUENCER_CTRL_2: 1472 case WM8996_AIF_CLOCKING_1: 1473 case WM8996_AIF_CLOCKING_2: 1474 case WM8996_CLOCKING_1: 1475 case WM8996_CLOCKING_2: 1476 case WM8996_AIF_RATE: 1477 case WM8996_FLL_CONTROL_1: 1478 case WM8996_FLL_CONTROL_2: 1479 case WM8996_FLL_CONTROL_3: 1480 case WM8996_FLL_CONTROL_4: 1481 case WM8996_FLL_CONTROL_5: 1482 case WM8996_FLL_CONTROL_6: 1483 case WM8996_FLL_EFS_1: 1484 case WM8996_FLL_EFS_2: 1485 case WM8996_AIF1_CONTROL: 1486 case WM8996_AIF1_BCLK: 1487 case WM8996_AIF1_TX_LRCLK_1: 1488 case WM8996_AIF1_TX_LRCLK_2: 1489 case WM8996_AIF1_RX_LRCLK_1: 1490 case WM8996_AIF1_RX_LRCLK_2: 1491 case WM8996_AIF1TX_DATA_CONFIGURATION_1: 1492 case WM8996_AIF1TX_DATA_CONFIGURATION_2: 1493 case WM8996_AIF1RX_DATA_CONFIGURATION: 1494 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION: 1495 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION: 1496 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION: 1497 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION: 1498 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION: 1499 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION: 1500 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION: 1501 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION: 1502 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION: 1503 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION: 1504 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION: 1505 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION: 1506 case WM8996_AIF1RX_MONO_CONFIGURATION: 1507 case WM8996_AIF1TX_TEST: 1508 case WM8996_AIF2_CONTROL: 1509 case WM8996_AIF2_BCLK: 1510 case WM8996_AIF2_TX_LRCLK_1: 1511 case WM8996_AIF2_TX_LRCLK_2: 1512 case WM8996_AIF2_RX_LRCLK_1: 1513 case WM8996_AIF2_RX_LRCLK_2: 1514 case WM8996_AIF2TX_DATA_CONFIGURATION_1: 1515 case WM8996_AIF2TX_DATA_CONFIGURATION_2: 1516 case WM8996_AIF2RX_DATA_CONFIGURATION: 1517 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION: 1518 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION: 1519 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION: 1520 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION: 1521 case WM8996_AIF2RX_MONO_CONFIGURATION: 1522 case WM8996_AIF2TX_TEST: 1523 case WM8996_DSP1_TX_LEFT_VOLUME: 1524 case WM8996_DSP1_TX_RIGHT_VOLUME: 1525 case WM8996_DSP1_RX_LEFT_VOLUME: 1526 case WM8996_DSP1_RX_RIGHT_VOLUME: 1527 case WM8996_DSP1_TX_FILTERS: 1528 case WM8996_DSP1_RX_FILTERS_1: 1529 case WM8996_DSP1_RX_FILTERS_2: 1530 case WM8996_DSP1_DRC_1: 1531 case WM8996_DSP1_DRC_2: 1532 case WM8996_DSP1_DRC_3: 1533 case WM8996_DSP1_DRC_4: 1534 case WM8996_DSP1_DRC_5: 1535 case WM8996_DSP1_RX_EQ_GAINS_1: 1536 case WM8996_DSP1_RX_EQ_GAINS_2: 1537 case WM8996_DSP1_RX_EQ_BAND_1_A: 1538 case WM8996_DSP1_RX_EQ_BAND_1_B: 1539 case WM8996_DSP1_RX_EQ_BAND_1_PG: 1540 case WM8996_DSP1_RX_EQ_BAND_2_A: 1541 case WM8996_DSP1_RX_EQ_BAND_2_B: 1542 case WM8996_DSP1_RX_EQ_BAND_2_C: 1543 case WM8996_DSP1_RX_EQ_BAND_2_PG: 1544 case WM8996_DSP1_RX_EQ_BAND_3_A: 1545 case WM8996_DSP1_RX_EQ_BAND_3_B: 1546 case WM8996_DSP1_RX_EQ_BAND_3_C: 1547 case WM8996_DSP1_RX_EQ_BAND_3_PG: 1548 case WM8996_DSP1_RX_EQ_BAND_4_A: 1549 case WM8996_DSP1_RX_EQ_BAND_4_B: 1550 case WM8996_DSP1_RX_EQ_BAND_4_C: 1551 case WM8996_DSP1_RX_EQ_BAND_4_PG: 1552 case WM8996_DSP1_RX_EQ_BAND_5_A: 1553 case WM8996_DSP1_RX_EQ_BAND_5_B: 1554 case WM8996_DSP1_RX_EQ_BAND_5_PG: 1555 case WM8996_DSP2_TX_LEFT_VOLUME: 1556 case WM8996_DSP2_TX_RIGHT_VOLUME: 1557 case WM8996_DSP2_RX_LEFT_VOLUME: 1558 case WM8996_DSP2_RX_RIGHT_VOLUME: 1559 case WM8996_DSP2_TX_FILTERS: 1560 case WM8996_DSP2_RX_FILTERS_1: 1561 case WM8996_DSP2_RX_FILTERS_2: 1562 case WM8996_DSP2_DRC_1: 1563 case WM8996_DSP2_DRC_2: 1564 case WM8996_DSP2_DRC_3: 1565 case WM8996_DSP2_DRC_4: 1566 case WM8996_DSP2_DRC_5: 1567 case WM8996_DSP2_RX_EQ_GAINS_1: 1568 case WM8996_DSP2_RX_EQ_GAINS_2: 1569 case WM8996_DSP2_RX_EQ_BAND_1_A: 1570 case WM8996_DSP2_RX_EQ_BAND_1_B: 1571 case WM8996_DSP2_RX_EQ_BAND_1_PG: 1572 case WM8996_DSP2_RX_EQ_BAND_2_A: 1573 case WM8996_DSP2_RX_EQ_BAND_2_B: 1574 case WM8996_DSP2_RX_EQ_BAND_2_C: 1575 case WM8996_DSP2_RX_EQ_BAND_2_PG: 1576 case WM8996_DSP2_RX_EQ_BAND_3_A: 1577 case WM8996_DSP2_RX_EQ_BAND_3_B: 1578 case WM8996_DSP2_RX_EQ_BAND_3_C: 1579 case WM8996_DSP2_RX_EQ_BAND_3_PG: 1580 case WM8996_DSP2_RX_EQ_BAND_4_A: 1581 case WM8996_DSP2_RX_EQ_BAND_4_B: 1582 case WM8996_DSP2_RX_EQ_BAND_4_C: 1583 case WM8996_DSP2_RX_EQ_BAND_4_PG: 1584 case WM8996_DSP2_RX_EQ_BAND_5_A: 1585 case WM8996_DSP2_RX_EQ_BAND_5_B: 1586 case WM8996_DSP2_RX_EQ_BAND_5_PG: 1587 case WM8996_DAC1_MIXER_VOLUMES: 1588 case WM8996_DAC1_LEFT_MIXER_ROUTING: 1589 case WM8996_DAC1_RIGHT_MIXER_ROUTING: 1590 case WM8996_DAC2_MIXER_VOLUMES: 1591 case WM8996_DAC2_LEFT_MIXER_ROUTING: 1592 case WM8996_DAC2_RIGHT_MIXER_ROUTING: 1593 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING: 1594 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING: 1595 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING: 1596 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING: 1597 case WM8996_DSP_TX_MIXER_SELECT: 1598 case WM8996_DAC_SOFTMUTE: 1599 case WM8996_OVERSAMPLING: 1600 case WM8996_SIDETONE: 1601 case WM8996_GPIO_1: 1602 case WM8996_GPIO_2: 1603 case WM8996_GPIO_3: 1604 case WM8996_GPIO_4: 1605 case WM8996_GPIO_5: 1606 case WM8996_PULL_CONTROL_1: 1607 case WM8996_PULL_CONTROL_2: 1608 case WM8996_INTERRUPT_STATUS_1: 1609 case WM8996_INTERRUPT_STATUS_2: 1610 case WM8996_INTERRUPT_RAW_STATUS_2: 1611 case WM8996_INTERRUPT_STATUS_1_MASK: 1612 case WM8996_INTERRUPT_STATUS_2_MASK: 1613 case WM8996_INTERRUPT_CONTROL: 1614 case WM8996_LEFT_PDM_SPEAKER: 1615 case WM8996_RIGHT_PDM_SPEAKER: 1616 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE: 1617 case WM8996_PDM_SPEAKER_VOLUME: 1618 return 1; 1619 default: 1620 return 0; 1621 } 1622 } 1623 1624 static int wm8996_volatile_register(struct snd_soc_codec *codec, 1625 unsigned int reg) 1626 { 1627 switch (reg) { 1628 case WM8996_SOFTWARE_RESET: 1629 case WM8996_CHIP_REVISION: 1630 case WM8996_LDO_1: 1631 case WM8996_LDO_2: 1632 case WM8996_INTERRUPT_STATUS_1: 1633 case WM8996_INTERRUPT_STATUS_2: 1634 case WM8996_INTERRUPT_RAW_STATUS_2: 1635 case WM8996_DC_SERVO_READBACK_0: 1636 case WM8996_DC_SERVO_2: 1637 case WM8996_DC_SERVO_6: 1638 case WM8996_DC_SERVO_7: 1639 case WM8996_FLL_CONTROL_6: 1640 case WM8996_MIC_DETECT_3: 1641 case WM8996_HEADPHONE_DETECT_1: 1642 case WM8996_HEADPHONE_DETECT_2: 1643 return 1; 1644 default: 1645 return 0; 1646 } 1647 } 1648 1649 static int wm8996_reset(struct snd_soc_codec *codec) 1650 { 1651 return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915); 1652 } 1653 1654 static const int bclk_divs[] = { 1655 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 1656 }; 1657 1658 static void wm8996_update_bclk(struct snd_soc_codec *codec) 1659 { 1660 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1661 int aif, best, cur_val, bclk_rate, bclk_reg, i; 1662 1663 /* Don't bother if we're in a low frequency idle mode that 1664 * can't support audio. 1665 */ 1666 if (wm8996->sysclk < 64000) 1667 return; 1668 1669 for (aif = 0; aif < WM8996_AIFS; aif++) { 1670 switch (aif) { 1671 case 0: 1672 bclk_reg = WM8996_AIF1_BCLK; 1673 break; 1674 case 1: 1675 bclk_reg = WM8996_AIF2_BCLK; 1676 break; 1677 } 1678 1679 bclk_rate = wm8996->bclk_rate[aif]; 1680 1681 /* Pick a divisor for BCLK as close as we can get to ideal */ 1682 best = 0; 1683 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1684 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate; 1685 if (cur_val < 0) /* BCLK table is sorted */ 1686 break; 1687 best = i; 1688 } 1689 bclk_rate = wm8996->sysclk / bclk_divs[best]; 1690 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1691 bclk_divs[best], bclk_rate); 1692 1693 snd_soc_update_bits(codec, bclk_reg, 1694 WM8996_AIF1_BCLK_DIV_MASK, best); 1695 } 1696 } 1697 1698 static int wm8996_set_bias_level(struct snd_soc_codec *codec, 1699 enum snd_soc_bias_level level) 1700 { 1701 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1702 int ret; 1703 1704 switch (level) { 1705 case SND_SOC_BIAS_ON: 1706 case SND_SOC_BIAS_PREPARE: 1707 break; 1708 1709 case SND_SOC_BIAS_STANDBY: 1710 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1711 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 1712 wm8996->supplies); 1713 if (ret != 0) { 1714 dev_err(codec->dev, 1715 "Failed to enable supplies: %d\n", 1716 ret); 1717 return ret; 1718 } 1719 1720 if (wm8996->pdata.ldo_ena >= 0) { 1721 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1722 1); 1723 msleep(5); 1724 } 1725 1726 codec->cache_only = false; 1727 snd_soc_cache_sync(codec); 1728 } 1729 break; 1730 1731 case SND_SOC_BIAS_OFF: 1732 codec->cache_only = true; 1733 if (wm8996->pdata.ldo_ena >= 0) 1734 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 1735 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), 1736 wm8996->supplies); 1737 break; 1738 } 1739 1740 codec->dapm.bias_level = level; 1741 1742 return 0; 1743 } 1744 1745 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1746 { 1747 struct snd_soc_codec *codec = dai->codec; 1748 int aifctrl = 0; 1749 int bclk = 0; 1750 int lrclk_tx = 0; 1751 int lrclk_rx = 0; 1752 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; 1753 1754 switch (dai->id) { 1755 case 0: 1756 aifctrl_reg = WM8996_AIF1_CONTROL; 1757 bclk_reg = WM8996_AIF1_BCLK; 1758 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2; 1759 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2; 1760 break; 1761 case 1: 1762 aifctrl_reg = WM8996_AIF2_CONTROL; 1763 bclk_reg = WM8996_AIF2_BCLK; 1764 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2; 1765 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2; 1766 break; 1767 default: 1768 BUG(); 1769 return -EINVAL; 1770 } 1771 1772 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1773 case SND_SOC_DAIFMT_NB_NF: 1774 break; 1775 case SND_SOC_DAIFMT_IB_NF: 1776 bclk |= WM8996_AIF1_BCLK_INV; 1777 break; 1778 case SND_SOC_DAIFMT_NB_IF: 1779 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1780 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1781 break; 1782 case SND_SOC_DAIFMT_IB_IF: 1783 bclk |= WM8996_AIF1_BCLK_INV; 1784 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1785 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1786 break; 1787 } 1788 1789 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1790 case SND_SOC_DAIFMT_CBS_CFS: 1791 break; 1792 case SND_SOC_DAIFMT_CBS_CFM: 1793 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1794 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1795 break; 1796 case SND_SOC_DAIFMT_CBM_CFS: 1797 bclk |= WM8996_AIF1_BCLK_MSTR; 1798 break; 1799 case SND_SOC_DAIFMT_CBM_CFM: 1800 bclk |= WM8996_AIF1_BCLK_MSTR; 1801 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1802 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1803 break; 1804 default: 1805 return -EINVAL; 1806 } 1807 1808 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1809 case SND_SOC_DAIFMT_DSP_A: 1810 break; 1811 case SND_SOC_DAIFMT_DSP_B: 1812 aifctrl |= 1; 1813 break; 1814 case SND_SOC_DAIFMT_I2S: 1815 aifctrl |= 2; 1816 break; 1817 case SND_SOC_DAIFMT_LEFT_J: 1818 aifctrl |= 3; 1819 break; 1820 default: 1821 return -EINVAL; 1822 } 1823 1824 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl); 1825 snd_soc_update_bits(codec, bclk_reg, 1826 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR, 1827 bclk); 1828 snd_soc_update_bits(codec, lrclk_tx_reg, 1829 WM8996_AIF1TX_LRCLK_INV | 1830 WM8996_AIF1TX_LRCLK_MSTR, 1831 lrclk_tx); 1832 snd_soc_update_bits(codec, lrclk_rx_reg, 1833 WM8996_AIF1RX_LRCLK_INV | 1834 WM8996_AIF1RX_LRCLK_MSTR, 1835 lrclk_rx); 1836 1837 return 0; 1838 } 1839 1840 static const int dsp_divs[] = { 1841 48000, 32000, 16000, 8000 1842 }; 1843 1844 static int wm8996_hw_params(struct snd_pcm_substream *substream, 1845 struct snd_pcm_hw_params *params, 1846 struct snd_soc_dai *dai) 1847 { 1848 struct snd_soc_codec *codec = dai->codec; 1849 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1850 int bits, i, bclk_rate; 1851 int aifdata = 0; 1852 int lrclk = 0; 1853 int dsp = 0; 1854 int aifdata_reg, lrclk_reg, dsp_shift; 1855 1856 switch (dai->id) { 1857 case 0: 1858 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1859 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) { 1860 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION; 1861 lrclk_reg = WM8996_AIF1_RX_LRCLK_1; 1862 } else { 1863 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1; 1864 lrclk_reg = WM8996_AIF1_TX_LRCLK_1; 1865 } 1866 dsp_shift = 0; 1867 break; 1868 case 1: 1869 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1870 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) { 1871 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION; 1872 lrclk_reg = WM8996_AIF2_RX_LRCLK_1; 1873 } else { 1874 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1; 1875 lrclk_reg = WM8996_AIF2_TX_LRCLK_1; 1876 } 1877 dsp_shift = WM8996_DSP2_DIV_SHIFT; 1878 break; 1879 default: 1880 BUG(); 1881 return -EINVAL; 1882 } 1883 1884 bclk_rate = snd_soc_params_to_bclk(params); 1885 if (bclk_rate < 0) { 1886 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); 1887 return bclk_rate; 1888 } 1889 1890 wm8996->bclk_rate[dai->id] = bclk_rate; 1891 wm8996->rx_rate[dai->id] = params_rate(params); 1892 1893 /* Needs looking at for TDM */ 1894 bits = snd_pcm_format_width(params_format(params)); 1895 if (bits < 0) 1896 return bits; 1897 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits; 1898 1899 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { 1900 if (dsp_divs[i] == params_rate(params)) 1901 break; 1902 } 1903 if (i == ARRAY_SIZE(dsp_divs)) { 1904 dev_err(codec->dev, "Unsupported sample rate %dHz\n", 1905 params_rate(params)); 1906 return -EINVAL; 1907 } 1908 dsp |= i << dsp_shift; 1909 1910 wm8996_update_bclk(codec); 1911 1912 lrclk = bclk_rate / params_rate(params); 1913 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1914 lrclk, bclk_rate / lrclk); 1915 1916 snd_soc_update_bits(codec, aifdata_reg, 1917 WM8996_AIF1TX_WL_MASK | 1918 WM8996_AIF1TX_SLOT_LEN_MASK, 1919 aifdata); 1920 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK, 1921 lrclk); 1922 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2, 1923 WM8996_DSP1_DIV_MASK << dsp_shift, dsp); 1924 1925 return 0; 1926 } 1927 1928 static int wm8996_set_sysclk(struct snd_soc_dai *dai, 1929 int clk_id, unsigned int freq, int dir) 1930 { 1931 struct snd_soc_codec *codec = dai->codec; 1932 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1933 int lfclk = 0; 1934 int ratediv = 0; 1935 int src; 1936 int old; 1937 1938 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src) 1939 return 0; 1940 1941 /* Disable SYSCLK while we reconfigure */ 1942 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA; 1943 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1944 WM8996_SYSCLK_ENA, 0); 1945 1946 switch (clk_id) { 1947 case WM8996_SYSCLK_MCLK1: 1948 wm8996->sysclk = freq; 1949 src = 0; 1950 break; 1951 case WM8996_SYSCLK_MCLK2: 1952 wm8996->sysclk = freq; 1953 src = 1; 1954 break; 1955 case WM8996_SYSCLK_FLL: 1956 wm8996->sysclk = freq; 1957 src = 2; 1958 break; 1959 default: 1960 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); 1961 return -EINVAL; 1962 } 1963 1964 switch (wm8996->sysclk) { 1965 case 6144000: 1966 snd_soc_update_bits(codec, WM8996_AIF_RATE, 1967 WM8996_SYSCLK_RATE, 0); 1968 break; 1969 case 24576000: 1970 ratediv = WM8996_SYSCLK_DIV; 1971 case 12288000: 1972 snd_soc_update_bits(codec, WM8996_AIF_RATE, 1973 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); 1974 break; 1975 case 32000: 1976 case 32768: 1977 lfclk = WM8996_LFCLK_ENA; 1978 break; 1979 default: 1980 dev_warn(codec->dev, "Unsupported clock rate %dHz\n", 1981 wm8996->sysclk); 1982 return -EINVAL; 1983 } 1984 1985 wm8996_update_bclk(codec); 1986 1987 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1988 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK, 1989 src << WM8996_SYSCLK_SRC_SHIFT | ratediv); 1990 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk); 1991 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1992 WM8996_SYSCLK_ENA, old); 1993 1994 wm8996->sysclk_src = clk_id; 1995 1996 return 0; 1997 } 1998 1999 struct _fll_div { 2000 u16 fll_fratio; 2001 u16 fll_outdiv; 2002 u16 fll_refclk_div; 2003 u16 fll_loop_gain; 2004 u16 fll_ref_freq; 2005 u16 n; 2006 u16 theta; 2007 u16 lambda; 2008 }; 2009 2010 static struct { 2011 unsigned int min; 2012 unsigned int max; 2013 u16 fll_fratio; 2014 int ratio; 2015 } fll_fratios[] = { 2016 { 0, 64000, 4, 16 }, 2017 { 64000, 128000, 3, 8 }, 2018 { 128000, 256000, 2, 4 }, 2019 { 256000, 1000000, 1, 2 }, 2020 { 1000000, 13500000, 0, 1 }, 2021 }; 2022 2023 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 2024 unsigned int Fout) 2025 { 2026 unsigned int target; 2027 unsigned int div; 2028 unsigned int fratio, gcd_fll; 2029 int i; 2030 2031 /* Fref must be <=13.5MHz */ 2032 div = 1; 2033 fll_div->fll_refclk_div = 0; 2034 while ((Fref / div) > 13500000) { 2035 div *= 2; 2036 fll_div->fll_refclk_div++; 2037 2038 if (div > 8) { 2039 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 2040 Fref); 2041 return -EINVAL; 2042 } 2043 } 2044 2045 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 2046 2047 /* Apply the division for our remaining calculations */ 2048 Fref /= div; 2049 2050 if (Fref >= 3000000) 2051 fll_div->fll_loop_gain = 5; 2052 else 2053 fll_div->fll_loop_gain = 0; 2054 2055 if (Fref >= 48000) 2056 fll_div->fll_ref_freq = 0; 2057 else 2058 fll_div->fll_ref_freq = 1; 2059 2060 /* Fvco should be 90-100MHz; don't check the upper bound */ 2061 div = 2; 2062 while (Fout * div < 90000000) { 2063 div++; 2064 if (div > 64) { 2065 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 2066 Fout); 2067 return -EINVAL; 2068 } 2069 } 2070 target = Fout * div; 2071 fll_div->fll_outdiv = div - 1; 2072 2073 pr_debug("FLL Fvco=%dHz\n", target); 2074 2075 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 2076 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 2077 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 2078 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 2079 fratio = fll_fratios[i].ratio; 2080 break; 2081 } 2082 } 2083 if (i == ARRAY_SIZE(fll_fratios)) { 2084 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 2085 return -EINVAL; 2086 } 2087 2088 fll_div->n = target / (fratio * Fref); 2089 2090 if (target % Fref == 0) { 2091 fll_div->theta = 0; 2092 fll_div->lambda = 0; 2093 } else { 2094 gcd_fll = gcd(target, fratio * Fref); 2095 2096 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 2097 / gcd_fll; 2098 fll_div->lambda = (fratio * Fref) / gcd_fll; 2099 } 2100 2101 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 2102 fll_div->n, fll_div->theta, fll_div->lambda); 2103 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 2104 fll_div->fll_fratio, fll_div->fll_outdiv, 2105 fll_div->fll_refclk_div); 2106 2107 return 0; 2108 } 2109 2110 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 2111 unsigned int Fref, unsigned int Fout) 2112 { 2113 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2114 struct i2c_client *i2c = to_i2c_client(codec->dev); 2115 struct _fll_div fll_div; 2116 unsigned long timeout; 2117 int ret, reg, retry; 2118 2119 /* Any change? */ 2120 if (source == wm8996->fll_src && Fref == wm8996->fll_fref && 2121 Fout == wm8996->fll_fout) 2122 return 0; 2123 2124 if (Fout == 0) { 2125 dev_dbg(codec->dev, "FLL disabled\n"); 2126 2127 wm8996->fll_fref = 0; 2128 wm8996->fll_fout = 0; 2129 2130 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2131 WM8996_FLL_ENA, 0); 2132 2133 wm8996_bg_disable(codec); 2134 2135 return 0; 2136 } 2137 2138 ret = fll_factors(&fll_div, Fref, Fout); 2139 if (ret != 0) 2140 return ret; 2141 2142 switch (source) { 2143 case WM8996_FLL_MCLK1: 2144 reg = 0; 2145 break; 2146 case WM8996_FLL_MCLK2: 2147 reg = 1; 2148 break; 2149 case WM8996_FLL_DACLRCLK1: 2150 reg = 2; 2151 break; 2152 case WM8996_FLL_BCLK1: 2153 reg = 3; 2154 break; 2155 default: 2156 dev_err(codec->dev, "Unknown FLL source %d\n", ret); 2157 return -EINVAL; 2158 } 2159 2160 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; 2161 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; 2162 2163 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5, 2164 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ | 2165 WM8996_FLL_REFCLK_SRC_MASK, reg); 2166 2167 reg = 0; 2168 if (fll_div.theta || fll_div.lambda) 2169 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); 2170 else 2171 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; 2172 snd_soc_write(codec, WM8996_FLL_EFS_2, reg); 2173 2174 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2, 2175 WM8996_FLL_OUTDIV_MASK | 2176 WM8996_FLL_FRATIO_MASK, 2177 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) | 2178 (fll_div.fll_fratio)); 2179 2180 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta); 2181 2182 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4, 2183 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK, 2184 (fll_div.n << WM8996_FLL_N_SHIFT) | 2185 fll_div.fll_loop_gain); 2186 2187 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda); 2188 2189 /* Enable the bandgap if it's not already enabled */ 2190 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1); 2191 if (!(ret & WM8996_FLL_ENA)) 2192 wm8996_bg_enable(codec); 2193 2194 /* Clear any pending completions (eg, from failed startups) */ 2195 try_wait_for_completion(&wm8996->fll_lock); 2196 2197 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2198 WM8996_FLL_ENA, WM8996_FLL_ENA); 2199 2200 /* The FLL supports live reconfiguration - kick that in case we were 2201 * already enabled. 2202 */ 2203 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK); 2204 2205 /* Wait for the FLL to lock, using the interrupt if possible */ 2206 if (Fref > 1000000) 2207 timeout = usecs_to_jiffies(300); 2208 else 2209 timeout = msecs_to_jiffies(2); 2210 2211 /* Allow substantially longer if we've actually got the IRQ, poll 2212 * at a slightly higher rate if we don't. 2213 */ 2214 if (i2c->irq) 2215 timeout *= 10; 2216 else 2217 timeout /= 2; 2218 2219 for (retry = 0; retry < 10; retry++) { 2220 ret = wait_for_completion_timeout(&wm8996->fll_lock, 2221 timeout); 2222 if (ret != 0) { 2223 WARN_ON(!i2c->irq); 2224 break; 2225 } 2226 2227 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2); 2228 if (ret & WM8996_FLL_LOCK_STS) 2229 break; 2230 } 2231 if (retry == 10) { 2232 dev_err(codec->dev, "Timed out waiting for FLL\n"); 2233 ret = -ETIMEDOUT; 2234 } 2235 2236 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2237 2238 wm8996->fll_fref = Fref; 2239 wm8996->fll_fout = Fout; 2240 wm8996->fll_src = source; 2241 2242 return ret; 2243 } 2244 2245 #ifdef CONFIG_GPIOLIB 2246 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip) 2247 { 2248 return container_of(chip, struct wm8996_priv, gpio_chip); 2249 } 2250 2251 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 2252 { 2253 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2254 struct snd_soc_codec *codec = wm8996->codec; 2255 2256 snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, 2257 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT); 2258 } 2259 2260 static int wm8996_gpio_direction_out(struct gpio_chip *chip, 2261 unsigned offset, int value) 2262 { 2263 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2264 struct snd_soc_codec *codec = wm8996->codec; 2265 int val; 2266 2267 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); 2268 2269 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, 2270 WM8996_GP1_FN_MASK | WM8996_GP1_DIR | 2271 WM8996_GP1_LVL, val); 2272 } 2273 2274 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset) 2275 { 2276 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2277 struct snd_soc_codec *codec = wm8996->codec; 2278 int ret; 2279 2280 ret = snd_soc_read(codec, WM8996_GPIO_1 + offset); 2281 if (ret < 0) 2282 return ret; 2283 2284 return (ret & WM8996_GP1_LVL) != 0; 2285 } 2286 2287 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 2288 { 2289 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2290 struct snd_soc_codec *codec = wm8996->codec; 2291 2292 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset, 2293 WM8996_GP1_FN_MASK | WM8996_GP1_DIR, 2294 (1 << WM8996_GP1_FN_SHIFT) | 2295 (1 << WM8996_GP1_DIR_SHIFT)); 2296 } 2297 2298 static struct gpio_chip wm8996_template_chip = { 2299 .label = "wm8996", 2300 .owner = THIS_MODULE, 2301 .direction_output = wm8996_gpio_direction_out, 2302 .set = wm8996_gpio_set, 2303 .direction_input = wm8996_gpio_direction_in, 2304 .get = wm8996_gpio_get, 2305 .can_sleep = 1, 2306 }; 2307 2308 static void wm8996_init_gpio(struct snd_soc_codec *codec) 2309 { 2310 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2311 int ret; 2312 2313 wm8996->gpio_chip = wm8996_template_chip; 2314 wm8996->gpio_chip.ngpio = 5; 2315 wm8996->gpio_chip.dev = codec->dev; 2316 2317 if (wm8996->pdata.gpio_base) 2318 wm8996->gpio_chip.base = wm8996->pdata.gpio_base; 2319 else 2320 wm8996->gpio_chip.base = -1; 2321 2322 ret = gpiochip_add(&wm8996->gpio_chip); 2323 if (ret != 0) 2324 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); 2325 } 2326 2327 static void wm8996_free_gpio(struct snd_soc_codec *codec) 2328 { 2329 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2330 int ret; 2331 2332 ret = gpiochip_remove(&wm8996->gpio_chip); 2333 if (ret != 0) 2334 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); 2335 } 2336 #else 2337 static void wm8996_init_gpio(struct snd_soc_codec *codec) 2338 { 2339 } 2340 2341 static void wm8996_free_gpio(struct snd_soc_codec *codec) 2342 { 2343 } 2344 #endif 2345 2346 /** 2347 * wm8996_detect - Enable default WM8996 jack detection 2348 * 2349 * The WM8996 has advanced accessory detection support for headsets. 2350 * This function provides a default implementation which integrates 2351 * the majority of this functionality with minimal user configuration. 2352 * 2353 * This will detect headset, headphone and short circuit button and 2354 * will also detect inverted microphone ground connections and update 2355 * the polarity of the connections. 2356 */ 2357 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2358 wm8996_polarity_fn polarity_cb) 2359 { 2360 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2361 2362 wm8996->jack = jack; 2363 wm8996->detecting = true; 2364 wm8996->polarity_cb = polarity_cb; 2365 2366 if (wm8996->polarity_cb) 2367 wm8996->polarity_cb(codec, 0); 2368 2369 /* Clear discarge to avoid noise during detection */ 2370 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 2371 WM8996_MICB1_DISCH, 0); 2372 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 2373 WM8996_MICB2_DISCH, 0); 2374 2375 /* LDO2 powers the microphones, SYSCLK clocks detection */ 2376 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); 2377 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); 2378 2379 /* We start off just enabling microphone detection - even a 2380 * plain headphone will trigger detection. 2381 */ 2382 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2383 WM8996_MICD_ENA, WM8996_MICD_ENA); 2384 2385 /* Slowest detection rate, gives debounce for initial detection */ 2386 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2387 WM8996_MICD_RATE_MASK, 2388 WM8996_MICD_RATE_MASK); 2389 2390 /* Enable interrupts and we're off */ 2391 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK, 2392 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0); 2393 2394 return 0; 2395 } 2396 EXPORT_SYMBOL_GPL(wm8996_detect); 2397 2398 static void wm8996_hpdet_irq(struct snd_soc_codec *codec) 2399 { 2400 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2401 int val, reg, report; 2402 2403 /* Assume headphone in error conditions; we need to report 2404 * something or we stall our state machine. 2405 */ 2406 report = SND_JACK_HEADPHONE; 2407 2408 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2); 2409 if (reg < 0) { 2410 dev_err(codec->dev, "Failed to read HPDET status\n"); 2411 goto out; 2412 } 2413 2414 if (!(reg & WM8996_HP_DONE)) { 2415 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n"); 2416 goto out; 2417 } 2418 2419 val = reg & WM8996_HP_LVL_MASK; 2420 2421 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val); 2422 2423 /* If we've got high enough impedence then report as line, 2424 * otherwise assume headphone. 2425 */ 2426 if (val >= 126) 2427 report = SND_JACK_LINEOUT; 2428 else 2429 report = SND_JACK_HEADPHONE; 2430 2431 out: 2432 if (wm8996->jack_mic) 2433 report |= SND_JACK_MICROPHONE; 2434 2435 snd_soc_jack_report(wm8996->jack, report, 2436 SND_JACK_LINEOUT | SND_JACK_HEADSET); 2437 2438 wm8996->detecting = false; 2439 2440 /* If the output isn't running re-clamp it */ 2441 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) & 2442 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT))) 2443 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2444 WM8996_HPOUT1L_RMV_SHORT | 2445 WM8996_HPOUT1R_RMV_SHORT, 0); 2446 2447 /* Go back to looking at the microphone */ 2448 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2449 WM8996_JD_MODE_MASK, 0); 2450 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 2451 WM8996_MICD_ENA); 2452 2453 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap"); 2454 snd_soc_dapm_sync(&codec->dapm); 2455 } 2456 2457 static void wm8996_hpdet_start(struct snd_soc_codec *codec) 2458 { 2459 /* Unclamp the output, we can't measure while we're shorting it */ 2460 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2461 WM8996_HPOUT1L_RMV_SHORT | 2462 WM8996_HPOUT1R_RMV_SHORT, 2463 WM8996_HPOUT1L_RMV_SHORT | 2464 WM8996_HPOUT1R_RMV_SHORT); 2465 2466 /* We need bandgap for HPDET */ 2467 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap"); 2468 snd_soc_dapm_sync(&codec->dapm); 2469 2470 /* Go into headphone detect left mode */ 2471 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0); 2472 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2473 WM8996_JD_MODE_MASK, 1); 2474 2475 /* Trigger a measurement */ 2476 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1, 2477 WM8996_HP_POLL, WM8996_HP_POLL); 2478 } 2479 2480 static void wm8996_micd(struct snd_soc_codec *codec) 2481 { 2482 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2483 int val, reg; 2484 2485 val = snd_soc_read(codec, WM8996_MIC_DETECT_3); 2486 2487 dev_dbg(codec->dev, "Microphone event: %x\n", val); 2488 2489 if (!(val & WM8996_MICD_VALID)) { 2490 dev_warn(codec->dev, "Microphone detection state invalid\n"); 2491 return; 2492 } 2493 2494 /* No accessory, reset everything and report removal */ 2495 if (!(val & WM8996_MICD_STS)) { 2496 dev_dbg(codec->dev, "Jack removal detected\n"); 2497 wm8996->jack_mic = false; 2498 wm8996->detecting = true; 2499 snd_soc_jack_report(wm8996->jack, 0, 2500 SND_JACK_LINEOUT | SND_JACK_HEADSET | 2501 SND_JACK_BTN_0); 2502 2503 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2504 WM8996_MICD_RATE_MASK, 2505 WM8996_MICD_RATE_MASK); 2506 return; 2507 } 2508 2509 /* If the measurement is very high we've got a microphone, 2510 * either we just detected one or if we already reported then 2511 * we've got a button release event. 2512 */ 2513 if (val & 0x400) { 2514 if (wm8996->detecting) { 2515 dev_dbg(codec->dev, "Microphone detected\n"); 2516 wm8996->jack_mic = true; 2517 wm8996_hpdet_start(codec); 2518 2519 /* Increase poll rate to give better responsiveness 2520 * for buttons */ 2521 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2522 WM8996_MICD_RATE_MASK, 2523 5 << WM8996_MICD_RATE_SHIFT); 2524 } else { 2525 dev_dbg(codec->dev, "Mic button up\n"); 2526 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0); 2527 } 2528 2529 return; 2530 } 2531 2532 /* If we detected a lower impedence during initial startup 2533 * then we probably have the wrong polarity, flip it. Don't 2534 * do this for the lowest impedences to speed up detection of 2535 * plain headphones. 2536 */ 2537 if (wm8996->detecting && (val & 0x3f0)) { 2538 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2); 2539 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2540 WM8996_MICD_BIAS_SRC; 2541 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, 2542 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2543 WM8996_MICD_BIAS_SRC, reg); 2544 2545 if (wm8996->polarity_cb) 2546 wm8996->polarity_cb(codec, 2547 (reg & WM8996_MICD_SRC) != 0); 2548 2549 dev_dbg(codec->dev, "Set microphone polarity to %d\n", 2550 (reg & WM8996_MICD_SRC) != 0); 2551 2552 return; 2553 } 2554 2555 /* Don't distinguish between buttons, just report any low 2556 * impedence as BTN_0. 2557 */ 2558 if (val & 0x3fc) { 2559 if (wm8996->jack_mic) { 2560 dev_dbg(codec->dev, "Mic button detected\n"); 2561 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0, 2562 SND_JACK_BTN_0); 2563 } else if (wm8996->detecting) { 2564 dev_dbg(codec->dev, "Headphone detected\n"); 2565 wm8996_hpdet_start(codec); 2566 2567 /* Increase the detection rate a bit for 2568 * responsiveness. 2569 */ 2570 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2571 WM8996_MICD_RATE_MASK, 2572 7 << WM8996_MICD_RATE_SHIFT); 2573 } 2574 } 2575 } 2576 2577 static irqreturn_t wm8996_irq(int irq, void *data) 2578 { 2579 struct snd_soc_codec *codec = data; 2580 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2581 int irq_val; 2582 2583 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2); 2584 if (irq_val < 0) { 2585 dev_err(codec->dev, "Failed to read IRQ status: %d\n", 2586 irq_val); 2587 return IRQ_NONE; 2588 } 2589 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK); 2590 2591 if (!irq_val) 2592 return IRQ_NONE; 2593 2594 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val); 2595 2596 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) { 2597 dev_dbg(codec->dev, "DC servo IRQ\n"); 2598 complete(&wm8996->dcs_done); 2599 } 2600 2601 if (irq_val & WM8996_FIFOS_ERR_EINT) 2602 dev_err(codec->dev, "Digital core FIFO error\n"); 2603 2604 if (irq_val & WM8996_FLL_LOCK_EINT) { 2605 dev_dbg(codec->dev, "FLL locked\n"); 2606 complete(&wm8996->fll_lock); 2607 } 2608 2609 if (irq_val & WM8996_MICD_EINT) 2610 wm8996_micd(codec); 2611 2612 if (irq_val & WM8996_HP_DONE_EINT) 2613 wm8996_hpdet_irq(codec); 2614 2615 return IRQ_HANDLED; 2616 } 2617 2618 static irqreturn_t wm8996_edge_irq(int irq, void *data) 2619 { 2620 irqreturn_t ret = IRQ_NONE; 2621 irqreturn_t val; 2622 2623 do { 2624 val = wm8996_irq(irq, data); 2625 if (val != IRQ_NONE) 2626 ret = val; 2627 } while (val != IRQ_NONE); 2628 2629 return ret; 2630 } 2631 2632 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec) 2633 { 2634 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2635 struct wm8996_pdata *pdata = &wm8996->pdata; 2636 2637 struct snd_kcontrol_new controls[] = { 2638 SOC_ENUM_EXT("DSP1 EQ Mode", 2639 wm8996->retune_mobile_enum, 2640 wm8996_get_retune_mobile_enum, 2641 wm8996_put_retune_mobile_enum), 2642 SOC_ENUM_EXT("DSP2 EQ Mode", 2643 wm8996->retune_mobile_enum, 2644 wm8996_get_retune_mobile_enum, 2645 wm8996_put_retune_mobile_enum), 2646 }; 2647 int ret, i, j; 2648 const char **t; 2649 2650 /* We need an array of texts for the enum API but the number 2651 * of texts is likely to be less than the number of 2652 * configurations due to the sample rate dependency of the 2653 * configurations. */ 2654 wm8996->num_retune_mobile_texts = 0; 2655 wm8996->retune_mobile_texts = NULL; 2656 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2657 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) { 2658 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2659 wm8996->retune_mobile_texts[j]) == 0) 2660 break; 2661 } 2662 2663 if (j != wm8996->num_retune_mobile_texts) 2664 continue; 2665 2666 /* Expand the array... */ 2667 t = krealloc(wm8996->retune_mobile_texts, 2668 sizeof(char *) * 2669 (wm8996->num_retune_mobile_texts + 1), 2670 GFP_KERNEL); 2671 if (t == NULL) 2672 continue; 2673 2674 /* ...store the new entry... */ 2675 t[wm8996->num_retune_mobile_texts] = 2676 pdata->retune_mobile_cfgs[i].name; 2677 2678 /* ...and remember the new version. */ 2679 wm8996->num_retune_mobile_texts++; 2680 wm8996->retune_mobile_texts = t; 2681 } 2682 2683 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2684 wm8996->num_retune_mobile_texts); 2685 2686 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts; 2687 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts; 2688 2689 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); 2690 if (ret != 0) 2691 dev_err(codec->dev, 2692 "Failed to add ReTune Mobile controls: %d\n", ret); 2693 } 2694 2695 static int wm8996_probe(struct snd_soc_codec *codec) 2696 { 2697 int ret; 2698 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2699 struct i2c_client *i2c = to_i2c_client(codec->dev); 2700 struct snd_soc_dapm_context *dapm = &codec->dapm; 2701 int i, irq_flags; 2702 2703 wm8996->codec = codec; 2704 2705 init_completion(&wm8996->dcs_done); 2706 init_completion(&wm8996->fll_lock); 2707 2708 dapm->idle_bias_off = true; 2709 2710 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); 2711 if (ret != 0) { 2712 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2713 goto err; 2714 } 2715 2716 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 2717 wm8996->supplies[i].supply = wm8996_supply_names[i]; 2718 2719 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies), 2720 wm8996->supplies); 2721 if (ret != 0) { 2722 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2723 goto err; 2724 } 2725 2726 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0; 2727 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1; 2728 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2; 2729 2730 wm8996->cpvdd = regulator_get(&i2c->dev, "CPVDD"); 2731 if (IS_ERR(wm8996->cpvdd)) { 2732 ret = PTR_ERR(wm8996->cpvdd); 2733 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret); 2734 goto err_get; 2735 } 2736 2737 /* This should really be moved into the regulator core */ 2738 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) { 2739 ret = regulator_register_notifier(wm8996->supplies[i].consumer, 2740 &wm8996->disable_nb[i]); 2741 if (ret != 0) { 2742 dev_err(codec->dev, 2743 "Failed to register regulator notifier: %d\n", 2744 ret); 2745 } 2746 } 2747 2748 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 2749 wm8996->supplies); 2750 if (ret != 0) { 2751 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2752 goto err_cpvdd; 2753 } 2754 2755 if (wm8996->pdata.ldo_ena >= 0) { 2756 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); 2757 msleep(5); 2758 } 2759 2760 ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET); 2761 if (ret < 0) { 2762 dev_err(codec->dev, "Failed to read ID register: %d\n", ret); 2763 goto err_enable; 2764 } 2765 if (ret != 0x8915) { 2766 dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret); 2767 ret = -EINVAL; 2768 goto err_enable; 2769 } 2770 2771 ret = snd_soc_read(codec, WM8996_CHIP_REVISION); 2772 if (ret < 0) { 2773 dev_err(codec->dev, "Failed to read device revision: %d\n", 2774 ret); 2775 goto err_enable; 2776 } 2777 2778 dev_info(codec->dev, "revision %c\n", 2779 (ret & WM8996_CHIP_REV_MASK) + 'A'); 2780 2781 if (wm8996->pdata.ldo_ena >= 0) { 2782 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 2783 } else { 2784 ret = wm8996_reset(codec); 2785 if (ret < 0) { 2786 dev_err(codec->dev, "Failed to issue reset\n"); 2787 goto err_enable; 2788 } 2789 } 2790 2791 codec->cache_only = true; 2792 2793 /* Apply platform data settings */ 2794 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL, 2795 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, 2796 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT | 2797 wm8996->pdata.inr_mode); 2798 2799 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) { 2800 if (!wm8996->pdata.gpio_default[i]) 2801 continue; 2802 2803 snd_soc_write(codec, WM8996_GPIO_1 + i, 2804 wm8996->pdata.gpio_default[i] & 0xffff); 2805 } 2806 2807 if (wm8996->pdata.spkmute_seq) 2808 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 2809 WM8996_SPK_MUTE_ENDIAN | 2810 WM8996_SPK_MUTE_SEQ1_MASK, 2811 wm8996->pdata.spkmute_seq); 2812 2813 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, 2814 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC | 2815 WM8996_MICD_SRC, wm8996->pdata.micdet_def); 2816 2817 /* Latch volume update bits */ 2818 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME, 2819 WM8996_IN1_VU, WM8996_IN1_VU); 2820 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME, 2821 WM8996_IN1_VU, WM8996_IN1_VU); 2822 2823 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME, 2824 WM8996_DAC1_VU, WM8996_DAC1_VU); 2825 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME, 2826 WM8996_DAC1_VU, WM8996_DAC1_VU); 2827 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME, 2828 WM8996_DAC2_VU, WM8996_DAC2_VU); 2829 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME, 2830 WM8996_DAC2_VU, WM8996_DAC2_VU); 2831 2832 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME, 2833 WM8996_DAC1_VU, WM8996_DAC1_VU); 2834 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME, 2835 WM8996_DAC1_VU, WM8996_DAC1_VU); 2836 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME, 2837 WM8996_DAC2_VU, WM8996_DAC2_VU); 2838 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME, 2839 WM8996_DAC2_VU, WM8996_DAC2_VU); 2840 2841 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME, 2842 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2843 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME, 2844 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2845 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME, 2846 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2847 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME, 2848 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2849 2850 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME, 2851 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2852 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME, 2853 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2854 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME, 2855 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2856 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME, 2857 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2858 2859 /* No support currently for the underclocked TDM modes and 2860 * pick a default TDM layout with each channel pair working with 2861 * slots 0 and 1. */ 2862 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 2863 WM8996_AIF1RX_CHAN0_SLOTS_MASK | 2864 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2865 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0); 2866 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 2867 WM8996_AIF1RX_CHAN1_SLOTS_MASK | 2868 WM8996_AIF1RX_CHAN1_START_SLOT_MASK, 2869 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1); 2870 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 2871 WM8996_AIF1RX_CHAN2_SLOTS_MASK | 2872 WM8996_AIF1RX_CHAN2_START_SLOT_MASK, 2873 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0); 2874 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 2875 WM8996_AIF1RX_CHAN3_SLOTS_MASK | 2876 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2877 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1); 2878 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 2879 WM8996_AIF1RX_CHAN4_SLOTS_MASK | 2880 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2881 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0); 2882 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 2883 WM8996_AIF1RX_CHAN5_SLOTS_MASK | 2884 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2885 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1); 2886 2887 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 2888 WM8996_AIF2RX_CHAN0_SLOTS_MASK | 2889 WM8996_AIF2RX_CHAN0_START_SLOT_MASK, 2890 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0); 2891 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 2892 WM8996_AIF2RX_CHAN1_SLOTS_MASK | 2893 WM8996_AIF2RX_CHAN1_START_SLOT_MASK, 2894 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1); 2895 2896 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 2897 WM8996_AIF1TX_CHAN0_SLOTS_MASK | 2898 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2899 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0); 2900 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 2901 WM8996_AIF1TX_CHAN1_SLOTS_MASK | 2902 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2903 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 2904 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 2905 WM8996_AIF1TX_CHAN2_SLOTS_MASK | 2906 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2907 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0); 2908 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 2909 WM8996_AIF1TX_CHAN3_SLOTS_MASK | 2910 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2911 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1); 2912 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 2913 WM8996_AIF1TX_CHAN4_SLOTS_MASK | 2914 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2915 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0); 2916 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 2917 WM8996_AIF1TX_CHAN5_SLOTS_MASK | 2918 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2919 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1); 2920 2921 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 2922 WM8996_AIF2TX_CHAN0_SLOTS_MASK | 2923 WM8996_AIF2TX_CHAN0_START_SLOT_MASK, 2924 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0); 2925 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 2926 WM8996_AIF2TX_CHAN1_SLOTS_MASK | 2927 WM8996_AIF2TX_CHAN1_START_SLOT_MASK, 2928 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 2929 2930 if (wm8996->pdata.num_retune_mobile_cfgs) 2931 wm8996_retune_mobile_pdata(codec); 2932 else 2933 snd_soc_add_controls(codec, wm8996_eq_controls, 2934 ARRAY_SIZE(wm8996_eq_controls)); 2935 2936 /* If the TX LRCLK pins are not in LRCLK mode configure the 2937 * AIFs to source their clocks from the RX LRCLKs. 2938 */ 2939 if ((snd_soc_read(codec, WM8996_GPIO_1))) 2940 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2, 2941 WM8996_AIF1TX_LRCLK_MODE, 2942 WM8996_AIF1TX_LRCLK_MODE); 2943 2944 if ((snd_soc_read(codec, WM8996_GPIO_2))) 2945 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2, 2946 WM8996_AIF2TX_LRCLK_MODE, 2947 WM8996_AIF2TX_LRCLK_MODE); 2948 2949 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 2950 2951 wm8996_init_gpio(codec); 2952 2953 if (i2c->irq) { 2954 if (wm8996->pdata.irq_flags) 2955 irq_flags = wm8996->pdata.irq_flags; 2956 else 2957 irq_flags = IRQF_TRIGGER_LOW; 2958 2959 irq_flags |= IRQF_ONESHOT; 2960 2961 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) 2962 ret = request_threaded_irq(i2c->irq, NULL, 2963 wm8996_edge_irq, 2964 irq_flags, "wm8996", codec); 2965 else 2966 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq, 2967 irq_flags, "wm8996", codec); 2968 2969 if (ret == 0) { 2970 /* Unmask the interrupt */ 2971 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 2972 WM8996_IM_IRQ, 0); 2973 2974 /* Enable error reporting and DC servo status */ 2975 snd_soc_update_bits(codec, 2976 WM8996_INTERRUPT_STATUS_2_MASK, 2977 WM8996_IM_DCS_DONE_23_EINT | 2978 WM8996_IM_DCS_DONE_01_EINT | 2979 WM8996_IM_FLL_LOCK_EINT | 2980 WM8996_IM_FIFOS_ERR_EINT, 2981 0); 2982 } else { 2983 dev_err(codec->dev, "Failed to request IRQ: %d\n", 2984 ret); 2985 } 2986 } 2987 2988 return 0; 2989 2990 err_enable: 2991 if (wm8996->pdata.ldo_ena >= 0) 2992 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 2993 2994 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 2995 err_cpvdd: 2996 regulator_put(wm8996->cpvdd); 2997 err_get: 2998 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 2999 err: 3000 return ret; 3001 } 3002 3003 static int wm8996_remove(struct snd_soc_codec *codec) 3004 { 3005 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 3006 struct i2c_client *i2c = to_i2c_client(codec->dev); 3007 int i; 3008 3009 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 3010 WM8996_IM_IRQ, WM8996_IM_IRQ); 3011 3012 if (i2c->irq) 3013 free_irq(i2c->irq, codec); 3014 3015 wm8996_free_gpio(codec); 3016 3017 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 3018 regulator_unregister_notifier(wm8996->supplies[i].consumer, 3019 &wm8996->disable_nb[i]); 3020 regulator_put(wm8996->cpvdd); 3021 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 3022 3023 return 0; 3024 } 3025 3026 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = { 3027 .probe = wm8996_probe, 3028 .remove = wm8996_remove, 3029 .set_bias_level = wm8996_set_bias_level, 3030 .seq_notifier = wm8996_seq_notifier, 3031 .reg_cache_size = WM8996_MAX_REGISTER + 1, 3032 .reg_word_size = sizeof(u16), 3033 .reg_cache_default = wm8996_reg, 3034 .volatile_register = wm8996_volatile_register, 3035 .readable_register = wm8996_readable_register, 3036 .compress_type = SND_SOC_RBTREE_COMPRESSION, 3037 .controls = wm8996_snd_controls, 3038 .num_controls = ARRAY_SIZE(wm8996_snd_controls), 3039 .dapm_widgets = wm8996_dapm_widgets, 3040 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets), 3041 .dapm_routes = wm8996_dapm_routes, 3042 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes), 3043 .set_pll = wm8996_set_fll, 3044 }; 3045 3046 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 3047 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) 3048 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 3049 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 3050 SNDRV_PCM_FMTBIT_S32_LE) 3051 3052 static struct snd_soc_dai_ops wm8996_dai_ops = { 3053 .set_fmt = wm8996_set_fmt, 3054 .hw_params = wm8996_hw_params, 3055 .set_sysclk = wm8996_set_sysclk, 3056 }; 3057 3058 static struct snd_soc_dai_driver wm8996_dai[] = { 3059 { 3060 .name = "wm8996-aif1", 3061 .playback = { 3062 .stream_name = "AIF1 Playback", 3063 .channels_min = 1, 3064 .channels_max = 6, 3065 .rates = WM8996_RATES, 3066 .formats = WM8996_FORMATS, 3067 }, 3068 .capture = { 3069 .stream_name = "AIF1 Capture", 3070 .channels_min = 1, 3071 .channels_max = 6, 3072 .rates = WM8996_RATES, 3073 .formats = WM8996_FORMATS, 3074 }, 3075 .ops = &wm8996_dai_ops, 3076 }, 3077 { 3078 .name = "wm8996-aif2", 3079 .playback = { 3080 .stream_name = "AIF2 Playback", 3081 .channels_min = 1, 3082 .channels_max = 2, 3083 .rates = WM8996_RATES, 3084 .formats = WM8996_FORMATS, 3085 }, 3086 .capture = { 3087 .stream_name = "AIF2 Capture", 3088 .channels_min = 1, 3089 .channels_max = 2, 3090 .rates = WM8996_RATES, 3091 .formats = WM8996_FORMATS, 3092 }, 3093 .ops = &wm8996_dai_ops, 3094 }, 3095 }; 3096 3097 static __devinit int wm8996_i2c_probe(struct i2c_client *i2c, 3098 const struct i2c_device_id *id) 3099 { 3100 struct wm8996_priv *wm8996; 3101 int ret; 3102 3103 wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL); 3104 if (wm8996 == NULL) 3105 return -ENOMEM; 3106 3107 i2c_set_clientdata(i2c, wm8996); 3108 3109 if (dev_get_platdata(&i2c->dev)) 3110 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev), 3111 sizeof(wm8996->pdata)); 3112 3113 if (wm8996->pdata.ldo_ena > 0) { 3114 ret = gpio_request_one(wm8996->pdata.ldo_ena, 3115 GPIOF_OUT_INIT_LOW, "WM8996 ENA"); 3116 if (ret < 0) { 3117 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", 3118 wm8996->pdata.ldo_ena, ret); 3119 goto err; 3120 } 3121 } 3122 3123 ret = snd_soc_register_codec(&i2c->dev, 3124 &soc_codec_dev_wm8996, wm8996_dai, 3125 ARRAY_SIZE(wm8996_dai)); 3126 if (ret < 0) 3127 goto err_gpio; 3128 3129 return ret; 3130 3131 err_gpio: 3132 if (wm8996->pdata.ldo_ena > 0) 3133 gpio_free(wm8996->pdata.ldo_ena); 3134 err: 3135 kfree(wm8996); 3136 3137 return ret; 3138 } 3139 3140 static __devexit int wm8996_i2c_remove(struct i2c_client *client) 3141 { 3142 struct wm8996_priv *wm8996 = i2c_get_clientdata(client); 3143 3144 snd_soc_unregister_codec(&client->dev); 3145 if (wm8996->pdata.ldo_ena > 0) 3146 gpio_free(wm8996->pdata.ldo_ena); 3147 kfree(i2c_get_clientdata(client)); 3148 return 0; 3149 } 3150 3151 static const struct i2c_device_id wm8996_i2c_id[] = { 3152 { "wm8996", 0 }, 3153 { } 3154 }; 3155 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); 3156 3157 static struct i2c_driver wm8996_i2c_driver = { 3158 .driver = { 3159 .name = "wm8996", 3160 .owner = THIS_MODULE, 3161 }, 3162 .probe = wm8996_i2c_probe, 3163 .remove = __devexit_p(wm8996_i2c_remove), 3164 .id_table = wm8996_i2c_id, 3165 }; 3166 3167 static int __init wm8996_modinit(void) 3168 { 3169 int ret; 3170 3171 ret = i2c_add_driver(&wm8996_i2c_driver); 3172 if (ret != 0) { 3173 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n", 3174 ret); 3175 } 3176 3177 return ret; 3178 } 3179 module_init(wm8996_modinit); 3180 3181 static void __exit wm8996_exit(void) 3182 { 3183 i2c_del_driver(&wm8996_i2c_driver); 3184 } 3185 module_exit(wm8996_exit); 3186 3187 MODULE_DESCRIPTION("ASoC WM8996 driver"); 3188 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3189 MODULE_LICENSE("GPL"); 3190