1 /* 2 * wm8996.c - WM8996 audio codec interface 3 * 4 * Copyright 2011 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/gpio.h> 21 #include <linux/i2c.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <linux/workqueue.h> 26 #include <sound/core.h> 27 #include <sound/jack.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <trace/events/asoc.h> 34 35 #include <sound/wm8996.h> 36 #include "wm8996.h" 37 38 #define WM8996_AIFS 2 39 40 #define HPOUT1L 1 41 #define HPOUT1R 2 42 #define HPOUT2L 4 43 #define HPOUT2R 8 44 45 #define WM8996_NUM_SUPPLIES 3 46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = { 47 "DBVDD", 48 "AVDD1", 49 "AVDD2", 50 }; 51 52 struct wm8996_priv { 53 struct device *dev; 54 struct regmap *regmap; 55 struct snd_soc_codec *codec; 56 57 int ldo1ena; 58 59 int sysclk; 60 int sysclk_src; 61 62 int fll_src; 63 int fll_fref; 64 int fll_fout; 65 66 struct completion fll_lock; 67 68 u16 dcs_pending; 69 struct completion dcs_done; 70 71 u16 hpout_ena; 72 u16 hpout_pending; 73 74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES]; 75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES]; 76 int bg_ena; 77 78 struct wm8996_pdata pdata; 79 80 int rx_rate[WM8996_AIFS]; 81 int bclk_rate[WM8996_AIFS]; 82 83 /* Platform dependant ReTune mobile configuration */ 84 int num_retune_mobile_texts; 85 const char **retune_mobile_texts; 86 int retune_mobile_cfg[2]; 87 struct soc_enum retune_mobile_enum; 88 89 struct snd_soc_jack *jack; 90 bool detecting; 91 bool jack_mic; 92 int jack_flips; 93 wm8996_polarity_fn polarity_cb; 94 95 #ifdef CONFIG_GPIOLIB 96 struct gpio_chip gpio_chip; 97 #endif 98 }; 99 100 /* We can't use the same notifier block for more than one supply and 101 * there's no way I can see to get from a callback to the caller 102 * except container_of(). 103 */ 104 #define WM8996_REGULATOR_EVENT(n) \ 105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \ 106 unsigned long event, void *data) \ 107 { \ 108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \ 109 disable_nb[n]); \ 110 if (event & REGULATOR_EVENT_DISABLE) { \ 111 regcache_mark_dirty(wm8996->regmap); \ 112 } \ 113 return 0; \ 114 } 115 116 WM8996_REGULATOR_EVENT(0) 117 WM8996_REGULATOR_EVENT(1) 118 WM8996_REGULATOR_EVENT(2) 119 120 static struct reg_default wm8996_reg[] = { 121 { WM8996_POWER_MANAGEMENT_1, 0x0 }, 122 { WM8996_POWER_MANAGEMENT_2, 0x0 }, 123 { WM8996_POWER_MANAGEMENT_3, 0x0 }, 124 { WM8996_POWER_MANAGEMENT_4, 0x0 }, 125 { WM8996_POWER_MANAGEMENT_5, 0x0 }, 126 { WM8996_POWER_MANAGEMENT_6, 0x0 }, 127 { WM8996_POWER_MANAGEMENT_7, 0x10 }, 128 { WM8996_POWER_MANAGEMENT_8, 0x0 }, 129 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 }, 130 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 }, 131 { WM8996_LINE_INPUT_CONTROL, 0x0 }, 132 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 }, 133 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 }, 134 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 }, 135 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 }, 136 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 }, 137 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 }, 138 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 }, 139 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 }, 140 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 }, 141 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 }, 142 { WM8996_MICBIAS_1, 0x39 }, 143 { WM8996_MICBIAS_2, 0x39 }, 144 { WM8996_LDO_1, 0x3 }, 145 { WM8996_LDO_2, 0x13 }, 146 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 }, 147 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 }, 148 { WM8996_HEADPHONE_DETECT_1, 0x20 }, 149 { WM8996_HEADPHONE_DETECT_2, 0x0 }, 150 { WM8996_MIC_DETECT_1, 0x7600 }, 151 { WM8996_MIC_DETECT_2, 0xbf }, 152 { WM8996_CHARGE_PUMP_1, 0x1f25 }, 153 { WM8996_CHARGE_PUMP_2, 0xab19 }, 154 { WM8996_DC_SERVO_1, 0x0 }, 155 { WM8996_DC_SERVO_3, 0x0 }, 156 { WM8996_DC_SERVO_5, 0x2a2a }, 157 { WM8996_DC_SERVO_6, 0x0 }, 158 { WM8996_DC_SERVO_7, 0x0 }, 159 { WM8996_ANALOGUE_HP_1, 0x0 }, 160 { WM8996_ANALOGUE_HP_2, 0x0 }, 161 { WM8996_CONTROL_INTERFACE_1, 0x8004 }, 162 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 }, 163 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 }, 164 { WM8996_AIF_CLOCKING_1, 0x0 }, 165 { WM8996_AIF_CLOCKING_2, 0x0 }, 166 { WM8996_CLOCKING_1, 0x10 }, 167 { WM8996_CLOCKING_2, 0x0 }, 168 { WM8996_AIF_RATE, 0x83 }, 169 { WM8996_FLL_CONTROL_1, 0x0 }, 170 { WM8996_FLL_CONTROL_2, 0x0 }, 171 { WM8996_FLL_CONTROL_3, 0x0 }, 172 { WM8996_FLL_CONTROL_4, 0x5dc0 }, 173 { WM8996_FLL_CONTROL_5, 0xc84 }, 174 { WM8996_FLL_EFS_1, 0x0 }, 175 { WM8996_FLL_EFS_2, 0x2 }, 176 { WM8996_AIF1_CONTROL, 0x0 }, 177 { WM8996_AIF1_BCLK, 0x0 }, 178 { WM8996_AIF1_TX_LRCLK_1, 0x80 }, 179 { WM8996_AIF1_TX_LRCLK_2, 0x8 }, 180 { WM8996_AIF1_RX_LRCLK_1, 0x80 }, 181 { WM8996_AIF1_RX_LRCLK_2, 0x0 }, 182 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 }, 183 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 }, 184 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 }, 185 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 }, 186 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 }, 187 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 }, 188 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 }, 189 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 }, 190 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 }, 191 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 }, 192 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 }, 193 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 }, 194 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 }, 195 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 }, 196 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 }, 197 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 }, 198 { WM8996_AIF1TX_TEST, 0x7 }, 199 { WM8996_AIF2_CONTROL, 0x0 }, 200 { WM8996_AIF2_BCLK, 0x0 }, 201 { WM8996_AIF2_TX_LRCLK_1, 0x80 }, 202 { WM8996_AIF2_TX_LRCLK_2, 0x8 }, 203 { WM8996_AIF2_RX_LRCLK_1, 0x80 }, 204 { WM8996_AIF2_RX_LRCLK_2, 0x0 }, 205 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 }, 206 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 }, 207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 }, 208 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 }, 209 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 }, 210 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 }, 211 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 }, 212 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 }, 213 { WM8996_AIF2TX_TEST, 0x1 }, 214 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 }, 215 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 }, 216 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 }, 217 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 }, 218 { WM8996_DSP1_TX_FILTERS, 0x2000 }, 219 { WM8996_DSP1_RX_FILTERS_1, 0x200 }, 220 { WM8996_DSP1_RX_FILTERS_2, 0x10 }, 221 { WM8996_DSP1_DRC_1, 0x98 }, 222 { WM8996_DSP1_DRC_2, 0x845 }, 223 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 }, 224 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 }, 225 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca }, 226 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 }, 227 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 }, 228 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 }, 229 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 }, 230 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 }, 231 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 }, 232 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 }, 233 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 }, 234 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 }, 235 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 }, 236 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e }, 237 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 }, 238 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad }, 239 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 }, 240 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 }, 241 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 }, 242 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 }, 243 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 }, 244 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 }, 245 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 }, 246 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 }, 247 { WM8996_DSP2_TX_FILTERS, 0x2000 }, 248 { WM8996_DSP2_RX_FILTERS_1, 0x200 }, 249 { WM8996_DSP2_RX_FILTERS_2, 0x10 }, 250 { WM8996_DSP2_DRC_1, 0x98 }, 251 { WM8996_DSP2_DRC_2, 0x845 }, 252 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 }, 253 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 }, 254 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca }, 255 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 }, 256 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 }, 257 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 }, 258 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 }, 259 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 }, 260 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 }, 261 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 }, 262 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 }, 263 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 }, 264 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 }, 265 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e }, 266 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 }, 267 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad }, 268 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 }, 269 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 }, 270 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 }, 271 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 }, 272 { WM8996_DAC1_MIXER_VOLUMES, 0x0 }, 273 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 }, 274 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 }, 275 { WM8996_DAC2_MIXER_VOLUMES, 0x0 }, 276 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 }, 277 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 }, 278 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 }, 279 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 }, 280 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 }, 281 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 }, 282 { WM8996_DSP_TX_MIXER_SELECT, 0x0 }, 283 { WM8996_DAC_SOFTMUTE, 0x0 }, 284 { WM8996_OVERSAMPLING, 0xd }, 285 { WM8996_SIDETONE, 0x1040 }, 286 { WM8996_GPIO_1, 0xa101 }, 287 { WM8996_GPIO_2, 0xa101 }, 288 { WM8996_GPIO_3, 0xa101 }, 289 { WM8996_GPIO_4, 0xa101 }, 290 { WM8996_GPIO_5, 0xa101 }, 291 { WM8996_PULL_CONTROL_1, 0x0 }, 292 { WM8996_PULL_CONTROL_2, 0x140 }, 293 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f }, 294 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf }, 295 { WM8996_LEFT_PDM_SPEAKER, 0x0 }, 296 { WM8996_RIGHT_PDM_SPEAKER, 0x1 }, 297 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 }, 298 { WM8996_PDM_SPEAKER_VOLUME, 0x66 }, 299 { WM8996_WRITE_SEQUENCER_0, 0x1 }, 300 { WM8996_WRITE_SEQUENCER_1, 0x1 }, 301 { WM8996_WRITE_SEQUENCER_3, 0x6 }, 302 { WM8996_WRITE_SEQUENCER_4, 0x40 }, 303 { WM8996_WRITE_SEQUENCER_5, 0x1 }, 304 { WM8996_WRITE_SEQUENCER_6, 0xf }, 305 { WM8996_WRITE_SEQUENCER_7, 0x6 }, 306 { WM8996_WRITE_SEQUENCER_8, 0x1 }, 307 { WM8996_WRITE_SEQUENCER_9, 0x3 }, 308 { WM8996_WRITE_SEQUENCER_10, 0x104 }, 309 { WM8996_WRITE_SEQUENCER_12, 0x60 }, 310 { WM8996_WRITE_SEQUENCER_13, 0x11 }, 311 { WM8996_WRITE_SEQUENCER_14, 0x401 }, 312 { WM8996_WRITE_SEQUENCER_16, 0x50 }, 313 { WM8996_WRITE_SEQUENCER_17, 0x3 }, 314 { WM8996_WRITE_SEQUENCER_18, 0x100 }, 315 { WM8996_WRITE_SEQUENCER_20, 0x51 }, 316 { WM8996_WRITE_SEQUENCER_21, 0x3 }, 317 { WM8996_WRITE_SEQUENCER_22, 0x104 }, 318 { WM8996_WRITE_SEQUENCER_23, 0xa }, 319 { WM8996_WRITE_SEQUENCER_24, 0x60 }, 320 { WM8996_WRITE_SEQUENCER_25, 0x3b }, 321 { WM8996_WRITE_SEQUENCER_26, 0x502 }, 322 { WM8996_WRITE_SEQUENCER_27, 0x100 }, 323 { WM8996_WRITE_SEQUENCER_28, 0x2fff }, 324 { WM8996_WRITE_SEQUENCER_32, 0x2fff }, 325 { WM8996_WRITE_SEQUENCER_36, 0x2fff }, 326 { WM8996_WRITE_SEQUENCER_40, 0x2fff }, 327 { WM8996_WRITE_SEQUENCER_44, 0x2fff }, 328 { WM8996_WRITE_SEQUENCER_48, 0x2fff }, 329 { WM8996_WRITE_SEQUENCER_52, 0x2fff }, 330 { WM8996_WRITE_SEQUENCER_56, 0x2fff }, 331 { WM8996_WRITE_SEQUENCER_60, 0x2fff }, 332 { WM8996_WRITE_SEQUENCER_64, 0x1 }, 333 { WM8996_WRITE_SEQUENCER_65, 0x1 }, 334 { WM8996_WRITE_SEQUENCER_67, 0x6 }, 335 { WM8996_WRITE_SEQUENCER_68, 0x40 }, 336 { WM8996_WRITE_SEQUENCER_69, 0x1 }, 337 { WM8996_WRITE_SEQUENCER_70, 0xf }, 338 { WM8996_WRITE_SEQUENCER_71, 0x6 }, 339 { WM8996_WRITE_SEQUENCER_72, 0x1 }, 340 { WM8996_WRITE_SEQUENCER_73, 0x3 }, 341 { WM8996_WRITE_SEQUENCER_74, 0x104 }, 342 { WM8996_WRITE_SEQUENCER_76, 0x60 }, 343 { WM8996_WRITE_SEQUENCER_77, 0x11 }, 344 { WM8996_WRITE_SEQUENCER_78, 0x401 }, 345 { WM8996_WRITE_SEQUENCER_80, 0x50 }, 346 { WM8996_WRITE_SEQUENCER_81, 0x3 }, 347 { WM8996_WRITE_SEQUENCER_82, 0x100 }, 348 { WM8996_WRITE_SEQUENCER_84, 0x60 }, 349 { WM8996_WRITE_SEQUENCER_85, 0x3b }, 350 { WM8996_WRITE_SEQUENCER_86, 0x502 }, 351 { WM8996_WRITE_SEQUENCER_87, 0x100 }, 352 { WM8996_WRITE_SEQUENCER_88, 0x2fff }, 353 { WM8996_WRITE_SEQUENCER_92, 0x2fff }, 354 { WM8996_WRITE_SEQUENCER_96, 0x2fff }, 355 { WM8996_WRITE_SEQUENCER_100, 0x2fff }, 356 { WM8996_WRITE_SEQUENCER_104, 0x2fff }, 357 { WM8996_WRITE_SEQUENCER_108, 0x2fff }, 358 { WM8996_WRITE_SEQUENCER_112, 0x2fff }, 359 { WM8996_WRITE_SEQUENCER_116, 0x2fff }, 360 { WM8996_WRITE_SEQUENCER_120, 0x2fff }, 361 { WM8996_WRITE_SEQUENCER_124, 0x2fff }, 362 { WM8996_WRITE_SEQUENCER_128, 0x1 }, 363 { WM8996_WRITE_SEQUENCER_129, 0x1 }, 364 { WM8996_WRITE_SEQUENCER_131, 0x6 }, 365 { WM8996_WRITE_SEQUENCER_132, 0x40 }, 366 { WM8996_WRITE_SEQUENCER_133, 0x1 }, 367 { WM8996_WRITE_SEQUENCER_134, 0xf }, 368 { WM8996_WRITE_SEQUENCER_135, 0x6 }, 369 { WM8996_WRITE_SEQUENCER_136, 0x1 }, 370 { WM8996_WRITE_SEQUENCER_137, 0x3 }, 371 { WM8996_WRITE_SEQUENCER_138, 0x106 }, 372 { WM8996_WRITE_SEQUENCER_140, 0x61 }, 373 { WM8996_WRITE_SEQUENCER_141, 0x11 }, 374 { WM8996_WRITE_SEQUENCER_142, 0x401 }, 375 { WM8996_WRITE_SEQUENCER_144, 0x50 }, 376 { WM8996_WRITE_SEQUENCER_145, 0x3 }, 377 { WM8996_WRITE_SEQUENCER_146, 0x102 }, 378 { WM8996_WRITE_SEQUENCER_148, 0x51 }, 379 { WM8996_WRITE_SEQUENCER_149, 0x3 }, 380 { WM8996_WRITE_SEQUENCER_150, 0x106 }, 381 { WM8996_WRITE_SEQUENCER_151, 0xa }, 382 { WM8996_WRITE_SEQUENCER_152, 0x61 }, 383 { WM8996_WRITE_SEQUENCER_153, 0x3b }, 384 { WM8996_WRITE_SEQUENCER_154, 0x502 }, 385 { WM8996_WRITE_SEQUENCER_155, 0x100 }, 386 { WM8996_WRITE_SEQUENCER_156, 0x2fff }, 387 { WM8996_WRITE_SEQUENCER_160, 0x2fff }, 388 { WM8996_WRITE_SEQUENCER_164, 0x2fff }, 389 { WM8996_WRITE_SEQUENCER_168, 0x2fff }, 390 { WM8996_WRITE_SEQUENCER_172, 0x2fff }, 391 { WM8996_WRITE_SEQUENCER_176, 0x2fff }, 392 { WM8996_WRITE_SEQUENCER_180, 0x2fff }, 393 { WM8996_WRITE_SEQUENCER_184, 0x2fff }, 394 { WM8996_WRITE_SEQUENCER_188, 0x2fff }, 395 { WM8996_WRITE_SEQUENCER_192, 0x1 }, 396 { WM8996_WRITE_SEQUENCER_193, 0x1 }, 397 { WM8996_WRITE_SEQUENCER_195, 0x6 }, 398 { WM8996_WRITE_SEQUENCER_196, 0x40 }, 399 { WM8996_WRITE_SEQUENCER_197, 0x1 }, 400 { WM8996_WRITE_SEQUENCER_198, 0xf }, 401 { WM8996_WRITE_SEQUENCER_199, 0x6 }, 402 { WM8996_WRITE_SEQUENCER_200, 0x1 }, 403 { WM8996_WRITE_SEQUENCER_201, 0x3 }, 404 { WM8996_WRITE_SEQUENCER_202, 0x106 }, 405 { WM8996_WRITE_SEQUENCER_204, 0x61 }, 406 { WM8996_WRITE_SEQUENCER_205, 0x11 }, 407 { WM8996_WRITE_SEQUENCER_206, 0x401 }, 408 { WM8996_WRITE_SEQUENCER_208, 0x50 }, 409 { WM8996_WRITE_SEQUENCER_209, 0x3 }, 410 { WM8996_WRITE_SEQUENCER_210, 0x102 }, 411 { WM8996_WRITE_SEQUENCER_212, 0x61 }, 412 { WM8996_WRITE_SEQUENCER_213, 0x3b }, 413 { WM8996_WRITE_SEQUENCER_214, 0x502 }, 414 { WM8996_WRITE_SEQUENCER_215, 0x100 }, 415 { WM8996_WRITE_SEQUENCER_216, 0x2fff }, 416 { WM8996_WRITE_SEQUENCER_220, 0x2fff }, 417 { WM8996_WRITE_SEQUENCER_224, 0x2fff }, 418 { WM8996_WRITE_SEQUENCER_228, 0x2fff }, 419 { WM8996_WRITE_SEQUENCER_232, 0x2fff }, 420 { WM8996_WRITE_SEQUENCER_236, 0x2fff }, 421 { WM8996_WRITE_SEQUENCER_240, 0x2fff }, 422 { WM8996_WRITE_SEQUENCER_244, 0x2fff }, 423 { WM8996_WRITE_SEQUENCER_248, 0x2fff }, 424 { WM8996_WRITE_SEQUENCER_252, 0x2fff }, 425 { WM8996_WRITE_SEQUENCER_256, 0x60 }, 426 { WM8996_WRITE_SEQUENCER_258, 0x601 }, 427 { WM8996_WRITE_SEQUENCER_260, 0x50 }, 428 { WM8996_WRITE_SEQUENCER_262, 0x100 }, 429 { WM8996_WRITE_SEQUENCER_264, 0x1 }, 430 { WM8996_WRITE_SEQUENCER_266, 0x104 }, 431 { WM8996_WRITE_SEQUENCER_267, 0x100 }, 432 { WM8996_WRITE_SEQUENCER_268, 0x2fff }, 433 { WM8996_WRITE_SEQUENCER_272, 0x2fff }, 434 { WM8996_WRITE_SEQUENCER_276, 0x2fff }, 435 { WM8996_WRITE_SEQUENCER_280, 0x2fff }, 436 { WM8996_WRITE_SEQUENCER_284, 0x2fff }, 437 { WM8996_WRITE_SEQUENCER_288, 0x2fff }, 438 { WM8996_WRITE_SEQUENCER_292, 0x2fff }, 439 { WM8996_WRITE_SEQUENCER_296, 0x2fff }, 440 { WM8996_WRITE_SEQUENCER_300, 0x2fff }, 441 { WM8996_WRITE_SEQUENCER_304, 0x2fff }, 442 { WM8996_WRITE_SEQUENCER_308, 0x2fff }, 443 { WM8996_WRITE_SEQUENCER_312, 0x2fff }, 444 { WM8996_WRITE_SEQUENCER_316, 0x2fff }, 445 { WM8996_WRITE_SEQUENCER_320, 0x61 }, 446 { WM8996_WRITE_SEQUENCER_322, 0x601 }, 447 { WM8996_WRITE_SEQUENCER_324, 0x50 }, 448 { WM8996_WRITE_SEQUENCER_326, 0x102 }, 449 { WM8996_WRITE_SEQUENCER_328, 0x1 }, 450 { WM8996_WRITE_SEQUENCER_330, 0x106 }, 451 { WM8996_WRITE_SEQUENCER_331, 0x100 }, 452 { WM8996_WRITE_SEQUENCER_332, 0x2fff }, 453 { WM8996_WRITE_SEQUENCER_336, 0x2fff }, 454 { WM8996_WRITE_SEQUENCER_340, 0x2fff }, 455 { WM8996_WRITE_SEQUENCER_344, 0x2fff }, 456 { WM8996_WRITE_SEQUENCER_348, 0x2fff }, 457 { WM8996_WRITE_SEQUENCER_352, 0x2fff }, 458 { WM8996_WRITE_SEQUENCER_356, 0x2fff }, 459 { WM8996_WRITE_SEQUENCER_360, 0x2fff }, 460 { WM8996_WRITE_SEQUENCER_364, 0x2fff }, 461 { WM8996_WRITE_SEQUENCER_368, 0x2fff }, 462 { WM8996_WRITE_SEQUENCER_372, 0x2fff }, 463 { WM8996_WRITE_SEQUENCER_376, 0x2fff }, 464 { WM8996_WRITE_SEQUENCER_380, 0x2fff }, 465 { WM8996_WRITE_SEQUENCER_384, 0x60 }, 466 { WM8996_WRITE_SEQUENCER_386, 0x601 }, 467 { WM8996_WRITE_SEQUENCER_388, 0x61 }, 468 { WM8996_WRITE_SEQUENCER_390, 0x601 }, 469 { WM8996_WRITE_SEQUENCER_392, 0x50 }, 470 { WM8996_WRITE_SEQUENCER_394, 0x300 }, 471 { WM8996_WRITE_SEQUENCER_396, 0x1 }, 472 { WM8996_WRITE_SEQUENCER_398, 0x304 }, 473 { WM8996_WRITE_SEQUENCER_400, 0x40 }, 474 { WM8996_WRITE_SEQUENCER_402, 0xf }, 475 { WM8996_WRITE_SEQUENCER_404, 0x1 }, 476 { WM8996_WRITE_SEQUENCER_407, 0x100 }, 477 }; 478 479 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); 480 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 481 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 482 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); 483 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); 484 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); 485 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 486 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1); 487 488 static const char *sidetone_hpf_text[] = { 489 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" 490 }; 491 492 static const struct soc_enum sidetone_hpf = 493 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text); 494 495 static const char *hpf_mode_text[] = { 496 "HiFi", "Custom", "Voice" 497 }; 498 499 static const struct soc_enum dsp1tx_hpf_mode = 500 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text); 501 502 static const struct soc_enum dsp2tx_hpf_mode = 503 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text); 504 505 static const char *hpf_cutoff_text[] = { 506 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" 507 }; 508 509 static const struct soc_enum dsp1tx_hpf_cutoff = 510 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text); 511 512 static const struct soc_enum dsp2tx_hpf_cutoff = 513 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text); 514 515 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block) 516 { 517 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 518 struct wm8996_pdata *pdata = &wm8996->pdata; 519 int base, best, best_val, save, i, cfg, iface; 520 521 if (!wm8996->num_retune_mobile_texts) 522 return; 523 524 switch (block) { 525 case 0: 526 base = WM8996_DSP1_RX_EQ_GAINS_1; 527 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 528 WM8996_DSP1RX_SRC) 529 iface = 1; 530 else 531 iface = 0; 532 break; 533 case 1: 534 base = WM8996_DSP1_RX_EQ_GAINS_2; 535 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 536 WM8996_DSP2RX_SRC) 537 iface = 1; 538 else 539 iface = 0; 540 break; 541 default: 542 return; 543 } 544 545 /* Find the version of the currently selected configuration 546 * with the nearest sample rate. */ 547 cfg = wm8996->retune_mobile_cfg[block]; 548 best = 0; 549 best_val = INT_MAX; 550 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 551 if (strcmp(pdata->retune_mobile_cfgs[i].name, 552 wm8996->retune_mobile_texts[cfg]) == 0 && 553 abs(pdata->retune_mobile_cfgs[i].rate 554 - wm8996->rx_rate[iface]) < best_val) { 555 best = i; 556 best_val = abs(pdata->retune_mobile_cfgs[i].rate 557 - wm8996->rx_rate[iface]); 558 } 559 } 560 561 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 562 block, 563 pdata->retune_mobile_cfgs[best].name, 564 pdata->retune_mobile_cfgs[best].rate, 565 wm8996->rx_rate[iface]); 566 567 /* The EQ will be disabled while reconfiguring it, remember the 568 * current configuration. 569 */ 570 save = snd_soc_read(codec, base); 571 save &= WM8996_DSP1RX_EQ_ENA; 572 573 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) 574 snd_soc_update_bits(codec, base + i, 0xffff, 575 pdata->retune_mobile_cfgs[best].regs[i]); 576 577 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save); 578 } 579 580 /* Icky as hell but saves code duplication */ 581 static int wm8996_get_retune_mobile_block(const char *name) 582 { 583 if (strcmp(name, "DSP1 EQ Mode") == 0) 584 return 0; 585 if (strcmp(name, "DSP2 EQ Mode") == 0) 586 return 1; 587 return -EINVAL; 588 } 589 590 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 591 struct snd_ctl_elem_value *ucontrol) 592 { 593 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 594 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 595 struct wm8996_pdata *pdata = &wm8996->pdata; 596 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 597 int value = ucontrol->value.integer.value[0]; 598 599 if (block < 0) 600 return block; 601 602 if (value >= pdata->num_retune_mobile_cfgs) 603 return -EINVAL; 604 605 wm8996->retune_mobile_cfg[block] = value; 606 607 wm8996_set_retune_mobile(codec, block); 608 609 return 0; 610 } 611 612 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 613 struct snd_ctl_elem_value *ucontrol) 614 { 615 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 616 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 617 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 618 619 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block]; 620 621 return 0; 622 } 623 624 static const struct snd_kcontrol_new wm8996_snd_controls[] = { 625 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME, 626 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), 627 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME, 628 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), 629 630 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES, 631 0, 5, 24, 0, sidetone_tlv), 632 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES, 633 0, 5, 24, 0, sidetone_tlv), 634 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0), 635 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), 636 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0), 637 638 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME, 639 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 640 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME, 641 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 642 643 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS, 644 13, 1, 0), 645 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0), 646 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), 647 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), 648 649 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS, 650 13, 1, 0), 651 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0), 652 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), 653 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), 654 655 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME, 656 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 657 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1), 658 659 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME, 660 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 661 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1), 662 663 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME, 664 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 665 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME, 666 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1), 667 668 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME, 669 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 670 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME, 671 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1), 672 673 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0), 674 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0), 675 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0), 676 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0), 677 678 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0), 679 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0), 680 681 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0), 682 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0), 683 684 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15, 685 0, threedstereo_tlv), 686 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15, 687 0, threedstereo_tlv), 688 689 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4, 690 8, 0, out_digital_tlv), 691 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4, 692 8, 0, out_digital_tlv), 693 694 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME, 695 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), 696 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME, 697 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), 698 699 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME, 700 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), 701 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME, 702 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), 703 704 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, 705 spk_tlv), 706 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER, 707 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1), 708 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER, 709 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0), 710 711 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0), 712 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0), 713 714 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0), 715 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0), 716 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0), 717 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5, 718 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA | 719 WM8996_DSP1TXR_DRC_ENA), 720 721 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0), 722 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0), 723 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0), 724 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5, 725 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA | 726 WM8996_DSP2TXR_DRC_ENA), 727 }; 728 729 static const struct snd_kcontrol_new wm8996_eq_controls[] = { 730 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0, 731 eq_tlv), 732 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0, 733 eq_tlv), 734 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0, 735 eq_tlv), 736 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0, 737 eq_tlv), 738 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0, 739 eq_tlv), 740 741 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0, 742 eq_tlv), 743 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0, 744 eq_tlv), 745 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0, 746 eq_tlv), 747 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0, 748 eq_tlv), 749 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0, 750 eq_tlv), 751 }; 752 753 static void wm8996_bg_enable(struct snd_soc_codec *codec) 754 { 755 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 756 757 wm8996->bg_ena++; 758 if (wm8996->bg_ena == 1) { 759 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 760 WM8996_BG_ENA, WM8996_BG_ENA); 761 msleep(2); 762 } 763 } 764 765 static void wm8996_bg_disable(struct snd_soc_codec *codec) 766 { 767 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 768 769 wm8996->bg_ena--; 770 if (!wm8996->bg_ena) 771 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 772 WM8996_BG_ENA, 0); 773 } 774 775 static int bg_event(struct snd_soc_dapm_widget *w, 776 struct snd_kcontrol *kcontrol, int event) 777 { 778 struct snd_soc_codec *codec = w->codec; 779 int ret = 0; 780 781 switch (event) { 782 case SND_SOC_DAPM_PRE_PMU: 783 wm8996_bg_enable(codec); 784 break; 785 case SND_SOC_DAPM_POST_PMD: 786 wm8996_bg_disable(codec); 787 break; 788 default: 789 BUG(); 790 ret = -EINVAL; 791 } 792 793 return ret; 794 } 795 796 static int cp_event(struct snd_soc_dapm_widget *w, 797 struct snd_kcontrol *kcontrol, int event) 798 { 799 int ret = 0; 800 801 switch (event) { 802 case SND_SOC_DAPM_POST_PMU: 803 msleep(5); 804 break; 805 default: 806 BUG(); 807 ret = -EINVAL; 808 } 809 810 return 0; 811 } 812 813 static int rmv_short_event(struct snd_soc_dapm_widget *w, 814 struct snd_kcontrol *kcontrol, int event) 815 { 816 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 817 818 /* Record which outputs we enabled */ 819 switch (event) { 820 case SND_SOC_DAPM_PRE_PMD: 821 wm8996->hpout_pending &= ~w->shift; 822 break; 823 case SND_SOC_DAPM_PRE_PMU: 824 wm8996->hpout_pending |= w->shift; 825 break; 826 default: 827 BUG(); 828 return -EINVAL; 829 } 830 831 return 0; 832 } 833 834 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) 835 { 836 struct i2c_client *i2c = to_i2c_client(codec->dev); 837 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 838 int ret; 839 unsigned long timeout = 200; 840 841 snd_soc_write(codec, WM8996_DC_SERVO_2, mask); 842 843 /* Use the interrupt if possible */ 844 do { 845 if (i2c->irq) { 846 timeout = wait_for_completion_timeout(&wm8996->dcs_done, 847 msecs_to_jiffies(200)); 848 if (timeout == 0) 849 dev_err(codec->dev, "DC servo timed out\n"); 850 851 } else { 852 msleep(1); 853 timeout--; 854 } 855 856 ret = snd_soc_read(codec, WM8996_DC_SERVO_2); 857 dev_dbg(codec->dev, "DC servo state: %x\n", ret); 858 } while (timeout && ret & mask); 859 860 if (timeout == 0) 861 dev_err(codec->dev, "DC servo timed out for %x\n", mask); 862 else 863 dev_dbg(codec->dev, "DC servo complete for %x\n", mask); 864 } 865 866 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm, 867 enum snd_soc_dapm_type event, int subseq) 868 { 869 struct snd_soc_codec *codec = container_of(dapm, 870 struct snd_soc_codec, dapm); 871 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 872 u16 val, mask; 873 874 /* Complete any pending DC servo starts */ 875 if (wm8996->dcs_pending) { 876 dev_dbg(codec->dev, "Starting DC servo for %x\n", 877 wm8996->dcs_pending); 878 879 /* Trigger a startup sequence */ 880 wait_for_dc_servo(codec, wm8996->dcs_pending 881 << WM8996_DCS_TRIG_STARTUP_0_SHIFT); 882 883 wm8996->dcs_pending = 0; 884 } 885 886 if (wm8996->hpout_pending != wm8996->hpout_ena) { 887 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", 888 wm8996->hpout_ena, wm8996->hpout_pending); 889 890 val = 0; 891 mask = 0; 892 if (wm8996->hpout_pending & HPOUT1L) { 893 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 894 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 895 } else { 896 mask |= WM8996_HPOUT1L_RMV_SHORT | 897 WM8996_HPOUT1L_OUTP | 898 WM8996_HPOUT1L_DLY; 899 } 900 901 if (wm8996->hpout_pending & HPOUT1R) { 902 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 903 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 904 } else { 905 mask |= WM8996_HPOUT1R_RMV_SHORT | 906 WM8996_HPOUT1R_OUTP | 907 WM8996_HPOUT1R_DLY; 908 } 909 910 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val); 911 912 val = 0; 913 mask = 0; 914 if (wm8996->hpout_pending & HPOUT2L) { 915 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 916 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 917 } else { 918 mask |= WM8996_HPOUT2L_RMV_SHORT | 919 WM8996_HPOUT2L_OUTP | 920 WM8996_HPOUT2L_DLY; 921 } 922 923 if (wm8996->hpout_pending & HPOUT2R) { 924 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 925 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 926 } else { 927 mask |= WM8996_HPOUT2R_RMV_SHORT | 928 WM8996_HPOUT2R_OUTP | 929 WM8996_HPOUT2R_DLY; 930 } 931 932 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val); 933 934 wm8996->hpout_ena = wm8996->hpout_pending; 935 } 936 } 937 938 static int dcs_start(struct snd_soc_dapm_widget *w, 939 struct snd_kcontrol *kcontrol, int event) 940 { 941 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 942 943 switch (event) { 944 case SND_SOC_DAPM_POST_PMU: 945 wm8996->dcs_pending |= 1 << w->shift; 946 break; 947 default: 948 BUG(); 949 return -EINVAL; 950 } 951 952 return 0; 953 } 954 955 static const char *sidetone_text[] = { 956 "IN1", "IN2", 957 }; 958 959 static const struct soc_enum left_sidetone_enum = 960 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text); 961 962 static const struct snd_kcontrol_new left_sidetone = 963 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); 964 965 static const struct soc_enum right_sidetone_enum = 966 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text); 967 968 static const struct snd_kcontrol_new right_sidetone = 969 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); 970 971 static const char *spk_text[] = { 972 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 973 }; 974 975 static const struct soc_enum spkl_enum = 976 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text); 977 978 static const struct snd_kcontrol_new spkl_mux = 979 SOC_DAPM_ENUM("SPKL", spkl_enum); 980 981 static const struct soc_enum spkr_enum = 982 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text); 983 984 static const struct snd_kcontrol_new spkr_mux = 985 SOC_DAPM_ENUM("SPKR", spkr_enum); 986 987 static const char *dsp1rx_text[] = { 988 "AIF1", "AIF2" 989 }; 990 991 static const struct soc_enum dsp1rx_enum = 992 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text); 993 994 static const struct snd_kcontrol_new dsp1rx = 995 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); 996 997 static const char *dsp2rx_text[] = { 998 "AIF2", "AIF1" 999 }; 1000 1001 static const struct soc_enum dsp2rx_enum = 1002 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text); 1003 1004 static const struct snd_kcontrol_new dsp2rx = 1005 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); 1006 1007 static const char *aif2tx_text[] = { 1008 "DSP2", "DSP1", "AIF1" 1009 }; 1010 1011 static const struct soc_enum aif2tx_enum = 1012 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text); 1013 1014 static const struct snd_kcontrol_new aif2tx = 1015 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); 1016 1017 static const char *inmux_text[] = { 1018 "ADC", "DMIC1", "DMIC2" 1019 }; 1020 1021 static const struct soc_enum in1_enum = 1022 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text); 1023 1024 static const struct snd_kcontrol_new in1_mux = 1025 SOC_DAPM_ENUM("IN1 Mux", in1_enum); 1026 1027 static const struct soc_enum in2_enum = 1028 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text); 1029 1030 static const struct snd_kcontrol_new in2_mux = 1031 SOC_DAPM_ENUM("IN2 Mux", in2_enum); 1032 1033 static const struct snd_kcontrol_new dac2r_mix[] = { 1034 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1035 5, 1, 0), 1036 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1037 4, 1, 0), 1038 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), 1039 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), 1040 }; 1041 1042 static const struct snd_kcontrol_new dac2l_mix[] = { 1043 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1044 5, 1, 0), 1045 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1046 4, 1, 0), 1047 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), 1048 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), 1049 }; 1050 1051 static const struct snd_kcontrol_new dac1r_mix[] = { 1052 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1053 5, 1, 0), 1054 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1055 4, 1, 0), 1056 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), 1057 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), 1058 }; 1059 1060 static const struct snd_kcontrol_new dac1l_mix[] = { 1061 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1062 5, 1, 0), 1063 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1064 4, 1, 0), 1065 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), 1066 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), 1067 }; 1068 1069 static const struct snd_kcontrol_new dsp1txl[] = { 1070 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 1071 1, 1, 0), 1072 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 1073 0, 1, 0), 1074 }; 1075 1076 static const struct snd_kcontrol_new dsp1txr[] = { 1077 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 1078 1, 1, 0), 1079 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 1080 0, 1, 0), 1081 }; 1082 1083 static const struct snd_kcontrol_new dsp2txl[] = { 1084 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 1085 1, 1, 0), 1086 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 1087 0, 1, 0), 1088 }; 1089 1090 static const struct snd_kcontrol_new dsp2txr[] = { 1091 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 1092 1, 1, 0), 1093 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 1094 0, 1, 0), 1095 }; 1096 1097 1098 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = { 1099 SND_SOC_DAPM_INPUT("IN1LN"), 1100 SND_SOC_DAPM_INPUT("IN1LP"), 1101 SND_SOC_DAPM_INPUT("IN1RN"), 1102 SND_SOC_DAPM_INPUT("IN1RP"), 1103 1104 SND_SOC_DAPM_INPUT("IN2LN"), 1105 SND_SOC_DAPM_INPUT("IN2LP"), 1106 SND_SOC_DAPM_INPUT("IN2RN"), 1107 SND_SOC_DAPM_INPUT("IN2RP"), 1108 1109 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1110 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1111 1112 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20), 1113 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0), 1114 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0), 1115 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0), 1116 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event, 1117 SND_SOC_DAPM_POST_PMU), 1118 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event, 1119 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1120 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 1121 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0), 1122 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0), 1123 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0), 1124 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0), 1125 1126 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0), 1127 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0), 1128 1129 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux), 1130 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux), 1131 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux), 1132 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux), 1133 1134 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0), 1135 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0), 1136 1137 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0), 1138 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0), 1139 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0), 1140 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0), 1141 1142 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0), 1143 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0), 1144 1145 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), 1146 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), 1147 1148 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0), 1149 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0), 1150 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0), 1151 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0), 1152 1153 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0, 1154 dsp2txl, ARRAY_SIZE(dsp2txl)), 1155 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0, 1156 dsp2txr, ARRAY_SIZE(dsp2txr)), 1157 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0, 1158 dsp1txl, ARRAY_SIZE(dsp1txl)), 1159 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0, 1160 dsp1txr, ARRAY_SIZE(dsp1txr)), 1161 1162 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1163 dac2l_mix, ARRAY_SIZE(dac2l_mix)), 1164 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1165 dac2r_mix, ARRAY_SIZE(dac2r_mix)), 1166 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1167 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1168 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1169 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1170 1171 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0), 1172 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0), 1173 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0), 1174 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0), 1175 1176 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0), 1177 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0), 1178 1179 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0), 1180 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0), 1181 1182 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0), 1183 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0), 1184 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0), 1185 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0), 1186 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0), 1187 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0), 1188 1189 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0), 1190 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0), 1191 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0), 1192 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0), 1193 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0), 1194 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0), 1195 1196 /* We route as stereo pairs so define some dummy widgets to squash 1197 * things down for now. RXA = 0,1, RXB = 2,3 and so on */ 1198 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), 1199 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), 1200 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), 1201 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), 1202 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), 1203 1204 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), 1205 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), 1206 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), 1207 1208 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), 1209 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), 1210 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), 1211 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), 1212 1213 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0), 1214 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0), 1215 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start, 1216 SND_SOC_DAPM_POST_PMU), 1217 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, 1218 rmv_short_event, 1219 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1220 1221 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0), 1222 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0), 1223 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start, 1224 SND_SOC_DAPM_POST_PMU), 1225 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, 1226 rmv_short_event, 1227 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1228 1229 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0), 1230 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0), 1231 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start, 1232 SND_SOC_DAPM_POST_PMU), 1233 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, 1234 rmv_short_event, 1235 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1236 1237 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0), 1238 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0), 1239 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start, 1240 SND_SOC_DAPM_POST_PMU), 1241 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, 1242 rmv_short_event, 1243 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1244 1245 SND_SOC_DAPM_OUTPUT("HPOUT1L"), 1246 SND_SOC_DAPM_OUTPUT("HPOUT1R"), 1247 SND_SOC_DAPM_OUTPUT("HPOUT2L"), 1248 SND_SOC_DAPM_OUTPUT("HPOUT2R"), 1249 SND_SOC_DAPM_OUTPUT("SPKDAT"), 1250 }; 1251 1252 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = { 1253 { "AIFCLK", NULL, "SYSCLK" }, 1254 { "SYSDSPCLK", NULL, "SYSCLK" }, 1255 { "Charge Pump", NULL, "SYSCLK" }, 1256 { "Charge Pump", NULL, "CPVDD" }, 1257 1258 { "MICB1", NULL, "LDO2" }, 1259 { "MICB1", NULL, "MICB1 Audio" }, 1260 { "MICB1", NULL, "Bandgap" }, 1261 { "MICB2", NULL, "LDO2" }, 1262 { "MICB2", NULL, "MICB2 Audio" }, 1263 { "MICB2", NULL, "Bandgap" }, 1264 1265 { "AIF1RX0", NULL, "AIF1 Playback" }, 1266 { "AIF1RX1", NULL, "AIF1 Playback" }, 1267 { "AIF1RX2", NULL, "AIF1 Playback" }, 1268 { "AIF1RX3", NULL, "AIF1 Playback" }, 1269 { "AIF1RX4", NULL, "AIF1 Playback" }, 1270 { "AIF1RX5", NULL, "AIF1 Playback" }, 1271 1272 { "AIF2RX0", NULL, "AIF2 Playback" }, 1273 { "AIF2RX1", NULL, "AIF2 Playback" }, 1274 1275 { "AIF1 Capture", NULL, "AIF1TX0" }, 1276 { "AIF1 Capture", NULL, "AIF1TX1" }, 1277 { "AIF1 Capture", NULL, "AIF1TX2" }, 1278 { "AIF1 Capture", NULL, "AIF1TX3" }, 1279 { "AIF1 Capture", NULL, "AIF1TX4" }, 1280 { "AIF1 Capture", NULL, "AIF1TX5" }, 1281 1282 { "AIF2 Capture", NULL, "AIF2TX0" }, 1283 { "AIF2 Capture", NULL, "AIF2TX1" }, 1284 1285 { "IN1L PGA", NULL, "IN2LN" }, 1286 { "IN1L PGA", NULL, "IN2LP" }, 1287 { "IN1L PGA", NULL, "IN1LN" }, 1288 { "IN1L PGA", NULL, "IN1LP" }, 1289 { "IN1L PGA", NULL, "Bandgap" }, 1290 1291 { "IN1R PGA", NULL, "IN2RN" }, 1292 { "IN1R PGA", NULL, "IN2RP" }, 1293 { "IN1R PGA", NULL, "IN1RN" }, 1294 { "IN1R PGA", NULL, "IN1RP" }, 1295 { "IN1R PGA", NULL, "Bandgap" }, 1296 1297 { "ADCL", NULL, "IN1L PGA" }, 1298 1299 { "ADCR", NULL, "IN1R PGA" }, 1300 1301 { "DMIC1L", NULL, "DMIC1DAT" }, 1302 { "DMIC1R", NULL, "DMIC1DAT" }, 1303 { "DMIC2L", NULL, "DMIC2DAT" }, 1304 { "DMIC2R", NULL, "DMIC2DAT" }, 1305 1306 { "DMIC2L", NULL, "DMIC2" }, 1307 { "DMIC2R", NULL, "DMIC2" }, 1308 { "DMIC1L", NULL, "DMIC1" }, 1309 { "DMIC1R", NULL, "DMIC1" }, 1310 1311 { "IN1L Mux", "ADC", "ADCL" }, 1312 { "IN1L Mux", "DMIC1", "DMIC1L" }, 1313 { "IN1L Mux", "DMIC2", "DMIC2L" }, 1314 1315 { "IN1R Mux", "ADC", "ADCR" }, 1316 { "IN1R Mux", "DMIC1", "DMIC1R" }, 1317 { "IN1R Mux", "DMIC2", "DMIC2R" }, 1318 1319 { "IN2L Mux", "ADC", "ADCL" }, 1320 { "IN2L Mux", "DMIC1", "DMIC1L" }, 1321 { "IN2L Mux", "DMIC2", "DMIC2L" }, 1322 1323 { "IN2R Mux", "ADC", "ADCR" }, 1324 { "IN2R Mux", "DMIC1", "DMIC1R" }, 1325 { "IN2R Mux", "DMIC2", "DMIC2R" }, 1326 1327 { "Left Sidetone", "IN1", "IN1L Mux" }, 1328 { "Left Sidetone", "IN2", "IN2L Mux" }, 1329 1330 { "Right Sidetone", "IN1", "IN1R Mux" }, 1331 { "Right Sidetone", "IN2", "IN2R Mux" }, 1332 1333 { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, 1334 { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, 1335 1336 { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, 1337 { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, 1338 1339 { "AIF1TX0", NULL, "DSP1TXL" }, 1340 { "AIF1TX1", NULL, "DSP1TXR" }, 1341 { "AIF1TX2", NULL, "DSP2TXL" }, 1342 { "AIF1TX3", NULL, "DSP2TXR" }, 1343 { "AIF1TX4", NULL, "AIF2RX0" }, 1344 { "AIF1TX5", NULL, "AIF2RX1" }, 1345 1346 { "AIF1RX0", NULL, "AIFCLK" }, 1347 { "AIF1RX1", NULL, "AIFCLK" }, 1348 { "AIF1RX2", NULL, "AIFCLK" }, 1349 { "AIF1RX3", NULL, "AIFCLK" }, 1350 { "AIF1RX4", NULL, "AIFCLK" }, 1351 { "AIF1RX5", NULL, "AIFCLK" }, 1352 1353 { "AIF2RX0", NULL, "AIFCLK" }, 1354 { "AIF2RX1", NULL, "AIFCLK" }, 1355 1356 { "AIF1TX0", NULL, "AIFCLK" }, 1357 { "AIF1TX1", NULL, "AIFCLK" }, 1358 { "AIF1TX2", NULL, "AIFCLK" }, 1359 { "AIF1TX3", NULL, "AIFCLK" }, 1360 { "AIF1TX4", NULL, "AIFCLK" }, 1361 { "AIF1TX5", NULL, "AIFCLK" }, 1362 1363 { "AIF2TX0", NULL, "AIFCLK" }, 1364 { "AIF2TX1", NULL, "AIFCLK" }, 1365 1366 { "DSP1RXL", NULL, "SYSDSPCLK" }, 1367 { "DSP1RXR", NULL, "SYSDSPCLK" }, 1368 { "DSP2RXL", NULL, "SYSDSPCLK" }, 1369 { "DSP2RXR", NULL, "SYSDSPCLK" }, 1370 { "DSP1TXL", NULL, "SYSDSPCLK" }, 1371 { "DSP1TXR", NULL, "SYSDSPCLK" }, 1372 { "DSP2TXL", NULL, "SYSDSPCLK" }, 1373 { "DSP2TXR", NULL, "SYSDSPCLK" }, 1374 1375 { "AIF1RXA", NULL, "AIF1RX0" }, 1376 { "AIF1RXA", NULL, "AIF1RX1" }, 1377 { "AIF1RXB", NULL, "AIF1RX2" }, 1378 { "AIF1RXB", NULL, "AIF1RX3" }, 1379 { "AIF1RXC", NULL, "AIF1RX4" }, 1380 { "AIF1RXC", NULL, "AIF1RX5" }, 1381 1382 { "AIF2RX", NULL, "AIF2RX0" }, 1383 { "AIF2RX", NULL, "AIF2RX1" }, 1384 1385 { "AIF2TX", "DSP2", "DSP2TX" }, 1386 { "AIF2TX", "DSP1", "DSP1RX" }, 1387 { "AIF2TX", "AIF1", "AIF1RXC" }, 1388 1389 { "DSP1RXL", NULL, "DSP1RX" }, 1390 { "DSP1RXR", NULL, "DSP1RX" }, 1391 { "DSP2RXL", NULL, "DSP2RX" }, 1392 { "DSP2RXR", NULL, "DSP2RX" }, 1393 1394 { "DSP2TX", NULL, "DSP2TXL" }, 1395 { "DSP2TX", NULL, "DSP2TXR" }, 1396 1397 { "DSP1RX", "AIF1", "AIF1RXA" }, 1398 { "DSP1RX", "AIF2", "AIF2RX" }, 1399 1400 { "DSP2RX", "AIF1", "AIF1RXB" }, 1401 { "DSP2RX", "AIF2", "AIF2RX" }, 1402 1403 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, 1404 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, 1405 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1406 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1407 1408 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, 1409 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, 1410 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1411 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1412 1413 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, 1414 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, 1415 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1416 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1417 1418 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, 1419 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, 1420 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1421 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1422 1423 { "DAC1L", NULL, "DAC1L Mixer" }, 1424 { "DAC1R", NULL, "DAC1R Mixer" }, 1425 { "DAC2L", NULL, "DAC2L Mixer" }, 1426 { "DAC2R", NULL, "DAC2R Mixer" }, 1427 1428 { "HPOUT2L PGA", NULL, "Charge Pump" }, 1429 { "HPOUT2L PGA", NULL, "Bandgap" }, 1430 { "HPOUT2L PGA", NULL, "DAC2L" }, 1431 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, 1432 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, 1433 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" }, 1434 1435 { "HPOUT2R PGA", NULL, "Charge Pump" }, 1436 { "HPOUT2R PGA", NULL, "Bandgap" }, 1437 { "HPOUT2R PGA", NULL, "DAC2R" }, 1438 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, 1439 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, 1440 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" }, 1441 1442 { "HPOUT1L PGA", NULL, "Charge Pump" }, 1443 { "HPOUT1L PGA", NULL, "Bandgap" }, 1444 { "HPOUT1L PGA", NULL, "DAC1L" }, 1445 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, 1446 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, 1447 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" }, 1448 1449 { "HPOUT1R PGA", NULL, "Charge Pump" }, 1450 { "HPOUT1R PGA", NULL, "Bandgap" }, 1451 { "HPOUT1R PGA", NULL, "DAC1R" }, 1452 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, 1453 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, 1454 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" }, 1455 1456 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, 1457 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, 1458 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, 1459 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, 1460 1461 { "SPKL", "DAC1L", "DAC1L" }, 1462 { "SPKL", "DAC1R", "DAC1R" }, 1463 { "SPKL", "DAC2L", "DAC2L" }, 1464 { "SPKL", "DAC2R", "DAC2R" }, 1465 1466 { "SPKR", "DAC1L", "DAC1L" }, 1467 { "SPKR", "DAC1R", "DAC1R" }, 1468 { "SPKR", "DAC2L", "DAC2L" }, 1469 { "SPKR", "DAC2R", "DAC2R" }, 1470 1471 { "SPKL PGA", NULL, "SPKL" }, 1472 { "SPKR PGA", NULL, "SPKR" }, 1473 1474 { "SPKDAT", NULL, "SPKL PGA" }, 1475 { "SPKDAT", NULL, "SPKR PGA" }, 1476 }; 1477 1478 static bool wm8996_readable_register(struct device *dev, unsigned int reg) 1479 { 1480 /* Due to the sparseness of the register map the compiler 1481 * output from an explicit switch statement ends up being much 1482 * more efficient than a table. 1483 */ 1484 switch (reg) { 1485 case WM8996_SOFTWARE_RESET: 1486 case WM8996_POWER_MANAGEMENT_1: 1487 case WM8996_POWER_MANAGEMENT_2: 1488 case WM8996_POWER_MANAGEMENT_3: 1489 case WM8996_POWER_MANAGEMENT_4: 1490 case WM8996_POWER_MANAGEMENT_5: 1491 case WM8996_POWER_MANAGEMENT_6: 1492 case WM8996_POWER_MANAGEMENT_7: 1493 case WM8996_POWER_MANAGEMENT_8: 1494 case WM8996_LEFT_LINE_INPUT_VOLUME: 1495 case WM8996_RIGHT_LINE_INPUT_VOLUME: 1496 case WM8996_LINE_INPUT_CONTROL: 1497 case WM8996_DAC1_HPOUT1_VOLUME: 1498 case WM8996_DAC2_HPOUT2_VOLUME: 1499 case WM8996_DAC1_LEFT_VOLUME: 1500 case WM8996_DAC1_RIGHT_VOLUME: 1501 case WM8996_DAC2_LEFT_VOLUME: 1502 case WM8996_DAC2_RIGHT_VOLUME: 1503 case WM8996_OUTPUT1_LEFT_VOLUME: 1504 case WM8996_OUTPUT1_RIGHT_VOLUME: 1505 case WM8996_OUTPUT2_LEFT_VOLUME: 1506 case WM8996_OUTPUT2_RIGHT_VOLUME: 1507 case WM8996_MICBIAS_1: 1508 case WM8996_MICBIAS_2: 1509 case WM8996_LDO_1: 1510 case WM8996_LDO_2: 1511 case WM8996_ACCESSORY_DETECT_MODE_1: 1512 case WM8996_ACCESSORY_DETECT_MODE_2: 1513 case WM8996_HEADPHONE_DETECT_1: 1514 case WM8996_HEADPHONE_DETECT_2: 1515 case WM8996_MIC_DETECT_1: 1516 case WM8996_MIC_DETECT_2: 1517 case WM8996_MIC_DETECT_3: 1518 case WM8996_CHARGE_PUMP_1: 1519 case WM8996_CHARGE_PUMP_2: 1520 case WM8996_DC_SERVO_1: 1521 case WM8996_DC_SERVO_2: 1522 case WM8996_DC_SERVO_3: 1523 case WM8996_DC_SERVO_5: 1524 case WM8996_DC_SERVO_6: 1525 case WM8996_DC_SERVO_7: 1526 case WM8996_DC_SERVO_READBACK_0: 1527 case WM8996_ANALOGUE_HP_1: 1528 case WM8996_ANALOGUE_HP_2: 1529 case WM8996_CHIP_REVISION: 1530 case WM8996_CONTROL_INTERFACE_1: 1531 case WM8996_WRITE_SEQUENCER_CTRL_1: 1532 case WM8996_WRITE_SEQUENCER_CTRL_2: 1533 case WM8996_AIF_CLOCKING_1: 1534 case WM8996_AIF_CLOCKING_2: 1535 case WM8996_CLOCKING_1: 1536 case WM8996_CLOCKING_2: 1537 case WM8996_AIF_RATE: 1538 case WM8996_FLL_CONTROL_1: 1539 case WM8996_FLL_CONTROL_2: 1540 case WM8996_FLL_CONTROL_3: 1541 case WM8996_FLL_CONTROL_4: 1542 case WM8996_FLL_CONTROL_5: 1543 case WM8996_FLL_CONTROL_6: 1544 case WM8996_FLL_EFS_1: 1545 case WM8996_FLL_EFS_2: 1546 case WM8996_AIF1_CONTROL: 1547 case WM8996_AIF1_BCLK: 1548 case WM8996_AIF1_TX_LRCLK_1: 1549 case WM8996_AIF1_TX_LRCLK_2: 1550 case WM8996_AIF1_RX_LRCLK_1: 1551 case WM8996_AIF1_RX_LRCLK_2: 1552 case WM8996_AIF1TX_DATA_CONFIGURATION_1: 1553 case WM8996_AIF1TX_DATA_CONFIGURATION_2: 1554 case WM8996_AIF1RX_DATA_CONFIGURATION: 1555 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION: 1556 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION: 1557 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION: 1558 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION: 1559 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION: 1560 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION: 1561 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION: 1562 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION: 1563 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION: 1564 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION: 1565 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION: 1566 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION: 1567 case WM8996_AIF1RX_MONO_CONFIGURATION: 1568 case WM8996_AIF1TX_TEST: 1569 case WM8996_AIF2_CONTROL: 1570 case WM8996_AIF2_BCLK: 1571 case WM8996_AIF2_TX_LRCLK_1: 1572 case WM8996_AIF2_TX_LRCLK_2: 1573 case WM8996_AIF2_RX_LRCLK_1: 1574 case WM8996_AIF2_RX_LRCLK_2: 1575 case WM8996_AIF2TX_DATA_CONFIGURATION_1: 1576 case WM8996_AIF2TX_DATA_CONFIGURATION_2: 1577 case WM8996_AIF2RX_DATA_CONFIGURATION: 1578 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION: 1579 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION: 1580 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION: 1581 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION: 1582 case WM8996_AIF2RX_MONO_CONFIGURATION: 1583 case WM8996_AIF2TX_TEST: 1584 case WM8996_DSP1_TX_LEFT_VOLUME: 1585 case WM8996_DSP1_TX_RIGHT_VOLUME: 1586 case WM8996_DSP1_RX_LEFT_VOLUME: 1587 case WM8996_DSP1_RX_RIGHT_VOLUME: 1588 case WM8996_DSP1_TX_FILTERS: 1589 case WM8996_DSP1_RX_FILTERS_1: 1590 case WM8996_DSP1_RX_FILTERS_2: 1591 case WM8996_DSP1_DRC_1: 1592 case WM8996_DSP1_DRC_2: 1593 case WM8996_DSP1_DRC_3: 1594 case WM8996_DSP1_DRC_4: 1595 case WM8996_DSP1_DRC_5: 1596 case WM8996_DSP1_RX_EQ_GAINS_1: 1597 case WM8996_DSP1_RX_EQ_GAINS_2: 1598 case WM8996_DSP1_RX_EQ_BAND_1_A: 1599 case WM8996_DSP1_RX_EQ_BAND_1_B: 1600 case WM8996_DSP1_RX_EQ_BAND_1_PG: 1601 case WM8996_DSP1_RX_EQ_BAND_2_A: 1602 case WM8996_DSP1_RX_EQ_BAND_2_B: 1603 case WM8996_DSP1_RX_EQ_BAND_2_C: 1604 case WM8996_DSP1_RX_EQ_BAND_2_PG: 1605 case WM8996_DSP1_RX_EQ_BAND_3_A: 1606 case WM8996_DSP1_RX_EQ_BAND_3_B: 1607 case WM8996_DSP1_RX_EQ_BAND_3_C: 1608 case WM8996_DSP1_RX_EQ_BAND_3_PG: 1609 case WM8996_DSP1_RX_EQ_BAND_4_A: 1610 case WM8996_DSP1_RX_EQ_BAND_4_B: 1611 case WM8996_DSP1_RX_EQ_BAND_4_C: 1612 case WM8996_DSP1_RX_EQ_BAND_4_PG: 1613 case WM8996_DSP1_RX_EQ_BAND_5_A: 1614 case WM8996_DSP1_RX_EQ_BAND_5_B: 1615 case WM8996_DSP1_RX_EQ_BAND_5_PG: 1616 case WM8996_DSP2_TX_LEFT_VOLUME: 1617 case WM8996_DSP2_TX_RIGHT_VOLUME: 1618 case WM8996_DSP2_RX_LEFT_VOLUME: 1619 case WM8996_DSP2_RX_RIGHT_VOLUME: 1620 case WM8996_DSP2_TX_FILTERS: 1621 case WM8996_DSP2_RX_FILTERS_1: 1622 case WM8996_DSP2_RX_FILTERS_2: 1623 case WM8996_DSP2_DRC_1: 1624 case WM8996_DSP2_DRC_2: 1625 case WM8996_DSP2_DRC_3: 1626 case WM8996_DSP2_DRC_4: 1627 case WM8996_DSP2_DRC_5: 1628 case WM8996_DSP2_RX_EQ_GAINS_1: 1629 case WM8996_DSP2_RX_EQ_GAINS_2: 1630 case WM8996_DSP2_RX_EQ_BAND_1_A: 1631 case WM8996_DSP2_RX_EQ_BAND_1_B: 1632 case WM8996_DSP2_RX_EQ_BAND_1_PG: 1633 case WM8996_DSP2_RX_EQ_BAND_2_A: 1634 case WM8996_DSP2_RX_EQ_BAND_2_B: 1635 case WM8996_DSP2_RX_EQ_BAND_2_C: 1636 case WM8996_DSP2_RX_EQ_BAND_2_PG: 1637 case WM8996_DSP2_RX_EQ_BAND_3_A: 1638 case WM8996_DSP2_RX_EQ_BAND_3_B: 1639 case WM8996_DSP2_RX_EQ_BAND_3_C: 1640 case WM8996_DSP2_RX_EQ_BAND_3_PG: 1641 case WM8996_DSP2_RX_EQ_BAND_4_A: 1642 case WM8996_DSP2_RX_EQ_BAND_4_B: 1643 case WM8996_DSP2_RX_EQ_BAND_4_C: 1644 case WM8996_DSP2_RX_EQ_BAND_4_PG: 1645 case WM8996_DSP2_RX_EQ_BAND_5_A: 1646 case WM8996_DSP2_RX_EQ_BAND_5_B: 1647 case WM8996_DSP2_RX_EQ_BAND_5_PG: 1648 case WM8996_DAC1_MIXER_VOLUMES: 1649 case WM8996_DAC1_LEFT_MIXER_ROUTING: 1650 case WM8996_DAC1_RIGHT_MIXER_ROUTING: 1651 case WM8996_DAC2_MIXER_VOLUMES: 1652 case WM8996_DAC2_LEFT_MIXER_ROUTING: 1653 case WM8996_DAC2_RIGHT_MIXER_ROUTING: 1654 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING: 1655 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING: 1656 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING: 1657 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING: 1658 case WM8996_DSP_TX_MIXER_SELECT: 1659 case WM8996_DAC_SOFTMUTE: 1660 case WM8996_OVERSAMPLING: 1661 case WM8996_SIDETONE: 1662 case WM8996_GPIO_1: 1663 case WM8996_GPIO_2: 1664 case WM8996_GPIO_3: 1665 case WM8996_GPIO_4: 1666 case WM8996_GPIO_5: 1667 case WM8996_PULL_CONTROL_1: 1668 case WM8996_PULL_CONTROL_2: 1669 case WM8996_INTERRUPT_STATUS_1: 1670 case WM8996_INTERRUPT_STATUS_2: 1671 case WM8996_INTERRUPT_RAW_STATUS_2: 1672 case WM8996_INTERRUPT_STATUS_1_MASK: 1673 case WM8996_INTERRUPT_STATUS_2_MASK: 1674 case WM8996_INTERRUPT_CONTROL: 1675 case WM8996_LEFT_PDM_SPEAKER: 1676 case WM8996_RIGHT_PDM_SPEAKER: 1677 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE: 1678 case WM8996_PDM_SPEAKER_VOLUME: 1679 return 1; 1680 default: 1681 return 0; 1682 } 1683 } 1684 1685 static bool wm8996_volatile_register(struct device *dev, unsigned int reg) 1686 { 1687 switch (reg) { 1688 case WM8996_SOFTWARE_RESET: 1689 case WM8996_CHIP_REVISION: 1690 case WM8996_LDO_1: 1691 case WM8996_LDO_2: 1692 case WM8996_INTERRUPT_STATUS_1: 1693 case WM8996_INTERRUPT_STATUS_2: 1694 case WM8996_INTERRUPT_RAW_STATUS_2: 1695 case WM8996_DC_SERVO_READBACK_0: 1696 case WM8996_DC_SERVO_2: 1697 case WM8996_DC_SERVO_6: 1698 case WM8996_DC_SERVO_7: 1699 case WM8996_FLL_CONTROL_6: 1700 case WM8996_MIC_DETECT_3: 1701 case WM8996_HEADPHONE_DETECT_1: 1702 case WM8996_HEADPHONE_DETECT_2: 1703 return 1; 1704 default: 1705 return 0; 1706 } 1707 } 1708 1709 static int wm8996_reset(struct wm8996_priv *wm8996) 1710 { 1711 if (wm8996->pdata.ldo_ena > 0) { 1712 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 1713 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); 1714 return 0; 1715 } else { 1716 return regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET, 1717 0x8915); 1718 } 1719 } 1720 1721 static const int bclk_divs[] = { 1722 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 1723 }; 1724 1725 static void wm8996_update_bclk(struct snd_soc_codec *codec) 1726 { 1727 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1728 int aif, best, cur_val, bclk_rate, bclk_reg, i; 1729 1730 /* Don't bother if we're in a low frequency idle mode that 1731 * can't support audio. 1732 */ 1733 if (wm8996->sysclk < 64000) 1734 return; 1735 1736 for (aif = 0; aif < WM8996_AIFS; aif++) { 1737 switch (aif) { 1738 case 0: 1739 bclk_reg = WM8996_AIF1_BCLK; 1740 break; 1741 case 1: 1742 bclk_reg = WM8996_AIF2_BCLK; 1743 break; 1744 } 1745 1746 bclk_rate = wm8996->bclk_rate[aif]; 1747 1748 /* Pick a divisor for BCLK as close as we can get to ideal */ 1749 best = 0; 1750 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1751 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate; 1752 if (cur_val < 0) /* BCLK table is sorted */ 1753 break; 1754 best = i; 1755 } 1756 bclk_rate = wm8996->sysclk / bclk_divs[best]; 1757 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1758 bclk_divs[best], bclk_rate); 1759 1760 snd_soc_update_bits(codec, bclk_reg, 1761 WM8996_AIF1_BCLK_DIV_MASK, best); 1762 } 1763 } 1764 1765 static int wm8996_set_bias_level(struct snd_soc_codec *codec, 1766 enum snd_soc_bias_level level) 1767 { 1768 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1769 int ret; 1770 1771 switch (level) { 1772 case SND_SOC_BIAS_ON: 1773 break; 1774 case SND_SOC_BIAS_PREPARE: 1775 /* Put the MICBIASes into regulating mode */ 1776 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 1777 WM8996_MICB1_MODE, 0); 1778 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 1779 WM8996_MICB2_MODE, 0); 1780 break; 1781 1782 case SND_SOC_BIAS_STANDBY: 1783 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1784 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 1785 wm8996->supplies); 1786 if (ret != 0) { 1787 dev_err(codec->dev, 1788 "Failed to enable supplies: %d\n", 1789 ret); 1790 return ret; 1791 } 1792 1793 if (wm8996->pdata.ldo_ena >= 0) { 1794 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1795 1); 1796 msleep(5); 1797 } 1798 1799 regcache_cache_only(codec->control_data, false); 1800 regcache_sync(codec->control_data); 1801 } 1802 1803 /* Bypass the MICBIASes for lowest power */ 1804 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 1805 WM8996_MICB1_MODE, WM8996_MICB1_MODE); 1806 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 1807 WM8996_MICB2_MODE, WM8996_MICB2_MODE); 1808 break; 1809 1810 case SND_SOC_BIAS_OFF: 1811 regcache_cache_only(codec->control_data, true); 1812 if (wm8996->pdata.ldo_ena >= 0) 1813 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 1814 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), 1815 wm8996->supplies); 1816 break; 1817 } 1818 1819 codec->dapm.bias_level = level; 1820 1821 return 0; 1822 } 1823 1824 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1825 { 1826 struct snd_soc_codec *codec = dai->codec; 1827 int aifctrl = 0; 1828 int bclk = 0; 1829 int lrclk_tx = 0; 1830 int lrclk_rx = 0; 1831 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; 1832 1833 switch (dai->id) { 1834 case 0: 1835 aifctrl_reg = WM8996_AIF1_CONTROL; 1836 bclk_reg = WM8996_AIF1_BCLK; 1837 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2; 1838 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2; 1839 break; 1840 case 1: 1841 aifctrl_reg = WM8996_AIF2_CONTROL; 1842 bclk_reg = WM8996_AIF2_BCLK; 1843 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2; 1844 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2; 1845 break; 1846 default: 1847 BUG(); 1848 return -EINVAL; 1849 } 1850 1851 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1852 case SND_SOC_DAIFMT_NB_NF: 1853 break; 1854 case SND_SOC_DAIFMT_IB_NF: 1855 bclk |= WM8996_AIF1_BCLK_INV; 1856 break; 1857 case SND_SOC_DAIFMT_NB_IF: 1858 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1859 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1860 break; 1861 case SND_SOC_DAIFMT_IB_IF: 1862 bclk |= WM8996_AIF1_BCLK_INV; 1863 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1864 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1865 break; 1866 } 1867 1868 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1869 case SND_SOC_DAIFMT_CBS_CFS: 1870 break; 1871 case SND_SOC_DAIFMT_CBS_CFM: 1872 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1873 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1874 break; 1875 case SND_SOC_DAIFMT_CBM_CFS: 1876 bclk |= WM8996_AIF1_BCLK_MSTR; 1877 break; 1878 case SND_SOC_DAIFMT_CBM_CFM: 1879 bclk |= WM8996_AIF1_BCLK_MSTR; 1880 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1881 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1882 break; 1883 default: 1884 return -EINVAL; 1885 } 1886 1887 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1888 case SND_SOC_DAIFMT_DSP_A: 1889 break; 1890 case SND_SOC_DAIFMT_DSP_B: 1891 aifctrl |= 1; 1892 break; 1893 case SND_SOC_DAIFMT_I2S: 1894 aifctrl |= 2; 1895 break; 1896 case SND_SOC_DAIFMT_LEFT_J: 1897 aifctrl |= 3; 1898 break; 1899 default: 1900 return -EINVAL; 1901 } 1902 1903 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl); 1904 snd_soc_update_bits(codec, bclk_reg, 1905 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR, 1906 bclk); 1907 snd_soc_update_bits(codec, lrclk_tx_reg, 1908 WM8996_AIF1TX_LRCLK_INV | 1909 WM8996_AIF1TX_LRCLK_MSTR, 1910 lrclk_tx); 1911 snd_soc_update_bits(codec, lrclk_rx_reg, 1912 WM8996_AIF1RX_LRCLK_INV | 1913 WM8996_AIF1RX_LRCLK_MSTR, 1914 lrclk_rx); 1915 1916 return 0; 1917 } 1918 1919 static const int dsp_divs[] = { 1920 48000, 32000, 16000, 8000 1921 }; 1922 1923 static int wm8996_hw_params(struct snd_pcm_substream *substream, 1924 struct snd_pcm_hw_params *params, 1925 struct snd_soc_dai *dai) 1926 { 1927 struct snd_soc_codec *codec = dai->codec; 1928 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1929 int bits, i, bclk_rate, best; 1930 int aifdata = 0; 1931 int lrclk = 0; 1932 int dsp = 0; 1933 int aifdata_reg, lrclk_reg, dsp_shift; 1934 1935 switch (dai->id) { 1936 case 0: 1937 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1938 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) { 1939 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION; 1940 lrclk_reg = WM8996_AIF1_RX_LRCLK_1; 1941 } else { 1942 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1; 1943 lrclk_reg = WM8996_AIF1_TX_LRCLK_1; 1944 } 1945 dsp_shift = 0; 1946 break; 1947 case 1: 1948 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1949 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) { 1950 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION; 1951 lrclk_reg = WM8996_AIF2_RX_LRCLK_1; 1952 } else { 1953 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1; 1954 lrclk_reg = WM8996_AIF2_TX_LRCLK_1; 1955 } 1956 dsp_shift = WM8996_DSP2_DIV_SHIFT; 1957 break; 1958 default: 1959 BUG(); 1960 return -EINVAL; 1961 } 1962 1963 bclk_rate = snd_soc_params_to_bclk(params); 1964 if (bclk_rate < 0) { 1965 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); 1966 return bclk_rate; 1967 } 1968 1969 wm8996->bclk_rate[dai->id] = bclk_rate; 1970 wm8996->rx_rate[dai->id] = params_rate(params); 1971 1972 /* Needs looking at for TDM */ 1973 bits = snd_pcm_format_width(params_format(params)); 1974 if (bits < 0) 1975 return bits; 1976 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits; 1977 1978 best = 0; 1979 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { 1980 if (abs(dsp_divs[i] - params_rate(params)) < 1981 abs(dsp_divs[best] - params_rate(params))) 1982 best = i; 1983 } 1984 dsp |= i << dsp_shift; 1985 1986 wm8996_update_bclk(codec); 1987 1988 lrclk = bclk_rate / params_rate(params); 1989 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1990 lrclk, bclk_rate / lrclk); 1991 1992 snd_soc_update_bits(codec, aifdata_reg, 1993 WM8996_AIF1TX_WL_MASK | 1994 WM8996_AIF1TX_SLOT_LEN_MASK, 1995 aifdata); 1996 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK, 1997 lrclk); 1998 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2, 1999 WM8996_DSP1_DIV_MASK << dsp_shift, dsp); 2000 2001 return 0; 2002 } 2003 2004 static int wm8996_set_sysclk(struct snd_soc_dai *dai, 2005 int clk_id, unsigned int freq, int dir) 2006 { 2007 struct snd_soc_codec *codec = dai->codec; 2008 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2009 int lfclk = 0; 2010 int ratediv = 0; 2011 int sync = WM8996_REG_SYNC; 2012 int src; 2013 int old; 2014 2015 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src) 2016 return 0; 2017 2018 /* Disable SYSCLK while we reconfigure */ 2019 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA; 2020 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 2021 WM8996_SYSCLK_ENA, 0); 2022 2023 switch (clk_id) { 2024 case WM8996_SYSCLK_MCLK1: 2025 wm8996->sysclk = freq; 2026 src = 0; 2027 break; 2028 case WM8996_SYSCLK_MCLK2: 2029 wm8996->sysclk = freq; 2030 src = 1; 2031 break; 2032 case WM8996_SYSCLK_FLL: 2033 wm8996->sysclk = freq; 2034 src = 2; 2035 break; 2036 default: 2037 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); 2038 return -EINVAL; 2039 } 2040 2041 switch (wm8996->sysclk) { 2042 case 5644800: 2043 case 6144000: 2044 snd_soc_update_bits(codec, WM8996_AIF_RATE, 2045 WM8996_SYSCLK_RATE, 0); 2046 break; 2047 case 22579200: 2048 case 24576000: 2049 ratediv = WM8996_SYSCLK_DIV; 2050 wm8996->sysclk /= 2; 2051 case 11289600: 2052 case 12288000: 2053 snd_soc_update_bits(codec, WM8996_AIF_RATE, 2054 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); 2055 break; 2056 case 32000: 2057 case 32768: 2058 lfclk = WM8996_LFCLK_ENA; 2059 sync = 0; 2060 break; 2061 default: 2062 dev_warn(codec->dev, "Unsupported clock rate %dHz\n", 2063 wm8996->sysclk); 2064 return -EINVAL; 2065 } 2066 2067 wm8996_update_bclk(codec); 2068 2069 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 2070 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK, 2071 src << WM8996_SYSCLK_SRC_SHIFT | ratediv); 2072 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk); 2073 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1, 2074 WM8996_REG_SYNC, sync); 2075 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 2076 WM8996_SYSCLK_ENA, old); 2077 2078 wm8996->sysclk_src = clk_id; 2079 2080 return 0; 2081 } 2082 2083 struct _fll_div { 2084 u16 fll_fratio; 2085 u16 fll_outdiv; 2086 u16 fll_refclk_div; 2087 u16 fll_loop_gain; 2088 u16 fll_ref_freq; 2089 u16 n; 2090 u16 theta; 2091 u16 lambda; 2092 }; 2093 2094 static struct { 2095 unsigned int min; 2096 unsigned int max; 2097 u16 fll_fratio; 2098 int ratio; 2099 } fll_fratios[] = { 2100 { 0, 64000, 4, 16 }, 2101 { 64000, 128000, 3, 8 }, 2102 { 128000, 256000, 2, 4 }, 2103 { 256000, 1000000, 1, 2 }, 2104 { 1000000, 13500000, 0, 1 }, 2105 }; 2106 2107 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 2108 unsigned int Fout) 2109 { 2110 unsigned int target; 2111 unsigned int div; 2112 unsigned int fratio, gcd_fll; 2113 int i; 2114 2115 /* Fref must be <=13.5MHz */ 2116 div = 1; 2117 fll_div->fll_refclk_div = 0; 2118 while ((Fref / div) > 13500000) { 2119 div *= 2; 2120 fll_div->fll_refclk_div++; 2121 2122 if (div > 8) { 2123 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 2124 Fref); 2125 return -EINVAL; 2126 } 2127 } 2128 2129 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 2130 2131 /* Apply the division for our remaining calculations */ 2132 Fref /= div; 2133 2134 if (Fref >= 3000000) 2135 fll_div->fll_loop_gain = 5; 2136 else 2137 fll_div->fll_loop_gain = 0; 2138 2139 if (Fref >= 48000) 2140 fll_div->fll_ref_freq = 0; 2141 else 2142 fll_div->fll_ref_freq = 1; 2143 2144 /* Fvco should be 90-100MHz; don't check the upper bound */ 2145 div = 2; 2146 while (Fout * div < 90000000) { 2147 div++; 2148 if (div > 64) { 2149 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 2150 Fout); 2151 return -EINVAL; 2152 } 2153 } 2154 target = Fout * div; 2155 fll_div->fll_outdiv = div - 1; 2156 2157 pr_debug("FLL Fvco=%dHz\n", target); 2158 2159 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 2160 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 2161 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 2162 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 2163 fratio = fll_fratios[i].ratio; 2164 break; 2165 } 2166 } 2167 if (i == ARRAY_SIZE(fll_fratios)) { 2168 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 2169 return -EINVAL; 2170 } 2171 2172 fll_div->n = target / (fratio * Fref); 2173 2174 if (target % Fref == 0) { 2175 fll_div->theta = 0; 2176 fll_div->lambda = 0; 2177 } else { 2178 gcd_fll = gcd(target, fratio * Fref); 2179 2180 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 2181 / gcd_fll; 2182 fll_div->lambda = (fratio * Fref) / gcd_fll; 2183 } 2184 2185 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 2186 fll_div->n, fll_div->theta, fll_div->lambda); 2187 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 2188 fll_div->fll_fratio, fll_div->fll_outdiv, 2189 fll_div->fll_refclk_div); 2190 2191 return 0; 2192 } 2193 2194 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 2195 unsigned int Fref, unsigned int Fout) 2196 { 2197 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2198 struct i2c_client *i2c = to_i2c_client(codec->dev); 2199 struct _fll_div fll_div; 2200 unsigned long timeout; 2201 int ret, reg, retry; 2202 2203 /* Any change? */ 2204 if (source == wm8996->fll_src && Fref == wm8996->fll_fref && 2205 Fout == wm8996->fll_fout) 2206 return 0; 2207 2208 if (Fout == 0) { 2209 dev_dbg(codec->dev, "FLL disabled\n"); 2210 2211 wm8996->fll_fref = 0; 2212 wm8996->fll_fout = 0; 2213 2214 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2215 WM8996_FLL_ENA, 0); 2216 2217 wm8996_bg_disable(codec); 2218 2219 return 0; 2220 } 2221 2222 ret = fll_factors(&fll_div, Fref, Fout); 2223 if (ret != 0) 2224 return ret; 2225 2226 switch (source) { 2227 case WM8996_FLL_MCLK1: 2228 reg = 0; 2229 break; 2230 case WM8996_FLL_MCLK2: 2231 reg = 1; 2232 break; 2233 case WM8996_FLL_DACLRCLK1: 2234 reg = 2; 2235 break; 2236 case WM8996_FLL_BCLK1: 2237 reg = 3; 2238 break; 2239 default: 2240 dev_err(codec->dev, "Unknown FLL source %d\n", ret); 2241 return -EINVAL; 2242 } 2243 2244 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; 2245 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; 2246 2247 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5, 2248 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ | 2249 WM8996_FLL_REFCLK_SRC_MASK, reg); 2250 2251 reg = 0; 2252 if (fll_div.theta || fll_div.lambda) 2253 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); 2254 else 2255 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; 2256 snd_soc_write(codec, WM8996_FLL_EFS_2, reg); 2257 2258 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2, 2259 WM8996_FLL_OUTDIV_MASK | 2260 WM8996_FLL_FRATIO_MASK, 2261 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) | 2262 (fll_div.fll_fratio)); 2263 2264 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta); 2265 2266 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4, 2267 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK, 2268 (fll_div.n << WM8996_FLL_N_SHIFT) | 2269 fll_div.fll_loop_gain); 2270 2271 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda); 2272 2273 /* Enable the bandgap if it's not already enabled */ 2274 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1); 2275 if (!(ret & WM8996_FLL_ENA)) 2276 wm8996_bg_enable(codec); 2277 2278 /* Clear any pending completions (eg, from failed startups) */ 2279 try_wait_for_completion(&wm8996->fll_lock); 2280 2281 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2282 WM8996_FLL_ENA, WM8996_FLL_ENA); 2283 2284 /* The FLL supports live reconfiguration - kick that in case we were 2285 * already enabled. 2286 */ 2287 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK); 2288 2289 /* Wait for the FLL to lock, using the interrupt if possible */ 2290 if (Fref > 1000000) 2291 timeout = usecs_to_jiffies(300); 2292 else 2293 timeout = msecs_to_jiffies(2); 2294 2295 /* Allow substantially longer if we've actually got the IRQ, poll 2296 * at a slightly higher rate if we don't. 2297 */ 2298 if (i2c->irq) 2299 timeout *= 10; 2300 else 2301 timeout /= 2; 2302 2303 for (retry = 0; retry < 10; retry++) { 2304 ret = wait_for_completion_timeout(&wm8996->fll_lock, 2305 timeout); 2306 if (ret != 0) { 2307 WARN_ON(!i2c->irq); 2308 break; 2309 } 2310 2311 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2); 2312 if (ret & WM8996_FLL_LOCK_STS) 2313 break; 2314 } 2315 if (retry == 10) { 2316 dev_err(codec->dev, "Timed out waiting for FLL\n"); 2317 ret = -ETIMEDOUT; 2318 } 2319 2320 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2321 2322 wm8996->fll_fref = Fref; 2323 wm8996->fll_fout = Fout; 2324 wm8996->fll_src = source; 2325 2326 return ret; 2327 } 2328 2329 #ifdef CONFIG_GPIOLIB 2330 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip) 2331 { 2332 return container_of(chip, struct wm8996_priv, gpio_chip); 2333 } 2334 2335 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 2336 { 2337 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2338 2339 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2340 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT); 2341 } 2342 2343 static int wm8996_gpio_direction_out(struct gpio_chip *chip, 2344 unsigned offset, int value) 2345 { 2346 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2347 int val; 2348 2349 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); 2350 2351 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2352 WM8996_GP1_FN_MASK | WM8996_GP1_DIR | 2353 WM8996_GP1_LVL, val); 2354 } 2355 2356 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset) 2357 { 2358 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2359 unsigned int reg; 2360 int ret; 2361 2362 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®); 2363 if (ret < 0) 2364 return ret; 2365 2366 return (reg & WM8996_GP1_LVL) != 0; 2367 } 2368 2369 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 2370 { 2371 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2372 2373 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2374 WM8996_GP1_FN_MASK | WM8996_GP1_DIR, 2375 (1 << WM8996_GP1_FN_SHIFT) | 2376 (1 << WM8996_GP1_DIR_SHIFT)); 2377 } 2378 2379 static struct gpio_chip wm8996_template_chip = { 2380 .label = "wm8996", 2381 .owner = THIS_MODULE, 2382 .direction_output = wm8996_gpio_direction_out, 2383 .set = wm8996_gpio_set, 2384 .direction_input = wm8996_gpio_direction_in, 2385 .get = wm8996_gpio_get, 2386 .can_sleep = 1, 2387 }; 2388 2389 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2390 { 2391 int ret; 2392 2393 wm8996->gpio_chip = wm8996_template_chip; 2394 wm8996->gpio_chip.ngpio = 5; 2395 wm8996->gpio_chip.dev = wm8996->dev; 2396 2397 if (wm8996->pdata.gpio_base) 2398 wm8996->gpio_chip.base = wm8996->pdata.gpio_base; 2399 else 2400 wm8996->gpio_chip.base = -1; 2401 2402 ret = gpiochip_add(&wm8996->gpio_chip); 2403 if (ret != 0) 2404 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret); 2405 } 2406 2407 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2408 { 2409 int ret; 2410 2411 ret = gpiochip_remove(&wm8996->gpio_chip); 2412 if (ret != 0) 2413 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret); 2414 } 2415 #else 2416 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2417 { 2418 } 2419 2420 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2421 { 2422 } 2423 #endif 2424 2425 /** 2426 * wm8996_detect - Enable default WM8996 jack detection 2427 * 2428 * The WM8996 has advanced accessory detection support for headsets. 2429 * This function provides a default implementation which integrates 2430 * the majority of this functionality with minimal user configuration. 2431 * 2432 * This will detect headset, headphone and short circuit button and 2433 * will also detect inverted microphone ground connections and update 2434 * the polarity of the connections. 2435 */ 2436 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2437 wm8996_polarity_fn polarity_cb) 2438 { 2439 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2440 2441 wm8996->jack = jack; 2442 wm8996->detecting = true; 2443 wm8996->polarity_cb = polarity_cb; 2444 wm8996->jack_flips = 0; 2445 2446 if (wm8996->polarity_cb) 2447 wm8996->polarity_cb(codec, 0); 2448 2449 /* Clear discarge to avoid noise during detection */ 2450 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 2451 WM8996_MICB1_DISCH, 0); 2452 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 2453 WM8996_MICB2_DISCH, 0); 2454 2455 /* LDO2 powers the microphones, SYSCLK clocks detection */ 2456 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2"); 2457 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); 2458 2459 /* We start off just enabling microphone detection - even a 2460 * plain headphone will trigger detection. 2461 */ 2462 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2463 WM8996_MICD_ENA, WM8996_MICD_ENA); 2464 2465 /* Slowest detection rate, gives debounce for initial detection */ 2466 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2467 WM8996_MICD_RATE_MASK, 2468 WM8996_MICD_RATE_MASK); 2469 2470 /* Enable interrupts and we're off */ 2471 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK, 2472 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0); 2473 2474 return 0; 2475 } 2476 EXPORT_SYMBOL_GPL(wm8996_detect); 2477 2478 static void wm8996_hpdet_irq(struct snd_soc_codec *codec) 2479 { 2480 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2481 int val, reg, report; 2482 2483 /* Assume headphone in error conditions; we need to report 2484 * something or we stall our state machine. 2485 */ 2486 report = SND_JACK_HEADPHONE; 2487 2488 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2); 2489 if (reg < 0) { 2490 dev_err(codec->dev, "Failed to read HPDET status\n"); 2491 goto out; 2492 } 2493 2494 if (!(reg & WM8996_HP_DONE)) { 2495 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n"); 2496 goto out; 2497 } 2498 2499 val = reg & WM8996_HP_LVL_MASK; 2500 2501 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val); 2502 2503 /* If we've got high enough impedence then report as line, 2504 * otherwise assume headphone. 2505 */ 2506 if (val >= 126) 2507 report = SND_JACK_LINEOUT; 2508 else 2509 report = SND_JACK_HEADPHONE; 2510 2511 out: 2512 if (wm8996->jack_mic) 2513 report |= SND_JACK_MICROPHONE; 2514 2515 snd_soc_jack_report(wm8996->jack, report, 2516 SND_JACK_LINEOUT | SND_JACK_HEADSET); 2517 2518 wm8996->detecting = false; 2519 2520 /* If the output isn't running re-clamp it */ 2521 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) & 2522 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT))) 2523 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2524 WM8996_HPOUT1L_RMV_SHORT | 2525 WM8996_HPOUT1R_RMV_SHORT, 0); 2526 2527 /* Go back to looking at the microphone */ 2528 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2529 WM8996_JD_MODE_MASK, 0); 2530 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 2531 WM8996_MICD_ENA); 2532 2533 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap"); 2534 snd_soc_dapm_sync(&codec->dapm); 2535 } 2536 2537 static void wm8996_hpdet_start(struct snd_soc_codec *codec) 2538 { 2539 /* Unclamp the output, we can't measure while we're shorting it */ 2540 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2541 WM8996_HPOUT1L_RMV_SHORT | 2542 WM8996_HPOUT1R_RMV_SHORT, 2543 WM8996_HPOUT1L_RMV_SHORT | 2544 WM8996_HPOUT1R_RMV_SHORT); 2545 2546 /* We need bandgap for HPDET */ 2547 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap"); 2548 snd_soc_dapm_sync(&codec->dapm); 2549 2550 /* Go into headphone detect left mode */ 2551 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0); 2552 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2553 WM8996_JD_MODE_MASK, 1); 2554 2555 /* Trigger a measurement */ 2556 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1, 2557 WM8996_HP_POLL, WM8996_HP_POLL); 2558 } 2559 2560 static void wm8996_report_headphone(struct snd_soc_codec *codec) 2561 { 2562 dev_dbg(codec->dev, "Headphone detected\n"); 2563 wm8996_hpdet_start(codec); 2564 2565 /* Increase the detection rate a bit for responsiveness. */ 2566 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2567 WM8996_MICD_RATE_MASK | 2568 WM8996_MICD_BIAS_STARTTIME_MASK, 2569 7 << WM8996_MICD_RATE_SHIFT | 2570 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2571 } 2572 2573 static void wm8996_micd(struct snd_soc_codec *codec) 2574 { 2575 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2576 int val, reg; 2577 2578 val = snd_soc_read(codec, WM8996_MIC_DETECT_3); 2579 2580 dev_dbg(codec->dev, "Microphone event: %x\n", val); 2581 2582 if (!(val & WM8996_MICD_VALID)) { 2583 dev_warn(codec->dev, "Microphone detection state invalid\n"); 2584 return; 2585 } 2586 2587 /* No accessory, reset everything and report removal */ 2588 if (!(val & WM8996_MICD_STS)) { 2589 dev_dbg(codec->dev, "Jack removal detected\n"); 2590 wm8996->jack_mic = false; 2591 wm8996->detecting = true; 2592 wm8996->jack_flips = 0; 2593 snd_soc_jack_report(wm8996->jack, 0, 2594 SND_JACK_LINEOUT | SND_JACK_HEADSET | 2595 SND_JACK_BTN_0); 2596 2597 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2598 WM8996_MICD_RATE_MASK | 2599 WM8996_MICD_BIAS_STARTTIME_MASK, 2600 WM8996_MICD_RATE_MASK | 2601 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2602 return; 2603 } 2604 2605 /* If the measurement is very high we've got a microphone, 2606 * either we just detected one or if we already reported then 2607 * we've got a button release event. 2608 */ 2609 if (val & 0x400) { 2610 if (wm8996->detecting) { 2611 dev_dbg(codec->dev, "Microphone detected\n"); 2612 wm8996->jack_mic = true; 2613 wm8996_hpdet_start(codec); 2614 2615 /* Increase poll rate to give better responsiveness 2616 * for buttons */ 2617 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2618 WM8996_MICD_RATE_MASK | 2619 WM8996_MICD_BIAS_STARTTIME_MASK, 2620 5 << WM8996_MICD_RATE_SHIFT | 2621 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2622 } else { 2623 dev_dbg(codec->dev, "Mic button up\n"); 2624 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0); 2625 } 2626 2627 return; 2628 } 2629 2630 /* If we detected a lower impedence during initial startup 2631 * then we probably have the wrong polarity, flip it. Don't 2632 * do this for the lowest impedences to speed up detection of 2633 * plain headphones. If both polarities report a low 2634 * impedence then give up and report headphones. 2635 */ 2636 if (wm8996->detecting && (val & 0x3f0)) { 2637 wm8996->jack_flips++; 2638 2639 if (wm8996->jack_flips > 1) { 2640 wm8996_report_headphone(codec); 2641 return; 2642 } 2643 2644 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2); 2645 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2646 WM8996_MICD_BIAS_SRC; 2647 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, 2648 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2649 WM8996_MICD_BIAS_SRC, reg); 2650 2651 if (wm8996->polarity_cb) 2652 wm8996->polarity_cb(codec, 2653 (reg & WM8996_MICD_SRC) != 0); 2654 2655 dev_dbg(codec->dev, "Set microphone polarity to %d\n", 2656 (reg & WM8996_MICD_SRC) != 0); 2657 2658 return; 2659 } 2660 2661 /* Don't distinguish between buttons, just report any low 2662 * impedence as BTN_0. 2663 */ 2664 if (val & 0x3fc) { 2665 if (wm8996->jack_mic) { 2666 dev_dbg(codec->dev, "Mic button detected\n"); 2667 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0, 2668 SND_JACK_BTN_0); 2669 } else if (wm8996->detecting) { 2670 wm8996_report_headphone(codec); 2671 } 2672 } 2673 } 2674 2675 static irqreturn_t wm8996_irq(int irq, void *data) 2676 { 2677 struct snd_soc_codec *codec = data; 2678 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2679 int irq_val; 2680 2681 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2); 2682 if (irq_val < 0) { 2683 dev_err(codec->dev, "Failed to read IRQ status: %d\n", 2684 irq_val); 2685 return IRQ_NONE; 2686 } 2687 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK); 2688 2689 if (!irq_val) 2690 return IRQ_NONE; 2691 2692 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val); 2693 2694 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) { 2695 dev_dbg(codec->dev, "DC servo IRQ\n"); 2696 complete(&wm8996->dcs_done); 2697 } 2698 2699 if (irq_val & WM8996_FIFOS_ERR_EINT) 2700 dev_err(codec->dev, "Digital core FIFO error\n"); 2701 2702 if (irq_val & WM8996_FLL_LOCK_EINT) { 2703 dev_dbg(codec->dev, "FLL locked\n"); 2704 complete(&wm8996->fll_lock); 2705 } 2706 2707 if (irq_val & WM8996_MICD_EINT) 2708 wm8996_micd(codec); 2709 2710 if (irq_val & WM8996_HP_DONE_EINT) 2711 wm8996_hpdet_irq(codec); 2712 2713 return IRQ_HANDLED; 2714 } 2715 2716 static irqreturn_t wm8996_edge_irq(int irq, void *data) 2717 { 2718 irqreturn_t ret = IRQ_NONE; 2719 irqreturn_t val; 2720 2721 do { 2722 val = wm8996_irq(irq, data); 2723 if (val != IRQ_NONE) 2724 ret = val; 2725 } while (val != IRQ_NONE); 2726 2727 return ret; 2728 } 2729 2730 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec) 2731 { 2732 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2733 struct wm8996_pdata *pdata = &wm8996->pdata; 2734 2735 struct snd_kcontrol_new controls[] = { 2736 SOC_ENUM_EXT("DSP1 EQ Mode", 2737 wm8996->retune_mobile_enum, 2738 wm8996_get_retune_mobile_enum, 2739 wm8996_put_retune_mobile_enum), 2740 SOC_ENUM_EXT("DSP2 EQ Mode", 2741 wm8996->retune_mobile_enum, 2742 wm8996_get_retune_mobile_enum, 2743 wm8996_put_retune_mobile_enum), 2744 }; 2745 int ret, i, j; 2746 const char **t; 2747 2748 /* We need an array of texts for the enum API but the number 2749 * of texts is likely to be less than the number of 2750 * configurations due to the sample rate dependency of the 2751 * configurations. */ 2752 wm8996->num_retune_mobile_texts = 0; 2753 wm8996->retune_mobile_texts = NULL; 2754 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2755 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) { 2756 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2757 wm8996->retune_mobile_texts[j]) == 0) 2758 break; 2759 } 2760 2761 if (j != wm8996->num_retune_mobile_texts) 2762 continue; 2763 2764 /* Expand the array... */ 2765 t = krealloc(wm8996->retune_mobile_texts, 2766 sizeof(char *) * 2767 (wm8996->num_retune_mobile_texts + 1), 2768 GFP_KERNEL); 2769 if (t == NULL) 2770 continue; 2771 2772 /* ...store the new entry... */ 2773 t[wm8996->num_retune_mobile_texts] = 2774 pdata->retune_mobile_cfgs[i].name; 2775 2776 /* ...and remember the new version. */ 2777 wm8996->num_retune_mobile_texts++; 2778 wm8996->retune_mobile_texts = t; 2779 } 2780 2781 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2782 wm8996->num_retune_mobile_texts); 2783 2784 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts; 2785 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts; 2786 2787 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 2788 if (ret != 0) 2789 dev_err(codec->dev, 2790 "Failed to add ReTune Mobile controls: %d\n", ret); 2791 } 2792 2793 static const struct regmap_config wm8996_regmap = { 2794 .reg_bits = 16, 2795 .val_bits = 16, 2796 2797 .max_register = WM8996_MAX_REGISTER, 2798 .reg_defaults = wm8996_reg, 2799 .num_reg_defaults = ARRAY_SIZE(wm8996_reg), 2800 .volatile_reg = wm8996_volatile_register, 2801 .readable_reg = wm8996_readable_register, 2802 .cache_type = REGCACHE_RBTREE, 2803 }; 2804 2805 static int wm8996_probe(struct snd_soc_codec *codec) 2806 { 2807 int ret; 2808 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2809 struct i2c_client *i2c = to_i2c_client(codec->dev); 2810 int i, irq_flags; 2811 2812 wm8996->codec = codec; 2813 2814 init_completion(&wm8996->dcs_done); 2815 init_completion(&wm8996->fll_lock); 2816 2817 codec->control_data = wm8996->regmap; 2818 2819 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 2820 if (ret != 0) { 2821 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2822 goto err; 2823 } 2824 2825 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0; 2826 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1; 2827 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2; 2828 2829 /* This should really be moved into the regulator core */ 2830 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) { 2831 ret = regulator_register_notifier(wm8996->supplies[i].consumer, 2832 &wm8996->disable_nb[i]); 2833 if (ret != 0) { 2834 dev_err(codec->dev, 2835 "Failed to register regulator notifier: %d\n", 2836 ret); 2837 } 2838 } 2839 2840 /* Apply platform data settings */ 2841 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL, 2842 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, 2843 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT | 2844 wm8996->pdata.inr_mode); 2845 2846 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) { 2847 if (!wm8996->pdata.gpio_default[i]) 2848 continue; 2849 2850 snd_soc_write(codec, WM8996_GPIO_1 + i, 2851 wm8996->pdata.gpio_default[i] & 0xffff); 2852 } 2853 2854 if (wm8996->pdata.spkmute_seq) 2855 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 2856 WM8996_SPK_MUTE_ENDIAN | 2857 WM8996_SPK_MUTE_SEQ1_MASK, 2858 wm8996->pdata.spkmute_seq); 2859 2860 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, 2861 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC | 2862 WM8996_MICD_SRC, wm8996->pdata.micdet_def); 2863 2864 /* Latch volume update bits */ 2865 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME, 2866 WM8996_IN1_VU, WM8996_IN1_VU); 2867 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME, 2868 WM8996_IN1_VU, WM8996_IN1_VU); 2869 2870 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME, 2871 WM8996_DAC1_VU, WM8996_DAC1_VU); 2872 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME, 2873 WM8996_DAC1_VU, WM8996_DAC1_VU); 2874 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME, 2875 WM8996_DAC2_VU, WM8996_DAC2_VU); 2876 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME, 2877 WM8996_DAC2_VU, WM8996_DAC2_VU); 2878 2879 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME, 2880 WM8996_DAC1_VU, WM8996_DAC1_VU); 2881 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME, 2882 WM8996_DAC1_VU, WM8996_DAC1_VU); 2883 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME, 2884 WM8996_DAC2_VU, WM8996_DAC2_VU); 2885 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME, 2886 WM8996_DAC2_VU, WM8996_DAC2_VU); 2887 2888 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME, 2889 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2890 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME, 2891 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2892 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME, 2893 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2894 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME, 2895 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2896 2897 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME, 2898 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2899 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME, 2900 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2901 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME, 2902 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2903 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME, 2904 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2905 2906 /* No support currently for the underclocked TDM modes and 2907 * pick a default TDM layout with each channel pair working with 2908 * slots 0 and 1. */ 2909 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 2910 WM8996_AIF1RX_CHAN0_SLOTS_MASK | 2911 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2912 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0); 2913 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 2914 WM8996_AIF1RX_CHAN1_SLOTS_MASK | 2915 WM8996_AIF1RX_CHAN1_START_SLOT_MASK, 2916 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1); 2917 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 2918 WM8996_AIF1RX_CHAN2_SLOTS_MASK | 2919 WM8996_AIF1RX_CHAN2_START_SLOT_MASK, 2920 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0); 2921 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 2922 WM8996_AIF1RX_CHAN3_SLOTS_MASK | 2923 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2924 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1); 2925 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 2926 WM8996_AIF1RX_CHAN4_SLOTS_MASK | 2927 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2928 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0); 2929 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 2930 WM8996_AIF1RX_CHAN5_SLOTS_MASK | 2931 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2932 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1); 2933 2934 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 2935 WM8996_AIF2RX_CHAN0_SLOTS_MASK | 2936 WM8996_AIF2RX_CHAN0_START_SLOT_MASK, 2937 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0); 2938 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 2939 WM8996_AIF2RX_CHAN1_SLOTS_MASK | 2940 WM8996_AIF2RX_CHAN1_START_SLOT_MASK, 2941 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1); 2942 2943 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 2944 WM8996_AIF1TX_CHAN0_SLOTS_MASK | 2945 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2946 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0); 2947 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 2948 WM8996_AIF1TX_CHAN1_SLOTS_MASK | 2949 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2950 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 2951 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 2952 WM8996_AIF1TX_CHAN2_SLOTS_MASK | 2953 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2954 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0); 2955 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 2956 WM8996_AIF1TX_CHAN3_SLOTS_MASK | 2957 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2958 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1); 2959 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 2960 WM8996_AIF1TX_CHAN4_SLOTS_MASK | 2961 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2962 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0); 2963 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 2964 WM8996_AIF1TX_CHAN5_SLOTS_MASK | 2965 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2966 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1); 2967 2968 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 2969 WM8996_AIF2TX_CHAN0_SLOTS_MASK | 2970 WM8996_AIF2TX_CHAN0_START_SLOT_MASK, 2971 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0); 2972 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 2973 WM8996_AIF2TX_CHAN1_SLOTS_MASK | 2974 WM8996_AIF2TX_CHAN1_START_SLOT_MASK, 2975 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 2976 2977 if (wm8996->pdata.num_retune_mobile_cfgs) 2978 wm8996_retune_mobile_pdata(codec); 2979 else 2980 snd_soc_add_codec_controls(codec, wm8996_eq_controls, 2981 ARRAY_SIZE(wm8996_eq_controls)); 2982 2983 /* If the TX LRCLK pins are not in LRCLK mode configure the 2984 * AIFs to source their clocks from the RX LRCLKs. 2985 */ 2986 if ((snd_soc_read(codec, WM8996_GPIO_1))) 2987 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2, 2988 WM8996_AIF1TX_LRCLK_MODE, 2989 WM8996_AIF1TX_LRCLK_MODE); 2990 2991 if ((snd_soc_read(codec, WM8996_GPIO_2))) 2992 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2, 2993 WM8996_AIF2TX_LRCLK_MODE, 2994 WM8996_AIF2TX_LRCLK_MODE); 2995 2996 if (i2c->irq) { 2997 if (wm8996->pdata.irq_flags) 2998 irq_flags = wm8996->pdata.irq_flags; 2999 else 3000 irq_flags = IRQF_TRIGGER_LOW; 3001 3002 irq_flags |= IRQF_ONESHOT; 3003 3004 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) 3005 ret = request_threaded_irq(i2c->irq, NULL, 3006 wm8996_edge_irq, 3007 irq_flags, "wm8996", codec); 3008 else 3009 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq, 3010 irq_flags, "wm8996", codec); 3011 3012 if (ret == 0) { 3013 /* Unmask the interrupt */ 3014 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 3015 WM8996_IM_IRQ, 0); 3016 3017 /* Enable error reporting and DC servo status */ 3018 snd_soc_update_bits(codec, 3019 WM8996_INTERRUPT_STATUS_2_MASK, 3020 WM8996_IM_DCS_DONE_23_EINT | 3021 WM8996_IM_DCS_DONE_01_EINT | 3022 WM8996_IM_FLL_LOCK_EINT | 3023 WM8996_IM_FIFOS_ERR_EINT, 3024 0); 3025 } else { 3026 dev_err(codec->dev, "Failed to request IRQ: %d\n", 3027 ret); 3028 } 3029 } 3030 3031 return 0; 3032 3033 err: 3034 return ret; 3035 } 3036 3037 static int wm8996_remove(struct snd_soc_codec *codec) 3038 { 3039 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 3040 struct i2c_client *i2c = to_i2c_client(codec->dev); 3041 int i; 3042 3043 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 3044 WM8996_IM_IRQ, WM8996_IM_IRQ); 3045 3046 if (i2c->irq) 3047 free_irq(i2c->irq, codec); 3048 3049 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 3050 regulator_unregister_notifier(wm8996->supplies[i].consumer, 3051 &wm8996->disable_nb[i]); 3052 3053 return 0; 3054 } 3055 3056 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = { 3057 .probe = wm8996_probe, 3058 .remove = wm8996_remove, 3059 .set_bias_level = wm8996_set_bias_level, 3060 .idle_bias_off = true, 3061 .seq_notifier = wm8996_seq_notifier, 3062 .controls = wm8996_snd_controls, 3063 .num_controls = ARRAY_SIZE(wm8996_snd_controls), 3064 .dapm_widgets = wm8996_dapm_widgets, 3065 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets), 3066 .dapm_routes = wm8996_dapm_routes, 3067 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes), 3068 .set_pll = wm8996_set_fll, 3069 }; 3070 3071 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 3072 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ 3073 SNDRV_PCM_RATE_48000) 3074 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 3075 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 3076 SNDRV_PCM_FMTBIT_S32_LE) 3077 3078 static const struct snd_soc_dai_ops wm8996_dai_ops = { 3079 .set_fmt = wm8996_set_fmt, 3080 .hw_params = wm8996_hw_params, 3081 .set_sysclk = wm8996_set_sysclk, 3082 }; 3083 3084 static struct snd_soc_dai_driver wm8996_dai[] = { 3085 { 3086 .name = "wm8996-aif1", 3087 .playback = { 3088 .stream_name = "AIF1 Playback", 3089 .channels_min = 1, 3090 .channels_max = 6, 3091 .rates = WM8996_RATES, 3092 .formats = WM8996_FORMATS, 3093 .sig_bits = 24, 3094 }, 3095 .capture = { 3096 .stream_name = "AIF1 Capture", 3097 .channels_min = 1, 3098 .channels_max = 6, 3099 .rates = WM8996_RATES, 3100 .formats = WM8996_FORMATS, 3101 .sig_bits = 24, 3102 }, 3103 .ops = &wm8996_dai_ops, 3104 }, 3105 { 3106 .name = "wm8996-aif2", 3107 .playback = { 3108 .stream_name = "AIF2 Playback", 3109 .channels_min = 1, 3110 .channels_max = 2, 3111 .rates = WM8996_RATES, 3112 .formats = WM8996_FORMATS, 3113 .sig_bits = 24, 3114 }, 3115 .capture = { 3116 .stream_name = "AIF2 Capture", 3117 .channels_min = 1, 3118 .channels_max = 2, 3119 .rates = WM8996_RATES, 3120 .formats = WM8996_FORMATS, 3121 .sig_bits = 24, 3122 }, 3123 .ops = &wm8996_dai_ops, 3124 }, 3125 }; 3126 3127 static __devinit int wm8996_i2c_probe(struct i2c_client *i2c, 3128 const struct i2c_device_id *id) 3129 { 3130 struct wm8996_priv *wm8996; 3131 int ret, i; 3132 unsigned int reg; 3133 3134 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv), 3135 GFP_KERNEL); 3136 if (wm8996 == NULL) 3137 return -ENOMEM; 3138 3139 i2c_set_clientdata(i2c, wm8996); 3140 wm8996->dev = &i2c->dev; 3141 3142 if (dev_get_platdata(&i2c->dev)) 3143 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev), 3144 sizeof(wm8996->pdata)); 3145 3146 if (wm8996->pdata.ldo_ena > 0) { 3147 ret = gpio_request_one(wm8996->pdata.ldo_ena, 3148 GPIOF_OUT_INIT_LOW, "WM8996 ENA"); 3149 if (ret < 0) { 3150 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", 3151 wm8996->pdata.ldo_ena, ret); 3152 goto err; 3153 } 3154 } 3155 3156 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 3157 wm8996->supplies[i].supply = wm8996_supply_names[i]; 3158 3159 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies), 3160 wm8996->supplies); 3161 if (ret != 0) { 3162 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 3163 goto err_gpio; 3164 } 3165 3166 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 3167 wm8996->supplies); 3168 if (ret != 0) { 3169 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 3170 goto err_gpio; 3171 } 3172 3173 if (wm8996->pdata.ldo_ena > 0) { 3174 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); 3175 msleep(5); 3176 } 3177 3178 wm8996->regmap = regmap_init_i2c(i2c, &wm8996_regmap); 3179 if (IS_ERR(wm8996->regmap)) { 3180 ret = PTR_ERR(wm8996->regmap); 3181 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 3182 goto err_enable; 3183 } 3184 3185 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®); 3186 if (ret < 0) { 3187 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 3188 goto err_regmap; 3189 } 3190 if (reg != 0x8915) { 3191 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg); 3192 ret = -EINVAL; 3193 goto err_regmap; 3194 } 3195 3196 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®); 3197 if (ret < 0) { 3198 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 3199 ret); 3200 goto err_regmap; 3201 } 3202 3203 dev_info(&i2c->dev, "revision %c\n", 3204 (reg & WM8996_CHIP_REV_MASK) + 'A'); 3205 3206 ret = wm8996_reset(wm8996); 3207 if (ret < 0) { 3208 dev_err(&i2c->dev, "Failed to issue reset\n"); 3209 goto err_regmap; 3210 } 3211 3212 regcache_cache_only(wm8996->regmap, true); 3213 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 3214 3215 wm8996_init_gpio(wm8996); 3216 3217 ret = snd_soc_register_codec(&i2c->dev, 3218 &soc_codec_dev_wm8996, wm8996_dai, 3219 ARRAY_SIZE(wm8996_dai)); 3220 if (ret < 0) 3221 goto err_gpiolib; 3222 3223 return ret; 3224 3225 err_gpiolib: 3226 wm8996_free_gpio(wm8996); 3227 err_regmap: 3228 regmap_exit(wm8996->regmap); 3229 err_enable: 3230 if (wm8996->pdata.ldo_ena > 0) 3231 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3232 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 3233 err_gpio: 3234 if (wm8996->pdata.ldo_ena > 0) 3235 gpio_free(wm8996->pdata.ldo_ena); 3236 err: 3237 3238 return ret; 3239 } 3240 3241 static __devexit int wm8996_i2c_remove(struct i2c_client *client) 3242 { 3243 struct wm8996_priv *wm8996 = i2c_get_clientdata(client); 3244 3245 snd_soc_unregister_codec(&client->dev); 3246 wm8996_free_gpio(wm8996); 3247 regmap_exit(wm8996->regmap); 3248 if (wm8996->pdata.ldo_ena > 0) { 3249 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3250 gpio_free(wm8996->pdata.ldo_ena); 3251 } 3252 return 0; 3253 } 3254 3255 static const struct i2c_device_id wm8996_i2c_id[] = { 3256 { "wm8996", 0 }, 3257 { } 3258 }; 3259 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); 3260 3261 static struct i2c_driver wm8996_i2c_driver = { 3262 .driver = { 3263 .name = "wm8996", 3264 .owner = THIS_MODULE, 3265 }, 3266 .probe = wm8996_i2c_probe, 3267 .remove = __devexit_p(wm8996_i2c_remove), 3268 .id_table = wm8996_i2c_id, 3269 }; 3270 3271 module_i2c_driver(wm8996_i2c_driver); 3272 3273 MODULE_DESCRIPTION("ASoC WM8996 driver"); 3274 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3275 MODULE_LICENSE("GPL"); 3276