1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm8994.c -- WM8994 ALSA SoC Audio driver 4 * 5 * Copyright 2009-12 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/cleanup.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/pm.h> 16 #include <linux/gcd.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <sound/core.h> 23 #include <sound/jack.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <trace/events/asoc.h> 30 31 #include <linux/mfd/wm8994/core.h> 32 #include <linux/mfd/wm8994/registers.h> 33 #include <linux/mfd/wm8994/pdata.h> 34 #include <linux/mfd/wm8994/gpio.h> 35 36 #include "wm8994.h" 37 #include "wm_hubs.h" 38 39 #define WM1811_JACKDET_MODE_NONE 0x0000 40 #define WM1811_JACKDET_MODE_JACK 0x0100 41 #define WM1811_JACKDET_MODE_MIC 0x0080 42 #define WM1811_JACKDET_MODE_AUDIO 0x0180 43 44 #define WM8994_NUM_DRC 3 45 #define WM8994_NUM_EQ 3 46 47 struct wm8994_reg_mask { 48 unsigned int reg; 49 unsigned int mask; 50 }; 51 52 static struct wm8994_reg_mask wm8994_vu_bits[] = { 53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, 55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, 57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, 58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, 59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, 61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, 63 64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, 65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, 66 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, 67 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, 68 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, 69 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, 70 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, 71 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 72 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, 73 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, 74 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, 75 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, 76 }; 77 78 /* VU bitfields for ADC2, DAC2 not available on WM1811 */ 79 static struct wm8994_reg_mask wm8994_adc2_dac2_vu_bits[] = { 80 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, 81 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, 82 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, 83 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, 84 }; 85 86 static int wm8994_drc_base[] = { 87 WM8994_AIF1_DRC1_1, 88 WM8994_AIF1_DRC2_1, 89 WM8994_AIF2_DRC_1, 90 }; 91 92 static int wm8994_retune_mobile_base[] = { 93 WM8994_AIF1_DAC1_EQ_GAINS_1, 94 WM8994_AIF1_DAC2_EQ_GAINS_1, 95 WM8994_AIF2_EQ_GAINS_1, 96 }; 97 98 static const struct wm8958_micd_rate micdet_rates[] = { 99 { 32768, true, 1, 4 }, 100 { 32768, false, 1, 1 }, 101 { 44100 * 256, true, 7, 10 }, 102 { 44100 * 256, false, 7, 10 }, 103 }; 104 105 static const struct wm8958_micd_rate jackdet_rates[] = { 106 { 32768, true, 0, 1 }, 107 { 32768, false, 0, 1 }, 108 { 44100 * 256, true, 10, 10 }, 109 { 44100 * 256, false, 7, 8 }, 110 }; 111 112 static void wm8958_micd_set_rate(struct snd_soc_component *component) 113 { 114 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 115 struct wm8994 *control = wm8994->wm8994; 116 int best, i, sysclk, val; 117 bool idle; 118 const struct wm8958_micd_rate *rates; 119 int num_rates; 120 121 idle = !wm8994->jack_mic; 122 123 sysclk = snd_soc_component_read(component, WM8994_CLOCKING_1); 124 if (sysclk & WM8994_SYSCLK_SRC) 125 sysclk = wm8994->aifclk[1]; 126 else 127 sysclk = wm8994->aifclk[0]; 128 129 if (control->pdata.micd_rates) { 130 rates = control->pdata.micd_rates; 131 num_rates = control->pdata.num_micd_rates; 132 } else if (wm8994->jackdet) { 133 rates = jackdet_rates; 134 num_rates = ARRAY_SIZE(jackdet_rates); 135 } else { 136 rates = micdet_rates; 137 num_rates = ARRAY_SIZE(micdet_rates); 138 } 139 140 best = 0; 141 for (i = 0; i < num_rates; i++) { 142 if (rates[i].idle != idle) 143 continue; 144 if (abs(rates[i].sysclk - sysclk) < 145 abs(rates[best].sysclk - sysclk)) 146 best = i; 147 else if (rates[best].idle != idle) 148 best = i; 149 } 150 151 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 152 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 153 154 dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n", 155 rates[best].start, rates[best].rate, sysclk, 156 idle ? "idle" : "active"); 157 158 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 159 WM8958_MICD_BIAS_STARTTIME_MASK | 160 WM8958_MICD_RATE_MASK, val); 161 } 162 163 static int configure_aif_clock(struct snd_soc_component *component, int aif) 164 { 165 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 166 int rate; 167 int reg1 = 0; 168 int offset; 169 170 if (aif) 171 offset = 4; 172 else 173 offset = 0; 174 175 switch (wm8994->sysclk[aif]) { 176 case WM8994_SYSCLK_MCLK1: 177 rate = wm8994->mclk_rate[0]; 178 break; 179 180 case WM8994_SYSCLK_MCLK2: 181 reg1 |= 0x8; 182 rate = wm8994->mclk_rate[1]; 183 break; 184 185 case WM8994_SYSCLK_FLL1: 186 reg1 |= 0x10; 187 rate = wm8994->fll[0].out; 188 break; 189 190 case WM8994_SYSCLK_FLL2: 191 reg1 |= 0x18; 192 rate = wm8994->fll[1].out; 193 break; 194 195 default: 196 return -EINVAL; 197 } 198 199 if (rate >= 13500000) { 200 rate /= 2; 201 reg1 |= WM8994_AIF1CLK_DIV; 202 203 dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n", 204 aif + 1, rate); 205 } 206 207 wm8994->aifclk[aif] = rate; 208 209 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset, 210 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 211 reg1); 212 213 return 0; 214 } 215 216 static int configure_clock(struct snd_soc_component *component) 217 { 218 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 219 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 220 int change, new; 221 222 /* Bring up the AIF clocks first */ 223 configure_aif_clock(component, 0); 224 configure_aif_clock(component, 1); 225 226 /* Then switch CLK_SYS over to the higher of them; a change 227 * can only happen as a result of a clocking change which can 228 * only be made outside of DAPM so we can safely redo the 229 * clocking. 230 */ 231 232 /* If they're equal it doesn't matter which is used */ 233 if (wm8994->aifclk[0] == wm8994->aifclk[1]) { 234 wm8958_micd_set_rate(component); 235 return 0; 236 } 237 238 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 239 new = WM8994_SYSCLK_SRC; 240 else 241 new = 0; 242 243 change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 244 WM8994_SYSCLK_SRC, new); 245 if (change) 246 snd_soc_dapm_sync(dapm); 247 248 wm8958_micd_set_rate(component); 249 250 return 0; 251 } 252 253 static int check_clk_sys(struct snd_soc_dapm_widget *source, 254 struct snd_soc_dapm_widget *sink) 255 { 256 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); 257 int reg = snd_soc_component_read(component, WM8994_CLOCKING_1); 258 const char *clk; 259 260 /* Check what we're currently using for CLK_SYS */ 261 if (reg & WM8994_SYSCLK_SRC) 262 clk = "AIF2CLK"; 263 else 264 clk = "AIF1CLK"; 265 266 return snd_soc_dapm_widget_name_cmp(source, clk) == 0; 267 } 268 269 static const char *sidetone_hpf_text[] = { 270 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 271 }; 272 273 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 274 WM8994_SIDETONE, 7, sidetone_hpf_text); 275 276 static const char *adc_hpf_text[] = { 277 "HiFi", "Voice 1", "Voice 2", "Voice 3" 278 }; 279 280 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf, 281 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text); 282 283 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf, 284 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text); 285 286 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf, 287 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text); 288 289 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 290 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 291 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 292 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 293 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 294 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); 295 296 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 297 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \ 298 snd_soc_get_volsw, wm8994_put_drc_sw) 299 300 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 301 struct snd_ctl_elem_value *ucontrol) 302 { 303 struct soc_mixer_control *mc = 304 (struct soc_mixer_control *)kcontrol->private_value; 305 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 306 int mask, ret; 307 308 /* Can't enable both ADC and DAC paths simultaneously */ 309 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 310 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 311 WM8994_AIF1ADC1R_DRC_ENA_MASK; 312 else 313 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 314 315 ret = snd_soc_component_read(component, mc->reg); 316 if (ret < 0) 317 return ret; 318 if (ret & mask) 319 return -EINVAL; 320 321 return snd_soc_put_volsw(kcontrol, ucontrol); 322 } 323 324 static void wm8994_set_drc(struct snd_soc_component *component, int drc) 325 { 326 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 327 struct wm8994 *control = wm8994->wm8994; 328 struct wm8994_pdata *pdata = &control->pdata; 329 int base = wm8994_drc_base[drc]; 330 int cfg = wm8994->drc_cfg[drc]; 331 int save, i; 332 333 /* Save any enables; the configuration should clear them. */ 334 save = snd_soc_component_read(component, base); 335 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 336 WM8994_AIF1ADC1R_DRC_ENA; 337 338 for (i = 0; i < WM8994_DRC_REGS; i++) 339 snd_soc_component_update_bits(component, base + i, 0xffff, 340 pdata->drc_cfgs[cfg].regs[i]); 341 342 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA | 343 WM8994_AIF1ADC1L_DRC_ENA | 344 WM8994_AIF1ADC1R_DRC_ENA, save); 345 } 346 347 /* Icky as hell but saves code duplication */ 348 static int wm8994_get_drc(const char *name) 349 { 350 if (strcmp(name, "AIF1DRC1 Mode") == 0) 351 return 0; 352 if (strcmp(name, "AIF1DRC2 Mode") == 0) 353 return 1; 354 if (strcmp(name, "AIF2DRC Mode") == 0) 355 return 2; 356 return -EINVAL; 357 } 358 359 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 360 struct snd_ctl_elem_value *ucontrol) 361 { 362 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 363 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 364 struct wm8994 *control = wm8994->wm8994; 365 struct wm8994_pdata *pdata = &control->pdata; 366 int drc = wm8994_get_drc(kcontrol->id.name); 367 int value = ucontrol->value.enumerated.item[0]; 368 369 if (drc < 0) 370 return drc; 371 372 if (value >= pdata->num_drc_cfgs) 373 return -EINVAL; 374 375 wm8994->drc_cfg[drc] = value; 376 377 wm8994_set_drc(component, drc); 378 379 return 0; 380 } 381 382 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 383 struct snd_ctl_elem_value *ucontrol) 384 { 385 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 386 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 387 int drc = wm8994_get_drc(kcontrol->id.name); 388 389 if (drc < 0) 390 return drc; 391 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 392 393 return 0; 394 } 395 396 static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block) 397 { 398 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 399 struct wm8994 *control = wm8994->wm8994; 400 struct wm8994_pdata *pdata = &control->pdata; 401 int base = wm8994_retune_mobile_base[block]; 402 int iface, best, best_val, save, i, cfg; 403 404 if (!pdata || !wm8994->num_retune_mobile_texts) 405 return; 406 407 switch (block) { 408 case 0: 409 case 1: 410 iface = 0; 411 break; 412 case 2: 413 iface = 1; 414 break; 415 default: 416 return; 417 } 418 419 /* Find the version of the currently selected configuration 420 * with the nearest sample rate. */ 421 cfg = wm8994->retune_mobile_cfg[block]; 422 best = 0; 423 best_val = INT_MAX; 424 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 425 if (strcmp(pdata->retune_mobile_cfgs[i].name, 426 wm8994->retune_mobile_texts[cfg]) == 0 && 427 abs(pdata->retune_mobile_cfgs[i].rate 428 - wm8994->dac_rates[iface]) < best_val) { 429 best = i; 430 best_val = abs(pdata->retune_mobile_cfgs[i].rate 431 - wm8994->dac_rates[iface]); 432 } 433 } 434 435 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 436 block, 437 pdata->retune_mobile_cfgs[best].name, 438 pdata->retune_mobile_cfgs[best].rate, 439 wm8994->dac_rates[iface]); 440 441 /* The EQ will be disabled while reconfiguring it, remember the 442 * current configuration. 443 */ 444 save = snd_soc_component_read(component, base); 445 save &= WM8994_AIF1DAC1_EQ_ENA; 446 447 for (i = 0; i < WM8994_EQ_REGS; i++) 448 snd_soc_component_update_bits(component, base + i, 0xffff, 449 pdata->retune_mobile_cfgs[best].regs[i]); 450 451 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save); 452 } 453 454 /* Icky as hell but saves code duplication */ 455 static int wm8994_get_retune_mobile_block(const char *name) 456 { 457 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 458 return 0; 459 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 460 return 1; 461 if (strcmp(name, "AIF2 EQ Mode") == 0) 462 return 2; 463 return -EINVAL; 464 } 465 466 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 467 struct snd_ctl_elem_value *ucontrol) 468 { 469 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 470 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 471 struct wm8994 *control = wm8994->wm8994; 472 struct wm8994_pdata *pdata = &control->pdata; 473 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 474 int value = ucontrol->value.enumerated.item[0]; 475 476 if (block < 0) 477 return block; 478 479 if (value >= pdata->num_retune_mobile_cfgs) 480 return -EINVAL; 481 482 wm8994->retune_mobile_cfg[block] = value; 483 484 wm8994_set_retune_mobile(component, block); 485 486 return 0; 487 } 488 489 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 490 struct snd_ctl_elem_value *ucontrol) 491 { 492 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 493 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 494 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 495 496 if (block < 0) 497 return block; 498 499 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 500 501 return 0; 502 } 503 504 static const char *aif_chan_src_text[] = { 505 "Left", "Right" 506 }; 507 508 static SOC_ENUM_SINGLE_DECL(aif1adcl_src, 509 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text); 510 511 static SOC_ENUM_SINGLE_DECL(aif1adcr_src, 512 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text); 513 514 static SOC_ENUM_SINGLE_DECL(aif2adcl_src, 515 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text); 516 517 static SOC_ENUM_SINGLE_DECL(aif2adcr_src, 518 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text); 519 520 static SOC_ENUM_SINGLE_DECL(aif1dacl_src, 521 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text); 522 523 static SOC_ENUM_SINGLE_DECL(aif1dacr_src, 524 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text); 525 526 static SOC_ENUM_SINGLE_DECL(aif2dacl_src, 527 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text); 528 529 static SOC_ENUM_SINGLE_DECL(aif2dacr_src, 530 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text); 531 532 static const char *osr_text[] = { 533 "Low Power", "High Performance", 534 }; 535 536 static SOC_ENUM_SINGLE_DECL(dac_osr, 537 WM8994_OVERSAMPLING, 0, osr_text); 538 539 static SOC_ENUM_SINGLE_DECL(adc_osr, 540 WM8994_OVERSAMPLING, 1, osr_text); 541 542 static const struct snd_kcontrol_new wm8994_common_snd_controls[] = { 543 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 544 WM8994_AIF1_ADC1_RIGHT_VOLUME, 545 1, 119, 0, digital_tlv), 546 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 547 WM8994_AIF2_ADC_RIGHT_VOLUME, 548 1, 119, 0, digital_tlv), 549 550 SOC_ENUM("AIF1ADCL Source", aif1adcl_src), 551 SOC_ENUM("AIF1ADCR Source", aif1adcr_src), 552 SOC_ENUM("AIF2ADCL Source", aif2adcl_src), 553 SOC_ENUM("AIF2ADCR Source", aif2adcr_src), 554 555 SOC_ENUM("AIF1DACL Source", aif1dacl_src), 556 SOC_ENUM("AIF1DACR Source", aif1dacr_src), 557 SOC_ENUM("AIF2DACL Source", aif2dacl_src), 558 SOC_ENUM("AIF2DACR Source", aif2dacr_src), 559 560 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 561 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 562 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 563 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 564 565 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 566 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 567 568 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 569 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 570 571 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 572 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 573 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 574 575 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 576 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 577 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 578 579 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 580 5, 12, 0, st_tlv), 581 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 582 0, 12, 0, st_tlv), 583 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 584 5, 12, 0, st_tlv), 585 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 586 0, 12, 0, st_tlv), 587 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 588 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 589 590 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), 591 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), 592 593 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), 594 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), 595 596 SOC_ENUM("ADC OSR", adc_osr), 597 SOC_ENUM("DAC OSR", dac_osr), 598 599 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 600 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 601 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 602 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 603 604 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 605 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 606 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 607 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 608 609 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 610 6, 1, 1, wm_hubs_spkmix_tlv), 611 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 612 2, 1, 1, wm_hubs_spkmix_tlv), 613 614 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 615 6, 1, 1, wm_hubs_spkmix_tlv), 616 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 617 2, 1, 1, wm_hubs_spkmix_tlv), 618 619 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 620 10, 15, 0, wm8994_3d_tlv), 621 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, 622 8, 1, 0), 623 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 624 10, 15, 0, wm8994_3d_tlv), 625 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 626 8, 1, 0), 627 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, 628 10, 15, 0, wm8994_3d_tlv), 629 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, 630 8, 1, 0), 631 }; 632 633 /* Controls not available on WM1811 */ 634 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 635 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 636 WM8994_AIF1_ADC2_RIGHT_VOLUME, 637 1, 119, 0, digital_tlv), 638 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 639 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 640 641 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 642 643 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 644 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 645 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 646 647 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), 648 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), 649 }; 650 651 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 652 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 653 eq_tlv), 654 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 655 eq_tlv), 656 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 657 eq_tlv), 658 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 659 eq_tlv), 660 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 661 eq_tlv), 662 663 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 664 eq_tlv), 665 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 666 eq_tlv), 667 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 668 eq_tlv), 669 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 670 eq_tlv), 671 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 672 eq_tlv), 673 674 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 675 eq_tlv), 676 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 677 eq_tlv), 678 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 679 eq_tlv), 680 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 681 eq_tlv), 682 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 683 eq_tlv), 684 }; 685 686 static const struct snd_kcontrol_new wm8994_drc_controls[] = { 687 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, 688 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 689 WM8994_AIF1ADC1R_DRC_ENA), 690 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, 691 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | 692 WM8994_AIF1ADC2R_DRC_ENA), 693 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, 694 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | 695 WM8994_AIF2ADCR_DRC_ENA), 696 }; 697 698 static const char *wm8958_ng_text[] = { 699 "30ms", "125ms", "250ms", "500ms", 700 }; 701 702 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold, 703 WM8958_AIF1_DAC1_NOISE_GATE, 704 WM8958_AIF1DAC1_NG_THR_SHIFT, 705 wm8958_ng_text); 706 707 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold, 708 WM8958_AIF1_DAC2_NOISE_GATE, 709 WM8958_AIF1DAC2_NG_THR_SHIFT, 710 wm8958_ng_text); 711 712 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold, 713 WM8958_AIF2_DAC_NOISE_GATE, 714 WM8958_AIF2DAC_NG_THR_SHIFT, 715 wm8958_ng_text); 716 717 static const struct snd_kcontrol_new wm8958_snd_controls[] = { 718 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), 719 720 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, 721 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), 722 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), 723 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", 724 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, 725 7, 1, ng_tlv), 726 727 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, 728 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), 729 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), 730 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", 731 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, 732 7, 1, ng_tlv), 733 734 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, 735 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), 736 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), 737 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", 738 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, 739 7, 1, ng_tlv), 740 }; 741 742 /* We run all mode setting through a function to enforce audio mode */ 743 static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode) 744 { 745 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 746 747 if (!wm8994->jackdet || !wm8994->micdet[0].jack) 748 return; 749 750 if (wm8994->active_refcount) 751 mode = WM1811_JACKDET_MODE_AUDIO; 752 753 if (mode == wm8994->jackdet_mode) 754 return; 755 756 wm8994->jackdet_mode = mode; 757 758 /* Always use audio mode to detect while the system is active */ 759 if (mode != WM1811_JACKDET_MODE_NONE) 760 mode = WM1811_JACKDET_MODE_AUDIO; 761 762 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 763 WM1811_JACKDET_MODE_MASK, mode); 764 } 765 766 static void active_reference(struct snd_soc_component *component) 767 { 768 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 769 770 guard(mutex)(&wm8994->accdet_lock); 771 772 wm8994->active_refcount++; 773 774 dev_dbg(component->dev, "Active refcount incremented, now %d\n", 775 wm8994->active_refcount); 776 777 /* If we're using jack detection go into audio mode */ 778 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO); 779 } 780 781 static void active_dereference(struct snd_soc_component *component) 782 { 783 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 784 u16 mode; 785 786 guard(mutex)(&wm8994->accdet_lock); 787 788 wm8994->active_refcount--; 789 790 dev_dbg(component->dev, "Active refcount decremented, now %d\n", 791 wm8994->active_refcount); 792 793 if (wm8994->active_refcount == 0) { 794 /* Go into appropriate detection only mode */ 795 if (wm8994->jack_mic || wm8994->mic_detecting) 796 mode = WM1811_JACKDET_MODE_MIC; 797 else 798 mode = WM1811_JACKDET_MODE_JACK; 799 800 wm1811_jackdet_set_mode(component, mode); 801 } 802 } 803 804 static int clk_sys_event(struct snd_soc_dapm_widget *w, 805 struct snd_kcontrol *kcontrol, int event) 806 { 807 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 808 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 809 810 switch (event) { 811 case SND_SOC_DAPM_PRE_PMU: 812 return configure_clock(component); 813 814 case SND_SOC_DAPM_POST_PMU: 815 /* 816 * JACKDET won't run until we start the clock and it 817 * only reports deltas, make sure we notify the state 818 * up the stack on startup. Use a *very* generous 819 * timeout for paranoia, there's no urgency and we 820 * don't want false reports. 821 */ 822 if (wm8994->jackdet && !wm8994->clk_has_run) { 823 queue_delayed_work(system_power_efficient_wq, 824 &wm8994->jackdet_bootstrap, 825 msecs_to_jiffies(1000)); 826 wm8994->clk_has_run = true; 827 } 828 break; 829 830 case SND_SOC_DAPM_POST_PMD: 831 configure_clock(component); 832 break; 833 } 834 835 return 0; 836 } 837 838 static void vmid_reference(struct snd_soc_component *component) 839 { 840 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 841 842 pm_runtime_get_sync(component->dev); 843 844 wm8994->vmid_refcount++; 845 846 dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n", 847 wm8994->vmid_refcount); 848 849 if (wm8994->vmid_refcount == 1) { 850 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 851 WM8994_LINEOUT1_DISCH | 852 WM8994_LINEOUT2_DISCH, 0); 853 854 wm_hubs_vmid_ena(component); 855 856 switch (wm8994->vmid_mode) { 857 default: 858 WARN_ON(NULL == "Invalid VMID mode"); 859 fallthrough; 860 case WM8994_VMID_NORMAL: 861 /* Startup bias, VMID ramp & buffer */ 862 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 863 WM8994_BIAS_SRC | 864 WM8994_VMID_DISCH | 865 WM8994_STARTUP_BIAS_ENA | 866 WM8994_VMID_BUF_ENA | 867 WM8994_VMID_RAMP_MASK, 868 WM8994_BIAS_SRC | 869 WM8994_STARTUP_BIAS_ENA | 870 WM8994_VMID_BUF_ENA | 871 (0x2 << WM8994_VMID_RAMP_SHIFT)); 872 873 /* Main bias enable, VMID=2x40k */ 874 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 875 WM8994_BIAS_ENA | 876 WM8994_VMID_SEL_MASK, 877 WM8994_BIAS_ENA | 0x2); 878 879 msleep(300); 880 881 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 882 WM8994_VMID_RAMP_MASK | 883 WM8994_BIAS_SRC, 884 0); 885 break; 886 887 case WM8994_VMID_FORCE: 888 /* Startup bias, slow VMID ramp & buffer */ 889 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 890 WM8994_BIAS_SRC | 891 WM8994_VMID_DISCH | 892 WM8994_STARTUP_BIAS_ENA | 893 WM8994_VMID_BUF_ENA | 894 WM8994_VMID_RAMP_MASK, 895 WM8994_BIAS_SRC | 896 WM8994_STARTUP_BIAS_ENA | 897 WM8994_VMID_BUF_ENA | 898 (0x2 << WM8994_VMID_RAMP_SHIFT)); 899 900 /* Main bias enable, VMID=2x40k */ 901 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 902 WM8994_BIAS_ENA | 903 WM8994_VMID_SEL_MASK, 904 WM8994_BIAS_ENA | 0x2); 905 906 msleep(400); 907 908 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 909 WM8994_VMID_RAMP_MASK | 910 WM8994_BIAS_SRC, 911 0); 912 break; 913 } 914 } 915 } 916 917 static void vmid_dereference(struct snd_soc_component *component) 918 { 919 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 920 921 wm8994->vmid_refcount--; 922 923 dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n", 924 wm8994->vmid_refcount); 925 926 if (wm8994->vmid_refcount == 0) { 927 if (wm8994->hubs.lineout1_se) 928 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 929 WM8994_LINEOUT1N_ENA | 930 WM8994_LINEOUT1P_ENA, 931 WM8994_LINEOUT1N_ENA | 932 WM8994_LINEOUT1P_ENA); 933 934 if (wm8994->hubs.lineout2_se) 935 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 936 WM8994_LINEOUT2N_ENA | 937 WM8994_LINEOUT2P_ENA, 938 WM8994_LINEOUT2N_ENA | 939 WM8994_LINEOUT2P_ENA); 940 941 /* Start discharging VMID */ 942 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 943 WM8994_BIAS_SRC | 944 WM8994_VMID_DISCH, 945 WM8994_BIAS_SRC | 946 WM8994_VMID_DISCH); 947 948 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 949 WM8994_VMID_SEL_MASK, 0); 950 951 msleep(400); 952 953 /* Active discharge */ 954 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 955 WM8994_LINEOUT1_DISCH | 956 WM8994_LINEOUT2_DISCH, 957 WM8994_LINEOUT1_DISCH | 958 WM8994_LINEOUT2_DISCH); 959 960 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3, 961 WM8994_LINEOUT1N_ENA | 962 WM8994_LINEOUT1P_ENA | 963 WM8994_LINEOUT2N_ENA | 964 WM8994_LINEOUT2P_ENA, 0); 965 966 /* Switch off startup biases */ 967 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2, 968 WM8994_BIAS_SRC | 969 WM8994_STARTUP_BIAS_ENA | 970 WM8994_VMID_BUF_ENA | 971 WM8994_VMID_RAMP_MASK, 0); 972 973 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1, 974 WM8994_VMID_SEL_MASK, 0); 975 } 976 977 pm_runtime_put(component->dev); 978 } 979 980 static int vmid_event(struct snd_soc_dapm_widget *w, 981 struct snd_kcontrol *kcontrol, int event) 982 { 983 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 984 985 switch (event) { 986 case SND_SOC_DAPM_PRE_PMU: 987 vmid_reference(component); 988 break; 989 990 case SND_SOC_DAPM_POST_PMD: 991 vmid_dereference(component); 992 break; 993 } 994 995 return 0; 996 } 997 998 static bool wm8994_check_class_w_digital(struct snd_soc_component *component) 999 { 1000 int source = 0; /* GCC flow analysis can't track enable */ 1001 int reg, reg_r; 1002 1003 /* We also need the same AIF source for L/R and only one path */ 1004 reg = snd_soc_component_read(component, WM8994_DAC1_LEFT_MIXER_ROUTING); 1005 switch (reg) { 1006 case WM8994_AIF2DACL_TO_DAC1L: 1007 dev_vdbg(component->dev, "Class W source AIF2DAC\n"); 1008 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1009 break; 1010 case WM8994_AIF1DAC2L_TO_DAC1L: 1011 dev_vdbg(component->dev, "Class W source AIF1DAC2\n"); 1012 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1013 break; 1014 case WM8994_AIF1DAC1L_TO_DAC1L: 1015 dev_vdbg(component->dev, "Class W source AIF1DAC1\n"); 1016 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 1017 break; 1018 default: 1019 dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg); 1020 return false; 1021 } 1022 1023 reg_r = snd_soc_component_read(component, WM8994_DAC1_RIGHT_MIXER_ROUTING); 1024 if (reg_r != reg) { 1025 dev_vdbg(component->dev, "Left and right DAC mixers different\n"); 1026 return false; 1027 } 1028 1029 /* Set the source up */ 1030 snd_soc_component_update_bits(component, WM8994_CLASS_W_1, 1031 WM8994_CP_DYN_SRC_SEL_MASK, source); 1032 1033 return true; 1034 } 1035 1036 static void wm8994_update_vu_bits(struct snd_soc_component *component) 1037 { 1038 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1039 struct wm8994 *control = wm8994->wm8994; 1040 int i; 1041 1042 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 1043 snd_soc_component_write(component, wm8994_vu_bits[i].reg, 1044 snd_soc_component_read(component, 1045 wm8994_vu_bits[i].reg)); 1046 if (control->type == WM1811) 1047 return; 1048 1049 for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++) 1050 snd_soc_component_write(component, 1051 wm8994_adc2_dac2_vu_bits[i].reg, 1052 snd_soc_component_read(component, 1053 wm8994_adc2_dac2_vu_bits[i].reg)); 1054 } 1055 1056 static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable) 1057 { 1058 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1059 unsigned int offset, val, clk_idx; 1060 int ret; 1061 1062 if (aif) 1063 offset = 4; 1064 else 1065 offset = 0; 1066 1067 val = snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1 + offset); 1068 val &= WM8994_AIF1CLK_SRC_MASK; 1069 1070 switch (val) { 1071 case 0: 1072 clk_idx = WM8994_MCLK1; 1073 break; 1074 case 1: 1075 clk_idx = WM8994_MCLK2; 1076 break; 1077 default: 1078 return 0; 1079 } 1080 1081 if (enable) { 1082 ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk); 1083 if (ret < 0) { 1084 dev_err(component->dev, "Failed to enable MCLK%d\n", 1085 clk_idx); 1086 return ret; 1087 } 1088 } else { 1089 clk_disable_unprepare(wm8994->mclk[clk_idx].clk); 1090 } 1091 1092 return 0; 1093 } 1094 1095 static int aif1clk_ev(struct snd_soc_dapm_widget *w, 1096 struct snd_kcontrol *kcontrol, int event) 1097 { 1098 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1099 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1100 struct wm8994 *control = wm8994->wm8994; 1101 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; 1102 int ret; 1103 int dac; 1104 int adc; 1105 int val; 1106 1107 switch (control->type) { 1108 case WM8994: 1109 case WM8958: 1110 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; 1111 break; 1112 default: 1113 break; 1114 } 1115 1116 switch (event) { 1117 case SND_SOC_DAPM_PRE_PMU: 1118 ret = aif_mclk_set(component, 0, true); 1119 if (ret < 0) 1120 return ret; 1121 1122 /* Don't enable timeslot 2 if not in use */ 1123 if (wm8994->channels[0] <= 2) 1124 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); 1125 1126 val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_1); 1127 if ((val & WM8994_AIF1ADCL_SRC) && 1128 (val & WM8994_AIF1ADCR_SRC)) 1129 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; 1130 else if (!(val & WM8994_AIF1ADCL_SRC) && 1131 !(val & WM8994_AIF1ADCR_SRC)) 1132 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1133 else 1134 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | 1135 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; 1136 1137 val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_2); 1138 if ((val & WM8994_AIF1DACL_SRC) && 1139 (val & WM8994_AIF1DACR_SRC)) 1140 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; 1141 else if (!(val & WM8994_AIF1DACL_SRC) && 1142 !(val & WM8994_AIF1DACR_SRC)) 1143 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1144 else 1145 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | 1146 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; 1147 1148 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1149 mask, adc); 1150 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1151 mask, dac); 1152 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1153 WM8994_AIF1DSPCLK_ENA | 1154 WM8994_SYSDSPCLK_ENA, 1155 WM8994_AIF1DSPCLK_ENA | 1156 WM8994_SYSDSPCLK_ENA); 1157 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask, 1158 WM8994_AIF1ADC1R_ENA | 1159 WM8994_AIF1ADC1L_ENA | 1160 WM8994_AIF1ADC2R_ENA | 1161 WM8994_AIF1ADC2L_ENA); 1162 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask, 1163 WM8994_AIF1DAC1R_ENA | 1164 WM8994_AIF1DAC1L_ENA | 1165 WM8994_AIF1DAC2R_ENA | 1166 WM8994_AIF1DAC2L_ENA); 1167 break; 1168 1169 case SND_SOC_DAPM_POST_PMU: 1170 wm8994_update_vu_bits(component); 1171 break; 1172 1173 case SND_SOC_DAPM_PRE_PMD: 1174 case SND_SOC_DAPM_POST_PMD: 1175 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1176 mask, 0); 1177 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1178 mask, 0); 1179 1180 val = snd_soc_component_read(component, WM8994_CLOCKING_1); 1181 if (val & WM8994_AIF2DSPCLK_ENA) 1182 val = WM8994_SYSDSPCLK_ENA; 1183 else 1184 val = 0; 1185 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1186 WM8994_SYSDSPCLK_ENA | 1187 WM8994_AIF1DSPCLK_ENA, val); 1188 break; 1189 } 1190 1191 switch (event) { 1192 case SND_SOC_DAPM_POST_PMD: 1193 aif_mclk_set(component, 0, false); 1194 break; 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int aif2clk_ev(struct snd_soc_dapm_widget *w, 1201 struct snd_kcontrol *kcontrol, int event) 1202 { 1203 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1204 int ret; 1205 int dac; 1206 int adc; 1207 int val; 1208 1209 switch (event) { 1210 case SND_SOC_DAPM_PRE_PMU: 1211 ret = aif_mclk_set(component, 1, true); 1212 if (ret < 0) 1213 return ret; 1214 1215 val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_1); 1216 if ((val & WM8994_AIF2ADCL_SRC) && 1217 (val & WM8994_AIF2ADCR_SRC)) 1218 adc = WM8994_AIF2ADCR_ENA; 1219 else if (!(val & WM8994_AIF2ADCL_SRC) && 1220 !(val & WM8994_AIF2ADCR_SRC)) 1221 adc = WM8994_AIF2ADCL_ENA; 1222 else 1223 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; 1224 1225 1226 val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_2); 1227 if ((val & WM8994_AIF2DACL_SRC) && 1228 (val & WM8994_AIF2DACR_SRC)) 1229 dac = WM8994_AIF2DACR_ENA; 1230 else if (!(val & WM8994_AIF2DACL_SRC) && 1231 !(val & WM8994_AIF2DACR_SRC)) 1232 dac = WM8994_AIF2DACL_ENA; 1233 else 1234 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; 1235 1236 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1237 WM8994_AIF2ADCL_ENA | 1238 WM8994_AIF2ADCR_ENA, adc); 1239 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1240 WM8994_AIF2DACL_ENA | 1241 WM8994_AIF2DACR_ENA, dac); 1242 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1243 WM8994_AIF2DSPCLK_ENA | 1244 WM8994_SYSDSPCLK_ENA, 1245 WM8994_AIF2DSPCLK_ENA | 1246 WM8994_SYSDSPCLK_ENA); 1247 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1248 WM8994_AIF2ADCL_ENA | 1249 WM8994_AIF2ADCR_ENA, 1250 WM8994_AIF2ADCL_ENA | 1251 WM8994_AIF2ADCR_ENA); 1252 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1253 WM8994_AIF2DACL_ENA | 1254 WM8994_AIF2DACR_ENA, 1255 WM8994_AIF2DACL_ENA | 1256 WM8994_AIF2DACR_ENA); 1257 break; 1258 1259 case SND_SOC_DAPM_POST_PMU: 1260 wm8994_update_vu_bits(component); 1261 break; 1262 1263 case SND_SOC_DAPM_PRE_PMD: 1264 case SND_SOC_DAPM_POST_PMD: 1265 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1266 WM8994_AIF2DACL_ENA | 1267 WM8994_AIF2DACR_ENA, 0); 1268 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, 1269 WM8994_AIF2ADCL_ENA | 1270 WM8994_AIF2ADCR_ENA, 0); 1271 1272 val = snd_soc_component_read(component, WM8994_CLOCKING_1); 1273 if (val & WM8994_AIF1DSPCLK_ENA) 1274 val = WM8994_SYSDSPCLK_ENA; 1275 else 1276 val = 0; 1277 snd_soc_component_update_bits(component, WM8994_CLOCKING_1, 1278 WM8994_SYSDSPCLK_ENA | 1279 WM8994_AIF2DSPCLK_ENA, val); 1280 break; 1281 } 1282 1283 switch (event) { 1284 case SND_SOC_DAPM_POST_PMD: 1285 aif_mclk_set(component, 1, false); 1286 break; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, 1293 struct snd_kcontrol *kcontrol, int event) 1294 { 1295 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1296 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1297 1298 switch (event) { 1299 case SND_SOC_DAPM_PRE_PMU: 1300 wm8994->aif1clk_enable = 1; 1301 break; 1302 case SND_SOC_DAPM_POST_PMD: 1303 wm8994->aif1clk_disable = 1; 1304 break; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, 1311 struct snd_kcontrol *kcontrol, int event) 1312 { 1313 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1314 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1315 1316 switch (event) { 1317 case SND_SOC_DAPM_PRE_PMU: 1318 wm8994->aif2clk_enable = 1; 1319 break; 1320 case SND_SOC_DAPM_POST_PMD: 1321 wm8994->aif2clk_disable = 1; 1322 break; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static int late_enable_ev(struct snd_soc_dapm_widget *w, 1329 struct snd_kcontrol *kcontrol, int event) 1330 { 1331 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1332 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1333 1334 switch (event) { 1335 case SND_SOC_DAPM_PRE_PMU: 1336 if (wm8994->aif1clk_enable) { 1337 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1338 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1, 1339 WM8994_AIF1CLK_ENA_MASK, 1340 WM8994_AIF1CLK_ENA); 1341 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1342 wm8994->aif1clk_enable = 0; 1343 } 1344 if (wm8994->aif2clk_enable) { 1345 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); 1346 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1, 1347 WM8994_AIF2CLK_ENA_MASK, 1348 WM8994_AIF2CLK_ENA); 1349 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); 1350 wm8994->aif2clk_enable = 0; 1351 } 1352 break; 1353 } 1354 1355 /* We may also have postponed startup of DSP, handle that. */ 1356 wm8958_aif_ev(w, kcontrol, event); 1357 1358 return 0; 1359 } 1360 1361 static int late_disable_ev(struct snd_soc_dapm_widget *w, 1362 struct snd_kcontrol *kcontrol, int event) 1363 { 1364 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1365 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 1366 1367 switch (event) { 1368 case SND_SOC_DAPM_POST_PMD: 1369 if (wm8994->aif1clk_disable) { 1370 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1371 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1, 1372 WM8994_AIF1CLK_ENA_MASK, 0); 1373 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1374 wm8994->aif1clk_disable = 0; 1375 } 1376 if (wm8994->aif2clk_disable) { 1377 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); 1378 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1, 1379 WM8994_AIF2CLK_ENA_MASK, 0); 1380 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); 1381 wm8994->aif2clk_disable = 0; 1382 } 1383 break; 1384 } 1385 1386 return 0; 1387 } 1388 1389 static int adc_mux_ev(struct snd_soc_dapm_widget *w, 1390 struct snd_kcontrol *kcontrol, int event) 1391 { 1392 late_enable_ev(w, kcontrol, event); 1393 return 0; 1394 } 1395 1396 static int micbias_ev(struct snd_soc_dapm_widget *w, 1397 struct snd_kcontrol *kcontrol, int event) 1398 { 1399 late_enable_ev(w, kcontrol, event); 1400 return 0; 1401 } 1402 1403 static int dac_ev(struct snd_soc_dapm_widget *w, 1404 struct snd_kcontrol *kcontrol, int event) 1405 { 1406 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1407 unsigned int mask = 1 << w->shift; 1408 1409 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, 1410 mask, mask); 1411 return 0; 1412 } 1413 1414 static const char *adc_mux_text[] = { 1415 "ADC", 1416 "DMIC", 1417 }; 1418 1419 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 1420 1421 static const struct snd_kcontrol_new adcl_mux = 1422 SOC_DAPM_ENUM("ADCL Mux", adc_enum); 1423 1424 static const struct snd_kcontrol_new adcr_mux = 1425 SOC_DAPM_ENUM("ADCR Mux", adc_enum); 1426 1427 static const struct snd_kcontrol_new left_speaker_mixer[] = { 1428 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1429 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 1430 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 1431 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 1432 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 1433 }; 1434 1435 static const struct snd_kcontrol_new right_speaker_mixer[] = { 1436 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 1437 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 1438 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 1439 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 1440 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 1441 }; 1442 1443 /* Debugging; dump chip status after DAPM transitions */ 1444 static int post_ev(struct snd_soc_dapm_widget *w, 1445 struct snd_kcontrol *kcontrol, int event) 1446 { 1447 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1448 dev_dbg(component->dev, "SRC status: %x\n", 1449 snd_soc_component_read(component, 1450 WM8994_RATE_STATUS)); 1451 return 0; 1452 } 1453 1454 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 1455 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1456 1, 1, 0), 1457 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 1458 0, 1, 0), 1459 }; 1460 1461 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 1462 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1463 1, 1, 0), 1464 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 1465 0, 1, 0), 1466 }; 1467 1468 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 1469 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1470 1, 1, 0), 1471 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, 1472 0, 1, 0), 1473 }; 1474 1475 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 1476 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1477 1, 1, 0), 1478 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, 1479 0, 1, 0), 1480 }; 1481 1482 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 1483 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1484 5, 1, 0), 1485 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1486 4, 1, 0), 1487 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1488 2, 1, 0), 1489 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1490 1, 1, 0), 1491 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 1492 0, 1, 0), 1493 }; 1494 1495 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 1496 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1497 5, 1, 0), 1498 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1499 4, 1, 0), 1500 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1501 2, 1, 0), 1502 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1503 1, 1, 0), 1504 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 1505 0, 1, 0), 1506 }; 1507 1508 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 1509 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 1510 snd_soc_dapm_get_volsw, wm8994_put_class_w) 1511 1512 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 1513 struct snd_ctl_elem_value *ucontrol) 1514 { 1515 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 1516 int ret; 1517 1518 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1519 1520 wm_hubs_update_class_w(component); 1521 1522 return ret; 1523 } 1524 1525 static const struct snd_kcontrol_new dac1l_mix[] = { 1526 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1527 5, 1, 0), 1528 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1529 4, 1, 0), 1530 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1531 2, 1, 0), 1532 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1533 1, 1, 0), 1534 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 1535 0, 1, 0), 1536 }; 1537 1538 static const struct snd_kcontrol_new dac1r_mix[] = { 1539 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1540 5, 1, 0), 1541 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1542 4, 1, 0), 1543 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1544 2, 1, 0), 1545 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1546 1, 1, 0), 1547 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 1548 0, 1, 0), 1549 }; 1550 1551 static const char *sidetone_text[] = { 1552 "ADC/DMIC1", "DMIC2", 1553 }; 1554 1555 static SOC_ENUM_SINGLE_DECL(sidetone1_enum, 1556 WM8994_SIDETONE, 0, sidetone_text); 1557 1558 static const struct snd_kcontrol_new sidetone1_mux = 1559 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 1560 1561 static SOC_ENUM_SINGLE_DECL(sidetone2_enum, 1562 WM8994_SIDETONE, 1, sidetone_text); 1563 1564 static const struct snd_kcontrol_new sidetone2_mux = 1565 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 1566 1567 static const char *aif1dac_text[] = { 1568 "AIF1DACDAT", "AIF3DACDAT", 1569 }; 1570 1571 static const char *loopback_text[] = { 1572 "None", "ADCDAT", 1573 }; 1574 1575 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum, 1576 WM8994_AIF1_CONTROL_2, 1577 WM8994_AIF1_LOOPBACK_SHIFT, 1578 loopback_text); 1579 1580 static const struct snd_kcontrol_new aif1_loopback = 1581 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum); 1582 1583 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum, 1584 WM8994_AIF2_CONTROL_2, 1585 WM8994_AIF2_LOOPBACK_SHIFT, 1586 loopback_text); 1587 1588 static const struct snd_kcontrol_new aif2_loopback = 1589 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum); 1590 1591 static SOC_ENUM_SINGLE_DECL(aif1dac_enum, 1592 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text); 1593 1594 static const struct snd_kcontrol_new aif1dac_mux = 1595 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 1596 1597 static const char *aif2dac_text[] = { 1598 "AIF2DACDAT", "AIF3DACDAT", 1599 }; 1600 1601 static SOC_ENUM_SINGLE_DECL(aif2dac_enum, 1602 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text); 1603 1604 static const struct snd_kcontrol_new aif2dac_mux = 1605 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 1606 1607 static const char *aif2adc_text[] = { 1608 "AIF2ADCDAT", "AIF3DACDAT", 1609 }; 1610 1611 static SOC_ENUM_SINGLE_DECL(aif2adc_enum, 1612 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text); 1613 1614 static const struct snd_kcontrol_new aif2adc_mux = 1615 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1616 1617 static const char *aif3adc_text[] = { 1618 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", 1619 }; 1620 1621 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum, 1622 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1623 1624 static const struct snd_kcontrol_new wm8994_aif3adc_mux = 1625 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); 1626 1627 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum, 1628 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text); 1629 1630 static const struct snd_kcontrol_new wm8958_aif3adc_mux = 1631 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1632 1633 static const char *mono_pcm_out_text[] = { 1634 "None", "AIF2ADCL", "AIF2ADCR", 1635 }; 1636 1637 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum, 1638 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text); 1639 1640 static const struct snd_kcontrol_new mono_pcm_out_mux = 1641 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); 1642 1643 static const char *aif2dac_src_text[] = { 1644 "AIF2", "AIF3", 1645 }; 1646 1647 /* Note that these two control shouldn't be simultaneously switched to AIF3 */ 1648 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum, 1649 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text); 1650 1651 static const struct snd_kcontrol_new aif2dacl_src_mux = 1652 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); 1653 1654 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum, 1655 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text); 1656 1657 static const struct snd_kcontrol_new aif2dacr_src_mux = 1658 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); 1659 1660 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { 1661 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, 1662 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1663 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, 1664 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1665 1666 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1667 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1668 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1669 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1670 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1671 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1672 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1673 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1674 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, 1675 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1676 1677 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1678 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), 1679 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1680 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1681 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1682 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1683 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, 1684 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1685 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, 1686 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1687 1688 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1689 }; 1690 1691 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { 1692 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, 1693 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1694 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1695 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, 1696 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1697 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1698 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), 1699 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 1700 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1701 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1702 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1703 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), 1704 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), 1705 }; 1706 1707 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1708 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, 1709 dac_ev, SND_SOC_DAPM_PRE_PMU), 1710 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, 1711 dac_ev, SND_SOC_DAPM_PRE_PMU), 1712 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, 1713 dac_ev, SND_SOC_DAPM_PRE_PMU), 1714 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, 1715 dac_ev, SND_SOC_DAPM_PRE_PMU), 1716 }; 1717 1718 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { 1719 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 1720 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 1721 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 1722 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 1723 }; 1724 1725 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1726 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1727 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1728 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1729 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1730 }; 1731 1732 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1733 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1734 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1735 }; 1736 1737 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1738 SND_SOC_DAPM_INPUT("DMIC1DAT"), 1739 SND_SOC_DAPM_INPUT("DMIC2DAT"), 1740 SND_SOC_DAPM_INPUT("Clock"), 1741 1742 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, 1743 SND_SOC_DAPM_PRE_PMU), 1744 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, 1745 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1746 1747 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 1748 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1749 SND_SOC_DAPM_PRE_PMD), 1750 1751 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), 1752 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), 1753 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), 1754 1755 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, 1756 0, SND_SOC_NOPM, 9, 0), 1757 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, 1758 0, SND_SOC_NOPM, 8, 0), 1759 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, 1760 SND_SOC_NOPM, 9, 0, wm8958_aif_ev, 1761 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1762 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, 1763 SND_SOC_NOPM, 8, 0, wm8958_aif_ev, 1764 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1765 1766 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, 1767 0, SND_SOC_NOPM, 11, 0), 1768 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, 1769 0, SND_SOC_NOPM, 10, 0), 1770 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, 1771 SND_SOC_NOPM, 11, 0, wm8958_aif_ev, 1772 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1773 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, 1774 SND_SOC_NOPM, 10, 0, wm8958_aif_ev, 1775 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1776 1777 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1778 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1779 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 1780 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 1781 1782 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 1783 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 1784 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 1785 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 1786 1787 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 1788 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 1789 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 1790 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 1791 1792 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1793 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1794 1795 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 1796 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 1797 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 1798 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 1799 1800 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 1801 SND_SOC_NOPM, 13, 0), 1802 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1803 SND_SOC_NOPM, 12, 0), 1804 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, 1805 SND_SOC_NOPM, 13, 0, wm8958_aif_ev, 1806 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1807 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, 1808 SND_SOC_NOPM, 12, 0, wm8958_aif_ev, 1809 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1810 1811 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1812 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1813 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1814 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1815 1816 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1817 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1818 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1819 1820 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1821 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), 1822 1823 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 1824 1825 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 1826 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 1827 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 1828 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 1829 1830 /* Power is done with the muxes since the ADC power also controls the 1831 * downsampling chain, the chip will automatically manage the analogue 1832 * specific portions. 1833 */ 1834 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 1835 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1836 1837 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback), 1838 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback), 1839 1840 SND_SOC_DAPM_POST("Debug log", post_ev), 1841 }; 1842 1843 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { 1844 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), 1845 }; 1846 1847 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1848 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), 1849 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1850 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1851 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1852 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), 1853 }; 1854 1855 static const struct snd_soc_dapm_route intercon[] = { 1856 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1857 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1858 1859 { "DSP1CLK", NULL, "CLK_SYS" }, 1860 { "DSP2CLK", NULL, "CLK_SYS" }, 1861 { "DSPINTCLK", NULL, "CLK_SYS" }, 1862 1863 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1864 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1865 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1866 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1867 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 1868 1869 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1870 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1871 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1872 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1873 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 1874 1875 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1876 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1877 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1878 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1879 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 1880 1881 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1882 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1883 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1884 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1885 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 1886 1887 { "AIF2ADCL", NULL, "AIF2CLK" }, 1888 { "AIF2ADCL", NULL, "DSP2CLK" }, 1889 { "AIF2ADCR", NULL, "AIF2CLK" }, 1890 { "AIF2ADCR", NULL, "DSP2CLK" }, 1891 { "AIF2ADCR", NULL, "DSPINTCLK" }, 1892 1893 { "AIF2DACL", NULL, "AIF2CLK" }, 1894 { "AIF2DACL", NULL, "DSP2CLK" }, 1895 { "AIF2DACR", NULL, "AIF2CLK" }, 1896 { "AIF2DACR", NULL, "DSP2CLK" }, 1897 { "AIF2DACR", NULL, "DSPINTCLK" }, 1898 1899 { "DMIC1L", NULL, "DMIC1DAT" }, 1900 { "DMIC1L", NULL, "CLK_SYS" }, 1901 { "DMIC1R", NULL, "DMIC1DAT" }, 1902 { "DMIC1R", NULL, "CLK_SYS" }, 1903 { "DMIC2L", NULL, "DMIC2DAT" }, 1904 { "DMIC2L", NULL, "CLK_SYS" }, 1905 { "DMIC2R", NULL, "DMIC2DAT" }, 1906 { "DMIC2R", NULL, "CLK_SYS" }, 1907 1908 { "ADCL", NULL, "AIF1CLK" }, 1909 { "ADCL", NULL, "DSP1CLK" }, 1910 { "ADCL", NULL, "DSPINTCLK" }, 1911 1912 { "ADCR", NULL, "AIF1CLK" }, 1913 { "ADCR", NULL, "DSP1CLK" }, 1914 { "ADCR", NULL, "DSPINTCLK" }, 1915 1916 { "ADCL Mux", "ADC", "ADCL" }, 1917 { "ADCL Mux", "DMIC", "DMIC1L" }, 1918 { "ADCR Mux", "ADC", "ADCR" }, 1919 { "ADCR Mux", "DMIC", "DMIC1R" }, 1920 1921 { "DAC1L", NULL, "AIF1CLK" }, 1922 { "DAC1L", NULL, "DSP1CLK" }, 1923 { "DAC1L", NULL, "DSPINTCLK" }, 1924 1925 { "DAC1R", NULL, "AIF1CLK" }, 1926 { "DAC1R", NULL, "DSP1CLK" }, 1927 { "DAC1R", NULL, "DSPINTCLK" }, 1928 1929 { "DAC2L", NULL, "AIF2CLK" }, 1930 { "DAC2L", NULL, "DSP2CLK" }, 1931 { "DAC2L", NULL, "DSPINTCLK" }, 1932 1933 { "DAC2R", NULL, "AIF2DACR" }, 1934 { "DAC2R", NULL, "AIF2CLK" }, 1935 { "DAC2R", NULL, "DSP2CLK" }, 1936 { "DAC2R", NULL, "DSPINTCLK" }, 1937 1938 { "TOCLK", NULL, "CLK_SYS" }, 1939 1940 { "AIF1DACDAT", NULL, "AIF1 Playback" }, 1941 { "AIF2DACDAT", NULL, "AIF2 Playback" }, 1942 { "AIF3DACDAT", NULL, "AIF3 Playback" }, 1943 1944 { "AIF1 Capture", NULL, "AIF1ADCDAT" }, 1945 { "AIF2 Capture", NULL, "AIF2ADCDAT" }, 1946 { "AIF3 Capture", NULL, "AIF3ADCDAT" }, 1947 1948 /* AIF1 outputs */ 1949 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1950 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1951 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1952 1953 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1954 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1955 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1956 1957 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1958 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1959 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1960 1961 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1962 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1963 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 1964 1965 /* Pin level routing for AIF3 */ 1966 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 1967 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 1968 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1969 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1970 1971 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" }, 1972 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1973 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" }, 1974 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1975 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 1976 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 1977 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 1978 1979 /* DAC1 inputs */ 1980 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 1981 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1982 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1983 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1984 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1985 1986 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 1987 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1988 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1989 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1990 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1991 1992 /* DAC2/AIF2 outputs */ 1993 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 1994 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 1995 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1996 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1997 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1998 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1999 2000 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 2001 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 2002 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 2003 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 2004 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 2005 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 2006 2007 { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, 2008 { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, 2009 { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, 2010 { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, 2011 2012 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 2013 2014 /* AIF3 output */ 2015 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" }, 2016 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" }, 2017 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" }, 2018 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" }, 2019 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 2020 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 2021 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" }, 2022 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" }, 2023 2024 { "AIF3ADCDAT", NULL, "AIF3ADC Mux" }, 2025 2026 /* Loopback */ 2027 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" }, 2028 { "AIF1 Loopback", "None", "AIF1DACDAT" }, 2029 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" }, 2030 { "AIF2 Loopback", "None", "AIF2DACDAT" }, 2031 2032 /* Sidetone */ 2033 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 2034 { "Left Sidetone", "DMIC2", "DMIC2L" }, 2035 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 2036 { "Right Sidetone", "DMIC2", "DMIC2R" }, 2037 2038 /* Output stages */ 2039 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 2040 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 2041 2042 { "SPKL", "DAC1 Switch", "DAC1L" }, 2043 { "SPKL", "DAC2 Switch", "DAC2L" }, 2044 2045 { "SPKR", "DAC1 Switch", "DAC1R" }, 2046 { "SPKR", "DAC2 Switch", "DAC2R" }, 2047 2048 { "Left Headphone Mux", "DAC", "DAC1L" }, 2049 { "Right Headphone Mux", "DAC", "DAC1R" }, 2050 }; 2051 2052 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { 2053 { "DAC1L", NULL, "Late DAC1L Enable PGA" }, 2054 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, 2055 { "DAC1R", NULL, "Late DAC1R Enable PGA" }, 2056 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, 2057 { "DAC2L", NULL, "Late DAC2L Enable PGA" }, 2058 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, 2059 { "DAC2R", NULL, "Late DAC2R Enable PGA" }, 2060 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } 2061 }; 2062 2063 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { 2064 { "DAC1L", NULL, "DAC1L Mixer" }, 2065 { "DAC1R", NULL, "DAC1R Mixer" }, 2066 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 2067 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 2068 }; 2069 2070 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { 2071 { "AIF1DACDAT", NULL, "AIF2DACDAT" }, 2072 { "AIF2DACDAT", NULL, "AIF1DACDAT" }, 2073 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, 2074 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, 2075 { "MICBIAS1", NULL, "CLK_SYS" }, 2076 { "MICBIAS1", NULL, "MICBIAS Supply" }, 2077 { "MICBIAS2", NULL, "CLK_SYS" }, 2078 { "MICBIAS2", NULL, "MICBIAS Supply" }, 2079 }; 2080 2081 static const struct snd_soc_dapm_route wm8994_intercon[] = { 2082 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 2083 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 2084 { "MICBIAS1", NULL, "VMID" }, 2085 { "MICBIAS2", NULL, "VMID" }, 2086 }; 2087 2088 static const struct snd_soc_dapm_route wm8958_intercon[] = { 2089 { "AIF2DACL", NULL, "AIF2DACL Mux" }, 2090 { "AIF2DACR", NULL, "AIF2DACR Mux" }, 2091 2092 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, 2093 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, 2094 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 2095 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 2096 2097 { "AIF3DACDAT", NULL, "AIF3" }, 2098 { "AIF3ADCDAT", NULL, "AIF3" }, 2099 2100 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 2101 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 2102 2103 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, 2104 }; 2105 2106 /* The size in bits of the FLL divide multiplied by 10 2107 * to allow rounding later */ 2108 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2109 2110 struct fll_div { 2111 u16 outdiv; 2112 u16 n; 2113 u16 k; 2114 u16 lambda; 2115 u16 clk_ref_div; 2116 u16 fll_fratio; 2117 }; 2118 2119 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll, 2120 int freq_in, int freq_out) 2121 { 2122 u64 Kpart; 2123 unsigned int K, Ndiv, Nmod, gcd_fll; 2124 2125 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2126 2127 /* Scale the input frequency down to <= 13.5MHz */ 2128 fll->clk_ref_div = 0; 2129 while (freq_in > 13500000) { 2130 fll->clk_ref_div++; 2131 freq_in /= 2; 2132 2133 if (fll->clk_ref_div > 3) 2134 return -EINVAL; 2135 } 2136 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2137 2138 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2139 fll->outdiv = 3; 2140 while (freq_out * (fll->outdiv + 1) < 90000000) { 2141 fll->outdiv++; 2142 if (fll->outdiv > 63) 2143 return -EINVAL; 2144 } 2145 freq_out *= fll->outdiv + 1; 2146 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2147 2148 if (freq_in > 1000000) { 2149 fll->fll_fratio = 0; 2150 } else if (freq_in > 256000) { 2151 fll->fll_fratio = 1; 2152 freq_in *= 2; 2153 } else if (freq_in > 128000) { 2154 fll->fll_fratio = 2; 2155 freq_in *= 4; 2156 } else if (freq_in > 64000) { 2157 fll->fll_fratio = 3; 2158 freq_in *= 8; 2159 } else { 2160 fll->fll_fratio = 4; 2161 freq_in *= 16; 2162 } 2163 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2164 2165 /* Now, calculate N.K */ 2166 Ndiv = freq_out / freq_in; 2167 2168 fll->n = Ndiv; 2169 Nmod = freq_out % freq_in; 2170 pr_debug("Nmod=%d\n", Nmod); 2171 2172 switch (control->type) { 2173 case WM8994: 2174 /* Calculate fractional part - scale up so we can round. */ 2175 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2176 2177 do_div(Kpart, freq_in); 2178 2179 K = Kpart & 0xFFFFFFFF; 2180 2181 if ((K % 10) >= 5) 2182 K += 5; 2183 2184 /* Move down to proper range now rounding is done */ 2185 fll->k = K / 10; 2186 fll->lambda = 0; 2187 2188 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2189 break; 2190 2191 default: 2192 gcd_fll = gcd(freq_out, freq_in); 2193 2194 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll; 2195 fll->lambda = freq_in / gcd_fll; 2196 2197 } 2198 2199 return 0; 2200 } 2201 2202 static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, 2203 unsigned int freq_in, unsigned int freq_out) 2204 { 2205 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2206 struct wm8994 *control = wm8994->wm8994; 2207 int reg_offset, ret; 2208 struct fll_div fll; 2209 u16 reg, clk1, aif_reg, aif_src; 2210 unsigned long time_left; 2211 bool was_enabled; 2212 struct clk *mclk; 2213 2214 switch (id) { 2215 case WM8994_FLL1: 2216 reg_offset = 0; 2217 id = 0; 2218 aif_src = 0x10; 2219 break; 2220 case WM8994_FLL2: 2221 reg_offset = 0x20; 2222 id = 1; 2223 aif_src = 0x18; 2224 break; 2225 default: 2226 return -EINVAL; 2227 } 2228 2229 reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset); 2230 was_enabled = reg & WM8994_FLL1_ENA; 2231 2232 switch (src) { 2233 case 0: 2234 /* Allow no source specification when stopping */ 2235 if (freq_out) 2236 return -EINVAL; 2237 src = wm8994->fll[id].src; 2238 break; 2239 case WM8994_FLL_SRC_MCLK1: 2240 case WM8994_FLL_SRC_MCLK2: 2241 case WM8994_FLL_SRC_LRCLK: 2242 case WM8994_FLL_SRC_BCLK: 2243 break; 2244 case WM8994_FLL_SRC_INTERNAL: 2245 freq_in = 12000000; 2246 freq_out = 12000000; 2247 break; 2248 default: 2249 return -EINVAL; 2250 } 2251 2252 /* Are we changing anything? */ 2253 if (wm8994->fll[id].src == src && 2254 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2255 return 0; 2256 2257 /* If we're stopping the FLL redo the old config - no 2258 * registers will actually be written but we avoid GCC flow 2259 * analysis bugs spewing warnings. 2260 */ 2261 if (freq_out) 2262 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out); 2263 else 2264 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in, 2265 wm8994->fll[id].out); 2266 if (ret < 0) 2267 return ret; 2268 2269 /* Make sure that we're not providing SYSCLK right now */ 2270 clk1 = snd_soc_component_read(component, WM8994_CLOCKING_1); 2271 if (clk1 & WM8994_SYSCLK_SRC) 2272 aif_reg = WM8994_AIF2_CLOCKING_1; 2273 else 2274 aif_reg = WM8994_AIF1_CLOCKING_1; 2275 reg = snd_soc_component_read(component, aif_reg); 2276 2277 if ((reg & WM8994_AIF1CLK_ENA) && 2278 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { 2279 dev_err(component->dev, "FLL%d is currently providing SYSCLK\n", 2280 id + 1); 2281 return -EBUSY; 2282 } 2283 2284 /* We always need to disable the FLL while reconfiguring */ 2285 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, 2286 WM8994_FLL1_ENA, 0); 2287 2288 /* Disable MCLK if needed before we possibly change to new clock parent */ 2289 if (was_enabled) { 2290 reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_5 2291 + reg_offset); 2292 reg = ((reg & WM8994_FLL1_REFCLK_SRC_MASK) 2293 >> WM8994_FLL1_REFCLK_SRC_SHIFT) + 1; 2294 2295 switch (reg) { 2296 case WM8994_FLL_SRC_MCLK1: 2297 mclk = wm8994->mclk[WM8994_MCLK1].clk; 2298 break; 2299 case WM8994_FLL_SRC_MCLK2: 2300 mclk = wm8994->mclk[WM8994_MCLK2].clk; 2301 break; 2302 default: 2303 mclk = NULL; 2304 } 2305 2306 clk_disable_unprepare(mclk); 2307 } 2308 2309 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && 2310 freq_in == freq_out && freq_out) { 2311 dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1); 2312 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, 2313 WM8958_FLL1_BYP, WM8958_FLL1_BYP); 2314 goto out; 2315 } 2316 2317 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2318 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2319 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset, 2320 WM8994_FLL1_OUTDIV_MASK | 2321 WM8994_FLL1_FRATIO_MASK, reg); 2322 2323 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset, 2324 WM8994_FLL1_K_MASK, fll.k); 2325 2326 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset, 2327 WM8994_FLL1_N_MASK, 2328 fll.n << WM8994_FLL1_N_SHIFT); 2329 2330 if (fll.lambda) { 2331 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset, 2332 WM8958_FLL1_LAMBDA_MASK, 2333 fll.lambda); 2334 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, 2335 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA); 2336 } else { 2337 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset, 2338 WM8958_FLL1_EFS_ENA, 0); 2339 } 2340 2341 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset, 2342 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | 2343 WM8994_FLL1_REFCLK_DIV_MASK | 2344 WM8994_FLL1_REFCLK_SRC_MASK, 2345 ((src == WM8994_FLL_SRC_INTERNAL) 2346 << WM8994_FLL1_FRC_NCO_SHIFT) | 2347 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2348 (src - 1)); 2349 2350 /* Clear any pending completion from a previous failure */ 2351 try_wait_for_completion(&wm8994->fll_locked[id]); 2352 2353 switch (src) { 2354 case WM8994_FLL_SRC_MCLK1: 2355 mclk = wm8994->mclk[WM8994_MCLK1].clk; 2356 break; 2357 case WM8994_FLL_SRC_MCLK2: 2358 mclk = wm8994->mclk[WM8994_MCLK2].clk; 2359 break; 2360 default: 2361 mclk = NULL; 2362 } 2363 2364 /* Enable (with fractional mode if required) */ 2365 if (freq_out) { 2366 ret = clk_prepare_enable(mclk); 2367 if (ret < 0) { 2368 dev_err(component->dev, "Failed to enable MCLK for FLL%d\n", 2369 id + 1); 2370 return ret; 2371 } 2372 2373 /* Enable VMID if we need it */ 2374 if (!was_enabled) { 2375 2376 active_reference(component); 2377 2378 switch (control->type) { 2379 case WM8994: 2380 vmid_reference(component); 2381 break; 2382 case WM8958: 2383 if (control->revision < 1) 2384 vmid_reference(component); 2385 break; 2386 default: 2387 break; 2388 } 2389 } 2390 2391 reg = WM8994_FLL1_ENA; 2392 2393 if (fll.k) 2394 reg |= WM8994_FLL1_FRAC; 2395 if (src == WM8994_FLL_SRC_INTERNAL) 2396 reg |= WM8994_FLL1_OSC_ENA; 2397 2398 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset, 2399 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | 2400 WM8994_FLL1_FRAC, reg); 2401 2402 if (wm8994->fll_locked_irq) { 2403 time_left = wait_for_completion_timeout(&wm8994->fll_locked[id], 2404 msecs_to_jiffies(10)); 2405 if (time_left == 0) 2406 dev_warn(component->dev, 2407 "Timed out waiting for FLL lock\n"); 2408 } else { 2409 msleep(5); 2410 } 2411 } else { 2412 if (was_enabled) { 2413 switch (control->type) { 2414 case WM8994: 2415 vmid_dereference(component); 2416 break; 2417 case WM8958: 2418 if (control->revision < 1) 2419 vmid_dereference(component); 2420 break; 2421 default: 2422 break; 2423 } 2424 2425 active_dereference(component); 2426 } 2427 } 2428 2429 out: 2430 wm8994->fll[id].in = freq_in; 2431 wm8994->fll[id].out = freq_out; 2432 wm8994->fll[id].src = src; 2433 2434 configure_clock(component); 2435 2436 /* 2437 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2438 * for detection. 2439 */ 2440 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2441 dev_dbg(component->dev, "Configuring AIFs for 128fs\n"); 2442 2443 wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE) 2444 & WM8994_AIF1CLK_RATE_MASK; 2445 wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE) 2446 & WM8994_AIF1CLK_RATE_MASK; 2447 2448 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2449 WM8994_AIF1CLK_RATE_MASK, 0x1); 2450 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2451 WM8994_AIF2CLK_RATE_MASK, 0x1); 2452 } else if (wm8994->aifdiv[0]) { 2453 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2454 WM8994_AIF1CLK_RATE_MASK, 2455 wm8994->aifdiv[0]); 2456 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2457 WM8994_AIF2CLK_RATE_MASK, 2458 wm8994->aifdiv[1]); 2459 2460 wm8994->aifdiv[0] = 0; 2461 wm8994->aifdiv[1] = 0; 2462 } 2463 2464 return 0; 2465 } 2466 2467 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) 2468 { 2469 struct completion *completion = data; 2470 2471 complete(completion); 2472 2473 return IRQ_HANDLED; 2474 } 2475 2476 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; 2477 2478 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2479 unsigned int freq_in, unsigned int freq_out) 2480 { 2481 return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out); 2482 } 2483 2484 static int wm8994_set_mclk_rate(struct wm8994_priv *wm8994, unsigned int id, 2485 unsigned int *freq) 2486 { 2487 int ret; 2488 2489 if (!wm8994->mclk[id].clk || *freq == wm8994->mclk_rate[id]) 2490 return 0; 2491 2492 ret = clk_set_rate(wm8994->mclk[id].clk, *freq); 2493 if (ret < 0) 2494 return ret; 2495 2496 *freq = clk_get_rate(wm8994->mclk[id].clk); 2497 2498 return 0; 2499 } 2500 2501 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2502 int clk_id, unsigned int freq, int dir) 2503 { 2504 struct snd_soc_component *component = dai->component; 2505 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2506 int ret, i; 2507 2508 switch (dai->id) { 2509 case 1: 2510 case 2: 2511 break; 2512 2513 default: 2514 /* AIF3 shares clocking with AIF1/2 */ 2515 return -EINVAL; 2516 } 2517 2518 switch (clk_id) { 2519 case WM8994_SYSCLK_MCLK1: 2520 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2521 2522 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq); 2523 if (ret < 0) 2524 return ret; 2525 2526 wm8994->mclk_rate[0] = freq; 2527 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2528 dai->id, freq); 2529 break; 2530 2531 case WM8994_SYSCLK_MCLK2: 2532 /* TODO: Set GPIO AF */ 2533 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2534 2535 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq); 2536 if (ret < 0) 2537 return ret; 2538 2539 wm8994->mclk_rate[1] = freq; 2540 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2541 dai->id, freq); 2542 break; 2543 2544 case WM8994_SYSCLK_FLL1: 2545 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2546 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2547 break; 2548 2549 case WM8994_SYSCLK_FLL2: 2550 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2551 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2552 break; 2553 2554 case WM8994_SYSCLK_OPCLK: 2555 /* Special case - a division (times 10) is given and 2556 * no effect on main clocking. 2557 */ 2558 if (freq) { 2559 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2560 if (opclk_divs[i] == freq) 2561 break; 2562 if (i == ARRAY_SIZE(opclk_divs)) 2563 return -EINVAL; 2564 snd_soc_component_update_bits(component, WM8994_CLOCKING_2, 2565 WM8994_OPCLK_DIV_MASK, i); 2566 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2, 2567 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); 2568 } else { 2569 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2, 2570 WM8994_OPCLK_ENA, 0); 2571 } 2572 break; 2573 2574 default: 2575 return -EINVAL; 2576 } 2577 2578 configure_clock(component); 2579 2580 /* 2581 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers 2582 * for detection. 2583 */ 2584 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { 2585 dev_dbg(component->dev, "Configuring AIFs for 128fs\n"); 2586 2587 wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE) 2588 & WM8994_AIF1CLK_RATE_MASK; 2589 wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE) 2590 & WM8994_AIF1CLK_RATE_MASK; 2591 2592 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2593 WM8994_AIF1CLK_RATE_MASK, 0x1); 2594 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2595 WM8994_AIF2CLK_RATE_MASK, 0x1); 2596 } else if (wm8994->aifdiv[0]) { 2597 snd_soc_component_update_bits(component, WM8994_AIF1_RATE, 2598 WM8994_AIF1CLK_RATE_MASK, 2599 wm8994->aifdiv[0]); 2600 snd_soc_component_update_bits(component, WM8994_AIF2_RATE, 2601 WM8994_AIF2CLK_RATE_MASK, 2602 wm8994->aifdiv[1]); 2603 2604 wm8994->aifdiv[0] = 0; 2605 wm8994->aifdiv[1] = 0; 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int wm8994_set_bias_level(struct snd_soc_component *component, 2612 enum snd_soc_bias_level level) 2613 { 2614 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2615 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2616 struct wm8994 *control = wm8994->wm8994; 2617 2618 wm_hubs_set_bias_level(component, level); 2619 2620 switch (level) { 2621 case SND_SOC_BIAS_ON: 2622 break; 2623 2624 case SND_SOC_BIAS_PREPARE: 2625 /* MICBIAS into regulating mode */ 2626 switch (control->type) { 2627 case WM8958: 2628 case WM1811: 2629 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 2630 WM8958_MICB1_MODE, 0); 2631 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 2632 WM8958_MICB2_MODE, 0); 2633 break; 2634 default: 2635 break; 2636 } 2637 2638 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_STANDBY) 2639 active_reference(component); 2640 break; 2641 2642 case SND_SOC_BIAS_STANDBY: 2643 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 2644 switch (control->type) { 2645 case WM8958: 2646 if (control->revision == 0) { 2647 /* Optimise performance for rev A */ 2648 snd_soc_component_update_bits(component, 2649 WM8958_CHARGE_PUMP_2, 2650 WM8958_CP_DISCH, 2651 WM8958_CP_DISCH); 2652 } 2653 break; 2654 2655 default: 2656 break; 2657 } 2658 2659 /* Discharge LINEOUT1 & 2 */ 2660 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1, 2661 WM8994_LINEOUT1_DISCH | 2662 WM8994_LINEOUT2_DISCH, 2663 WM8994_LINEOUT1_DISCH | 2664 WM8994_LINEOUT2_DISCH); 2665 } 2666 2667 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_PREPARE) 2668 active_dereference(component); 2669 2670 /* MICBIAS into bypass mode on newer devices */ 2671 switch (control->type) { 2672 case WM8958: 2673 case WM1811: 2674 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 2675 WM8958_MICB1_MODE, 2676 WM8958_MICB1_MODE); 2677 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 2678 WM8958_MICB2_MODE, 2679 WM8958_MICB2_MODE); 2680 break; 2681 default: 2682 break; 2683 } 2684 break; 2685 2686 case SND_SOC_BIAS_OFF: 2687 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_STANDBY) 2688 wm8994->cur_fw = NULL; 2689 break; 2690 } 2691 2692 return 0; 2693 } 2694 2695 int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode) 2696 { 2697 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2698 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2699 2700 switch (mode) { 2701 case WM8994_VMID_NORMAL: 2702 snd_soc_dapm_mutex_lock(dapm); 2703 2704 if (wm8994->hubs.lineout1_se) { 2705 snd_soc_dapm_disable_pin_unlocked(dapm, 2706 "LINEOUT1N Driver"); 2707 snd_soc_dapm_disable_pin_unlocked(dapm, 2708 "LINEOUT1P Driver"); 2709 } 2710 if (wm8994->hubs.lineout2_se) { 2711 snd_soc_dapm_disable_pin_unlocked(dapm, 2712 "LINEOUT2N Driver"); 2713 snd_soc_dapm_disable_pin_unlocked(dapm, 2714 "LINEOUT2P Driver"); 2715 } 2716 2717 /* Do the sync with the old mode to allow it to clean up */ 2718 snd_soc_dapm_sync_unlocked(dapm); 2719 wm8994->vmid_mode = mode; 2720 2721 snd_soc_dapm_mutex_unlock(dapm); 2722 break; 2723 2724 case WM8994_VMID_FORCE: 2725 snd_soc_dapm_mutex_lock(dapm); 2726 2727 if (wm8994->hubs.lineout1_se) { 2728 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2729 "LINEOUT1N Driver"); 2730 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2731 "LINEOUT1P Driver"); 2732 } 2733 if (wm8994->hubs.lineout2_se) { 2734 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2735 "LINEOUT2N Driver"); 2736 snd_soc_dapm_force_enable_pin_unlocked(dapm, 2737 "LINEOUT2P Driver"); 2738 } 2739 2740 wm8994->vmid_mode = mode; 2741 snd_soc_dapm_sync_unlocked(dapm); 2742 2743 snd_soc_dapm_mutex_unlock(dapm); 2744 break; 2745 2746 default: 2747 return -EINVAL; 2748 } 2749 2750 return 0; 2751 } 2752 2753 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2754 { 2755 struct snd_soc_component *component = dai->component; 2756 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2757 struct wm8994 *control = wm8994->wm8994; 2758 int ms_reg; 2759 int aif1_reg; 2760 int dac_reg; 2761 int adc_reg; 2762 int ms = 0; 2763 int aif1 = 0; 2764 int lrclk = 0; 2765 2766 switch (dai->id) { 2767 case 1: 2768 ms_reg = WM8994_AIF1_MASTER_SLAVE; 2769 aif1_reg = WM8994_AIF1_CONTROL_1; 2770 dac_reg = WM8994_AIF1DAC_LRCLK; 2771 adc_reg = WM8994_AIF1ADC_LRCLK; 2772 break; 2773 case 2: 2774 ms_reg = WM8994_AIF2_MASTER_SLAVE; 2775 aif1_reg = WM8994_AIF2_CONTROL_1; 2776 dac_reg = WM8994_AIF1DAC_LRCLK; 2777 adc_reg = WM8994_AIF1ADC_LRCLK; 2778 break; 2779 default: 2780 return -EINVAL; 2781 } 2782 2783 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2784 case SND_SOC_DAIFMT_CBC_CFC: 2785 break; 2786 case SND_SOC_DAIFMT_CBP_CFP: 2787 ms = WM8994_AIF1_MSTR; 2788 break; 2789 default: 2790 return -EINVAL; 2791 } 2792 2793 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2794 case SND_SOC_DAIFMT_DSP_B: 2795 aif1 |= WM8994_AIF1_LRCLK_INV; 2796 lrclk |= WM8958_AIF1_LRCLK_INV; 2797 fallthrough; 2798 case SND_SOC_DAIFMT_DSP_A: 2799 aif1 |= 0x18; 2800 break; 2801 case SND_SOC_DAIFMT_I2S: 2802 aif1 |= 0x10; 2803 break; 2804 case SND_SOC_DAIFMT_RIGHT_J: 2805 break; 2806 case SND_SOC_DAIFMT_LEFT_J: 2807 aif1 |= 0x8; 2808 break; 2809 default: 2810 return -EINVAL; 2811 } 2812 2813 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2814 case SND_SOC_DAIFMT_DSP_A: 2815 case SND_SOC_DAIFMT_DSP_B: 2816 /* frame inversion not valid for DSP modes */ 2817 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2818 case SND_SOC_DAIFMT_NB_NF: 2819 break; 2820 case SND_SOC_DAIFMT_IB_NF: 2821 aif1 |= WM8994_AIF1_BCLK_INV; 2822 break; 2823 default: 2824 return -EINVAL; 2825 } 2826 break; 2827 2828 case SND_SOC_DAIFMT_I2S: 2829 case SND_SOC_DAIFMT_RIGHT_J: 2830 case SND_SOC_DAIFMT_LEFT_J: 2831 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2832 case SND_SOC_DAIFMT_NB_NF: 2833 break; 2834 case SND_SOC_DAIFMT_IB_IF: 2835 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 2836 lrclk |= WM8958_AIF1_LRCLK_INV; 2837 break; 2838 case SND_SOC_DAIFMT_IB_NF: 2839 aif1 |= WM8994_AIF1_BCLK_INV; 2840 break; 2841 case SND_SOC_DAIFMT_NB_IF: 2842 aif1 |= WM8994_AIF1_LRCLK_INV; 2843 lrclk |= WM8958_AIF1_LRCLK_INV; 2844 break; 2845 default: 2846 return -EINVAL; 2847 } 2848 break; 2849 default: 2850 return -EINVAL; 2851 } 2852 2853 /* The AIF2 format configuration needs to be mirrored to AIF3 2854 * on WM8958 if it's in use so just do it all the time. */ 2855 switch (control->type) { 2856 case WM1811: 2857 case WM8958: 2858 if (dai->id == 2) 2859 snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1, 2860 WM8994_AIF1_LRCLK_INV | 2861 WM8958_AIF3_FMT_MASK, aif1); 2862 break; 2863 2864 default: 2865 break; 2866 } 2867 2868 snd_soc_component_update_bits(component, aif1_reg, 2869 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2870 WM8994_AIF1_FMT_MASK, 2871 aif1); 2872 snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR, 2873 ms); 2874 snd_soc_component_update_bits(component, dac_reg, 2875 WM8958_AIF1_LRCLK_INV, lrclk); 2876 snd_soc_component_update_bits(component, adc_reg, 2877 WM8958_AIF1_LRCLK_INV, lrclk); 2878 2879 return 0; 2880 } 2881 2882 static struct { 2883 int val, rate; 2884 } srs[] = { 2885 { 0, 8000 }, 2886 { 1, 11025 }, 2887 { 2, 12000 }, 2888 { 3, 16000 }, 2889 { 4, 22050 }, 2890 { 5, 24000 }, 2891 { 6, 32000 }, 2892 { 7, 44100 }, 2893 { 8, 48000 }, 2894 { 9, 88200 }, 2895 { 10, 96000 }, 2896 }; 2897 2898 static int fs_ratios[] = { 2899 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 2900 }; 2901 2902 static int bclk_divs[] = { 2903 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 2904 640, 880, 960, 1280, 1760, 1920 2905 }; 2906 2907 static int wm8994_hw_params(struct snd_pcm_substream *substream, 2908 struct snd_pcm_hw_params *params, 2909 struct snd_soc_dai *dai) 2910 { 2911 struct snd_soc_component *component = dai->component; 2912 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 2913 struct wm8994 *control = wm8994->wm8994; 2914 struct wm8994_pdata *pdata = &control->pdata; 2915 int aif1_reg; 2916 int aif2_reg; 2917 int bclk_reg; 2918 int lrclk_reg; 2919 int rate_reg; 2920 int aif1 = 0; 2921 int aif2 = 0; 2922 int bclk = 0; 2923 int lrclk = 0; 2924 int rate_val = 0; 2925 int id = dai->id - 1; 2926 2927 int i, cur_val, best_val, bclk_rate, best; 2928 2929 switch (dai->id) { 2930 case 1: 2931 aif1_reg = WM8994_AIF1_CONTROL_1; 2932 aif2_reg = WM8994_AIF1_CONTROL_2; 2933 bclk_reg = WM8994_AIF1_BCLK; 2934 rate_reg = WM8994_AIF1_RATE; 2935 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2936 wm8994->lrclk_shared[0]) { 2937 lrclk_reg = WM8994_AIF1DAC_LRCLK; 2938 } else { 2939 lrclk_reg = WM8994_AIF1ADC_LRCLK; 2940 dev_dbg(component->dev, "AIF1 using split LRCLK\n"); 2941 } 2942 break; 2943 case 2: 2944 aif1_reg = WM8994_AIF2_CONTROL_1; 2945 aif2_reg = WM8994_AIF2_CONTROL_2; 2946 bclk_reg = WM8994_AIF2_BCLK; 2947 rate_reg = WM8994_AIF2_RATE; 2948 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2949 wm8994->lrclk_shared[1]) { 2950 lrclk_reg = WM8994_AIF2DAC_LRCLK; 2951 } else { 2952 lrclk_reg = WM8994_AIF2ADC_LRCLK; 2953 dev_dbg(component->dev, "AIF2 using split LRCLK\n"); 2954 } 2955 break; 2956 default: 2957 return -EINVAL; 2958 } 2959 2960 bclk_rate = params_rate(params); 2961 switch (params_width(params)) { 2962 case 16: 2963 bclk_rate *= 16; 2964 break; 2965 case 20: 2966 bclk_rate *= 20; 2967 aif1 |= 0x20; 2968 break; 2969 case 24: 2970 bclk_rate *= 24; 2971 aif1 |= 0x40; 2972 break; 2973 case 32: 2974 bclk_rate *= 32; 2975 aif1 |= 0x60; 2976 break; 2977 default: 2978 return -EINVAL; 2979 } 2980 2981 wm8994->channels[id] = params_channels(params); 2982 if (pdata->max_channels_clocked[id] && 2983 wm8994->channels[id] > pdata->max_channels_clocked[id]) { 2984 dev_dbg(dai->dev, "Constraining channels to %d from %d\n", 2985 pdata->max_channels_clocked[id], wm8994->channels[id]); 2986 wm8994->channels[id] = pdata->max_channels_clocked[id]; 2987 } 2988 2989 switch (wm8994->channels[id]) { 2990 case 1: 2991 case 2: 2992 bclk_rate *= 2; 2993 break; 2994 default: 2995 bclk_rate *= 4; 2996 break; 2997 } 2998 2999 /* Try to find an appropriate sample rate; look for an exact match. */ 3000 for (i = 0; i < ARRAY_SIZE(srs); i++) 3001 if (srs[i].rate == params_rate(params)) 3002 break; 3003 if (i == ARRAY_SIZE(srs)) 3004 return -EINVAL; 3005 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 3006 3007 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 3008 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 3009 dai->id, wm8994->aifclk[id], bclk_rate); 3010 3011 if (wm8994->channels[id] == 1 && 3012 (snd_soc_component_read(component, aif1_reg) & 0x18) == 0x18) 3013 aif2 |= WM8994_AIF1_MONO; 3014 3015 if (wm8994->aifclk[id] == 0) { 3016 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 3017 return -EINVAL; 3018 } 3019 3020 /* AIFCLK/fs ratio; look for a close match in either direction */ 3021 best = 0; 3022 best_val = abs((fs_ratios[0] * params_rate(params)) 3023 - wm8994->aifclk[id]); 3024 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 3025 cur_val = abs((fs_ratios[i] * params_rate(params)) 3026 - wm8994->aifclk[id]); 3027 if (cur_val >= best_val) 3028 continue; 3029 best = i; 3030 best_val = cur_val; 3031 } 3032 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 3033 dai->id, fs_ratios[best]); 3034 rate_val |= best; 3035 3036 /* We may not get quite the right frequency if using 3037 * approximate clocks so look for the closest match that is 3038 * higher than the target (we need to ensure that there enough 3039 * BCLKs to clock out the samples). 3040 */ 3041 best = 0; 3042 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 3043 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 3044 if (cur_val < 0) /* BCLK table is sorted */ 3045 break; 3046 best = i; 3047 } 3048 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 3049 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 3050 bclk_divs[best], bclk_rate); 3051 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 3052 3053 lrclk = bclk_rate / params_rate(params); 3054 if (!lrclk) { 3055 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", 3056 bclk_rate); 3057 return -EINVAL; 3058 } 3059 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 3060 lrclk, bclk_rate / lrclk); 3061 3062 snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 3063 snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2); 3064 snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 3065 snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 3066 lrclk); 3067 snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK | 3068 WM8994_AIF1CLK_RATE_MASK, rate_val); 3069 3070 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3071 switch (dai->id) { 3072 case 1: 3073 wm8994->dac_rates[0] = params_rate(params); 3074 wm8994_set_retune_mobile(component, 0); 3075 wm8994_set_retune_mobile(component, 1); 3076 break; 3077 case 2: 3078 wm8994->dac_rates[1] = params_rate(params); 3079 wm8994_set_retune_mobile(component, 2); 3080 break; 3081 } 3082 } 3083 3084 return 0; 3085 } 3086 3087 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, 3088 struct snd_pcm_hw_params *params, 3089 struct snd_soc_dai *dai) 3090 { 3091 struct snd_soc_component *component = dai->component; 3092 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3093 struct wm8994 *control = wm8994->wm8994; 3094 int aif1_reg; 3095 int aif1 = 0; 3096 3097 switch (dai->id) { 3098 case 3: 3099 switch (control->type) { 3100 case WM1811: 3101 case WM8958: 3102 aif1_reg = WM8958_AIF3_CONTROL_1; 3103 break; 3104 default: 3105 return 0; 3106 } 3107 break; 3108 default: 3109 return 0; 3110 } 3111 3112 switch (params_width(params)) { 3113 case 16: 3114 break; 3115 case 20: 3116 aif1 |= 0x20; 3117 break; 3118 case 24: 3119 aif1 |= 0x40; 3120 break; 3121 case 32: 3122 aif1 |= 0x60; 3123 break; 3124 default: 3125 return -EINVAL; 3126 } 3127 3128 return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 3129 } 3130 3131 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute, 3132 int direction) 3133 { 3134 struct snd_soc_component *component = codec_dai->component; 3135 int mute_reg; 3136 int reg; 3137 3138 switch (codec_dai->id) { 3139 case 1: 3140 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 3141 break; 3142 case 2: 3143 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 3144 break; 3145 default: 3146 return -EINVAL; 3147 } 3148 3149 if (mute) 3150 reg = WM8994_AIF1DAC1_MUTE; 3151 else 3152 reg = 0; 3153 3154 snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 3155 3156 return 0; 3157 } 3158 3159 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 3160 { 3161 struct snd_soc_component *component = codec_dai->component; 3162 int reg, val, mask; 3163 3164 switch (codec_dai->id) { 3165 case 1: 3166 reg = WM8994_AIF1_MASTER_SLAVE; 3167 mask = WM8994_AIF1_TRI; 3168 break; 3169 case 2: 3170 reg = WM8994_AIF2_MASTER_SLAVE; 3171 mask = WM8994_AIF2_TRI; 3172 break; 3173 default: 3174 return -EINVAL; 3175 } 3176 3177 if (tristate) 3178 val = mask; 3179 else 3180 val = 0; 3181 3182 return snd_soc_component_update_bits(component, reg, mask, val); 3183 } 3184 3185 static int wm8994_aif2_probe(struct snd_soc_dai *dai) 3186 { 3187 struct snd_soc_component *component = dai->component; 3188 3189 /* Disable the pulls on the AIF if we're using it to save power. */ 3190 snd_soc_component_update_bits(component, WM8994_GPIO_3, 3191 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3192 snd_soc_component_update_bits(component, WM8994_GPIO_4, 3193 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3194 snd_soc_component_update_bits(component, WM8994_GPIO_5, 3195 WM8994_GPN_PU | WM8994_GPN_PD, 0); 3196 3197 return 0; 3198 } 3199 3200 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 3201 3202 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3203 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3204 3205 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 3206 .set_sysclk = wm8994_set_dai_sysclk, 3207 .set_fmt = wm8994_set_dai_fmt, 3208 .hw_params = wm8994_hw_params, 3209 .mute_stream = wm8994_aif_mute, 3210 .set_pll = wm8994_set_fll, 3211 .set_tristate = wm8994_set_tristate, 3212 .no_capture_mute = 1, 3213 }; 3214 3215 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 3216 .probe = wm8994_aif2_probe, 3217 .set_sysclk = wm8994_set_dai_sysclk, 3218 .set_fmt = wm8994_set_dai_fmt, 3219 .hw_params = wm8994_hw_params, 3220 .mute_stream = wm8994_aif_mute, 3221 .set_pll = wm8994_set_fll, 3222 .set_tristate = wm8994_set_tristate, 3223 .no_capture_mute = 1, 3224 }; 3225 3226 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 3227 .hw_params = wm8994_aif3_hw_params, 3228 }; 3229 3230 static struct snd_soc_dai_driver wm8994_dai[] = { 3231 { 3232 .name = "wm8994-aif1", 3233 .id = 1, 3234 .playback = { 3235 .stream_name = "AIF1 Playback", 3236 .channels_min = 1, 3237 .channels_max = 2, 3238 .rates = WM8994_RATES, 3239 .formats = WM8994_FORMATS, 3240 .sig_bits = 24, 3241 }, 3242 .capture = { 3243 .stream_name = "AIF1 Capture", 3244 .channels_min = 1, 3245 .channels_max = 2, 3246 .rates = WM8994_RATES, 3247 .formats = WM8994_FORMATS, 3248 .sig_bits = 24, 3249 }, 3250 .ops = &wm8994_aif1_dai_ops, 3251 }, 3252 { 3253 .name = "wm8994-aif2", 3254 .id = 2, 3255 .playback = { 3256 .stream_name = "AIF2 Playback", 3257 .channels_min = 1, 3258 .channels_max = 2, 3259 .rates = WM8994_RATES, 3260 .formats = WM8994_FORMATS, 3261 .sig_bits = 24, 3262 }, 3263 .capture = { 3264 .stream_name = "AIF2 Capture", 3265 .channels_min = 1, 3266 .channels_max = 2, 3267 .rates = WM8994_RATES, 3268 .formats = WM8994_FORMATS, 3269 .sig_bits = 24, 3270 }, 3271 .ops = &wm8994_aif2_dai_ops, 3272 }, 3273 { 3274 .name = "wm8994-aif3", 3275 .id = 3, 3276 .playback = { 3277 .stream_name = "AIF3 Playback", 3278 .channels_min = 1, 3279 .channels_max = 2, 3280 .rates = WM8994_RATES, 3281 .formats = WM8994_FORMATS, 3282 .sig_bits = 24, 3283 }, 3284 .capture = { 3285 .stream_name = "AIF3 Capture", 3286 .channels_min = 1, 3287 .channels_max = 2, 3288 .rates = WM8994_RATES, 3289 .formats = WM8994_FORMATS, 3290 .sig_bits = 24, 3291 }, 3292 .ops = &wm8994_aif3_dai_ops, 3293 } 3294 }; 3295 3296 #ifdef CONFIG_PM 3297 static int wm8994_component_suspend(struct snd_soc_component *component) 3298 { 3299 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3300 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3301 int i, ret; 3302 3303 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3304 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3305 sizeof(struct wm8994_fll_config)); 3306 ret = _wm8994_set_fll(component, i + 1, 0, 0, 0); 3307 if (ret < 0) 3308 dev_warn(component->dev, "Failed to stop FLL%d: %d\n", 3309 i + 1, ret); 3310 } 3311 3312 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF); 3313 3314 return 0; 3315 } 3316 3317 static int wm8994_component_resume(struct snd_soc_component *component) 3318 { 3319 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3320 int i, ret; 3321 3322 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3323 if (!wm8994->fll_suspend[i].out) 3324 continue; 3325 3326 ret = _wm8994_set_fll(component, i + 1, 3327 wm8994->fll_suspend[i].src, 3328 wm8994->fll_suspend[i].in, 3329 wm8994->fll_suspend[i].out); 3330 if (ret < 0) 3331 dev_warn(component->dev, "Failed to restore FLL%d: %d\n", 3332 i + 1, ret); 3333 } 3334 3335 return 0; 3336 } 3337 #else 3338 #define wm8994_component_suspend NULL 3339 #define wm8994_component_resume NULL 3340 #endif 3341 3342 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3343 { 3344 struct snd_soc_component *component = wm8994->hubs.component; 3345 struct wm8994 *control = wm8994->wm8994; 3346 struct wm8994_pdata *pdata = &control->pdata; 3347 struct snd_kcontrol_new controls[] = { 3348 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3349 wm8994->retune_mobile_enum, 3350 wm8994_get_retune_mobile_enum, 3351 wm8994_put_retune_mobile_enum), 3352 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3353 wm8994->retune_mobile_enum, 3354 wm8994_get_retune_mobile_enum, 3355 wm8994_put_retune_mobile_enum), 3356 SOC_ENUM_EXT("AIF2 EQ Mode", 3357 wm8994->retune_mobile_enum, 3358 wm8994_get_retune_mobile_enum, 3359 wm8994_put_retune_mobile_enum), 3360 }; 3361 int ret, i, j; 3362 const char **t; 3363 3364 /* We need an array of texts for the enum API but the number 3365 * of texts is likely to be less than the number of 3366 * configurations due to the sample rate dependency of the 3367 * configurations. */ 3368 wm8994->num_retune_mobile_texts = 0; 3369 wm8994->retune_mobile_texts = NULL; 3370 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3371 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3372 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3373 wm8994->retune_mobile_texts[j]) == 0) 3374 break; 3375 } 3376 3377 if (j != wm8994->num_retune_mobile_texts) 3378 continue; 3379 3380 /* Expand the array... */ 3381 t = krealloc(wm8994->retune_mobile_texts, 3382 sizeof(char *) * 3383 (wm8994->num_retune_mobile_texts + 1), 3384 GFP_KERNEL); 3385 if (t == NULL) 3386 continue; 3387 3388 /* ...store the new entry... */ 3389 t[wm8994->num_retune_mobile_texts] = 3390 pdata->retune_mobile_cfgs[i].name; 3391 3392 /* ...and remember the new version. */ 3393 wm8994->num_retune_mobile_texts++; 3394 wm8994->retune_mobile_texts = t; 3395 } 3396 3397 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", 3398 wm8994->num_retune_mobile_texts); 3399 3400 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts; 3401 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3402 3403 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls, 3404 ARRAY_SIZE(controls)); 3405 if (ret != 0) 3406 dev_err(wm8994->hubs.component->dev, 3407 "Failed to add ReTune Mobile controls: %d\n", ret); 3408 } 3409 3410 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3411 { 3412 struct snd_soc_component *component = wm8994->hubs.component; 3413 struct wm8994 *control = wm8994->wm8994; 3414 struct wm8994_pdata *pdata = &control->pdata; 3415 int ret, i; 3416 3417 if (!pdata) 3418 return; 3419 3420 wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff, 3421 pdata->lineout2_diff, 3422 pdata->lineout1fb, 3423 pdata->lineout2fb, 3424 pdata->jd_scthr, 3425 pdata->jd_thr, 3426 pdata->micb1_delay, 3427 pdata->micb2_delay, 3428 pdata->micbias1_lvl, 3429 pdata->micbias2_lvl); 3430 3431 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3432 3433 if (pdata->num_drc_cfgs) { 3434 struct snd_kcontrol_new controls[] = { 3435 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3436 wm8994_get_drc_enum, wm8994_put_drc_enum), 3437 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3438 wm8994_get_drc_enum, wm8994_put_drc_enum), 3439 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3440 wm8994_get_drc_enum, wm8994_put_drc_enum), 3441 }; 3442 3443 /* We need an array of texts for the enum API */ 3444 wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev, 3445 pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL); 3446 if (!wm8994->drc_texts) 3447 return; 3448 3449 for (i = 0; i < pdata->num_drc_cfgs; i++) 3450 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3451 3452 wm8994->drc_enum.items = pdata->num_drc_cfgs; 3453 wm8994->drc_enum.texts = wm8994->drc_texts; 3454 3455 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls, 3456 ARRAY_SIZE(controls)); 3457 for (i = 0; i < WM8994_NUM_DRC; i++) 3458 wm8994_set_drc(component, i); 3459 } else { 3460 ret = snd_soc_add_component_controls(wm8994->hubs.component, 3461 wm8994_drc_controls, 3462 ARRAY_SIZE(wm8994_drc_controls)); 3463 } 3464 3465 if (ret != 0) 3466 dev_err(wm8994->hubs.component->dev, 3467 "Failed to add DRC mode controls: %d\n", ret); 3468 3469 3470 dev_dbg(component->dev, "%d ReTune Mobile configurations\n", 3471 pdata->num_retune_mobile_cfgs); 3472 3473 if (pdata->num_retune_mobile_cfgs) 3474 wm8994_handle_retune_mobile_pdata(wm8994); 3475 else 3476 snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls, 3477 ARRAY_SIZE(wm8994_eq_controls)); 3478 3479 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { 3480 if (pdata->micbias[i]) { 3481 snd_soc_component_write(component, WM8958_MICBIAS1 + i, 3482 pdata->micbias[i] & 0xffff); 3483 } 3484 } 3485 } 3486 3487 /** 3488 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3489 * 3490 * @component: WM8994 component 3491 * @jack: jack to report detection events on 3492 * @micbias: microphone bias to detect on 3493 * 3494 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3495 * being used to bring out signals to the processor then only platform 3496 * data configuration is needed for WM8994 and processor GPIOs should 3497 * be configured using snd_soc_jack_add_gpios() instead. 3498 * 3499 * Configuration of detection levels is available via the micbias1_lvl 3500 * and micbias2_lvl platform data members. 3501 */ 3502 int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 3503 int micbias) 3504 { 3505 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3506 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3507 struct wm8994_micdet *micdet; 3508 struct wm8994 *control = wm8994->wm8994; 3509 int reg, ret; 3510 3511 if (control->type != WM8994) { 3512 dev_warn(component->dev, "Not a WM8994\n"); 3513 return -EINVAL; 3514 } 3515 3516 pm_runtime_get_sync(component->dev); 3517 3518 switch (micbias) { 3519 case 1: 3520 micdet = &wm8994->micdet[0]; 3521 if (jack) 3522 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3523 else 3524 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3525 break; 3526 case 2: 3527 micdet = &wm8994->micdet[1]; 3528 if (jack) 3529 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 3530 else 3531 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 3532 break; 3533 default: 3534 dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias); 3535 return -EINVAL; 3536 } 3537 3538 if (ret != 0) 3539 dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n", 3540 micbias, ret); 3541 3542 dev_dbg(component->dev, "Configuring microphone detection on %d %p\n", 3543 micbias, jack); 3544 3545 /* Store the configuration */ 3546 micdet->jack = jack; 3547 micdet->detecting = true; 3548 3549 /* If either of the jacks is set up then enable detection */ 3550 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3551 reg = WM8994_MICD_ENA; 3552 else 3553 reg = 0; 3554 3555 snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3556 3557 /* enable MICDET and MICSHRT deboune */ 3558 snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE, 3559 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | 3560 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, 3561 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); 3562 3563 snd_soc_dapm_sync(dapm); 3564 3565 pm_runtime_put(component->dev); 3566 3567 return 0; 3568 } 3569 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3570 3571 static void wm8994_mic_work(struct work_struct *work) 3572 { 3573 struct wm8994_priv *priv = container_of(work, 3574 struct wm8994_priv, 3575 mic_work.work); 3576 struct regmap *regmap = priv->wm8994->regmap; 3577 struct device *dev = priv->wm8994->dev; 3578 unsigned int reg; 3579 int ret; 3580 int report; 3581 3582 pm_runtime_get_sync(dev); 3583 3584 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); 3585 if (ret < 0) { 3586 dev_err(dev, "Failed to read microphone status: %d\n", 3587 ret); 3588 pm_runtime_put(dev); 3589 return; 3590 } 3591 3592 dev_dbg(dev, "Microphone status: %x\n", reg); 3593 3594 report = 0; 3595 if (reg & WM8994_MIC1_DET_STS) { 3596 if (priv->micdet[0].detecting) 3597 report = SND_JACK_HEADSET; 3598 } 3599 if (reg & WM8994_MIC1_SHRT_STS) { 3600 if (priv->micdet[0].detecting) 3601 report = SND_JACK_HEADPHONE; 3602 else 3603 report |= SND_JACK_BTN_0; 3604 } 3605 if (report) 3606 priv->micdet[0].detecting = false; 3607 else 3608 priv->micdet[0].detecting = true; 3609 3610 snd_soc_jack_report(priv->micdet[0].jack, report, 3611 SND_JACK_HEADSET | SND_JACK_BTN_0); 3612 3613 report = 0; 3614 if (reg & WM8994_MIC2_DET_STS) { 3615 if (priv->micdet[1].detecting) 3616 report = SND_JACK_HEADSET; 3617 } 3618 if (reg & WM8994_MIC2_SHRT_STS) { 3619 if (priv->micdet[1].detecting) 3620 report = SND_JACK_HEADPHONE; 3621 else 3622 report |= SND_JACK_BTN_0; 3623 } 3624 if (report) 3625 priv->micdet[1].detecting = false; 3626 else 3627 priv->micdet[1].detecting = true; 3628 3629 snd_soc_jack_report(priv->micdet[1].jack, report, 3630 SND_JACK_HEADSET | SND_JACK_BTN_0); 3631 3632 pm_runtime_put(dev); 3633 } 3634 3635 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3636 { 3637 struct wm8994_priv *priv = data; 3638 struct snd_soc_component *component = priv->hubs.component; 3639 3640 #ifndef CONFIG_SND_SOC_WM8994_MODULE 3641 trace_snd_soc_jack_irq(dev_name(component->dev)); 3642 #endif 3643 3644 pm_wakeup_event(component->dev, 300); 3645 3646 queue_delayed_work(system_power_efficient_wq, 3647 &priv->mic_work, msecs_to_jiffies(250)); 3648 3649 return IRQ_HANDLED; 3650 } 3651 3652 /* Should be called with accdet_lock held */ 3653 static void wm1811_micd_stop(struct snd_soc_component *component) 3654 { 3655 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3656 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3657 3658 if (!wm8994->jackdet) 3659 return; 3660 3661 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0); 3662 3663 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK); 3664 3665 if (wm8994->wm8994->pdata.jd_ext_cap) 3666 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3667 } 3668 3669 static void wm8958_button_det(struct snd_soc_component *component, u16 status) 3670 { 3671 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3672 int report; 3673 3674 report = 0; 3675 if (status & 0x4) 3676 report |= SND_JACK_BTN_0; 3677 3678 if (status & 0x8) 3679 report |= SND_JACK_BTN_1; 3680 3681 if (status & 0x10) 3682 report |= SND_JACK_BTN_2; 3683 3684 if (status & 0x20) 3685 report |= SND_JACK_BTN_3; 3686 3687 if (status & 0x40) 3688 report |= SND_JACK_BTN_4; 3689 3690 if (status & 0x80) 3691 report |= SND_JACK_BTN_5; 3692 3693 snd_soc_jack_report(wm8994->micdet[0].jack, report, 3694 wm8994->btn_mask); 3695 } 3696 3697 static void wm8958_open_circuit_work(struct work_struct *work) 3698 { 3699 struct wm8994_priv *wm8994 = container_of(work, 3700 struct wm8994_priv, 3701 open_circuit_work.work); 3702 struct device *dev = wm8994->wm8994->dev; 3703 3704 guard(mutex)(&wm8994->accdet_lock); 3705 3706 wm1811_micd_stop(wm8994->hubs.component); 3707 3708 dev_dbg(dev, "Reporting open circuit\n"); 3709 3710 wm8994->jack_mic = false; 3711 wm8994->mic_detecting = true; 3712 3713 wm8958_micd_set_rate(wm8994->hubs.component); 3714 3715 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3716 wm8994->btn_mask | 3717 SND_JACK_HEADSET); 3718 } 3719 3720 static void wm8958_mic_id(void *data, u16 status) 3721 { 3722 struct snd_soc_component *component = data; 3723 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3724 3725 /* Either nothing present or just starting detection */ 3726 if (!(status & WM8958_MICD_STS)) { 3727 /* If nothing present then clear our statuses */ 3728 dev_dbg(component->dev, "Detected open circuit\n"); 3729 3730 queue_delayed_work(system_power_efficient_wq, 3731 &wm8994->open_circuit_work, 3732 msecs_to_jiffies(2500)); 3733 return; 3734 } 3735 3736 /* If the measurement is showing a high impedence we've got a 3737 * microphone. 3738 */ 3739 if (status & 0x600) { 3740 dev_dbg(component->dev, "Detected microphone\n"); 3741 3742 wm8994->mic_detecting = false; 3743 wm8994->jack_mic = true; 3744 3745 wm8958_micd_set_rate(component); 3746 3747 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, 3748 SND_JACK_HEADSET); 3749 } 3750 3751 3752 if (status & 0xfc) { 3753 dev_dbg(component->dev, "Detected headphone\n"); 3754 wm8994->mic_detecting = false; 3755 3756 wm8958_micd_set_rate(component); 3757 3758 /* If we have jackdet that will detect removal */ 3759 wm1811_micd_stop(component); 3760 3761 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, 3762 SND_JACK_HEADSET); 3763 } 3764 } 3765 3766 /* Deferred mic detection to allow for extra settling time */ 3767 static void wm1811_mic_work(struct work_struct *work) 3768 { 3769 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, 3770 mic_work.work); 3771 struct wm8994 *control = wm8994->wm8994; 3772 struct snd_soc_component *component = wm8994->hubs.component; 3773 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3774 3775 guard(pm_runtime_active)(component->dev); 3776 3777 /* If required for an external cap force MICBIAS on */ 3778 if (control->pdata.jd_ext_cap) { 3779 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 3780 snd_soc_dapm_sync(dapm); 3781 } 3782 3783 guard(mutex)(&wm8994->accdet_lock); 3784 3785 dev_dbg(component->dev, "Starting mic detection\n"); 3786 3787 /* Use a user-supplied callback if we have one */ 3788 if (wm8994->micd_cb) { 3789 wm8994->micd_cb(wm8994->micd_cb_data); 3790 } else { 3791 /* 3792 * Start off measument of microphone impedence to find out 3793 * what's actually there. 3794 */ 3795 wm8994->mic_detecting = true; 3796 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC); 3797 3798 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3799 WM8958_MICD_ENA, WM8958_MICD_ENA); 3800 } 3801 } 3802 3803 static irqreturn_t wm1811_jackdet_irq(int irq, void *data) 3804 { 3805 struct wm8994_priv *wm8994 = data; 3806 struct wm8994 *control = wm8994->wm8994; 3807 struct snd_soc_component *component = wm8994->hubs.component; 3808 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3809 int reg, delay; 3810 bool present; 3811 3812 pm_runtime_get_sync(component->dev); 3813 3814 cancel_delayed_work_sync(&wm8994->mic_complete_work); 3815 3816 mutex_lock(&wm8994->accdet_lock); 3817 3818 reg = snd_soc_component_read(component, WM1811_JACKDET_CTRL); 3819 if (reg < 0) { 3820 dev_err(component->dev, "Failed to read jack status: %d\n", reg); 3821 mutex_unlock(&wm8994->accdet_lock); 3822 pm_runtime_put(component->dev); 3823 return IRQ_NONE; 3824 } 3825 3826 dev_dbg(component->dev, "JACKDET %x\n", reg); 3827 3828 present = reg & WM1811_JACKDET_LVL; 3829 3830 if (present) { 3831 dev_dbg(component->dev, "Jack detected\n"); 3832 3833 wm8958_micd_set_rate(component); 3834 3835 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3836 WM8958_MICB2_DISCH, 0); 3837 3838 /* Disable debounce while inserted */ 3839 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3840 WM1811_JACKDET_DB, 0); 3841 3842 delay = control->pdata.micdet_delay; 3843 queue_delayed_work(system_power_efficient_wq, 3844 &wm8994->mic_work, 3845 msecs_to_jiffies(delay)); 3846 } else { 3847 dev_dbg(component->dev, "Jack not detected\n"); 3848 3849 /* Release wm8994->accdet_lock to avoid deadlock: 3850 * cancel_delayed_work_sync() takes wm8994->mic_work internal 3851 * lock and wm1811_mic_work takes wm8994->accdet_lock */ 3852 mutex_unlock(&wm8994->accdet_lock); 3853 cancel_delayed_work_sync(&wm8994->mic_work); 3854 mutex_lock(&wm8994->accdet_lock); 3855 3856 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3857 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); 3858 3859 /* Enable debounce while removed */ 3860 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3861 WM1811_JACKDET_DB, WM1811_JACKDET_DB); 3862 3863 wm8994->mic_detecting = false; 3864 wm8994->jack_mic = false; 3865 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3866 WM8958_MICD_ENA, 0); 3867 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK); 3868 } 3869 3870 mutex_unlock(&wm8994->accdet_lock); 3871 3872 /* Turn off MICBIAS if it was on for an external cap */ 3873 if (control->pdata.jd_ext_cap && !present) 3874 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 3875 3876 if (present) 3877 snd_soc_jack_report(wm8994->micdet[0].jack, 3878 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); 3879 else 3880 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 3881 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 3882 wm8994->btn_mask); 3883 3884 /* Since we only report deltas force an update, ensures we 3885 * avoid bootstrapping issues with the core. */ 3886 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); 3887 3888 pm_runtime_put(component->dev); 3889 return IRQ_HANDLED; 3890 } 3891 3892 static void wm1811_jackdet_bootstrap(struct work_struct *work) 3893 { 3894 struct wm8994_priv *wm8994 = container_of(work, 3895 struct wm8994_priv, 3896 jackdet_bootstrap.work); 3897 wm1811_jackdet_irq(0, wm8994); 3898 } 3899 3900 /** 3901 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ 3902 * 3903 * @component: WM8958 component 3904 * @jack: jack to report detection events on 3905 * @det_cb: detection callback 3906 * @det_cb_data: data for detection callback 3907 * @id_cb: mic id callback 3908 * @id_cb_data: data for mic id callback 3909 * 3910 * Enable microphone detection functionality for the WM8958. By 3911 * default simple detection which supports the detection of up to 6 3912 * buttons plus video and microphone functionality is supported. 3913 * 3914 * The WM8958 has an advanced jack detection facility which is able to 3915 * support complex accessory detection, especially when used in 3916 * conjunction with external circuitry. In order to provide maximum 3917 * flexiblity a callback is provided which allows a completely custom 3918 * detection algorithm. 3919 */ 3920 int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 3921 wm1811_micdet_cb det_cb, void *det_cb_data, 3922 wm1811_mic_id_cb id_cb, void *id_cb_data) 3923 { 3924 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 3925 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 3926 struct wm8994 *control = wm8994->wm8994; 3927 u16 micd_lvl_sel; 3928 3929 switch (control->type) { 3930 case WM1811: 3931 case WM8958: 3932 break; 3933 default: 3934 return -EINVAL; 3935 } 3936 3937 pm_runtime_get_sync(component->dev); 3938 3939 if (jack) { 3940 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS"); 3941 snd_soc_dapm_sync(dapm); 3942 3943 wm8994->micdet[0].jack = jack; 3944 3945 if (det_cb) { 3946 wm8994->micd_cb = det_cb; 3947 wm8994->micd_cb_data = det_cb_data; 3948 } else { 3949 wm8994->mic_detecting = true; 3950 wm8994->jack_mic = false; 3951 } 3952 3953 if (id_cb) { 3954 wm8994->mic_id_cb = id_cb; 3955 wm8994->mic_id_cb_data = id_cb_data; 3956 } else { 3957 wm8994->mic_id_cb = wm8958_mic_id; 3958 wm8994->mic_id_cb_data = component; 3959 } 3960 3961 wm8958_micd_set_rate(component); 3962 3963 /* Detect microphones and short circuits by default */ 3964 if (control->pdata.micd_lvl_sel) 3965 micd_lvl_sel = control->pdata.micd_lvl_sel; 3966 else 3967 micd_lvl_sel = 0x41; 3968 3969 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 3970 SND_JACK_BTN_2 | SND_JACK_BTN_3 | 3971 SND_JACK_BTN_4 | SND_JACK_BTN_5; 3972 3973 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2, 3974 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); 3975 3976 WARN_ON(snd_soc_dapm_get_bias_level(dapm) > SND_SOC_BIAS_STANDBY); 3977 3978 /* 3979 * If we can use jack detection start off with that, 3980 * otherwise jump straight to microphone detection. 3981 */ 3982 if (wm8994->jackdet) { 3983 /* Disable debounce for the initial detect */ 3984 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL, 3985 WM1811_JACKDET_DB, 0); 3986 3987 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 3988 WM8958_MICB2_DISCH, 3989 WM8958_MICB2_DISCH); 3990 snd_soc_component_update_bits(component, WM8994_LDO_1, 3991 WM8994_LDO1_DISCH, 0); 3992 wm1811_jackdet_set_mode(component, 3993 WM1811_JACKDET_MODE_JACK); 3994 } else { 3995 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 3996 WM8958_MICD_ENA, WM8958_MICD_ENA); 3997 } 3998 3999 } else { 4000 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, 4001 WM8958_MICD_ENA, 0); 4002 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE); 4003 snd_soc_dapm_disable_pin(dapm, "CLK_SYS"); 4004 snd_soc_dapm_sync(dapm); 4005 } 4006 4007 pm_runtime_put(component->dev); 4008 4009 return 0; 4010 } 4011 EXPORT_SYMBOL_GPL(wm8958_mic_detect); 4012 4013 static void wm8958_mic_work(struct work_struct *work) 4014 { 4015 struct wm8994_priv *wm8994 = container_of(work, 4016 struct wm8994_priv, 4017 mic_complete_work.work); 4018 struct snd_soc_component *component = wm8994->hubs.component; 4019 4020 guard(pm_runtime_active)(component->dev); 4021 guard(mutex)(&wm8994->accdet_lock); 4022 4023 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status); 4024 } 4025 4026 static irqreturn_t wm8958_mic_irq(int irq, void *data) 4027 { 4028 struct wm8994_priv *wm8994 = data; 4029 struct snd_soc_component *component = wm8994->hubs.component; 4030 int reg, count, ret, id_delay; 4031 4032 /* 4033 * Jack detection may have detected a removal simulataneously 4034 * with an update of the MICDET status; if so it will have 4035 * stopped detection and we can ignore this interrupt. 4036 */ 4037 if (!(snd_soc_component_read(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) 4038 return IRQ_HANDLED; 4039 4040 cancel_delayed_work_sync(&wm8994->mic_complete_work); 4041 cancel_delayed_work_sync(&wm8994->open_circuit_work); 4042 4043 pm_runtime_get_sync(component->dev); 4044 4045 /* We may occasionally read a detection without an impedence 4046 * range being provided - if that happens loop again. 4047 */ 4048 count = 10; 4049 do { 4050 reg = snd_soc_component_read(component, WM8958_MIC_DETECT_3); 4051 if (reg < 0) { 4052 dev_err(component->dev, 4053 "Failed to read mic detect status: %d\n", 4054 reg); 4055 pm_runtime_put(component->dev); 4056 return IRQ_NONE; 4057 } 4058 4059 if (!(reg & WM8958_MICD_VALID)) { 4060 dev_dbg(component->dev, "Mic detect data not valid\n"); 4061 goto out; 4062 } 4063 4064 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) 4065 break; 4066 4067 msleep(1); 4068 } while (count--); 4069 4070 if (count == 0) 4071 dev_warn(component->dev, "No impedance range reported for jack\n"); 4072 4073 #ifndef CONFIG_SND_SOC_WM8994_MODULE 4074 trace_snd_soc_jack_irq(dev_name(component->dev)); 4075 #endif 4076 4077 /* Avoid a transient report when the accessory is being removed */ 4078 if (wm8994->jackdet) { 4079 ret = snd_soc_component_read(component, WM1811_JACKDET_CTRL); 4080 if (ret < 0) { 4081 dev_err(component->dev, "Failed to read jack status: %d\n", 4082 ret); 4083 } else if (!(ret & WM1811_JACKDET_LVL)) { 4084 dev_dbg(component->dev, "Ignoring removed jack\n"); 4085 goto out; 4086 } 4087 } else if (!(reg & WM8958_MICD_STS)) { 4088 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 4089 SND_JACK_MECHANICAL | SND_JACK_HEADSET | 4090 wm8994->btn_mask); 4091 wm8994->mic_detecting = true; 4092 goto out; 4093 } 4094 4095 wm8994->mic_status = reg; 4096 id_delay = wm8994->wm8994->pdata.mic_id_delay; 4097 4098 if (wm8994->mic_detecting) 4099 queue_delayed_work(system_power_efficient_wq, 4100 &wm8994->mic_complete_work, 4101 msecs_to_jiffies(id_delay)); 4102 else 4103 wm8958_button_det(component, reg); 4104 4105 out: 4106 pm_runtime_put(component->dev); 4107 return IRQ_HANDLED; 4108 } 4109 4110 static irqreturn_t wm8994_fifo_error(int irq, void *data) 4111 { 4112 struct snd_soc_component *component = data; 4113 4114 dev_err(component->dev, "FIFO error\n"); 4115 4116 return IRQ_HANDLED; 4117 } 4118 4119 static irqreturn_t wm8994_temp_warn(int irq, void *data) 4120 { 4121 struct snd_soc_component *component = data; 4122 4123 dev_err(component->dev, "Thermal warning\n"); 4124 4125 return IRQ_HANDLED; 4126 } 4127 4128 static irqreturn_t wm8994_temp_shut(int irq, void *data) 4129 { 4130 struct snd_soc_component *component = data; 4131 4132 dev_crit(component->dev, "Thermal shutdown\n"); 4133 4134 return IRQ_HANDLED; 4135 } 4136 4137 static int wm8994_component_probe(struct snd_soc_component *component) 4138 { 4139 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 4140 struct wm8994 *control = dev_get_drvdata(component->dev->parent); 4141 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 4142 unsigned int reg; 4143 int ret, i; 4144 4145 snd_soc_component_init_regmap(component, control->regmap); 4146 4147 wm8994->hubs.component = component; 4148 4149 mutex_init(&wm8994->accdet_lock); 4150 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 4151 wm1811_jackdet_bootstrap); 4152 INIT_DELAYED_WORK(&wm8994->open_circuit_work, 4153 wm8958_open_circuit_work); 4154 4155 switch (control->type) { 4156 case WM8994: 4157 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); 4158 break; 4159 case WM1811: 4160 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); 4161 break; 4162 default: 4163 break; 4164 } 4165 4166 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work); 4167 4168 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4169 init_completion(&wm8994->fll_locked[i]); 4170 4171 wm8994->micdet_irq = control->pdata.micdet_irq; 4172 4173 /* By default use idle_bias false, will override for WM8994 */ 4174 snd_soc_dapm_set_idle_bias(dapm, false); 4175 4176 /* Set revision-specific configuration */ 4177 switch (control->type) { 4178 case WM8994: 4179 /* Single ended line outputs should have VMID on. */ 4180 if (!control->pdata.lineout1_diff || 4181 !control->pdata.lineout2_diff) 4182 snd_soc_dapm_set_idle_bias(dapm, true); 4183 4184 switch (control->revision) { 4185 case 2: 4186 case 3: 4187 wm8994->hubs.dcs_codes_l = -5; 4188 wm8994->hubs.dcs_codes_r = -5; 4189 wm8994->hubs.hp_startup_mode = 1; 4190 wm8994->hubs.dcs_readback_mode = 1; 4191 wm8994->hubs.series_startup = 1; 4192 break; 4193 default: 4194 wm8994->hubs.dcs_readback_mode = 2; 4195 break; 4196 } 4197 wm8994->hubs.micd_scthr = true; 4198 break; 4199 4200 case WM8958: 4201 wm8994->hubs.dcs_readback_mode = 1; 4202 wm8994->hubs.hp_startup_mode = 1; 4203 wm8994->hubs.micd_scthr = true; 4204 4205 switch (control->revision) { 4206 case 0: 4207 break; 4208 default: 4209 wm8994->fll_byp = true; 4210 break; 4211 } 4212 break; 4213 4214 case WM1811: 4215 wm8994->hubs.dcs_readback_mode = 2; 4216 wm8994->hubs.no_series_update = 1; 4217 wm8994->hubs.hp_startup_mode = 1; 4218 wm8994->hubs.no_cache_dac_hp_direct = true; 4219 wm8994->fll_byp = true; 4220 4221 wm8994->hubs.dcs_codes_l = -9; 4222 wm8994->hubs.dcs_codes_r = -7; 4223 4224 snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1, 4225 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); 4226 break; 4227 4228 default: 4229 break; 4230 } 4231 4232 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, 4233 wm8994_fifo_error, "FIFO error", component); 4234 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, 4235 wm8994_temp_warn, "Thermal warning", component); 4236 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, 4237 wm8994_temp_shut, "Thermal shutdown", component); 4238 4239 switch (control->type) { 4240 case WM8994: 4241 if (wm8994->micdet_irq) 4242 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4243 wm8994_mic_irq, 4244 IRQF_TRIGGER_RISING | 4245 IRQF_ONESHOT, 4246 "Mic1 detect", 4247 wm8994); 4248 else 4249 ret = wm8994_request_irq(wm8994->wm8994, 4250 WM8994_IRQ_MIC1_DET, 4251 wm8994_mic_irq, "Mic 1 detect", 4252 wm8994); 4253 4254 if (ret != 0) 4255 dev_warn(component->dev, 4256 "Failed to request Mic1 detect IRQ: %d\n", 4257 ret); 4258 4259 4260 ret = wm8994_request_irq(wm8994->wm8994, 4261 WM8994_IRQ_MIC1_SHRT, 4262 wm8994_mic_irq, "Mic 1 short", 4263 wm8994); 4264 if (ret != 0) 4265 dev_warn(component->dev, 4266 "Failed to request Mic1 short IRQ: %d\n", 4267 ret); 4268 4269 ret = wm8994_request_irq(wm8994->wm8994, 4270 WM8994_IRQ_MIC2_DET, 4271 wm8994_mic_irq, "Mic 2 detect", 4272 wm8994); 4273 if (ret != 0) 4274 dev_warn(component->dev, 4275 "Failed to request Mic2 detect IRQ: %d\n", 4276 ret); 4277 4278 ret = wm8994_request_irq(wm8994->wm8994, 4279 WM8994_IRQ_MIC2_SHRT, 4280 wm8994_mic_irq, "Mic 2 short", 4281 wm8994); 4282 if (ret != 0) 4283 dev_warn(component->dev, 4284 "Failed to request Mic2 short IRQ: %d\n", 4285 ret); 4286 break; 4287 4288 case WM8958: 4289 case WM1811: 4290 if (wm8994->micdet_irq) { 4291 ret = request_threaded_irq(wm8994->micdet_irq, NULL, 4292 wm8958_mic_irq, 4293 IRQF_TRIGGER_RISING | 4294 IRQF_ONESHOT, 4295 "Mic detect", 4296 wm8994); 4297 if (ret != 0) 4298 dev_warn(component->dev, 4299 "Failed to request Mic detect IRQ: %d\n", 4300 ret); 4301 } else { 4302 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4303 wm8958_mic_irq, "Mic detect", 4304 wm8994); 4305 } 4306 } 4307 4308 switch (control->type) { 4309 case WM1811: 4310 if (control->cust_id > 1 || control->revision > 1) { 4311 ret = wm8994_request_irq(wm8994->wm8994, 4312 WM8994_IRQ_GPIO(6), 4313 wm1811_jackdet_irq, "JACKDET", 4314 wm8994); 4315 if (ret == 0) 4316 wm8994->jackdet = true; 4317 } 4318 break; 4319 default: 4320 break; 4321 } 4322 4323 wm8994->fll_locked_irq = true; 4324 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { 4325 ret = wm8994_request_irq(wm8994->wm8994, 4326 WM8994_IRQ_FLL1_LOCK + i, 4327 wm8994_fll_locked_irq, "FLL lock", 4328 &wm8994->fll_locked[i]); 4329 if (ret != 0) 4330 wm8994->fll_locked_irq = false; 4331 } 4332 4333 /* Make sure we can read from the GPIOs if they're inputs */ 4334 pm_runtime_get_sync(component->dev); 4335 4336 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 4337 * configured on init - if a system wants to do this dynamically 4338 * at runtime we can deal with that then. 4339 */ 4340 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); 4341 if (ret < 0) { 4342 dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret); 4343 goto err_irq; 4344 } 4345 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4346 wm8994->lrclk_shared[0] = 1; 4347 wm8994_dai[0].symmetric_rate = 1; 4348 } else { 4349 wm8994->lrclk_shared[0] = 0; 4350 } 4351 4352 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); 4353 if (ret < 0) { 4354 dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret); 4355 goto err_irq; 4356 } 4357 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 4358 wm8994->lrclk_shared[1] = 1; 4359 wm8994_dai[1].symmetric_rate = 1; 4360 } else { 4361 wm8994->lrclk_shared[1] = 0; 4362 } 4363 4364 pm_runtime_put(component->dev); 4365 4366 /* Latch volume update bits */ 4367 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) 4368 snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg, 4369 wm8994_vu_bits[i].mask, 4370 wm8994_vu_bits[i].mask); 4371 4372 if (control->type != WM1811) { 4373 for (i = 0; i < ARRAY_SIZE(wm8994_adc2_dac2_vu_bits); i++) 4374 snd_soc_component_update_bits(component, 4375 wm8994_adc2_dac2_vu_bits[i].reg, 4376 wm8994_adc2_dac2_vu_bits[i].mask, 4377 wm8994_adc2_dac2_vu_bits[i].mask); 4378 } 4379 4380 /* Set the low bit of the 3D stereo depth so TLV matches */ 4381 snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2, 4382 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 4383 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4384 snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2, 4385 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4386 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4387 snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2, 4388 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4389 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4390 4391 /* Unconditionally enable AIF1 ADC TDM mode on chips which can 4392 * use this; it only affects behaviour on idle TDM clock 4393 * cycles. */ 4394 switch (control->type) { 4395 case WM8994: 4396 case WM8958: 4397 snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1, 4398 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); 4399 break; 4400 default: 4401 break; 4402 } 4403 4404 /* Put MICBIAS into bypass mode by default on newer devices */ 4405 switch (control->type) { 4406 case WM8958: 4407 case WM1811: 4408 snd_soc_component_update_bits(component, WM8958_MICBIAS1, 4409 WM8958_MICB1_MODE, WM8958_MICB1_MODE); 4410 snd_soc_component_update_bits(component, WM8958_MICBIAS2, 4411 WM8958_MICB2_MODE, WM8958_MICB2_MODE); 4412 break; 4413 default: 4414 break; 4415 } 4416 4417 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; 4418 wm_hubs_update_class_w(component); 4419 4420 wm8994_handle_pdata(wm8994); 4421 4422 wm_hubs_add_analogue_controls(component); 4423 snd_soc_add_component_controls(component, wm8994_common_snd_controls, 4424 ARRAY_SIZE(wm8994_common_snd_controls)); 4425 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, 4426 ARRAY_SIZE(wm8994_dapm_widgets)); 4427 4428 switch (control->type) { 4429 case WM8994: 4430 snd_soc_add_component_controls(component, wm8994_snd_controls, 4431 ARRAY_SIZE(wm8994_snd_controls)); 4432 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, 4433 ARRAY_SIZE(wm8994_specific_dapm_widgets)); 4434 if (control->revision < 4) { 4435 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4436 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4437 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4438 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4439 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4440 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4441 } else { 4442 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4443 ARRAY_SIZE(wm8994_lateclk_widgets)); 4444 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4445 ARRAY_SIZE(wm8994_adc_widgets)); 4446 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4447 ARRAY_SIZE(wm8994_dac_widgets)); 4448 } 4449 break; 4450 case WM8958: 4451 snd_soc_add_component_controls(component, wm8994_snd_controls, 4452 ARRAY_SIZE(wm8994_snd_controls)); 4453 snd_soc_add_component_controls(component, wm8958_snd_controls, 4454 ARRAY_SIZE(wm8958_snd_controls)); 4455 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4456 ARRAY_SIZE(wm8958_dapm_widgets)); 4457 if (control->revision < 1) { 4458 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, 4459 ARRAY_SIZE(wm8994_lateclk_revd_widgets)); 4460 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, 4461 ARRAY_SIZE(wm8994_adc_revd_widgets)); 4462 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, 4463 ARRAY_SIZE(wm8994_dac_revd_widgets)); 4464 } else { 4465 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4466 ARRAY_SIZE(wm8994_lateclk_widgets)); 4467 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4468 ARRAY_SIZE(wm8994_adc_widgets)); 4469 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4470 ARRAY_SIZE(wm8994_dac_widgets)); 4471 } 4472 break; 4473 4474 case WM1811: 4475 snd_soc_add_component_controls(component, wm8958_snd_controls, 4476 ARRAY_SIZE(wm8958_snd_controls)); 4477 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, 4478 ARRAY_SIZE(wm8958_dapm_widgets)); 4479 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, 4480 ARRAY_SIZE(wm8994_lateclk_widgets)); 4481 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, 4482 ARRAY_SIZE(wm8994_adc_widgets)); 4483 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, 4484 ARRAY_SIZE(wm8994_dac_widgets)); 4485 break; 4486 } 4487 4488 wm_hubs_add_analogue_routes(component, 0, 0); 4489 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4490 wm_hubs_dcs_done, "DC servo done", 4491 &wm8994->hubs); 4492 if (ret == 0) 4493 wm8994->hubs.dcs_done_irq = true; 4494 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4495 4496 switch (control->type) { 4497 case WM8994: 4498 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4499 ARRAY_SIZE(wm8994_intercon)); 4500 4501 if (control->revision < 4) { 4502 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4503 ARRAY_SIZE(wm8994_revd_intercon)); 4504 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4505 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4506 } else { 4507 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4508 ARRAY_SIZE(wm8994_lateclk_intercon)); 4509 } 4510 break; 4511 case WM8958: 4512 if (control->revision < 1) { 4513 snd_soc_dapm_add_routes(dapm, wm8994_intercon, 4514 ARRAY_SIZE(wm8994_intercon)); 4515 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, 4516 ARRAY_SIZE(wm8994_revd_intercon)); 4517 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, 4518 ARRAY_SIZE(wm8994_lateclk_revd_intercon)); 4519 } else { 4520 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4521 ARRAY_SIZE(wm8994_lateclk_intercon)); 4522 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4523 ARRAY_SIZE(wm8958_intercon)); 4524 } 4525 4526 wm8958_dsp2_init(component); 4527 break; 4528 case WM1811: 4529 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, 4530 ARRAY_SIZE(wm8994_lateclk_intercon)); 4531 snd_soc_dapm_add_routes(dapm, wm8958_intercon, 4532 ARRAY_SIZE(wm8958_intercon)); 4533 break; 4534 } 4535 4536 return 0; 4537 4538 err_irq: 4539 if (wm8994->jackdet) 4540 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4541 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); 4542 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); 4543 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); 4544 if (wm8994->micdet_irq) 4545 free_irq(wm8994->micdet_irq, wm8994); 4546 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4547 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4548 &wm8994->fll_locked[i]); 4549 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4550 &wm8994->hubs); 4551 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component); 4552 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component); 4553 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component); 4554 4555 return ret; 4556 } 4557 4558 static void wm8994_component_remove(struct snd_soc_component *component) 4559 { 4560 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component); 4561 struct wm8994 *control = wm8994->wm8994; 4562 int i; 4563 4564 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 4565 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, 4566 &wm8994->fll_locked[i]); 4567 4568 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, 4569 &wm8994->hubs); 4570 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component); 4571 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component); 4572 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component); 4573 4574 if (wm8994->jackdet) 4575 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); 4576 4577 switch (control->type) { 4578 case WM8994: 4579 if (wm8994->micdet_irq) 4580 free_irq(wm8994->micdet_irq, wm8994); 4581 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, 4582 wm8994); 4583 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, 4584 wm8994); 4585 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, 4586 wm8994); 4587 break; 4588 4589 case WM1811: 4590 case WM8958: 4591 if (wm8994->micdet_irq) 4592 free_irq(wm8994->micdet_irq, wm8994); 4593 break; 4594 } 4595 release_firmware(wm8994->mbc); 4596 release_firmware(wm8994->mbc_vss); 4597 release_firmware(wm8994->enh_eq); 4598 kfree(wm8994->retune_mobile_texts); 4599 } 4600 4601 static const struct snd_soc_component_driver soc_component_dev_wm8994 = { 4602 .probe = wm8994_component_probe, 4603 .remove = wm8994_component_remove, 4604 .suspend = wm8994_component_suspend, 4605 .resume = wm8994_component_resume, 4606 .set_bias_level = wm8994_set_bias_level, 4607 .idle_bias_on = 1, 4608 .use_pmdown_time = 1, 4609 .endianness = 1, 4610 }; 4611 4612 static int wm8994_probe(struct platform_device *pdev) 4613 { 4614 struct wm8994_priv *wm8994; 4615 int ret; 4616 4617 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), 4618 GFP_KERNEL); 4619 if (wm8994 == NULL) 4620 return -ENOMEM; 4621 platform_set_drvdata(pdev, wm8994); 4622 4623 mutex_init(&wm8994->fw_lock); 4624 4625 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); 4626 4627 wm8994->mclk[WM8994_MCLK1].id = "MCLK1"; 4628 wm8994->mclk[WM8994_MCLK2].id = "MCLK2"; 4629 4630 ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk), 4631 wm8994->mclk); 4632 if (ret < 0) { 4633 dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret); 4634 return ret; 4635 } 4636 4637 pm_runtime_enable(&pdev->dev); 4638 pm_runtime_idle(&pdev->dev); 4639 4640 ret = devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994, 4641 wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4642 if (ret < 0) 4643 pm_runtime_disable(&pdev->dev); 4644 4645 return ret; 4646 } 4647 4648 static void wm8994_remove(struct platform_device *pdev) 4649 { 4650 pm_runtime_disable(&pdev->dev); 4651 } 4652 4653 static int wm8994_suspend(struct device *dev) 4654 { 4655 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4656 4657 /* Drop down to power saving mode when system is suspended */ 4658 if (wm8994->jackdet && !wm8994->active_refcount) 4659 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4660 WM1811_JACKDET_MODE_MASK, 4661 wm8994->jackdet_mode); 4662 4663 return 0; 4664 } 4665 4666 static int wm8994_resume(struct device *dev) 4667 { 4668 struct wm8994_priv *wm8994 = dev_get_drvdata(dev); 4669 4670 if (wm8994->jackdet && wm8994->jackdet_mode) 4671 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, 4672 WM1811_JACKDET_MODE_MASK, 4673 WM1811_JACKDET_MODE_AUDIO); 4674 4675 return 0; 4676 } 4677 4678 static const struct dev_pm_ops wm8994_pm_ops = { 4679 SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) 4680 }; 4681 4682 static struct platform_driver wm8994_codec_driver = { 4683 .driver = { 4684 .name = "wm8994-codec", 4685 .pm = pm_ptr(&wm8994_pm_ops), 4686 }, 4687 .probe = wm8994_probe, 4688 .remove = wm8994_remove, 4689 }; 4690 4691 module_platform_driver(wm8994_codec_driver); 4692 4693 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4694 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4695 MODULE_LICENSE("GPL"); 4696 MODULE_ALIAS("platform:wm8994-codec"); 4697