1 /* 2 * wm8994.c -- WM8994 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 31 #include <linux/mfd/wm8994/core.h> 32 #include <linux/mfd/wm8994/registers.h> 33 #include <linux/mfd/wm8994/pdata.h> 34 #include <linux/mfd/wm8994/gpio.h> 35 36 #include "wm8994.h" 37 #include "wm_hubs.h" 38 39 static struct snd_soc_codec *wm8994_codec; 40 struct snd_soc_codec_device soc_codec_dev_wm8994; 41 42 struct fll_config { 43 int src; 44 int in; 45 int out; 46 }; 47 48 #define WM8994_NUM_DRC 3 49 #define WM8994_NUM_EQ 3 50 51 static int wm8994_drc_base[] = { 52 WM8994_AIF1_DRC1_1, 53 WM8994_AIF1_DRC2_1, 54 WM8994_AIF2_DRC_1, 55 }; 56 57 static int wm8994_retune_mobile_base[] = { 58 WM8994_AIF1_DAC1_EQ_GAINS_1, 59 WM8994_AIF1_DAC2_EQ_GAINS_1, 60 WM8994_AIF2_EQ_GAINS_1, 61 }; 62 63 #define WM8994_REG_CACHE_SIZE 0x621 64 65 struct wm8994_micdet { 66 struct snd_soc_jack *jack; 67 int det; 68 int shrt; 69 }; 70 71 /* codec private data */ 72 struct wm8994_priv { 73 struct wm_hubs_data hubs; 74 struct snd_soc_codec codec; 75 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1]; 76 int sysclk[2]; 77 int sysclk_rate[2]; 78 int mclk[2]; 79 int aifclk[2]; 80 struct fll_config fll[2], fll_suspend[2]; 81 82 int dac_rates[2]; 83 int lrclk_shared[2]; 84 85 /* Platform dependant DRC configuration */ 86 const char **drc_texts; 87 int drc_cfg[WM8994_NUM_DRC]; 88 struct soc_enum drc_enum; 89 90 /* Platform dependant ReTune mobile configuration */ 91 int num_retune_mobile_texts; 92 const char **retune_mobile_texts; 93 int retune_mobile_cfg[WM8994_NUM_EQ]; 94 struct soc_enum retune_mobile_enum; 95 96 struct wm8994_micdet micdet[2]; 97 98 struct wm8994_pdata *pdata; 99 }; 100 101 static struct { 102 unsigned short readable; /* Mask of readable bits */ 103 unsigned short writable; /* Mask of writable bits */ 104 unsigned short vol; /* Mask of volatile bits */ 105 } access_masks[] = { 106 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Software Reset */ 107 { 0x3B37, 0x3B37, 0x0000 }, /* R1 - Power Management (1) */ 108 { 0x6BF0, 0x6BF0, 0x0000 }, /* R2 - Power Management (2) */ 109 { 0x3FF0, 0x3FF0, 0x0000 }, /* R3 - Power Management (3) */ 110 { 0x3F3F, 0x3F3F, 0x0000 }, /* R4 - Power Management (4) */ 111 { 0x3F0F, 0x3F0F, 0x0000 }, /* R5 - Power Management (5) */ 112 { 0x003F, 0x003F, 0x0000 }, /* R6 - Power Management (6) */ 113 { 0x0000, 0x0000, 0x0000 }, /* R7 */ 114 { 0x0000, 0x0000, 0x0000 }, /* R8 */ 115 { 0x0000, 0x0000, 0x0000 }, /* R9 */ 116 { 0x0000, 0x0000, 0x0000 }, /* R10 */ 117 { 0x0000, 0x0000, 0x0000 }, /* R11 */ 118 { 0x0000, 0x0000, 0x0000 }, /* R12 */ 119 { 0x0000, 0x0000, 0x0000 }, /* R13 */ 120 { 0x0000, 0x0000, 0x0000 }, /* R14 */ 121 { 0x0000, 0x0000, 0x0000 }, /* R15 */ 122 { 0x0000, 0x0000, 0x0000 }, /* R16 */ 123 { 0x0000, 0x0000, 0x0000 }, /* R17 */ 124 { 0x0000, 0x0000, 0x0000 }, /* R18 */ 125 { 0x0000, 0x0000, 0x0000 }, /* R19 */ 126 { 0x0000, 0x0000, 0x0000 }, /* R20 */ 127 { 0x01C0, 0x01C0, 0x0000 }, /* R21 - Input Mixer (1) */ 128 { 0x0000, 0x0000, 0x0000 }, /* R22 */ 129 { 0x0000, 0x0000, 0x0000 }, /* R23 */ 130 { 0x00DF, 0x01DF, 0x0000 }, /* R24 - Left Line Input 1&2 Volume */ 131 { 0x00DF, 0x01DF, 0x0000 }, /* R25 - Left Line Input 3&4 Volume */ 132 { 0x00DF, 0x01DF, 0x0000 }, /* R26 - Right Line Input 1&2 Volume */ 133 { 0x00DF, 0x01DF, 0x0000 }, /* R27 - Right Line Input 3&4 Volume */ 134 { 0x00FF, 0x01FF, 0x0000 }, /* R28 - Left Output Volume */ 135 { 0x00FF, 0x01FF, 0x0000 }, /* R29 - Right Output Volume */ 136 { 0x0077, 0x0077, 0x0000 }, /* R30 - Line Outputs Volume */ 137 { 0x0030, 0x0030, 0x0000 }, /* R31 - HPOUT2 Volume */ 138 { 0x00FF, 0x01FF, 0x0000 }, /* R32 - Left OPGA Volume */ 139 { 0x00FF, 0x01FF, 0x0000 }, /* R33 - Right OPGA Volume */ 140 { 0x007F, 0x007F, 0x0000 }, /* R34 - SPKMIXL Attenuation */ 141 { 0x017F, 0x017F, 0x0000 }, /* R35 - SPKMIXR Attenuation */ 142 { 0x003F, 0x003F, 0x0000 }, /* R36 - SPKOUT Mixers */ 143 { 0x003F, 0x003F, 0x0000 }, /* R37 - ClassD */ 144 { 0x00FF, 0x01FF, 0x0000 }, /* R38 - Speaker Volume Left */ 145 { 0x00FF, 0x01FF, 0x0000 }, /* R39 - Speaker Volume Right */ 146 { 0x00FF, 0x00FF, 0x0000 }, /* R40 - Input Mixer (2) */ 147 { 0x01B7, 0x01B7, 0x0000 }, /* R41 - Input Mixer (3) */ 148 { 0x01B7, 0x01B7, 0x0000 }, /* R42 - Input Mixer (4) */ 149 { 0x01C7, 0x01C7, 0x0000 }, /* R43 - Input Mixer (5) */ 150 { 0x01C7, 0x01C7, 0x0000 }, /* R44 - Input Mixer (6) */ 151 { 0x01FF, 0x01FF, 0x0000 }, /* R45 - Output Mixer (1) */ 152 { 0x01FF, 0x01FF, 0x0000 }, /* R46 - Output Mixer (2) */ 153 { 0x0FFF, 0x0FFF, 0x0000 }, /* R47 - Output Mixer (3) */ 154 { 0x0FFF, 0x0FFF, 0x0000 }, /* R48 - Output Mixer (4) */ 155 { 0x0FFF, 0x0FFF, 0x0000 }, /* R49 - Output Mixer (5) */ 156 { 0x0FFF, 0x0FFF, 0x0000 }, /* R50 - Output Mixer (6) */ 157 { 0x0038, 0x0038, 0x0000 }, /* R51 - HPOUT2 Mixer */ 158 { 0x0077, 0x0077, 0x0000 }, /* R52 - Line Mixer (1) */ 159 { 0x0077, 0x0077, 0x0000 }, /* R53 - Line Mixer (2) */ 160 { 0x03FF, 0x03FF, 0x0000 }, /* R54 - Speaker Mixer */ 161 { 0x00C1, 0x00C1, 0x0000 }, /* R55 - Additional Control */ 162 { 0x00F0, 0x00F0, 0x0000 }, /* R56 - AntiPOP (1) */ 163 { 0x01EF, 0x01EF, 0x0000 }, /* R57 - AntiPOP (2) */ 164 { 0x00FF, 0x00FF, 0x0000 }, /* R58 - MICBIAS */ 165 { 0x000F, 0x000F, 0x0000 }, /* R59 - LDO 1 */ 166 { 0x0007, 0x0007, 0x0000 }, /* R60 - LDO 2 */ 167 { 0x0000, 0x0000, 0x0000 }, /* R61 */ 168 { 0x0000, 0x0000, 0x0000 }, /* R62 */ 169 { 0x0000, 0x0000, 0x0000 }, /* R63 */ 170 { 0x0000, 0x0000, 0x0000 }, /* R64 */ 171 { 0x0000, 0x0000, 0x0000 }, /* R65 */ 172 { 0x0000, 0x0000, 0x0000 }, /* R66 */ 173 { 0x0000, 0x0000, 0x0000 }, /* R67 */ 174 { 0x0000, 0x0000, 0x0000 }, /* R68 */ 175 { 0x0000, 0x0000, 0x0000 }, /* R69 */ 176 { 0x0000, 0x0000, 0x0000 }, /* R70 */ 177 { 0x0000, 0x0000, 0x0000 }, /* R71 */ 178 { 0x0000, 0x0000, 0x0000 }, /* R72 */ 179 { 0x0000, 0x0000, 0x0000 }, /* R73 */ 180 { 0x0000, 0x0000, 0x0000 }, /* R74 */ 181 { 0x0000, 0x0000, 0x0000 }, /* R75 */ 182 { 0x8000, 0x8000, 0x0000 }, /* R76 - Charge Pump (1) */ 183 { 0x0000, 0x0000, 0x0000 }, /* R77 */ 184 { 0x0000, 0x0000, 0x0000 }, /* R78 */ 185 { 0x0000, 0x0000, 0x0000 }, /* R79 */ 186 { 0x0000, 0x0000, 0x0000 }, /* R80 */ 187 { 0x0301, 0x0301, 0x0000 }, /* R81 - Class W (1) */ 188 { 0x0000, 0x0000, 0x0000 }, /* R82 */ 189 { 0x0000, 0x0000, 0x0000 }, /* R83 */ 190 { 0x333F, 0x333F, 0x0000 }, /* R84 - DC Servo (1) */ 191 { 0x0FEF, 0x0FEF, 0x0000 }, /* R85 - DC Servo (2) */ 192 { 0x0000, 0x0000, 0x0000 }, /* R86 */ 193 { 0xFFFF, 0xFFFF, 0x0000 }, /* R87 - DC Servo (4) */ 194 { 0x0333, 0x0000, 0x0000 }, /* R88 - DC Servo Readback */ 195 { 0x0000, 0x0000, 0x0000 }, /* R89 */ 196 { 0x0000, 0x0000, 0x0000 }, /* R90 */ 197 { 0x0000, 0x0000, 0x0000 }, /* R91 */ 198 { 0x0000, 0x0000, 0x0000 }, /* R92 */ 199 { 0x0000, 0x0000, 0x0000 }, /* R93 */ 200 { 0x0000, 0x0000, 0x0000 }, /* R94 */ 201 { 0x0000, 0x0000, 0x0000 }, /* R95 */ 202 { 0x00EE, 0x00EE, 0x0000 }, /* R96 - Analogue HP (1) */ 203 { 0x0000, 0x0000, 0x0000 }, /* R97 */ 204 { 0x0000, 0x0000, 0x0000 }, /* R98 */ 205 { 0x0000, 0x0000, 0x0000 }, /* R99 */ 206 { 0x0000, 0x0000, 0x0000 }, /* R100 */ 207 { 0x0000, 0x0000, 0x0000 }, /* R101 */ 208 { 0x0000, 0x0000, 0x0000 }, /* R102 */ 209 { 0x0000, 0x0000, 0x0000 }, /* R103 */ 210 { 0x0000, 0x0000, 0x0000 }, /* R104 */ 211 { 0x0000, 0x0000, 0x0000 }, /* R105 */ 212 { 0x0000, 0x0000, 0x0000 }, /* R106 */ 213 { 0x0000, 0x0000, 0x0000 }, /* R107 */ 214 { 0x0000, 0x0000, 0x0000 }, /* R108 */ 215 { 0x0000, 0x0000, 0x0000 }, /* R109 */ 216 { 0x0000, 0x0000, 0x0000 }, /* R110 */ 217 { 0x0000, 0x0000, 0x0000 }, /* R111 */ 218 { 0x0000, 0x0000, 0x0000 }, /* R112 */ 219 { 0x0000, 0x0000, 0x0000 }, /* R113 */ 220 { 0x0000, 0x0000, 0x0000 }, /* R114 */ 221 { 0x0000, 0x0000, 0x0000 }, /* R115 */ 222 { 0x0000, 0x0000, 0x0000 }, /* R116 */ 223 { 0x0000, 0x0000, 0x0000 }, /* R117 */ 224 { 0x0000, 0x0000, 0x0000 }, /* R118 */ 225 { 0x0000, 0x0000, 0x0000 }, /* R119 */ 226 { 0x0000, 0x0000, 0x0000 }, /* R120 */ 227 { 0x0000, 0x0000, 0x0000 }, /* R121 */ 228 { 0x0000, 0x0000, 0x0000 }, /* R122 */ 229 { 0x0000, 0x0000, 0x0000 }, /* R123 */ 230 { 0x0000, 0x0000, 0x0000 }, /* R124 */ 231 { 0x0000, 0x0000, 0x0000 }, /* R125 */ 232 { 0x0000, 0x0000, 0x0000 }, /* R126 */ 233 { 0x0000, 0x0000, 0x0000 }, /* R127 */ 234 { 0x0000, 0x0000, 0x0000 }, /* R128 */ 235 { 0x0000, 0x0000, 0x0000 }, /* R129 */ 236 { 0x0000, 0x0000, 0x0000 }, /* R130 */ 237 { 0x0000, 0x0000, 0x0000 }, /* R131 */ 238 { 0x0000, 0x0000, 0x0000 }, /* R132 */ 239 { 0x0000, 0x0000, 0x0000 }, /* R133 */ 240 { 0x0000, 0x0000, 0x0000 }, /* R134 */ 241 { 0x0000, 0x0000, 0x0000 }, /* R135 */ 242 { 0x0000, 0x0000, 0x0000 }, /* R136 */ 243 { 0x0000, 0x0000, 0x0000 }, /* R137 */ 244 { 0x0000, 0x0000, 0x0000 }, /* R138 */ 245 { 0x0000, 0x0000, 0x0000 }, /* R139 */ 246 { 0x0000, 0x0000, 0x0000 }, /* R140 */ 247 { 0x0000, 0x0000, 0x0000 }, /* R141 */ 248 { 0x0000, 0x0000, 0x0000 }, /* R142 */ 249 { 0x0000, 0x0000, 0x0000 }, /* R143 */ 250 { 0x0000, 0x0000, 0x0000 }, /* R144 */ 251 { 0x0000, 0x0000, 0x0000 }, /* R145 */ 252 { 0x0000, 0x0000, 0x0000 }, /* R146 */ 253 { 0x0000, 0x0000, 0x0000 }, /* R147 */ 254 { 0x0000, 0x0000, 0x0000 }, /* R148 */ 255 { 0x0000, 0x0000, 0x0000 }, /* R149 */ 256 { 0x0000, 0x0000, 0x0000 }, /* R150 */ 257 { 0x0000, 0x0000, 0x0000 }, /* R151 */ 258 { 0x0000, 0x0000, 0x0000 }, /* R152 */ 259 { 0x0000, 0x0000, 0x0000 }, /* R153 */ 260 { 0x0000, 0x0000, 0x0000 }, /* R154 */ 261 { 0x0000, 0x0000, 0x0000 }, /* R155 */ 262 { 0x0000, 0x0000, 0x0000 }, /* R156 */ 263 { 0x0000, 0x0000, 0x0000 }, /* R157 */ 264 { 0x0000, 0x0000, 0x0000 }, /* R158 */ 265 { 0x0000, 0x0000, 0x0000 }, /* R159 */ 266 { 0x0000, 0x0000, 0x0000 }, /* R160 */ 267 { 0x0000, 0x0000, 0x0000 }, /* R161 */ 268 { 0x0000, 0x0000, 0x0000 }, /* R162 */ 269 { 0x0000, 0x0000, 0x0000 }, /* R163 */ 270 { 0x0000, 0x0000, 0x0000 }, /* R164 */ 271 { 0x0000, 0x0000, 0x0000 }, /* R165 */ 272 { 0x0000, 0x0000, 0x0000 }, /* R166 */ 273 { 0x0000, 0x0000, 0x0000 }, /* R167 */ 274 { 0x0000, 0x0000, 0x0000 }, /* R168 */ 275 { 0x0000, 0x0000, 0x0000 }, /* R169 */ 276 { 0x0000, 0x0000, 0x0000 }, /* R170 */ 277 { 0x0000, 0x0000, 0x0000 }, /* R171 */ 278 { 0x0000, 0x0000, 0x0000 }, /* R172 */ 279 { 0x0000, 0x0000, 0x0000 }, /* R173 */ 280 { 0x0000, 0x0000, 0x0000 }, /* R174 */ 281 { 0x0000, 0x0000, 0x0000 }, /* R175 */ 282 { 0x0000, 0x0000, 0x0000 }, /* R176 */ 283 { 0x0000, 0x0000, 0x0000 }, /* R177 */ 284 { 0x0000, 0x0000, 0x0000 }, /* R178 */ 285 { 0x0000, 0x0000, 0x0000 }, /* R179 */ 286 { 0x0000, 0x0000, 0x0000 }, /* R180 */ 287 { 0x0000, 0x0000, 0x0000 }, /* R181 */ 288 { 0x0000, 0x0000, 0x0000 }, /* R182 */ 289 { 0x0000, 0x0000, 0x0000 }, /* R183 */ 290 { 0x0000, 0x0000, 0x0000 }, /* R184 */ 291 { 0x0000, 0x0000, 0x0000 }, /* R185 */ 292 { 0x0000, 0x0000, 0x0000 }, /* R186 */ 293 { 0x0000, 0x0000, 0x0000 }, /* R187 */ 294 { 0x0000, 0x0000, 0x0000 }, /* R188 */ 295 { 0x0000, 0x0000, 0x0000 }, /* R189 */ 296 { 0x0000, 0x0000, 0x0000 }, /* R190 */ 297 { 0x0000, 0x0000, 0x0000 }, /* R191 */ 298 { 0x0000, 0x0000, 0x0000 }, /* R192 */ 299 { 0x0000, 0x0000, 0x0000 }, /* R193 */ 300 { 0x0000, 0x0000, 0x0000 }, /* R194 */ 301 { 0x0000, 0x0000, 0x0000 }, /* R195 */ 302 { 0x0000, 0x0000, 0x0000 }, /* R196 */ 303 { 0x0000, 0x0000, 0x0000 }, /* R197 */ 304 { 0x0000, 0x0000, 0x0000 }, /* R198 */ 305 { 0x0000, 0x0000, 0x0000 }, /* R199 */ 306 { 0x0000, 0x0000, 0x0000 }, /* R200 */ 307 { 0x0000, 0x0000, 0x0000 }, /* R201 */ 308 { 0x0000, 0x0000, 0x0000 }, /* R202 */ 309 { 0x0000, 0x0000, 0x0000 }, /* R203 */ 310 { 0x0000, 0x0000, 0x0000 }, /* R204 */ 311 { 0x0000, 0x0000, 0x0000 }, /* R205 */ 312 { 0x0000, 0x0000, 0x0000 }, /* R206 */ 313 { 0x0000, 0x0000, 0x0000 }, /* R207 */ 314 { 0x0000, 0x0000, 0x0000 }, /* R208 */ 315 { 0x0000, 0x0000, 0x0000 }, /* R209 */ 316 { 0x0000, 0x0000, 0x0000 }, /* R210 */ 317 { 0x0000, 0x0000, 0x0000 }, /* R211 */ 318 { 0x0000, 0x0000, 0x0000 }, /* R212 */ 319 { 0x0000, 0x0000, 0x0000 }, /* R213 */ 320 { 0x0000, 0x0000, 0x0000 }, /* R214 */ 321 { 0x0000, 0x0000, 0x0000 }, /* R215 */ 322 { 0x0000, 0x0000, 0x0000 }, /* R216 */ 323 { 0x0000, 0x0000, 0x0000 }, /* R217 */ 324 { 0x0000, 0x0000, 0x0000 }, /* R218 */ 325 { 0x0000, 0x0000, 0x0000 }, /* R219 */ 326 { 0x0000, 0x0000, 0x0000 }, /* R220 */ 327 { 0x0000, 0x0000, 0x0000 }, /* R221 */ 328 { 0x0000, 0x0000, 0x0000 }, /* R222 */ 329 { 0x0000, 0x0000, 0x0000 }, /* R223 */ 330 { 0x0000, 0x0000, 0x0000 }, /* R224 */ 331 { 0x0000, 0x0000, 0x0000 }, /* R225 */ 332 { 0x0000, 0x0000, 0x0000 }, /* R226 */ 333 { 0x0000, 0x0000, 0x0000 }, /* R227 */ 334 { 0x0000, 0x0000, 0x0000 }, /* R228 */ 335 { 0x0000, 0x0000, 0x0000 }, /* R229 */ 336 { 0x0000, 0x0000, 0x0000 }, /* R230 */ 337 { 0x0000, 0x0000, 0x0000 }, /* R231 */ 338 { 0x0000, 0x0000, 0x0000 }, /* R232 */ 339 { 0x0000, 0x0000, 0x0000 }, /* R233 */ 340 { 0x0000, 0x0000, 0x0000 }, /* R234 */ 341 { 0x0000, 0x0000, 0x0000 }, /* R235 */ 342 { 0x0000, 0x0000, 0x0000 }, /* R236 */ 343 { 0x0000, 0x0000, 0x0000 }, /* R237 */ 344 { 0x0000, 0x0000, 0x0000 }, /* R238 */ 345 { 0x0000, 0x0000, 0x0000 }, /* R239 */ 346 { 0x0000, 0x0000, 0x0000 }, /* R240 */ 347 { 0x0000, 0x0000, 0x0000 }, /* R241 */ 348 { 0x0000, 0x0000, 0x0000 }, /* R242 */ 349 { 0x0000, 0x0000, 0x0000 }, /* R243 */ 350 { 0x0000, 0x0000, 0x0000 }, /* R244 */ 351 { 0x0000, 0x0000, 0x0000 }, /* R245 */ 352 { 0x0000, 0x0000, 0x0000 }, /* R246 */ 353 { 0x0000, 0x0000, 0x0000 }, /* R247 */ 354 { 0x0000, 0x0000, 0x0000 }, /* R248 */ 355 { 0x0000, 0x0000, 0x0000 }, /* R249 */ 356 { 0x0000, 0x0000, 0x0000 }, /* R250 */ 357 { 0x0000, 0x0000, 0x0000 }, /* R251 */ 358 { 0x0000, 0x0000, 0x0000 }, /* R252 */ 359 { 0x0000, 0x0000, 0x0000 }, /* R253 */ 360 { 0x0000, 0x0000, 0x0000 }, /* R254 */ 361 { 0x0000, 0x0000, 0x0000 }, /* R255 */ 362 { 0x000F, 0x0000, 0x0000 }, /* R256 - Chip Revision */ 363 { 0x0074, 0x0074, 0x0000 }, /* R257 - Control Interface */ 364 { 0x0000, 0x0000, 0x0000 }, /* R258 */ 365 { 0x0000, 0x0000, 0x0000 }, /* R259 */ 366 { 0x0000, 0x0000, 0x0000 }, /* R260 */ 367 { 0x0000, 0x0000, 0x0000 }, /* R261 */ 368 { 0x0000, 0x0000, 0x0000 }, /* R262 */ 369 { 0x0000, 0x0000, 0x0000 }, /* R263 */ 370 { 0x0000, 0x0000, 0x0000 }, /* R264 */ 371 { 0x0000, 0x0000, 0x0000 }, /* R265 */ 372 { 0x0000, 0x0000, 0x0000 }, /* R266 */ 373 { 0x0000, 0x0000, 0x0000 }, /* R267 */ 374 { 0x0000, 0x0000, 0x0000 }, /* R268 */ 375 { 0x0000, 0x0000, 0x0000 }, /* R269 */ 376 { 0x0000, 0x0000, 0x0000 }, /* R270 */ 377 { 0x0000, 0x0000, 0x0000 }, /* R271 */ 378 { 0x807F, 0x837F, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */ 379 { 0x017F, 0x0000, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ 380 { 0x0000, 0x0000, 0x0000 }, /* R274 */ 381 { 0x0000, 0x0000, 0x0000 }, /* R275 */ 382 { 0x0000, 0x0000, 0x0000 }, /* R276 */ 383 { 0x0000, 0x0000, 0x0000 }, /* R277 */ 384 { 0x0000, 0x0000, 0x0000 }, /* R278 */ 385 { 0x0000, 0x0000, 0x0000 }, /* R279 */ 386 { 0x0000, 0x0000, 0x0000 }, /* R280 */ 387 { 0x0000, 0x0000, 0x0000 }, /* R281 */ 388 { 0x0000, 0x0000, 0x0000 }, /* R282 */ 389 { 0x0000, 0x0000, 0x0000 }, /* R283 */ 390 { 0x0000, 0x0000, 0x0000 }, /* R284 */ 391 { 0x0000, 0x0000, 0x0000 }, /* R285 */ 392 { 0x0000, 0x0000, 0x0000 }, /* R286 */ 393 { 0x0000, 0x0000, 0x0000 }, /* R287 */ 394 { 0x0000, 0x0000, 0x0000 }, /* R288 */ 395 { 0x0000, 0x0000, 0x0000 }, /* R289 */ 396 { 0x0000, 0x0000, 0x0000 }, /* R290 */ 397 { 0x0000, 0x0000, 0x0000 }, /* R291 */ 398 { 0x0000, 0x0000, 0x0000 }, /* R292 */ 399 { 0x0000, 0x0000, 0x0000 }, /* R293 */ 400 { 0x0000, 0x0000, 0x0000 }, /* R294 */ 401 { 0x0000, 0x0000, 0x0000 }, /* R295 */ 402 { 0x0000, 0x0000, 0x0000 }, /* R296 */ 403 { 0x0000, 0x0000, 0x0000 }, /* R297 */ 404 { 0x0000, 0x0000, 0x0000 }, /* R298 */ 405 { 0x0000, 0x0000, 0x0000 }, /* R299 */ 406 { 0x0000, 0x0000, 0x0000 }, /* R300 */ 407 { 0x0000, 0x0000, 0x0000 }, /* R301 */ 408 { 0x0000, 0x0000, 0x0000 }, /* R302 */ 409 { 0x0000, 0x0000, 0x0000 }, /* R303 */ 410 { 0x0000, 0x0000, 0x0000 }, /* R304 */ 411 { 0x0000, 0x0000, 0x0000 }, /* R305 */ 412 { 0x0000, 0x0000, 0x0000 }, /* R306 */ 413 { 0x0000, 0x0000, 0x0000 }, /* R307 */ 414 { 0x0000, 0x0000, 0x0000 }, /* R308 */ 415 { 0x0000, 0x0000, 0x0000 }, /* R309 */ 416 { 0x0000, 0x0000, 0x0000 }, /* R310 */ 417 { 0x0000, 0x0000, 0x0000 }, /* R311 */ 418 { 0x0000, 0x0000, 0x0000 }, /* R312 */ 419 { 0x0000, 0x0000, 0x0000 }, /* R313 */ 420 { 0x0000, 0x0000, 0x0000 }, /* R314 */ 421 { 0x0000, 0x0000, 0x0000 }, /* R315 */ 422 { 0x0000, 0x0000, 0x0000 }, /* R316 */ 423 { 0x0000, 0x0000, 0x0000 }, /* R317 */ 424 { 0x0000, 0x0000, 0x0000 }, /* R318 */ 425 { 0x0000, 0x0000, 0x0000 }, /* R319 */ 426 { 0x0000, 0x0000, 0x0000 }, /* R320 */ 427 { 0x0000, 0x0000, 0x0000 }, /* R321 */ 428 { 0x0000, 0x0000, 0x0000 }, /* R322 */ 429 { 0x0000, 0x0000, 0x0000 }, /* R323 */ 430 { 0x0000, 0x0000, 0x0000 }, /* R324 */ 431 { 0x0000, 0x0000, 0x0000 }, /* R325 */ 432 { 0x0000, 0x0000, 0x0000 }, /* R326 */ 433 { 0x0000, 0x0000, 0x0000 }, /* R327 */ 434 { 0x0000, 0x0000, 0x0000 }, /* R328 */ 435 { 0x0000, 0x0000, 0x0000 }, /* R329 */ 436 { 0x0000, 0x0000, 0x0000 }, /* R330 */ 437 { 0x0000, 0x0000, 0x0000 }, /* R331 */ 438 { 0x0000, 0x0000, 0x0000 }, /* R332 */ 439 { 0x0000, 0x0000, 0x0000 }, /* R333 */ 440 { 0x0000, 0x0000, 0x0000 }, /* R334 */ 441 { 0x0000, 0x0000, 0x0000 }, /* R335 */ 442 { 0x0000, 0x0000, 0x0000 }, /* R336 */ 443 { 0x0000, 0x0000, 0x0000 }, /* R337 */ 444 { 0x0000, 0x0000, 0x0000 }, /* R338 */ 445 { 0x0000, 0x0000, 0x0000 }, /* R339 */ 446 { 0x0000, 0x0000, 0x0000 }, /* R340 */ 447 { 0x0000, 0x0000, 0x0000 }, /* R341 */ 448 { 0x0000, 0x0000, 0x0000 }, /* R342 */ 449 { 0x0000, 0x0000, 0x0000 }, /* R343 */ 450 { 0x0000, 0x0000, 0x0000 }, /* R344 */ 451 { 0x0000, 0x0000, 0x0000 }, /* R345 */ 452 { 0x0000, 0x0000, 0x0000 }, /* R346 */ 453 { 0x0000, 0x0000, 0x0000 }, /* R347 */ 454 { 0x0000, 0x0000, 0x0000 }, /* R348 */ 455 { 0x0000, 0x0000, 0x0000 }, /* R349 */ 456 { 0x0000, 0x0000, 0x0000 }, /* R350 */ 457 { 0x0000, 0x0000, 0x0000 }, /* R351 */ 458 { 0x0000, 0x0000, 0x0000 }, /* R352 */ 459 { 0x0000, 0x0000, 0x0000 }, /* R353 */ 460 { 0x0000, 0x0000, 0x0000 }, /* R354 */ 461 { 0x0000, 0x0000, 0x0000 }, /* R355 */ 462 { 0x0000, 0x0000, 0x0000 }, /* R356 */ 463 { 0x0000, 0x0000, 0x0000 }, /* R357 */ 464 { 0x0000, 0x0000, 0x0000 }, /* R358 */ 465 { 0x0000, 0x0000, 0x0000 }, /* R359 */ 466 { 0x0000, 0x0000, 0x0000 }, /* R360 */ 467 { 0x0000, 0x0000, 0x0000 }, /* R361 */ 468 { 0x0000, 0x0000, 0x0000 }, /* R362 */ 469 { 0x0000, 0x0000, 0x0000 }, /* R363 */ 470 { 0x0000, 0x0000, 0x0000 }, /* R364 */ 471 { 0x0000, 0x0000, 0x0000 }, /* R365 */ 472 { 0x0000, 0x0000, 0x0000 }, /* R366 */ 473 { 0x0000, 0x0000, 0x0000 }, /* R367 */ 474 { 0x0000, 0x0000, 0x0000 }, /* R368 */ 475 { 0x0000, 0x0000, 0x0000 }, /* R369 */ 476 { 0x0000, 0x0000, 0x0000 }, /* R370 */ 477 { 0x0000, 0x0000, 0x0000 }, /* R371 */ 478 { 0x0000, 0x0000, 0x0000 }, /* R372 */ 479 { 0x0000, 0x0000, 0x0000 }, /* R373 */ 480 { 0x0000, 0x0000, 0x0000 }, /* R374 */ 481 { 0x0000, 0x0000, 0x0000 }, /* R375 */ 482 { 0x0000, 0x0000, 0x0000 }, /* R376 */ 483 { 0x0000, 0x0000, 0x0000 }, /* R377 */ 484 { 0x0000, 0x0000, 0x0000 }, /* R378 */ 485 { 0x0000, 0x0000, 0x0000 }, /* R379 */ 486 { 0x0000, 0x0000, 0x0000 }, /* R380 */ 487 { 0x0000, 0x0000, 0x0000 }, /* R381 */ 488 { 0x0000, 0x0000, 0x0000 }, /* R382 */ 489 { 0x0000, 0x0000, 0x0000 }, /* R383 */ 490 { 0x0000, 0x0000, 0x0000 }, /* R384 */ 491 { 0x0000, 0x0000, 0x0000 }, /* R385 */ 492 { 0x0000, 0x0000, 0x0000 }, /* R386 */ 493 { 0x0000, 0x0000, 0x0000 }, /* R387 */ 494 { 0x0000, 0x0000, 0x0000 }, /* R388 */ 495 { 0x0000, 0x0000, 0x0000 }, /* R389 */ 496 { 0x0000, 0x0000, 0x0000 }, /* R390 */ 497 { 0x0000, 0x0000, 0x0000 }, /* R391 */ 498 { 0x0000, 0x0000, 0x0000 }, /* R392 */ 499 { 0x0000, 0x0000, 0x0000 }, /* R393 */ 500 { 0x0000, 0x0000, 0x0000 }, /* R394 */ 501 { 0x0000, 0x0000, 0x0000 }, /* R395 */ 502 { 0x0000, 0x0000, 0x0000 }, /* R396 */ 503 { 0x0000, 0x0000, 0x0000 }, /* R397 */ 504 { 0x0000, 0x0000, 0x0000 }, /* R398 */ 505 { 0x0000, 0x0000, 0x0000 }, /* R399 */ 506 { 0x0000, 0x0000, 0x0000 }, /* R400 */ 507 { 0x0000, 0x0000, 0x0000 }, /* R401 */ 508 { 0x0000, 0x0000, 0x0000 }, /* R402 */ 509 { 0x0000, 0x0000, 0x0000 }, /* R403 */ 510 { 0x0000, 0x0000, 0x0000 }, /* R404 */ 511 { 0x0000, 0x0000, 0x0000 }, /* R405 */ 512 { 0x0000, 0x0000, 0x0000 }, /* R406 */ 513 { 0x0000, 0x0000, 0x0000 }, /* R407 */ 514 { 0x0000, 0x0000, 0x0000 }, /* R408 */ 515 { 0x0000, 0x0000, 0x0000 }, /* R409 */ 516 { 0x0000, 0x0000, 0x0000 }, /* R410 */ 517 { 0x0000, 0x0000, 0x0000 }, /* R411 */ 518 { 0x0000, 0x0000, 0x0000 }, /* R412 */ 519 { 0x0000, 0x0000, 0x0000 }, /* R413 */ 520 { 0x0000, 0x0000, 0x0000 }, /* R414 */ 521 { 0x0000, 0x0000, 0x0000 }, /* R415 */ 522 { 0x0000, 0x0000, 0x0000 }, /* R416 */ 523 { 0x0000, 0x0000, 0x0000 }, /* R417 */ 524 { 0x0000, 0x0000, 0x0000 }, /* R418 */ 525 { 0x0000, 0x0000, 0x0000 }, /* R419 */ 526 { 0x0000, 0x0000, 0x0000 }, /* R420 */ 527 { 0x0000, 0x0000, 0x0000 }, /* R421 */ 528 { 0x0000, 0x0000, 0x0000 }, /* R422 */ 529 { 0x0000, 0x0000, 0x0000 }, /* R423 */ 530 { 0x0000, 0x0000, 0x0000 }, /* R424 */ 531 { 0x0000, 0x0000, 0x0000 }, /* R425 */ 532 { 0x0000, 0x0000, 0x0000 }, /* R426 */ 533 { 0x0000, 0x0000, 0x0000 }, /* R427 */ 534 { 0x0000, 0x0000, 0x0000 }, /* R428 */ 535 { 0x0000, 0x0000, 0x0000 }, /* R429 */ 536 { 0x0000, 0x0000, 0x0000 }, /* R430 */ 537 { 0x0000, 0x0000, 0x0000 }, /* R431 */ 538 { 0x0000, 0x0000, 0x0000 }, /* R432 */ 539 { 0x0000, 0x0000, 0x0000 }, /* R433 */ 540 { 0x0000, 0x0000, 0x0000 }, /* R434 */ 541 { 0x0000, 0x0000, 0x0000 }, /* R435 */ 542 { 0x0000, 0x0000, 0x0000 }, /* R436 */ 543 { 0x0000, 0x0000, 0x0000 }, /* R437 */ 544 { 0x0000, 0x0000, 0x0000 }, /* R438 */ 545 { 0x0000, 0x0000, 0x0000 }, /* R439 */ 546 { 0x0000, 0x0000, 0x0000 }, /* R440 */ 547 { 0x0000, 0x0000, 0x0000 }, /* R441 */ 548 { 0x0000, 0x0000, 0x0000 }, /* R442 */ 549 { 0x0000, 0x0000, 0x0000 }, /* R443 */ 550 { 0x0000, 0x0000, 0x0000 }, /* R444 */ 551 { 0x0000, 0x0000, 0x0000 }, /* R445 */ 552 { 0x0000, 0x0000, 0x0000 }, /* R446 */ 553 { 0x0000, 0x0000, 0x0000 }, /* R447 */ 554 { 0x0000, 0x0000, 0x0000 }, /* R448 */ 555 { 0x0000, 0x0000, 0x0000 }, /* R449 */ 556 { 0x0000, 0x0000, 0x0000 }, /* R450 */ 557 { 0x0000, 0x0000, 0x0000 }, /* R451 */ 558 { 0x0000, 0x0000, 0x0000 }, /* R452 */ 559 { 0x0000, 0x0000, 0x0000 }, /* R453 */ 560 { 0x0000, 0x0000, 0x0000 }, /* R454 */ 561 { 0x0000, 0x0000, 0x0000 }, /* R455 */ 562 { 0x0000, 0x0000, 0x0000 }, /* R456 */ 563 { 0x0000, 0x0000, 0x0000 }, /* R457 */ 564 { 0x0000, 0x0000, 0x0000 }, /* R458 */ 565 { 0x0000, 0x0000, 0x0000 }, /* R459 */ 566 { 0x0000, 0x0000, 0x0000 }, /* R460 */ 567 { 0x0000, 0x0000, 0x0000 }, /* R461 */ 568 { 0x0000, 0x0000, 0x0000 }, /* R462 */ 569 { 0x0000, 0x0000, 0x0000 }, /* R463 */ 570 { 0x0000, 0x0000, 0x0000 }, /* R464 */ 571 { 0x0000, 0x0000, 0x0000 }, /* R465 */ 572 { 0x0000, 0x0000, 0x0000 }, /* R466 */ 573 { 0x0000, 0x0000, 0x0000 }, /* R467 */ 574 { 0x0000, 0x0000, 0x0000 }, /* R468 */ 575 { 0x0000, 0x0000, 0x0000 }, /* R469 */ 576 { 0x0000, 0x0000, 0x0000 }, /* R470 */ 577 { 0x0000, 0x0000, 0x0000 }, /* R471 */ 578 { 0x0000, 0x0000, 0x0000 }, /* R472 */ 579 { 0x0000, 0x0000, 0x0000 }, /* R473 */ 580 { 0x0000, 0x0000, 0x0000 }, /* R474 */ 581 { 0x0000, 0x0000, 0x0000 }, /* R475 */ 582 { 0x0000, 0x0000, 0x0000 }, /* R476 */ 583 { 0x0000, 0x0000, 0x0000 }, /* R477 */ 584 { 0x0000, 0x0000, 0x0000 }, /* R478 */ 585 { 0x0000, 0x0000, 0x0000 }, /* R479 */ 586 { 0x0000, 0x0000, 0x0000 }, /* R480 */ 587 { 0x0000, 0x0000, 0x0000 }, /* R481 */ 588 { 0x0000, 0x0000, 0x0000 }, /* R482 */ 589 { 0x0000, 0x0000, 0x0000 }, /* R483 */ 590 { 0x0000, 0x0000, 0x0000 }, /* R484 */ 591 { 0x0000, 0x0000, 0x0000 }, /* R485 */ 592 { 0x0000, 0x0000, 0x0000 }, /* R486 */ 593 { 0x0000, 0x0000, 0x0000 }, /* R487 */ 594 { 0x0000, 0x0000, 0x0000 }, /* R488 */ 595 { 0x0000, 0x0000, 0x0000 }, /* R489 */ 596 { 0x0000, 0x0000, 0x0000 }, /* R490 */ 597 { 0x0000, 0x0000, 0x0000 }, /* R491 */ 598 { 0x0000, 0x0000, 0x0000 }, /* R492 */ 599 { 0x0000, 0x0000, 0x0000 }, /* R493 */ 600 { 0x0000, 0x0000, 0x0000 }, /* R494 */ 601 { 0x0000, 0x0000, 0x0000 }, /* R495 */ 602 { 0x0000, 0x0000, 0x0000 }, /* R496 */ 603 { 0x0000, 0x0000, 0x0000 }, /* R497 */ 604 { 0x0000, 0x0000, 0x0000 }, /* R498 */ 605 { 0x0000, 0x0000, 0x0000 }, /* R499 */ 606 { 0x0000, 0x0000, 0x0000 }, /* R500 */ 607 { 0x0000, 0x0000, 0x0000 }, /* R501 */ 608 { 0x0000, 0x0000, 0x0000 }, /* R502 */ 609 { 0x0000, 0x0000, 0x0000 }, /* R503 */ 610 { 0x0000, 0x0000, 0x0000 }, /* R504 */ 611 { 0x0000, 0x0000, 0x0000 }, /* R505 */ 612 { 0x0000, 0x0000, 0x0000 }, /* R506 */ 613 { 0x0000, 0x0000, 0x0000 }, /* R507 */ 614 { 0x0000, 0x0000, 0x0000 }, /* R508 */ 615 { 0x0000, 0x0000, 0x0000 }, /* R509 */ 616 { 0x0000, 0x0000, 0x0000 }, /* R510 */ 617 { 0x0000, 0x0000, 0x0000 }, /* R511 */ 618 { 0x001F, 0x001F, 0x0000 }, /* R512 - AIF1 Clocking (1) */ 619 { 0x003F, 0x003F, 0x0000 }, /* R513 - AIF1 Clocking (2) */ 620 { 0x0000, 0x0000, 0x0000 }, /* R514 */ 621 { 0x0000, 0x0000, 0x0000 }, /* R515 */ 622 { 0x001F, 0x001F, 0x0000 }, /* R516 - AIF2 Clocking (1) */ 623 { 0x003F, 0x003F, 0x0000 }, /* R517 - AIF2 Clocking (2) */ 624 { 0x0000, 0x0000, 0x0000 }, /* R518 */ 625 { 0x0000, 0x0000, 0x0000 }, /* R519 */ 626 { 0x001F, 0x001F, 0x0000 }, /* R520 - Clocking (1) */ 627 { 0x0777, 0x0777, 0x0000 }, /* R521 - Clocking (2) */ 628 { 0x0000, 0x0000, 0x0000 }, /* R522 */ 629 { 0x0000, 0x0000, 0x0000 }, /* R523 */ 630 { 0x0000, 0x0000, 0x0000 }, /* R524 */ 631 { 0x0000, 0x0000, 0x0000 }, /* R525 */ 632 { 0x0000, 0x0000, 0x0000 }, /* R526 */ 633 { 0x0000, 0x0000, 0x0000 }, /* R527 */ 634 { 0x00FF, 0x00FF, 0x0000 }, /* R528 - AIF1 Rate */ 635 { 0x00FF, 0x00FF, 0x0000 }, /* R529 - AIF2 Rate */ 636 { 0x000F, 0x0000, 0x0000 }, /* R530 - Rate Status */ 637 { 0x0000, 0x0000, 0x0000 }, /* R531 */ 638 { 0x0000, 0x0000, 0x0000 }, /* R532 */ 639 { 0x0000, 0x0000, 0x0000 }, /* R533 */ 640 { 0x0000, 0x0000, 0x0000 }, /* R534 */ 641 { 0x0000, 0x0000, 0x0000 }, /* R535 */ 642 { 0x0000, 0x0000, 0x0000 }, /* R536 */ 643 { 0x0000, 0x0000, 0x0000 }, /* R537 */ 644 { 0x0000, 0x0000, 0x0000 }, /* R538 */ 645 { 0x0000, 0x0000, 0x0000 }, /* R539 */ 646 { 0x0000, 0x0000, 0x0000 }, /* R540 */ 647 { 0x0000, 0x0000, 0x0000 }, /* R541 */ 648 { 0x0000, 0x0000, 0x0000 }, /* R542 */ 649 { 0x0000, 0x0000, 0x0000 }, /* R543 */ 650 { 0x0007, 0x0007, 0x0000 }, /* R544 - FLL1 Control (1) */ 651 { 0x3F77, 0x3F77, 0x0000 }, /* R545 - FLL1 Control (2) */ 652 { 0xFFFF, 0xFFFF, 0x0000 }, /* R546 - FLL1 Control (3) */ 653 { 0x7FEF, 0x7FEF, 0x0000 }, /* R547 - FLL1 Control (4) */ 654 { 0x1FDB, 0x1FDB, 0x0000 }, /* R548 - FLL1 Control (5) */ 655 { 0x0000, 0x0000, 0x0000 }, /* R549 */ 656 { 0x0000, 0x0000, 0x0000 }, /* R550 */ 657 { 0x0000, 0x0000, 0x0000 }, /* R551 */ 658 { 0x0000, 0x0000, 0x0000 }, /* R552 */ 659 { 0x0000, 0x0000, 0x0000 }, /* R553 */ 660 { 0x0000, 0x0000, 0x0000 }, /* R554 */ 661 { 0x0000, 0x0000, 0x0000 }, /* R555 */ 662 { 0x0000, 0x0000, 0x0000 }, /* R556 */ 663 { 0x0000, 0x0000, 0x0000 }, /* R557 */ 664 { 0x0000, 0x0000, 0x0000 }, /* R558 */ 665 { 0x0000, 0x0000, 0x0000 }, /* R559 */ 666 { 0x0000, 0x0000, 0x0000 }, /* R560 */ 667 { 0x0000, 0x0000, 0x0000 }, /* R561 */ 668 { 0x0000, 0x0000, 0x0000 }, /* R562 */ 669 { 0x0000, 0x0000, 0x0000 }, /* R563 */ 670 { 0x0000, 0x0000, 0x0000 }, /* R564 */ 671 { 0x0000, 0x0000, 0x0000 }, /* R565 */ 672 { 0x0000, 0x0000, 0x0000 }, /* R566 */ 673 { 0x0000, 0x0000, 0x0000 }, /* R567 */ 674 { 0x0000, 0x0000, 0x0000 }, /* R568 */ 675 { 0x0000, 0x0000, 0x0000 }, /* R569 */ 676 { 0x0000, 0x0000, 0x0000 }, /* R570 */ 677 { 0x0000, 0x0000, 0x0000 }, /* R571 */ 678 { 0x0000, 0x0000, 0x0000 }, /* R572 */ 679 { 0x0000, 0x0000, 0x0000 }, /* R573 */ 680 { 0x0000, 0x0000, 0x0000 }, /* R574 */ 681 { 0x0000, 0x0000, 0x0000 }, /* R575 */ 682 { 0x0007, 0x0007, 0x0000 }, /* R576 - FLL2 Control (1) */ 683 { 0x3F77, 0x3F77, 0x0000 }, /* R577 - FLL2 Control (2) */ 684 { 0xFFFF, 0xFFFF, 0x0000 }, /* R578 - FLL2 Control (3) */ 685 { 0x7FEF, 0x7FEF, 0x0000 }, /* R579 - FLL2 Control (4) */ 686 { 0x1FDB, 0x1FDB, 0x0000 }, /* R580 - FLL2 Control (5) */ 687 { 0x0000, 0x0000, 0x0000 }, /* R581 */ 688 { 0x0000, 0x0000, 0x0000 }, /* R582 */ 689 { 0x0000, 0x0000, 0x0000 }, /* R583 */ 690 { 0x0000, 0x0000, 0x0000 }, /* R584 */ 691 { 0x0000, 0x0000, 0x0000 }, /* R585 */ 692 { 0x0000, 0x0000, 0x0000 }, /* R586 */ 693 { 0x0000, 0x0000, 0x0000 }, /* R587 */ 694 { 0x0000, 0x0000, 0x0000 }, /* R588 */ 695 { 0x0000, 0x0000, 0x0000 }, /* R589 */ 696 { 0x0000, 0x0000, 0x0000 }, /* R590 */ 697 { 0x0000, 0x0000, 0x0000 }, /* R591 */ 698 { 0x0000, 0x0000, 0x0000 }, /* R592 */ 699 { 0x0000, 0x0000, 0x0000 }, /* R593 */ 700 { 0x0000, 0x0000, 0x0000 }, /* R594 */ 701 { 0x0000, 0x0000, 0x0000 }, /* R595 */ 702 { 0x0000, 0x0000, 0x0000 }, /* R596 */ 703 { 0x0000, 0x0000, 0x0000 }, /* R597 */ 704 { 0x0000, 0x0000, 0x0000 }, /* R598 */ 705 { 0x0000, 0x0000, 0x0000 }, /* R599 */ 706 { 0x0000, 0x0000, 0x0000 }, /* R600 */ 707 { 0x0000, 0x0000, 0x0000 }, /* R601 */ 708 { 0x0000, 0x0000, 0x0000 }, /* R602 */ 709 { 0x0000, 0x0000, 0x0000 }, /* R603 */ 710 { 0x0000, 0x0000, 0x0000 }, /* R604 */ 711 { 0x0000, 0x0000, 0x0000 }, /* R605 */ 712 { 0x0000, 0x0000, 0x0000 }, /* R606 */ 713 { 0x0000, 0x0000, 0x0000 }, /* R607 */ 714 { 0x0000, 0x0000, 0x0000 }, /* R608 */ 715 { 0x0000, 0x0000, 0x0000 }, /* R609 */ 716 { 0x0000, 0x0000, 0x0000 }, /* R610 */ 717 { 0x0000, 0x0000, 0x0000 }, /* R611 */ 718 { 0x0000, 0x0000, 0x0000 }, /* R612 */ 719 { 0x0000, 0x0000, 0x0000 }, /* R613 */ 720 { 0x0000, 0x0000, 0x0000 }, /* R614 */ 721 { 0x0000, 0x0000, 0x0000 }, /* R615 */ 722 { 0x0000, 0x0000, 0x0000 }, /* R616 */ 723 { 0x0000, 0x0000, 0x0000 }, /* R617 */ 724 { 0x0000, 0x0000, 0x0000 }, /* R618 */ 725 { 0x0000, 0x0000, 0x0000 }, /* R619 */ 726 { 0x0000, 0x0000, 0x0000 }, /* R620 */ 727 { 0x0000, 0x0000, 0x0000 }, /* R621 */ 728 { 0x0000, 0x0000, 0x0000 }, /* R622 */ 729 { 0x0000, 0x0000, 0x0000 }, /* R623 */ 730 { 0x0000, 0x0000, 0x0000 }, /* R624 */ 731 { 0x0000, 0x0000, 0x0000 }, /* R625 */ 732 { 0x0000, 0x0000, 0x0000 }, /* R626 */ 733 { 0x0000, 0x0000, 0x0000 }, /* R627 */ 734 { 0x0000, 0x0000, 0x0000 }, /* R628 */ 735 { 0x0000, 0x0000, 0x0000 }, /* R629 */ 736 { 0x0000, 0x0000, 0x0000 }, /* R630 */ 737 { 0x0000, 0x0000, 0x0000 }, /* R631 */ 738 { 0x0000, 0x0000, 0x0000 }, /* R632 */ 739 { 0x0000, 0x0000, 0x0000 }, /* R633 */ 740 { 0x0000, 0x0000, 0x0000 }, /* R634 */ 741 { 0x0000, 0x0000, 0x0000 }, /* R635 */ 742 { 0x0000, 0x0000, 0x0000 }, /* R636 */ 743 { 0x0000, 0x0000, 0x0000 }, /* R637 */ 744 { 0x0000, 0x0000, 0x0000 }, /* R638 */ 745 { 0x0000, 0x0000, 0x0000 }, /* R639 */ 746 { 0x0000, 0x0000, 0x0000 }, /* R640 */ 747 { 0x0000, 0x0000, 0x0000 }, /* R641 */ 748 { 0x0000, 0x0000, 0x0000 }, /* R642 */ 749 { 0x0000, 0x0000, 0x0000 }, /* R643 */ 750 { 0x0000, 0x0000, 0x0000 }, /* R644 */ 751 { 0x0000, 0x0000, 0x0000 }, /* R645 */ 752 { 0x0000, 0x0000, 0x0000 }, /* R646 */ 753 { 0x0000, 0x0000, 0x0000 }, /* R647 */ 754 { 0x0000, 0x0000, 0x0000 }, /* R648 */ 755 { 0x0000, 0x0000, 0x0000 }, /* R649 */ 756 { 0x0000, 0x0000, 0x0000 }, /* R650 */ 757 { 0x0000, 0x0000, 0x0000 }, /* R651 */ 758 { 0x0000, 0x0000, 0x0000 }, /* R652 */ 759 { 0x0000, 0x0000, 0x0000 }, /* R653 */ 760 { 0x0000, 0x0000, 0x0000 }, /* R654 */ 761 { 0x0000, 0x0000, 0x0000 }, /* R655 */ 762 { 0x0000, 0x0000, 0x0000 }, /* R656 */ 763 { 0x0000, 0x0000, 0x0000 }, /* R657 */ 764 { 0x0000, 0x0000, 0x0000 }, /* R658 */ 765 { 0x0000, 0x0000, 0x0000 }, /* R659 */ 766 { 0x0000, 0x0000, 0x0000 }, /* R660 */ 767 { 0x0000, 0x0000, 0x0000 }, /* R661 */ 768 { 0x0000, 0x0000, 0x0000 }, /* R662 */ 769 { 0x0000, 0x0000, 0x0000 }, /* R663 */ 770 { 0x0000, 0x0000, 0x0000 }, /* R664 */ 771 { 0x0000, 0x0000, 0x0000 }, /* R665 */ 772 { 0x0000, 0x0000, 0x0000 }, /* R666 */ 773 { 0x0000, 0x0000, 0x0000 }, /* R667 */ 774 { 0x0000, 0x0000, 0x0000 }, /* R668 */ 775 { 0x0000, 0x0000, 0x0000 }, /* R669 */ 776 { 0x0000, 0x0000, 0x0000 }, /* R670 */ 777 { 0x0000, 0x0000, 0x0000 }, /* R671 */ 778 { 0x0000, 0x0000, 0x0000 }, /* R672 */ 779 { 0x0000, 0x0000, 0x0000 }, /* R673 */ 780 { 0x0000, 0x0000, 0x0000 }, /* R674 */ 781 { 0x0000, 0x0000, 0x0000 }, /* R675 */ 782 { 0x0000, 0x0000, 0x0000 }, /* R676 */ 783 { 0x0000, 0x0000, 0x0000 }, /* R677 */ 784 { 0x0000, 0x0000, 0x0000 }, /* R678 */ 785 { 0x0000, 0x0000, 0x0000 }, /* R679 */ 786 { 0x0000, 0x0000, 0x0000 }, /* R680 */ 787 { 0x0000, 0x0000, 0x0000 }, /* R681 */ 788 { 0x0000, 0x0000, 0x0000 }, /* R682 */ 789 { 0x0000, 0x0000, 0x0000 }, /* R683 */ 790 { 0x0000, 0x0000, 0x0000 }, /* R684 */ 791 { 0x0000, 0x0000, 0x0000 }, /* R685 */ 792 { 0x0000, 0x0000, 0x0000 }, /* R686 */ 793 { 0x0000, 0x0000, 0x0000 }, /* R687 */ 794 { 0x0000, 0x0000, 0x0000 }, /* R688 */ 795 { 0x0000, 0x0000, 0x0000 }, /* R689 */ 796 { 0x0000, 0x0000, 0x0000 }, /* R690 */ 797 { 0x0000, 0x0000, 0x0000 }, /* R691 */ 798 { 0x0000, 0x0000, 0x0000 }, /* R692 */ 799 { 0x0000, 0x0000, 0x0000 }, /* R693 */ 800 { 0x0000, 0x0000, 0x0000 }, /* R694 */ 801 { 0x0000, 0x0000, 0x0000 }, /* R695 */ 802 { 0x0000, 0x0000, 0x0000 }, /* R696 */ 803 { 0x0000, 0x0000, 0x0000 }, /* R697 */ 804 { 0x0000, 0x0000, 0x0000 }, /* R698 */ 805 { 0x0000, 0x0000, 0x0000 }, /* R699 */ 806 { 0x0000, 0x0000, 0x0000 }, /* R700 */ 807 { 0x0000, 0x0000, 0x0000 }, /* R701 */ 808 { 0x0000, 0x0000, 0x0000 }, /* R702 */ 809 { 0x0000, 0x0000, 0x0000 }, /* R703 */ 810 { 0x0000, 0x0000, 0x0000 }, /* R704 */ 811 { 0x0000, 0x0000, 0x0000 }, /* R705 */ 812 { 0x0000, 0x0000, 0x0000 }, /* R706 */ 813 { 0x0000, 0x0000, 0x0000 }, /* R707 */ 814 { 0x0000, 0x0000, 0x0000 }, /* R708 */ 815 { 0x0000, 0x0000, 0x0000 }, /* R709 */ 816 { 0x0000, 0x0000, 0x0000 }, /* R710 */ 817 { 0x0000, 0x0000, 0x0000 }, /* R711 */ 818 { 0x0000, 0x0000, 0x0000 }, /* R712 */ 819 { 0x0000, 0x0000, 0x0000 }, /* R713 */ 820 { 0x0000, 0x0000, 0x0000 }, /* R714 */ 821 { 0x0000, 0x0000, 0x0000 }, /* R715 */ 822 { 0x0000, 0x0000, 0x0000 }, /* R716 */ 823 { 0x0000, 0x0000, 0x0000 }, /* R717 */ 824 { 0x0000, 0x0000, 0x0000 }, /* R718 */ 825 { 0x0000, 0x0000, 0x0000 }, /* R719 */ 826 { 0x0000, 0x0000, 0x0000 }, /* R720 */ 827 { 0x0000, 0x0000, 0x0000 }, /* R721 */ 828 { 0x0000, 0x0000, 0x0000 }, /* R722 */ 829 { 0x0000, 0x0000, 0x0000 }, /* R723 */ 830 { 0x0000, 0x0000, 0x0000 }, /* R724 */ 831 { 0x0000, 0x0000, 0x0000 }, /* R725 */ 832 { 0x0000, 0x0000, 0x0000 }, /* R726 */ 833 { 0x0000, 0x0000, 0x0000 }, /* R727 */ 834 { 0x0000, 0x0000, 0x0000 }, /* R728 */ 835 { 0x0000, 0x0000, 0x0000 }, /* R729 */ 836 { 0x0000, 0x0000, 0x0000 }, /* R730 */ 837 { 0x0000, 0x0000, 0x0000 }, /* R731 */ 838 { 0x0000, 0x0000, 0x0000 }, /* R732 */ 839 { 0x0000, 0x0000, 0x0000 }, /* R733 */ 840 { 0x0000, 0x0000, 0x0000 }, /* R734 */ 841 { 0x0000, 0x0000, 0x0000 }, /* R735 */ 842 { 0x0000, 0x0000, 0x0000 }, /* R736 */ 843 { 0x0000, 0x0000, 0x0000 }, /* R737 */ 844 { 0x0000, 0x0000, 0x0000 }, /* R738 */ 845 { 0x0000, 0x0000, 0x0000 }, /* R739 */ 846 { 0x0000, 0x0000, 0x0000 }, /* R740 */ 847 { 0x0000, 0x0000, 0x0000 }, /* R741 */ 848 { 0x0000, 0x0000, 0x0000 }, /* R742 */ 849 { 0x0000, 0x0000, 0x0000 }, /* R743 */ 850 { 0x0000, 0x0000, 0x0000 }, /* R744 */ 851 { 0x0000, 0x0000, 0x0000 }, /* R745 */ 852 { 0x0000, 0x0000, 0x0000 }, /* R746 */ 853 { 0x0000, 0x0000, 0x0000 }, /* R747 */ 854 { 0x0000, 0x0000, 0x0000 }, /* R748 */ 855 { 0x0000, 0x0000, 0x0000 }, /* R749 */ 856 { 0x0000, 0x0000, 0x0000 }, /* R750 */ 857 { 0x0000, 0x0000, 0x0000 }, /* R751 */ 858 { 0x0000, 0x0000, 0x0000 }, /* R752 */ 859 { 0x0000, 0x0000, 0x0000 }, /* R753 */ 860 { 0x0000, 0x0000, 0x0000 }, /* R754 */ 861 { 0x0000, 0x0000, 0x0000 }, /* R755 */ 862 { 0x0000, 0x0000, 0x0000 }, /* R756 */ 863 { 0x0000, 0x0000, 0x0000 }, /* R757 */ 864 { 0x0000, 0x0000, 0x0000 }, /* R758 */ 865 { 0x0000, 0x0000, 0x0000 }, /* R759 */ 866 { 0x0000, 0x0000, 0x0000 }, /* R760 */ 867 { 0x0000, 0x0000, 0x0000 }, /* R761 */ 868 { 0x0000, 0x0000, 0x0000 }, /* R762 */ 869 { 0x0000, 0x0000, 0x0000 }, /* R763 */ 870 { 0x0000, 0x0000, 0x0000 }, /* R764 */ 871 { 0x0000, 0x0000, 0x0000 }, /* R765 */ 872 { 0x0000, 0x0000, 0x0000 }, /* R766 */ 873 { 0x0000, 0x0000, 0x0000 }, /* R767 */ 874 { 0xE1F8, 0xE1F8, 0x0000 }, /* R768 - AIF1 Control (1) */ 875 { 0xCD1F, 0xCD1F, 0x0000 }, /* R769 - AIF1 Control (2) */ 876 { 0xF000, 0xF000, 0x0000 }, /* R770 - AIF1 Master/Slave */ 877 { 0x01F0, 0x01F0, 0x0000 }, /* R771 - AIF1 BCLK */ 878 { 0x0FFF, 0x0FFF, 0x0000 }, /* R772 - AIF1ADC LRCLK */ 879 { 0x0FFF, 0x0FFF, 0x0000 }, /* R773 - AIF1DAC LRCLK */ 880 { 0x0003, 0x0003, 0x0000 }, /* R774 - AIF1DAC Data */ 881 { 0x0003, 0x0003, 0x0000 }, /* R775 - AIF1ADC Data */ 882 { 0x0000, 0x0000, 0x0000 }, /* R776 */ 883 { 0x0000, 0x0000, 0x0000 }, /* R777 */ 884 { 0x0000, 0x0000, 0x0000 }, /* R778 */ 885 { 0x0000, 0x0000, 0x0000 }, /* R779 */ 886 { 0x0000, 0x0000, 0x0000 }, /* R780 */ 887 { 0x0000, 0x0000, 0x0000 }, /* R781 */ 888 { 0x0000, 0x0000, 0x0000 }, /* R782 */ 889 { 0x0000, 0x0000, 0x0000 }, /* R783 */ 890 { 0xF1F8, 0xF1F8, 0x0000 }, /* R784 - AIF2 Control (1) */ 891 { 0xFD1F, 0xFD1F, 0x0000 }, /* R785 - AIF2 Control (2) */ 892 { 0xF000, 0xF000, 0x0000 }, /* R786 - AIF2 Master/Slave */ 893 { 0x01F0, 0x01F0, 0x0000 }, /* R787 - AIF2 BCLK */ 894 { 0x0FFF, 0x0FFF, 0x0000 }, /* R788 - AIF2ADC LRCLK */ 895 { 0x0FFF, 0x0FFF, 0x0000 }, /* R789 - AIF2DAC LRCLK */ 896 { 0x0003, 0x0003, 0x0000 }, /* R790 - AIF2DAC Data */ 897 { 0x0003, 0x0003, 0x0000 }, /* R791 - AIF2ADC Data */ 898 { 0x0000, 0x0000, 0x0000 }, /* R792 */ 899 { 0x0000, 0x0000, 0x0000 }, /* R793 */ 900 { 0x0000, 0x0000, 0x0000 }, /* R794 */ 901 { 0x0000, 0x0000, 0x0000 }, /* R795 */ 902 { 0x0000, 0x0000, 0x0000 }, /* R796 */ 903 { 0x0000, 0x0000, 0x0000 }, /* R797 */ 904 { 0x0000, 0x0000, 0x0000 }, /* R798 */ 905 { 0x0000, 0x0000, 0x0000 }, /* R799 */ 906 { 0x0000, 0x0000, 0x0000 }, /* R800 */ 907 { 0x0000, 0x0000, 0x0000 }, /* R801 */ 908 { 0x0000, 0x0000, 0x0000 }, /* R802 */ 909 { 0x0000, 0x0000, 0x0000 }, /* R803 */ 910 { 0x0000, 0x0000, 0x0000 }, /* R804 */ 911 { 0x0000, 0x0000, 0x0000 }, /* R805 */ 912 { 0x0000, 0x0000, 0x0000 }, /* R806 */ 913 { 0x0000, 0x0000, 0x0000 }, /* R807 */ 914 { 0x0000, 0x0000, 0x0000 }, /* R808 */ 915 { 0x0000, 0x0000, 0x0000 }, /* R809 */ 916 { 0x0000, 0x0000, 0x0000 }, /* R810 */ 917 { 0x0000, 0x0000, 0x0000 }, /* R811 */ 918 { 0x0000, 0x0000, 0x0000 }, /* R812 */ 919 { 0x0000, 0x0000, 0x0000 }, /* R813 */ 920 { 0x0000, 0x0000, 0x0000 }, /* R814 */ 921 { 0x0000, 0x0000, 0x0000 }, /* R815 */ 922 { 0x0000, 0x0000, 0x0000 }, /* R816 */ 923 { 0x0000, 0x0000, 0x0000 }, /* R817 */ 924 { 0x0000, 0x0000, 0x0000 }, /* R818 */ 925 { 0x0000, 0x0000, 0x0000 }, /* R819 */ 926 { 0x0000, 0x0000, 0x0000 }, /* R820 */ 927 { 0x0000, 0x0000, 0x0000 }, /* R821 */ 928 { 0x0000, 0x0000, 0x0000 }, /* R822 */ 929 { 0x0000, 0x0000, 0x0000 }, /* R823 */ 930 { 0x0000, 0x0000, 0x0000 }, /* R824 */ 931 { 0x0000, 0x0000, 0x0000 }, /* R825 */ 932 { 0x0000, 0x0000, 0x0000 }, /* R826 */ 933 { 0x0000, 0x0000, 0x0000 }, /* R827 */ 934 { 0x0000, 0x0000, 0x0000 }, /* R828 */ 935 { 0x0000, 0x0000, 0x0000 }, /* R829 */ 936 { 0x0000, 0x0000, 0x0000 }, /* R830 */ 937 { 0x0000, 0x0000, 0x0000 }, /* R831 */ 938 { 0x0000, 0x0000, 0x0000 }, /* R832 */ 939 { 0x0000, 0x0000, 0x0000 }, /* R833 */ 940 { 0x0000, 0x0000, 0x0000 }, /* R834 */ 941 { 0x0000, 0x0000, 0x0000 }, /* R835 */ 942 { 0x0000, 0x0000, 0x0000 }, /* R836 */ 943 { 0x0000, 0x0000, 0x0000 }, /* R837 */ 944 { 0x0000, 0x0000, 0x0000 }, /* R838 */ 945 { 0x0000, 0x0000, 0x0000 }, /* R839 */ 946 { 0x0000, 0x0000, 0x0000 }, /* R840 */ 947 { 0x0000, 0x0000, 0x0000 }, /* R841 */ 948 { 0x0000, 0x0000, 0x0000 }, /* R842 */ 949 { 0x0000, 0x0000, 0x0000 }, /* R843 */ 950 { 0x0000, 0x0000, 0x0000 }, /* R844 */ 951 { 0x0000, 0x0000, 0x0000 }, /* R845 */ 952 { 0x0000, 0x0000, 0x0000 }, /* R846 */ 953 { 0x0000, 0x0000, 0x0000 }, /* R847 */ 954 { 0x0000, 0x0000, 0x0000 }, /* R848 */ 955 { 0x0000, 0x0000, 0x0000 }, /* R849 */ 956 { 0x0000, 0x0000, 0x0000 }, /* R850 */ 957 { 0x0000, 0x0000, 0x0000 }, /* R851 */ 958 { 0x0000, 0x0000, 0x0000 }, /* R852 */ 959 { 0x0000, 0x0000, 0x0000 }, /* R853 */ 960 { 0x0000, 0x0000, 0x0000 }, /* R854 */ 961 { 0x0000, 0x0000, 0x0000 }, /* R855 */ 962 { 0x0000, 0x0000, 0x0000 }, /* R856 */ 963 { 0x0000, 0x0000, 0x0000 }, /* R857 */ 964 { 0x0000, 0x0000, 0x0000 }, /* R858 */ 965 { 0x0000, 0x0000, 0x0000 }, /* R859 */ 966 { 0x0000, 0x0000, 0x0000 }, /* R860 */ 967 { 0x0000, 0x0000, 0x0000 }, /* R861 */ 968 { 0x0000, 0x0000, 0x0000 }, /* R862 */ 969 { 0x0000, 0x0000, 0x0000 }, /* R863 */ 970 { 0x0000, 0x0000, 0x0000 }, /* R864 */ 971 { 0x0000, 0x0000, 0x0000 }, /* R865 */ 972 { 0x0000, 0x0000, 0x0000 }, /* R866 */ 973 { 0x0000, 0x0000, 0x0000 }, /* R867 */ 974 { 0x0000, 0x0000, 0x0000 }, /* R868 */ 975 { 0x0000, 0x0000, 0x0000 }, /* R869 */ 976 { 0x0000, 0x0000, 0x0000 }, /* R870 */ 977 { 0x0000, 0x0000, 0x0000 }, /* R871 */ 978 { 0x0000, 0x0000, 0x0000 }, /* R872 */ 979 { 0x0000, 0x0000, 0x0000 }, /* R873 */ 980 { 0x0000, 0x0000, 0x0000 }, /* R874 */ 981 { 0x0000, 0x0000, 0x0000 }, /* R875 */ 982 { 0x0000, 0x0000, 0x0000 }, /* R876 */ 983 { 0x0000, 0x0000, 0x0000 }, /* R877 */ 984 { 0x0000, 0x0000, 0x0000 }, /* R878 */ 985 { 0x0000, 0x0000, 0x0000 }, /* R879 */ 986 { 0x0000, 0x0000, 0x0000 }, /* R880 */ 987 { 0x0000, 0x0000, 0x0000 }, /* R881 */ 988 { 0x0000, 0x0000, 0x0000 }, /* R882 */ 989 { 0x0000, 0x0000, 0x0000 }, /* R883 */ 990 { 0x0000, 0x0000, 0x0000 }, /* R884 */ 991 { 0x0000, 0x0000, 0x0000 }, /* R885 */ 992 { 0x0000, 0x0000, 0x0000 }, /* R886 */ 993 { 0x0000, 0x0000, 0x0000 }, /* R887 */ 994 { 0x0000, 0x0000, 0x0000 }, /* R888 */ 995 { 0x0000, 0x0000, 0x0000 }, /* R889 */ 996 { 0x0000, 0x0000, 0x0000 }, /* R890 */ 997 { 0x0000, 0x0000, 0x0000 }, /* R891 */ 998 { 0x0000, 0x0000, 0x0000 }, /* R892 */ 999 { 0x0000, 0x0000, 0x0000 }, /* R893 */ 1000 { 0x0000, 0x0000, 0x0000 }, /* R894 */ 1001 { 0x0000, 0x0000, 0x0000 }, /* R895 */ 1002 { 0x0000, 0x0000, 0x0000 }, /* R896 */ 1003 { 0x0000, 0x0000, 0x0000 }, /* R897 */ 1004 { 0x0000, 0x0000, 0x0000 }, /* R898 */ 1005 { 0x0000, 0x0000, 0x0000 }, /* R899 */ 1006 { 0x0000, 0x0000, 0x0000 }, /* R900 */ 1007 { 0x0000, 0x0000, 0x0000 }, /* R901 */ 1008 { 0x0000, 0x0000, 0x0000 }, /* R902 */ 1009 { 0x0000, 0x0000, 0x0000 }, /* R903 */ 1010 { 0x0000, 0x0000, 0x0000 }, /* R904 */ 1011 { 0x0000, 0x0000, 0x0000 }, /* R905 */ 1012 { 0x0000, 0x0000, 0x0000 }, /* R906 */ 1013 { 0x0000, 0x0000, 0x0000 }, /* R907 */ 1014 { 0x0000, 0x0000, 0x0000 }, /* R908 */ 1015 { 0x0000, 0x0000, 0x0000 }, /* R909 */ 1016 { 0x0000, 0x0000, 0x0000 }, /* R910 */ 1017 { 0x0000, 0x0000, 0x0000 }, /* R911 */ 1018 { 0x0000, 0x0000, 0x0000 }, /* R912 */ 1019 { 0x0000, 0x0000, 0x0000 }, /* R913 */ 1020 { 0x0000, 0x0000, 0x0000 }, /* R914 */ 1021 { 0x0000, 0x0000, 0x0000 }, /* R915 */ 1022 { 0x0000, 0x0000, 0x0000 }, /* R916 */ 1023 { 0x0000, 0x0000, 0x0000 }, /* R917 */ 1024 { 0x0000, 0x0000, 0x0000 }, /* R918 */ 1025 { 0x0000, 0x0000, 0x0000 }, /* R919 */ 1026 { 0x0000, 0x0000, 0x0000 }, /* R920 */ 1027 { 0x0000, 0x0000, 0x0000 }, /* R921 */ 1028 { 0x0000, 0x0000, 0x0000 }, /* R922 */ 1029 { 0x0000, 0x0000, 0x0000 }, /* R923 */ 1030 { 0x0000, 0x0000, 0x0000 }, /* R924 */ 1031 { 0x0000, 0x0000, 0x0000 }, /* R925 */ 1032 { 0x0000, 0x0000, 0x0000 }, /* R926 */ 1033 { 0x0000, 0x0000, 0x0000 }, /* R927 */ 1034 { 0x0000, 0x0000, 0x0000 }, /* R928 */ 1035 { 0x0000, 0x0000, 0x0000 }, /* R929 */ 1036 { 0x0000, 0x0000, 0x0000 }, /* R930 */ 1037 { 0x0000, 0x0000, 0x0000 }, /* R931 */ 1038 { 0x0000, 0x0000, 0x0000 }, /* R932 */ 1039 { 0x0000, 0x0000, 0x0000 }, /* R933 */ 1040 { 0x0000, 0x0000, 0x0000 }, /* R934 */ 1041 { 0x0000, 0x0000, 0x0000 }, /* R935 */ 1042 { 0x0000, 0x0000, 0x0000 }, /* R936 */ 1043 { 0x0000, 0x0000, 0x0000 }, /* R937 */ 1044 { 0x0000, 0x0000, 0x0000 }, /* R938 */ 1045 { 0x0000, 0x0000, 0x0000 }, /* R939 */ 1046 { 0x0000, 0x0000, 0x0000 }, /* R940 */ 1047 { 0x0000, 0x0000, 0x0000 }, /* R941 */ 1048 { 0x0000, 0x0000, 0x0000 }, /* R942 */ 1049 { 0x0000, 0x0000, 0x0000 }, /* R943 */ 1050 { 0x0000, 0x0000, 0x0000 }, /* R944 */ 1051 { 0x0000, 0x0000, 0x0000 }, /* R945 */ 1052 { 0x0000, 0x0000, 0x0000 }, /* R946 */ 1053 { 0x0000, 0x0000, 0x0000 }, /* R947 */ 1054 { 0x0000, 0x0000, 0x0000 }, /* R948 */ 1055 { 0x0000, 0x0000, 0x0000 }, /* R949 */ 1056 { 0x0000, 0x0000, 0x0000 }, /* R950 */ 1057 { 0x0000, 0x0000, 0x0000 }, /* R951 */ 1058 { 0x0000, 0x0000, 0x0000 }, /* R952 */ 1059 { 0x0000, 0x0000, 0x0000 }, /* R953 */ 1060 { 0x0000, 0x0000, 0x0000 }, /* R954 */ 1061 { 0x0000, 0x0000, 0x0000 }, /* R955 */ 1062 { 0x0000, 0x0000, 0x0000 }, /* R956 */ 1063 { 0x0000, 0x0000, 0x0000 }, /* R957 */ 1064 { 0x0000, 0x0000, 0x0000 }, /* R958 */ 1065 { 0x0000, 0x0000, 0x0000 }, /* R959 */ 1066 { 0x0000, 0x0000, 0x0000 }, /* R960 */ 1067 { 0x0000, 0x0000, 0x0000 }, /* R961 */ 1068 { 0x0000, 0x0000, 0x0000 }, /* R962 */ 1069 { 0x0000, 0x0000, 0x0000 }, /* R963 */ 1070 { 0x0000, 0x0000, 0x0000 }, /* R964 */ 1071 { 0x0000, 0x0000, 0x0000 }, /* R965 */ 1072 { 0x0000, 0x0000, 0x0000 }, /* R966 */ 1073 { 0x0000, 0x0000, 0x0000 }, /* R967 */ 1074 { 0x0000, 0x0000, 0x0000 }, /* R968 */ 1075 { 0x0000, 0x0000, 0x0000 }, /* R969 */ 1076 { 0x0000, 0x0000, 0x0000 }, /* R970 */ 1077 { 0x0000, 0x0000, 0x0000 }, /* R971 */ 1078 { 0x0000, 0x0000, 0x0000 }, /* R972 */ 1079 { 0x0000, 0x0000, 0x0000 }, /* R973 */ 1080 { 0x0000, 0x0000, 0x0000 }, /* R974 */ 1081 { 0x0000, 0x0000, 0x0000 }, /* R975 */ 1082 { 0x0000, 0x0000, 0x0000 }, /* R976 */ 1083 { 0x0000, 0x0000, 0x0000 }, /* R977 */ 1084 { 0x0000, 0x0000, 0x0000 }, /* R978 */ 1085 { 0x0000, 0x0000, 0x0000 }, /* R979 */ 1086 { 0x0000, 0x0000, 0x0000 }, /* R980 */ 1087 { 0x0000, 0x0000, 0x0000 }, /* R981 */ 1088 { 0x0000, 0x0000, 0x0000 }, /* R982 */ 1089 { 0x0000, 0x0000, 0x0000 }, /* R983 */ 1090 { 0x0000, 0x0000, 0x0000 }, /* R984 */ 1091 { 0x0000, 0x0000, 0x0000 }, /* R985 */ 1092 { 0x0000, 0x0000, 0x0000 }, /* R986 */ 1093 { 0x0000, 0x0000, 0x0000 }, /* R987 */ 1094 { 0x0000, 0x0000, 0x0000 }, /* R988 */ 1095 { 0x0000, 0x0000, 0x0000 }, /* R989 */ 1096 { 0x0000, 0x0000, 0x0000 }, /* R990 */ 1097 { 0x0000, 0x0000, 0x0000 }, /* R991 */ 1098 { 0x0000, 0x0000, 0x0000 }, /* R992 */ 1099 { 0x0000, 0x0000, 0x0000 }, /* R993 */ 1100 { 0x0000, 0x0000, 0x0000 }, /* R994 */ 1101 { 0x0000, 0x0000, 0x0000 }, /* R995 */ 1102 { 0x0000, 0x0000, 0x0000 }, /* R996 */ 1103 { 0x0000, 0x0000, 0x0000 }, /* R997 */ 1104 { 0x0000, 0x0000, 0x0000 }, /* R998 */ 1105 { 0x0000, 0x0000, 0x0000 }, /* R999 */ 1106 { 0x0000, 0x0000, 0x0000 }, /* R1000 */ 1107 { 0x0000, 0x0000, 0x0000 }, /* R1001 */ 1108 { 0x0000, 0x0000, 0x0000 }, /* R1002 */ 1109 { 0x0000, 0x0000, 0x0000 }, /* R1003 */ 1110 { 0x0000, 0x0000, 0x0000 }, /* R1004 */ 1111 { 0x0000, 0x0000, 0x0000 }, /* R1005 */ 1112 { 0x0000, 0x0000, 0x0000 }, /* R1006 */ 1113 { 0x0000, 0x0000, 0x0000 }, /* R1007 */ 1114 { 0x0000, 0x0000, 0x0000 }, /* R1008 */ 1115 { 0x0000, 0x0000, 0x0000 }, /* R1009 */ 1116 { 0x0000, 0x0000, 0x0000 }, /* R1010 */ 1117 { 0x0000, 0x0000, 0x0000 }, /* R1011 */ 1118 { 0x0000, 0x0000, 0x0000 }, /* R1012 */ 1119 { 0x0000, 0x0000, 0x0000 }, /* R1013 */ 1120 { 0x0000, 0x0000, 0x0000 }, /* R1014 */ 1121 { 0x0000, 0x0000, 0x0000 }, /* R1015 */ 1122 { 0x0000, 0x0000, 0x0000 }, /* R1016 */ 1123 { 0x0000, 0x0000, 0x0000 }, /* R1017 */ 1124 { 0x0000, 0x0000, 0x0000 }, /* R1018 */ 1125 { 0x0000, 0x0000, 0x0000 }, /* R1019 */ 1126 { 0x0000, 0x0000, 0x0000 }, /* R1020 */ 1127 { 0x0000, 0x0000, 0x0000 }, /* R1021 */ 1128 { 0x0000, 0x0000, 0x0000 }, /* R1022 */ 1129 { 0x0000, 0x0000, 0x0000 }, /* R1023 */ 1130 { 0x00FF, 0x01FF, 0x0000 }, /* R1024 - AIF1 ADC1 Left Volume */ 1131 { 0x00FF, 0x01FF, 0x0000 }, /* R1025 - AIF1 ADC1 Right Volume */ 1132 { 0x00FF, 0x01FF, 0x0000 }, /* R1026 - AIF1 DAC1 Left Volume */ 1133 { 0x00FF, 0x01FF, 0x0000 }, /* R1027 - AIF1 DAC1 Right Volume */ 1134 { 0x00FF, 0x01FF, 0x0000 }, /* R1028 - AIF1 ADC2 Left Volume */ 1135 { 0x00FF, 0x01FF, 0x0000 }, /* R1029 - AIF1 ADC2 Right Volume */ 1136 { 0x00FF, 0x01FF, 0x0000 }, /* R1030 - AIF1 DAC2 Left Volume */ 1137 { 0x00FF, 0x01FF, 0x0000 }, /* R1031 - AIF1 DAC2 Right Volume */ 1138 { 0x0000, 0x0000, 0x0000 }, /* R1032 */ 1139 { 0x0000, 0x0000, 0x0000 }, /* R1033 */ 1140 { 0x0000, 0x0000, 0x0000 }, /* R1034 */ 1141 { 0x0000, 0x0000, 0x0000 }, /* R1035 */ 1142 { 0x0000, 0x0000, 0x0000 }, /* R1036 */ 1143 { 0x0000, 0x0000, 0x0000 }, /* R1037 */ 1144 { 0x0000, 0x0000, 0x0000 }, /* R1038 */ 1145 { 0x0000, 0x0000, 0x0000 }, /* R1039 */ 1146 { 0xF800, 0xF800, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */ 1147 { 0x7800, 0x7800, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */ 1148 { 0x0000, 0x0000, 0x0000 }, /* R1042 */ 1149 { 0x0000, 0x0000, 0x0000 }, /* R1043 */ 1150 { 0x0000, 0x0000, 0x0000 }, /* R1044 */ 1151 { 0x0000, 0x0000, 0x0000 }, /* R1045 */ 1152 { 0x0000, 0x0000, 0x0000 }, /* R1046 */ 1153 { 0x0000, 0x0000, 0x0000 }, /* R1047 */ 1154 { 0x0000, 0x0000, 0x0000 }, /* R1048 */ 1155 { 0x0000, 0x0000, 0x0000 }, /* R1049 */ 1156 { 0x0000, 0x0000, 0x0000 }, /* R1050 */ 1157 { 0x0000, 0x0000, 0x0000 }, /* R1051 */ 1158 { 0x0000, 0x0000, 0x0000 }, /* R1052 */ 1159 { 0x0000, 0x0000, 0x0000 }, /* R1053 */ 1160 { 0x0000, 0x0000, 0x0000 }, /* R1054 */ 1161 { 0x0000, 0x0000, 0x0000 }, /* R1055 */ 1162 { 0x02B6, 0x02B6, 0x0000 }, /* R1056 - AIF1 DAC1 Filters (1) */ 1163 { 0x3F00, 0x3F00, 0x0000 }, /* R1057 - AIF1 DAC1 Filters (2) */ 1164 { 0x02B6, 0x02B6, 0x0000 }, /* R1058 - AIF1 DAC2 Filters (1) */ 1165 { 0x3F00, 0x3F00, 0x0000 }, /* R1059 - AIF1 DAC2 Filters (2) */ 1166 { 0x0000, 0x0000, 0x0000 }, /* R1060 */ 1167 { 0x0000, 0x0000, 0x0000 }, /* R1061 */ 1168 { 0x0000, 0x0000, 0x0000 }, /* R1062 */ 1169 { 0x0000, 0x0000, 0x0000 }, /* R1063 */ 1170 { 0x0000, 0x0000, 0x0000 }, /* R1064 */ 1171 { 0x0000, 0x0000, 0x0000 }, /* R1065 */ 1172 { 0x0000, 0x0000, 0x0000 }, /* R1066 */ 1173 { 0x0000, 0x0000, 0x0000 }, /* R1067 */ 1174 { 0x0000, 0x0000, 0x0000 }, /* R1068 */ 1175 { 0x0000, 0x0000, 0x0000 }, /* R1069 */ 1176 { 0x0000, 0x0000, 0x0000 }, /* R1070 */ 1177 { 0x0000, 0x0000, 0x0000 }, /* R1071 */ 1178 { 0x0000, 0x0000, 0x0000 }, /* R1072 */ 1179 { 0x0000, 0x0000, 0x0000 }, /* R1073 */ 1180 { 0x0000, 0x0000, 0x0000 }, /* R1074 */ 1181 { 0x0000, 0x0000, 0x0000 }, /* R1075 */ 1182 { 0x0000, 0x0000, 0x0000 }, /* R1076 */ 1183 { 0x0000, 0x0000, 0x0000 }, /* R1077 */ 1184 { 0x0000, 0x0000, 0x0000 }, /* R1078 */ 1185 { 0x0000, 0x0000, 0x0000 }, /* R1079 */ 1186 { 0x0000, 0x0000, 0x0000 }, /* R1080 */ 1187 { 0x0000, 0x0000, 0x0000 }, /* R1081 */ 1188 { 0x0000, 0x0000, 0x0000 }, /* R1082 */ 1189 { 0x0000, 0x0000, 0x0000 }, /* R1083 */ 1190 { 0x0000, 0x0000, 0x0000 }, /* R1084 */ 1191 { 0x0000, 0x0000, 0x0000 }, /* R1085 */ 1192 { 0x0000, 0x0000, 0x0000 }, /* R1086 */ 1193 { 0x0000, 0x0000, 0x0000 }, /* R1087 */ 1194 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1088 - AIF1 DRC1 (1) */ 1195 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1089 - AIF1 DRC1 (2) */ 1196 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */ 1197 { 0x07FF, 0x07FF, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */ 1198 { 0x03FF, 0x03FF, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */ 1199 { 0x0000, 0x0000, 0x0000 }, /* R1093 */ 1200 { 0x0000, 0x0000, 0x0000 }, /* R1094 */ 1201 { 0x0000, 0x0000, 0x0000 }, /* R1095 */ 1202 { 0x0000, 0x0000, 0x0000 }, /* R1096 */ 1203 { 0x0000, 0x0000, 0x0000 }, /* R1097 */ 1204 { 0x0000, 0x0000, 0x0000 }, /* R1098 */ 1205 { 0x0000, 0x0000, 0x0000 }, /* R1099 */ 1206 { 0x0000, 0x0000, 0x0000 }, /* R1100 */ 1207 { 0x0000, 0x0000, 0x0000 }, /* R1101 */ 1208 { 0x0000, 0x0000, 0x0000 }, /* R1102 */ 1209 { 0x0000, 0x0000, 0x0000 }, /* R1103 */ 1210 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1104 - AIF1 DRC2 (1) */ 1211 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1105 - AIF1 DRC2 (2) */ 1212 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */ 1213 { 0x07FF, 0x07FF, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */ 1214 { 0x03FF, 0x03FF, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */ 1215 { 0x0000, 0x0000, 0x0000 }, /* R1109 */ 1216 { 0x0000, 0x0000, 0x0000 }, /* R1110 */ 1217 { 0x0000, 0x0000, 0x0000 }, /* R1111 */ 1218 { 0x0000, 0x0000, 0x0000 }, /* R1112 */ 1219 { 0x0000, 0x0000, 0x0000 }, /* R1113 */ 1220 { 0x0000, 0x0000, 0x0000 }, /* R1114 */ 1221 { 0x0000, 0x0000, 0x0000 }, /* R1115 */ 1222 { 0x0000, 0x0000, 0x0000 }, /* R1116 */ 1223 { 0x0000, 0x0000, 0x0000 }, /* R1117 */ 1224 { 0x0000, 0x0000, 0x0000 }, /* R1118 */ 1225 { 0x0000, 0x0000, 0x0000 }, /* R1119 */ 1226 { 0x0000, 0x0000, 0x0000 }, /* R1120 */ 1227 { 0x0000, 0x0000, 0x0000 }, /* R1121 */ 1228 { 0x0000, 0x0000, 0x0000 }, /* R1122 */ 1229 { 0x0000, 0x0000, 0x0000 }, /* R1123 */ 1230 { 0x0000, 0x0000, 0x0000 }, /* R1124 */ 1231 { 0x0000, 0x0000, 0x0000 }, /* R1125 */ 1232 { 0x0000, 0x0000, 0x0000 }, /* R1126 */ 1233 { 0x0000, 0x0000, 0x0000 }, /* R1127 */ 1234 { 0x0000, 0x0000, 0x0000 }, /* R1128 */ 1235 { 0x0000, 0x0000, 0x0000 }, /* R1129 */ 1236 { 0x0000, 0x0000, 0x0000 }, /* R1130 */ 1237 { 0x0000, 0x0000, 0x0000 }, /* R1131 */ 1238 { 0x0000, 0x0000, 0x0000 }, /* R1132 */ 1239 { 0x0000, 0x0000, 0x0000 }, /* R1133 */ 1240 { 0x0000, 0x0000, 0x0000 }, /* R1134 */ 1241 { 0x0000, 0x0000, 0x0000 }, /* R1135 */ 1242 { 0x0000, 0x0000, 0x0000 }, /* R1136 */ 1243 { 0x0000, 0x0000, 0x0000 }, /* R1137 */ 1244 { 0x0000, 0x0000, 0x0000 }, /* R1138 */ 1245 { 0x0000, 0x0000, 0x0000 }, /* R1139 */ 1246 { 0x0000, 0x0000, 0x0000 }, /* R1140 */ 1247 { 0x0000, 0x0000, 0x0000 }, /* R1141 */ 1248 { 0x0000, 0x0000, 0x0000 }, /* R1142 */ 1249 { 0x0000, 0x0000, 0x0000 }, /* R1143 */ 1250 { 0x0000, 0x0000, 0x0000 }, /* R1144 */ 1251 { 0x0000, 0x0000, 0x0000 }, /* R1145 */ 1252 { 0x0000, 0x0000, 0x0000 }, /* R1146 */ 1253 { 0x0000, 0x0000, 0x0000 }, /* R1147 */ 1254 { 0x0000, 0x0000, 0x0000 }, /* R1148 */ 1255 { 0x0000, 0x0000, 0x0000 }, /* R1149 */ 1256 { 0x0000, 0x0000, 0x0000 }, /* R1150 */ 1257 { 0x0000, 0x0000, 0x0000 }, /* R1151 */ 1258 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ 1259 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ 1260 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ 1261 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ 1262 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ 1263 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ 1264 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ 1265 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ 1266 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ 1267 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ 1268 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ 1269 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ 1270 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ 1271 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ 1272 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ 1273 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ 1274 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ 1275 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ 1276 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ 1277 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ 1278 { 0x0000, 0x0000, 0x0000 }, /* R1172 */ 1279 { 0x0000, 0x0000, 0x0000 }, /* R1173 */ 1280 { 0x0000, 0x0000, 0x0000 }, /* R1174 */ 1281 { 0x0000, 0x0000, 0x0000 }, /* R1175 */ 1282 { 0x0000, 0x0000, 0x0000 }, /* R1176 */ 1283 { 0x0000, 0x0000, 0x0000 }, /* R1177 */ 1284 { 0x0000, 0x0000, 0x0000 }, /* R1178 */ 1285 { 0x0000, 0x0000, 0x0000 }, /* R1179 */ 1286 { 0x0000, 0x0000, 0x0000 }, /* R1180 */ 1287 { 0x0000, 0x0000, 0x0000 }, /* R1181 */ 1288 { 0x0000, 0x0000, 0x0000 }, /* R1182 */ 1289 { 0x0000, 0x0000, 0x0000 }, /* R1183 */ 1290 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ 1291 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ 1292 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ 1293 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ 1294 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ 1295 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ 1296 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ 1297 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ 1298 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ 1299 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ 1300 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ 1301 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ 1302 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ 1303 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ 1304 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ 1305 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ 1306 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ 1307 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ 1308 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ 1309 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ 1310 { 0x0000, 0x0000, 0x0000 }, /* R1204 */ 1311 { 0x0000, 0x0000, 0x0000 }, /* R1205 */ 1312 { 0x0000, 0x0000, 0x0000 }, /* R1206 */ 1313 { 0x0000, 0x0000, 0x0000 }, /* R1207 */ 1314 { 0x0000, 0x0000, 0x0000 }, /* R1208 */ 1315 { 0x0000, 0x0000, 0x0000 }, /* R1209 */ 1316 { 0x0000, 0x0000, 0x0000 }, /* R1210 */ 1317 { 0x0000, 0x0000, 0x0000 }, /* R1211 */ 1318 { 0x0000, 0x0000, 0x0000 }, /* R1212 */ 1319 { 0x0000, 0x0000, 0x0000 }, /* R1213 */ 1320 { 0x0000, 0x0000, 0x0000 }, /* R1214 */ 1321 { 0x0000, 0x0000, 0x0000 }, /* R1215 */ 1322 { 0x0000, 0x0000, 0x0000 }, /* R1216 */ 1323 { 0x0000, 0x0000, 0x0000 }, /* R1217 */ 1324 { 0x0000, 0x0000, 0x0000 }, /* R1218 */ 1325 { 0x0000, 0x0000, 0x0000 }, /* R1219 */ 1326 { 0x0000, 0x0000, 0x0000 }, /* R1220 */ 1327 { 0x0000, 0x0000, 0x0000 }, /* R1221 */ 1328 { 0x0000, 0x0000, 0x0000 }, /* R1222 */ 1329 { 0x0000, 0x0000, 0x0000 }, /* R1223 */ 1330 { 0x0000, 0x0000, 0x0000 }, /* R1224 */ 1331 { 0x0000, 0x0000, 0x0000 }, /* R1225 */ 1332 { 0x0000, 0x0000, 0x0000 }, /* R1226 */ 1333 { 0x0000, 0x0000, 0x0000 }, /* R1227 */ 1334 { 0x0000, 0x0000, 0x0000 }, /* R1228 */ 1335 { 0x0000, 0x0000, 0x0000 }, /* R1229 */ 1336 { 0x0000, 0x0000, 0x0000 }, /* R1230 */ 1337 { 0x0000, 0x0000, 0x0000 }, /* R1231 */ 1338 { 0x0000, 0x0000, 0x0000 }, /* R1232 */ 1339 { 0x0000, 0x0000, 0x0000 }, /* R1233 */ 1340 { 0x0000, 0x0000, 0x0000 }, /* R1234 */ 1341 { 0x0000, 0x0000, 0x0000 }, /* R1235 */ 1342 { 0x0000, 0x0000, 0x0000 }, /* R1236 */ 1343 { 0x0000, 0x0000, 0x0000 }, /* R1237 */ 1344 { 0x0000, 0x0000, 0x0000 }, /* R1238 */ 1345 { 0x0000, 0x0000, 0x0000 }, /* R1239 */ 1346 { 0x0000, 0x0000, 0x0000 }, /* R1240 */ 1347 { 0x0000, 0x0000, 0x0000 }, /* R1241 */ 1348 { 0x0000, 0x0000, 0x0000 }, /* R1242 */ 1349 { 0x0000, 0x0000, 0x0000 }, /* R1243 */ 1350 { 0x0000, 0x0000, 0x0000 }, /* R1244 */ 1351 { 0x0000, 0x0000, 0x0000 }, /* R1245 */ 1352 { 0x0000, 0x0000, 0x0000 }, /* R1246 */ 1353 { 0x0000, 0x0000, 0x0000 }, /* R1247 */ 1354 { 0x0000, 0x0000, 0x0000 }, /* R1248 */ 1355 { 0x0000, 0x0000, 0x0000 }, /* R1249 */ 1356 { 0x0000, 0x0000, 0x0000 }, /* R1250 */ 1357 { 0x0000, 0x0000, 0x0000 }, /* R1251 */ 1358 { 0x0000, 0x0000, 0x0000 }, /* R1252 */ 1359 { 0x0000, 0x0000, 0x0000 }, /* R1253 */ 1360 { 0x0000, 0x0000, 0x0000 }, /* R1254 */ 1361 { 0x0000, 0x0000, 0x0000 }, /* R1255 */ 1362 { 0x0000, 0x0000, 0x0000 }, /* R1256 */ 1363 { 0x0000, 0x0000, 0x0000 }, /* R1257 */ 1364 { 0x0000, 0x0000, 0x0000 }, /* R1258 */ 1365 { 0x0000, 0x0000, 0x0000 }, /* R1259 */ 1366 { 0x0000, 0x0000, 0x0000 }, /* R1260 */ 1367 { 0x0000, 0x0000, 0x0000 }, /* R1261 */ 1368 { 0x0000, 0x0000, 0x0000 }, /* R1262 */ 1369 { 0x0000, 0x0000, 0x0000 }, /* R1263 */ 1370 { 0x0000, 0x0000, 0x0000 }, /* R1264 */ 1371 { 0x0000, 0x0000, 0x0000 }, /* R1265 */ 1372 { 0x0000, 0x0000, 0x0000 }, /* R1266 */ 1373 { 0x0000, 0x0000, 0x0000 }, /* R1267 */ 1374 { 0x0000, 0x0000, 0x0000 }, /* R1268 */ 1375 { 0x0000, 0x0000, 0x0000 }, /* R1269 */ 1376 { 0x0000, 0x0000, 0x0000 }, /* R1270 */ 1377 { 0x0000, 0x0000, 0x0000 }, /* R1271 */ 1378 { 0x0000, 0x0000, 0x0000 }, /* R1272 */ 1379 { 0x0000, 0x0000, 0x0000 }, /* R1273 */ 1380 { 0x0000, 0x0000, 0x0000 }, /* R1274 */ 1381 { 0x0000, 0x0000, 0x0000 }, /* R1275 */ 1382 { 0x0000, 0x0000, 0x0000 }, /* R1276 */ 1383 { 0x0000, 0x0000, 0x0000 }, /* R1277 */ 1384 { 0x0000, 0x0000, 0x0000 }, /* R1278 */ 1385 { 0x0000, 0x0000, 0x0000 }, /* R1279 */ 1386 { 0x00FF, 0x01FF, 0x0000 }, /* R1280 - AIF2 ADC Left Volume */ 1387 { 0x00FF, 0x01FF, 0x0000 }, /* R1281 - AIF2 ADC Right Volume */ 1388 { 0x00FF, 0x01FF, 0x0000 }, /* R1282 - AIF2 DAC Left Volume */ 1389 { 0x00FF, 0x01FF, 0x0000 }, /* R1283 - AIF2 DAC Right Volume */ 1390 { 0x0000, 0x0000, 0x0000 }, /* R1284 */ 1391 { 0x0000, 0x0000, 0x0000 }, /* R1285 */ 1392 { 0x0000, 0x0000, 0x0000 }, /* R1286 */ 1393 { 0x0000, 0x0000, 0x0000 }, /* R1287 */ 1394 { 0x0000, 0x0000, 0x0000 }, /* R1288 */ 1395 { 0x0000, 0x0000, 0x0000 }, /* R1289 */ 1396 { 0x0000, 0x0000, 0x0000 }, /* R1290 */ 1397 { 0x0000, 0x0000, 0x0000 }, /* R1291 */ 1398 { 0x0000, 0x0000, 0x0000 }, /* R1292 */ 1399 { 0x0000, 0x0000, 0x0000 }, /* R1293 */ 1400 { 0x0000, 0x0000, 0x0000 }, /* R1294 */ 1401 { 0x0000, 0x0000, 0x0000 }, /* R1295 */ 1402 { 0xF800, 0xF800, 0x0000 }, /* R1296 - AIF2 ADC Filters */ 1403 { 0x0000, 0x0000, 0x0000 }, /* R1297 */ 1404 { 0x0000, 0x0000, 0x0000 }, /* R1298 */ 1405 { 0x0000, 0x0000, 0x0000 }, /* R1299 */ 1406 { 0x0000, 0x0000, 0x0000 }, /* R1300 */ 1407 { 0x0000, 0x0000, 0x0000 }, /* R1301 */ 1408 { 0x0000, 0x0000, 0x0000 }, /* R1302 */ 1409 { 0x0000, 0x0000, 0x0000 }, /* R1303 */ 1410 { 0x0000, 0x0000, 0x0000 }, /* R1304 */ 1411 { 0x0000, 0x0000, 0x0000 }, /* R1305 */ 1412 { 0x0000, 0x0000, 0x0000 }, /* R1306 */ 1413 { 0x0000, 0x0000, 0x0000 }, /* R1307 */ 1414 { 0x0000, 0x0000, 0x0000 }, /* R1308 */ 1415 { 0x0000, 0x0000, 0x0000 }, /* R1309 */ 1416 { 0x0000, 0x0000, 0x0000 }, /* R1310 */ 1417 { 0x0000, 0x0000, 0x0000 }, /* R1311 */ 1418 { 0x02B6, 0x02B6, 0x0000 }, /* R1312 - AIF2 DAC Filters (1) */ 1419 { 0x3F00, 0x3F00, 0x0000 }, /* R1313 - AIF2 DAC Filters (2) */ 1420 { 0x0000, 0x0000, 0x0000 }, /* R1314 */ 1421 { 0x0000, 0x0000, 0x0000 }, /* R1315 */ 1422 { 0x0000, 0x0000, 0x0000 }, /* R1316 */ 1423 { 0x0000, 0x0000, 0x0000 }, /* R1317 */ 1424 { 0x0000, 0x0000, 0x0000 }, /* R1318 */ 1425 { 0x0000, 0x0000, 0x0000 }, /* R1319 */ 1426 { 0x0000, 0x0000, 0x0000 }, /* R1320 */ 1427 { 0x0000, 0x0000, 0x0000 }, /* R1321 */ 1428 { 0x0000, 0x0000, 0x0000 }, /* R1322 */ 1429 { 0x0000, 0x0000, 0x0000 }, /* R1323 */ 1430 { 0x0000, 0x0000, 0x0000 }, /* R1324 */ 1431 { 0x0000, 0x0000, 0x0000 }, /* R1325 */ 1432 { 0x0000, 0x0000, 0x0000 }, /* R1326 */ 1433 { 0x0000, 0x0000, 0x0000 }, /* R1327 */ 1434 { 0x0000, 0x0000, 0x0000 }, /* R1328 */ 1435 { 0x0000, 0x0000, 0x0000 }, /* R1329 */ 1436 { 0x0000, 0x0000, 0x0000 }, /* R1330 */ 1437 { 0x0000, 0x0000, 0x0000 }, /* R1331 */ 1438 { 0x0000, 0x0000, 0x0000 }, /* R1332 */ 1439 { 0x0000, 0x0000, 0x0000 }, /* R1333 */ 1440 { 0x0000, 0x0000, 0x0000 }, /* R1334 */ 1441 { 0x0000, 0x0000, 0x0000 }, /* R1335 */ 1442 { 0x0000, 0x0000, 0x0000 }, /* R1336 */ 1443 { 0x0000, 0x0000, 0x0000 }, /* R1337 */ 1444 { 0x0000, 0x0000, 0x0000 }, /* R1338 */ 1445 { 0x0000, 0x0000, 0x0000 }, /* R1339 */ 1446 { 0x0000, 0x0000, 0x0000 }, /* R1340 */ 1447 { 0x0000, 0x0000, 0x0000 }, /* R1341 */ 1448 { 0x0000, 0x0000, 0x0000 }, /* R1342 */ 1449 { 0x0000, 0x0000, 0x0000 }, /* R1343 */ 1450 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1344 - AIF2 DRC (1) */ 1451 { 0x1FFF, 0x1FFF, 0x0000 }, /* R1345 - AIF2 DRC (2) */ 1452 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1346 - AIF2 DRC (3) */ 1453 { 0x07FF, 0x07FF, 0x0000 }, /* R1347 - AIF2 DRC (4) */ 1454 { 0x03FF, 0x03FF, 0x0000 }, /* R1348 - AIF2 DRC (5) */ 1455 { 0x0000, 0x0000, 0x0000 }, /* R1349 */ 1456 { 0x0000, 0x0000, 0x0000 }, /* R1350 */ 1457 { 0x0000, 0x0000, 0x0000 }, /* R1351 */ 1458 { 0x0000, 0x0000, 0x0000 }, /* R1352 */ 1459 { 0x0000, 0x0000, 0x0000 }, /* R1353 */ 1460 { 0x0000, 0x0000, 0x0000 }, /* R1354 */ 1461 { 0x0000, 0x0000, 0x0000 }, /* R1355 */ 1462 { 0x0000, 0x0000, 0x0000 }, /* R1356 */ 1463 { 0x0000, 0x0000, 0x0000 }, /* R1357 */ 1464 { 0x0000, 0x0000, 0x0000 }, /* R1358 */ 1465 { 0x0000, 0x0000, 0x0000 }, /* R1359 */ 1466 { 0x0000, 0x0000, 0x0000 }, /* R1360 */ 1467 { 0x0000, 0x0000, 0x0000 }, /* R1361 */ 1468 { 0x0000, 0x0000, 0x0000 }, /* R1362 */ 1469 { 0x0000, 0x0000, 0x0000 }, /* R1363 */ 1470 { 0x0000, 0x0000, 0x0000 }, /* R1364 */ 1471 { 0x0000, 0x0000, 0x0000 }, /* R1365 */ 1472 { 0x0000, 0x0000, 0x0000 }, /* R1366 */ 1473 { 0x0000, 0x0000, 0x0000 }, /* R1367 */ 1474 { 0x0000, 0x0000, 0x0000 }, /* R1368 */ 1475 { 0x0000, 0x0000, 0x0000 }, /* R1369 */ 1476 { 0x0000, 0x0000, 0x0000 }, /* R1370 */ 1477 { 0x0000, 0x0000, 0x0000 }, /* R1371 */ 1478 { 0x0000, 0x0000, 0x0000 }, /* R1372 */ 1479 { 0x0000, 0x0000, 0x0000 }, /* R1373 */ 1480 { 0x0000, 0x0000, 0x0000 }, /* R1374 */ 1481 { 0x0000, 0x0000, 0x0000 }, /* R1375 */ 1482 { 0x0000, 0x0000, 0x0000 }, /* R1376 */ 1483 { 0x0000, 0x0000, 0x0000 }, /* R1377 */ 1484 { 0x0000, 0x0000, 0x0000 }, /* R1378 */ 1485 { 0x0000, 0x0000, 0x0000 }, /* R1379 */ 1486 { 0x0000, 0x0000, 0x0000 }, /* R1380 */ 1487 { 0x0000, 0x0000, 0x0000 }, /* R1381 */ 1488 { 0x0000, 0x0000, 0x0000 }, /* R1382 */ 1489 { 0x0000, 0x0000, 0x0000 }, /* R1383 */ 1490 { 0x0000, 0x0000, 0x0000 }, /* R1384 */ 1491 { 0x0000, 0x0000, 0x0000 }, /* R1385 */ 1492 { 0x0000, 0x0000, 0x0000 }, /* R1386 */ 1493 { 0x0000, 0x0000, 0x0000 }, /* R1387 */ 1494 { 0x0000, 0x0000, 0x0000 }, /* R1388 */ 1495 { 0x0000, 0x0000, 0x0000 }, /* R1389 */ 1496 { 0x0000, 0x0000, 0x0000 }, /* R1390 */ 1497 { 0x0000, 0x0000, 0x0000 }, /* R1391 */ 1498 { 0x0000, 0x0000, 0x0000 }, /* R1392 */ 1499 { 0x0000, 0x0000, 0x0000 }, /* R1393 */ 1500 { 0x0000, 0x0000, 0x0000 }, /* R1394 */ 1501 { 0x0000, 0x0000, 0x0000 }, /* R1395 */ 1502 { 0x0000, 0x0000, 0x0000 }, /* R1396 */ 1503 { 0x0000, 0x0000, 0x0000 }, /* R1397 */ 1504 { 0x0000, 0x0000, 0x0000 }, /* R1398 */ 1505 { 0x0000, 0x0000, 0x0000 }, /* R1399 */ 1506 { 0x0000, 0x0000, 0x0000 }, /* R1400 */ 1507 { 0x0000, 0x0000, 0x0000 }, /* R1401 */ 1508 { 0x0000, 0x0000, 0x0000 }, /* R1402 */ 1509 { 0x0000, 0x0000, 0x0000 }, /* R1403 */ 1510 { 0x0000, 0x0000, 0x0000 }, /* R1404 */ 1511 { 0x0000, 0x0000, 0x0000 }, /* R1405 */ 1512 { 0x0000, 0x0000, 0x0000 }, /* R1406 */ 1513 { 0x0000, 0x0000, 0x0000 }, /* R1407 */ 1514 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1408 - AIF2 EQ Gains (1) */ 1515 { 0xFFC0, 0xFFC0, 0x0000 }, /* R1409 - AIF2 EQ Gains (2) */ 1516 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1410 - AIF2 EQ Band 1 A */ 1517 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1411 - AIF2 EQ Band 1 B */ 1518 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1412 - AIF2 EQ Band 1 PG */ 1519 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1413 - AIF2 EQ Band 2 A */ 1520 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1414 - AIF2 EQ Band 2 B */ 1521 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1415 - AIF2 EQ Band 2 C */ 1522 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1416 - AIF2 EQ Band 2 PG */ 1523 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1417 - AIF2 EQ Band 3 A */ 1524 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1418 - AIF2 EQ Band 3 B */ 1525 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1419 - AIF2 EQ Band 3 C */ 1526 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1420 - AIF2 EQ Band 3 PG */ 1527 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1421 - AIF2 EQ Band 4 A */ 1528 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1422 - AIF2 EQ Band 4 B */ 1529 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1423 - AIF2 EQ Band 4 C */ 1530 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1424 - AIF2 EQ Band 4 PG */ 1531 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1425 - AIF2 EQ Band 5 A */ 1532 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1426 - AIF2 EQ Band 5 B */ 1533 { 0xFFFF, 0xFFFF, 0x0000 }, /* R1427 - AIF2 EQ Band 5 PG */ 1534 { 0x0000, 0x0000, 0x0000 }, /* R1428 */ 1535 { 0x0000, 0x0000, 0x0000 }, /* R1429 */ 1536 { 0x0000, 0x0000, 0x0000 }, /* R1430 */ 1537 { 0x0000, 0x0000, 0x0000 }, /* R1431 */ 1538 { 0x0000, 0x0000, 0x0000 }, /* R1432 */ 1539 { 0x0000, 0x0000, 0x0000 }, /* R1433 */ 1540 { 0x0000, 0x0000, 0x0000 }, /* R1434 */ 1541 { 0x0000, 0x0000, 0x0000 }, /* R1435 */ 1542 { 0x0000, 0x0000, 0x0000 }, /* R1436 */ 1543 { 0x0000, 0x0000, 0x0000 }, /* R1437 */ 1544 { 0x0000, 0x0000, 0x0000 }, /* R1438 */ 1545 { 0x0000, 0x0000, 0x0000 }, /* R1439 */ 1546 { 0x0000, 0x0000, 0x0000 }, /* R1440 */ 1547 { 0x0000, 0x0000, 0x0000 }, /* R1441 */ 1548 { 0x0000, 0x0000, 0x0000 }, /* R1442 */ 1549 { 0x0000, 0x0000, 0x0000 }, /* R1443 */ 1550 { 0x0000, 0x0000, 0x0000 }, /* R1444 */ 1551 { 0x0000, 0x0000, 0x0000 }, /* R1445 */ 1552 { 0x0000, 0x0000, 0x0000 }, /* R1446 */ 1553 { 0x0000, 0x0000, 0x0000 }, /* R1447 */ 1554 { 0x0000, 0x0000, 0x0000 }, /* R1448 */ 1555 { 0x0000, 0x0000, 0x0000 }, /* R1449 */ 1556 { 0x0000, 0x0000, 0x0000 }, /* R1450 */ 1557 { 0x0000, 0x0000, 0x0000 }, /* R1451 */ 1558 { 0x0000, 0x0000, 0x0000 }, /* R1452 */ 1559 { 0x0000, 0x0000, 0x0000 }, /* R1453 */ 1560 { 0x0000, 0x0000, 0x0000 }, /* R1454 */ 1561 { 0x0000, 0x0000, 0x0000 }, /* R1455 */ 1562 { 0x0000, 0x0000, 0x0000 }, /* R1456 */ 1563 { 0x0000, 0x0000, 0x0000 }, /* R1457 */ 1564 { 0x0000, 0x0000, 0x0000 }, /* R1458 */ 1565 { 0x0000, 0x0000, 0x0000 }, /* R1459 */ 1566 { 0x0000, 0x0000, 0x0000 }, /* R1460 */ 1567 { 0x0000, 0x0000, 0x0000 }, /* R1461 */ 1568 { 0x0000, 0x0000, 0x0000 }, /* R1462 */ 1569 { 0x0000, 0x0000, 0x0000 }, /* R1463 */ 1570 { 0x0000, 0x0000, 0x0000 }, /* R1464 */ 1571 { 0x0000, 0x0000, 0x0000 }, /* R1465 */ 1572 { 0x0000, 0x0000, 0x0000 }, /* R1466 */ 1573 { 0x0000, 0x0000, 0x0000 }, /* R1467 */ 1574 { 0x0000, 0x0000, 0x0000 }, /* R1468 */ 1575 { 0x0000, 0x0000, 0x0000 }, /* R1469 */ 1576 { 0x0000, 0x0000, 0x0000 }, /* R1470 */ 1577 { 0x0000, 0x0000, 0x0000 }, /* R1471 */ 1578 { 0x0000, 0x0000, 0x0000 }, /* R1472 */ 1579 { 0x0000, 0x0000, 0x0000 }, /* R1473 */ 1580 { 0x0000, 0x0000, 0x0000 }, /* R1474 */ 1581 { 0x0000, 0x0000, 0x0000 }, /* R1475 */ 1582 { 0x0000, 0x0000, 0x0000 }, /* R1476 */ 1583 { 0x0000, 0x0000, 0x0000 }, /* R1477 */ 1584 { 0x0000, 0x0000, 0x0000 }, /* R1478 */ 1585 { 0x0000, 0x0000, 0x0000 }, /* R1479 */ 1586 { 0x0000, 0x0000, 0x0000 }, /* R1480 */ 1587 { 0x0000, 0x0000, 0x0000 }, /* R1481 */ 1588 { 0x0000, 0x0000, 0x0000 }, /* R1482 */ 1589 { 0x0000, 0x0000, 0x0000 }, /* R1483 */ 1590 { 0x0000, 0x0000, 0x0000 }, /* R1484 */ 1591 { 0x0000, 0x0000, 0x0000 }, /* R1485 */ 1592 { 0x0000, 0x0000, 0x0000 }, /* R1486 */ 1593 { 0x0000, 0x0000, 0x0000 }, /* R1487 */ 1594 { 0x0000, 0x0000, 0x0000 }, /* R1488 */ 1595 { 0x0000, 0x0000, 0x0000 }, /* R1489 */ 1596 { 0x0000, 0x0000, 0x0000 }, /* R1490 */ 1597 { 0x0000, 0x0000, 0x0000 }, /* R1491 */ 1598 { 0x0000, 0x0000, 0x0000 }, /* R1492 */ 1599 { 0x0000, 0x0000, 0x0000 }, /* R1493 */ 1600 { 0x0000, 0x0000, 0x0000 }, /* R1494 */ 1601 { 0x0000, 0x0000, 0x0000 }, /* R1495 */ 1602 { 0x0000, 0x0000, 0x0000 }, /* R1496 */ 1603 { 0x0000, 0x0000, 0x0000 }, /* R1497 */ 1604 { 0x0000, 0x0000, 0x0000 }, /* R1498 */ 1605 { 0x0000, 0x0000, 0x0000 }, /* R1499 */ 1606 { 0x0000, 0x0000, 0x0000 }, /* R1500 */ 1607 { 0x0000, 0x0000, 0x0000 }, /* R1501 */ 1608 { 0x0000, 0x0000, 0x0000 }, /* R1502 */ 1609 { 0x0000, 0x0000, 0x0000 }, /* R1503 */ 1610 { 0x0000, 0x0000, 0x0000 }, /* R1504 */ 1611 { 0x0000, 0x0000, 0x0000 }, /* R1505 */ 1612 { 0x0000, 0x0000, 0x0000 }, /* R1506 */ 1613 { 0x0000, 0x0000, 0x0000 }, /* R1507 */ 1614 { 0x0000, 0x0000, 0x0000 }, /* R1508 */ 1615 { 0x0000, 0x0000, 0x0000 }, /* R1509 */ 1616 { 0x0000, 0x0000, 0x0000 }, /* R1510 */ 1617 { 0x0000, 0x0000, 0x0000 }, /* R1511 */ 1618 { 0x0000, 0x0000, 0x0000 }, /* R1512 */ 1619 { 0x0000, 0x0000, 0x0000 }, /* R1513 */ 1620 { 0x0000, 0x0000, 0x0000 }, /* R1514 */ 1621 { 0x0000, 0x0000, 0x0000 }, /* R1515 */ 1622 { 0x0000, 0x0000, 0x0000 }, /* R1516 */ 1623 { 0x0000, 0x0000, 0x0000 }, /* R1517 */ 1624 { 0x0000, 0x0000, 0x0000 }, /* R1518 */ 1625 { 0x0000, 0x0000, 0x0000 }, /* R1519 */ 1626 { 0x0000, 0x0000, 0x0000 }, /* R1520 */ 1627 { 0x0000, 0x0000, 0x0000 }, /* R1521 */ 1628 { 0x0000, 0x0000, 0x0000 }, /* R1522 */ 1629 { 0x0000, 0x0000, 0x0000 }, /* R1523 */ 1630 { 0x0000, 0x0000, 0x0000 }, /* R1524 */ 1631 { 0x0000, 0x0000, 0x0000 }, /* R1525 */ 1632 { 0x0000, 0x0000, 0x0000 }, /* R1526 */ 1633 { 0x0000, 0x0000, 0x0000 }, /* R1527 */ 1634 { 0x0000, 0x0000, 0x0000 }, /* R1528 */ 1635 { 0x0000, 0x0000, 0x0000 }, /* R1529 */ 1636 { 0x0000, 0x0000, 0x0000 }, /* R1530 */ 1637 { 0x0000, 0x0000, 0x0000 }, /* R1531 */ 1638 { 0x0000, 0x0000, 0x0000 }, /* R1532 */ 1639 { 0x0000, 0x0000, 0x0000 }, /* R1533 */ 1640 { 0x0000, 0x0000, 0x0000 }, /* R1534 */ 1641 { 0x0000, 0x0000, 0x0000 }, /* R1535 */ 1642 { 0x01EF, 0x01EF, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */ 1643 { 0x0037, 0x0037, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */ 1644 { 0x0037, 0x0037, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */ 1645 { 0x01EF, 0x01EF, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */ 1646 { 0x0037, 0x0037, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */ 1647 { 0x0037, 0x0037, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */ 1648 { 0x0003, 0x0003, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ 1649 { 0x0003, 0x0003, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ 1650 { 0x0003, 0x0003, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ 1651 { 0x0003, 0x0003, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ 1652 { 0x0000, 0x0000, 0x0000 }, /* R1546 */ 1653 { 0x0000, 0x0000, 0x0000 }, /* R1547 */ 1654 { 0x0000, 0x0000, 0x0000 }, /* R1548 */ 1655 { 0x0000, 0x0000, 0x0000 }, /* R1549 */ 1656 { 0x0000, 0x0000, 0x0000 }, /* R1550 */ 1657 { 0x0000, 0x0000, 0x0000 }, /* R1551 */ 1658 { 0x02FF, 0x03FF, 0x0000 }, /* R1552 - DAC1 Left Volume */ 1659 { 0x02FF, 0x03FF, 0x0000 }, /* R1553 - DAC1 Right Volume */ 1660 { 0x02FF, 0x03FF, 0x0000 }, /* R1554 - DAC2 Left Volume */ 1661 { 0x02FF, 0x03FF, 0x0000 }, /* R1555 - DAC2 Right Volume */ 1662 { 0x0003, 0x0003, 0x0000 }, /* R1556 - DAC Softmute */ 1663 { 0x0000, 0x0000, 0x0000 }, /* R1557 */ 1664 { 0x0000, 0x0000, 0x0000 }, /* R1558 */ 1665 { 0x0000, 0x0000, 0x0000 }, /* R1559 */ 1666 { 0x0000, 0x0000, 0x0000 }, /* R1560 */ 1667 { 0x0000, 0x0000, 0x0000 }, /* R1561 */ 1668 { 0x0000, 0x0000, 0x0000 }, /* R1562 */ 1669 { 0x0000, 0x0000, 0x0000 }, /* R1563 */ 1670 { 0x0000, 0x0000, 0x0000 }, /* R1564 */ 1671 { 0x0000, 0x0000, 0x0000 }, /* R1565 */ 1672 { 0x0000, 0x0000, 0x0000 }, /* R1566 */ 1673 { 0x0000, 0x0000, 0x0000 }, /* R1567 */ 1674 { 0x0003, 0x0003, 0x0000 }, /* R1568 - Oversampling */ 1675 { 0x03C3, 0x03C3, 0x0000 }, /* R1569 - Sidetone */ 1676 }; 1677 1678 static int wm8994_readable(unsigned int reg) 1679 { 1680 if (reg >= ARRAY_SIZE(access_masks)) 1681 return 0; 1682 return access_masks[reg].readable != 0; 1683 } 1684 1685 static int wm8994_volatile(unsigned int reg) 1686 { 1687 if (reg >= WM8994_REG_CACHE_SIZE) 1688 return 1; 1689 1690 switch (reg) { 1691 case WM8994_SOFTWARE_RESET: 1692 case WM8994_CHIP_REVISION: 1693 case WM8994_DC_SERVO_1: 1694 case WM8994_DC_SERVO_READBACK: 1695 case WM8994_RATE_STATUS: 1696 case WM8994_LDO_1: 1697 case WM8994_LDO_2: 1698 return 1; 1699 default: 1700 return 0; 1701 } 1702 } 1703 1704 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 1705 unsigned int value) 1706 { 1707 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1708 1709 BUG_ON(reg > WM8994_MAX_REGISTER); 1710 1711 if (!wm8994_volatile(reg)) 1712 wm8994->reg_cache[reg] = value; 1713 1714 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value); 1715 1716 return wm8994_reg_write(codec->control_data, reg, value); 1717 } 1718 1719 static unsigned int wm8994_read(struct snd_soc_codec *codec, 1720 unsigned int reg) 1721 { 1722 u16 *reg_cache = codec->reg_cache; 1723 1724 BUG_ON(reg > WM8994_MAX_REGISTER); 1725 1726 if (wm8994_volatile(reg)) 1727 return wm8994_reg_read(codec->control_data, reg); 1728 else 1729 return reg_cache[reg]; 1730 } 1731 1732 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 1733 { 1734 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1735 int rate; 1736 int reg1 = 0; 1737 int offset; 1738 1739 if (aif) 1740 offset = 4; 1741 else 1742 offset = 0; 1743 1744 switch (wm8994->sysclk[aif]) { 1745 case WM8994_SYSCLK_MCLK1: 1746 rate = wm8994->mclk[0]; 1747 break; 1748 1749 case WM8994_SYSCLK_MCLK2: 1750 reg1 |= 0x8; 1751 rate = wm8994->mclk[1]; 1752 break; 1753 1754 case WM8994_SYSCLK_FLL1: 1755 reg1 |= 0x10; 1756 rate = wm8994->fll[0].out; 1757 break; 1758 1759 case WM8994_SYSCLK_FLL2: 1760 reg1 |= 0x18; 1761 rate = wm8994->fll[1].out; 1762 break; 1763 1764 default: 1765 return -EINVAL; 1766 } 1767 1768 if (rate >= 13500000) { 1769 rate /= 2; 1770 reg1 |= WM8994_AIF1CLK_DIV; 1771 1772 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 1773 aif + 1, rate); 1774 } 1775 1776 if (rate && rate < 3000000) 1777 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n", 1778 aif + 1, rate); 1779 1780 wm8994->aifclk[aif] = rate; 1781 1782 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, 1783 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, 1784 reg1); 1785 1786 return 0; 1787 } 1788 1789 static int configure_clock(struct snd_soc_codec *codec) 1790 { 1791 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1792 int old, new; 1793 1794 /* Bring up the AIF clocks first */ 1795 configure_aif_clock(codec, 0); 1796 configure_aif_clock(codec, 1); 1797 1798 /* Then switch CLK_SYS over to the higher of them; a change 1799 * can only happen as a result of a clocking change which can 1800 * only be made outside of DAPM so we can safely redo the 1801 * clocking. 1802 */ 1803 1804 /* If they're equal it doesn't matter which is used */ 1805 if (wm8994->aifclk[0] == wm8994->aifclk[1]) 1806 return 0; 1807 1808 if (wm8994->aifclk[0] < wm8994->aifclk[1]) 1809 new = WM8994_SYSCLK_SRC; 1810 else 1811 new = 0; 1812 1813 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC; 1814 1815 /* If there's no change then we're done. */ 1816 if (old == new) 1817 return 0; 1818 1819 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 1820 1821 snd_soc_dapm_sync(codec); 1822 1823 return 0; 1824 } 1825 1826 static int check_clk_sys(struct snd_soc_dapm_widget *source, 1827 struct snd_soc_dapm_widget *sink) 1828 { 1829 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); 1830 const char *clk; 1831 1832 /* Check what we're currently using for CLK_SYS */ 1833 if (reg & WM8994_SYSCLK_SRC) 1834 clk = "AIF2CLK"; 1835 else 1836 clk = "AIF1CLK"; 1837 1838 return strcmp(source->name, clk) == 0; 1839 } 1840 1841 static const char *sidetone_hpf_text[] = { 1842 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" 1843 }; 1844 1845 static const struct soc_enum sidetone_hpf = 1846 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 1847 1848 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 1849 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 1850 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 1851 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); 1852 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 1853 1854 #define WM8994_DRC_SWITCH(xname, reg, shift) \ 1855 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1856 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 1857 .put = wm8994_put_drc_sw, \ 1858 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } 1859 1860 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, 1861 struct snd_ctl_elem_value *ucontrol) 1862 { 1863 struct soc_mixer_control *mc = 1864 (struct soc_mixer_control *)kcontrol->private_value; 1865 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1866 int mask, ret; 1867 1868 /* Can't enable both ADC and DAC paths simultaneously */ 1869 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) 1870 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | 1871 WM8994_AIF1ADC1R_DRC_ENA_MASK; 1872 else 1873 mask = WM8994_AIF1DAC1_DRC_ENA_MASK; 1874 1875 ret = snd_soc_read(codec, mc->reg); 1876 if (ret < 0) 1877 return ret; 1878 if (ret & mask) 1879 return -EINVAL; 1880 1881 return snd_soc_put_volsw(kcontrol, ucontrol); 1882 } 1883 1884 1885 1886 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) 1887 { 1888 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1889 struct wm8994_pdata *pdata = wm8994->pdata; 1890 int base = wm8994_drc_base[drc]; 1891 int cfg = wm8994->drc_cfg[drc]; 1892 int save, i; 1893 1894 /* Save any enables; the configuration should clear them. */ 1895 save = snd_soc_read(codec, base); 1896 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | 1897 WM8994_AIF1ADC1R_DRC_ENA; 1898 1899 for (i = 0; i < WM8994_DRC_REGS; i++) 1900 snd_soc_update_bits(codec, base + i, 0xffff, 1901 pdata->drc_cfgs[cfg].regs[i]); 1902 1903 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | 1904 WM8994_AIF1ADC1L_DRC_ENA | 1905 WM8994_AIF1ADC1R_DRC_ENA, save); 1906 } 1907 1908 /* Icky as hell but saves code duplication */ 1909 static int wm8994_get_drc(const char *name) 1910 { 1911 if (strcmp(name, "AIF1DRC1 Mode") == 0) 1912 return 0; 1913 if (strcmp(name, "AIF1DRC2 Mode") == 0) 1914 return 1; 1915 if (strcmp(name, "AIF2DRC Mode") == 0) 1916 return 2; 1917 return -EINVAL; 1918 } 1919 1920 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 1921 struct snd_ctl_elem_value *ucontrol) 1922 { 1923 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1924 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1925 struct wm8994_pdata *pdata = wm8994->pdata; 1926 int drc = wm8994_get_drc(kcontrol->id.name); 1927 int value = ucontrol->value.integer.value[0]; 1928 1929 if (drc < 0) 1930 return drc; 1931 1932 if (value >= pdata->num_drc_cfgs) 1933 return -EINVAL; 1934 1935 wm8994->drc_cfg[drc] = value; 1936 1937 wm8994_set_drc(codec, drc); 1938 1939 return 0; 1940 } 1941 1942 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 1943 struct snd_ctl_elem_value *ucontrol) 1944 { 1945 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1946 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1947 int drc = wm8994_get_drc(kcontrol->id.name); 1948 1949 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; 1950 1951 return 0; 1952 } 1953 1954 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) 1955 { 1956 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1957 struct wm8994_pdata *pdata = wm8994->pdata; 1958 int base = wm8994_retune_mobile_base[block]; 1959 int iface, best, best_val, save, i, cfg; 1960 1961 if (!pdata || !wm8994->num_retune_mobile_texts) 1962 return; 1963 1964 switch (block) { 1965 case 0: 1966 case 1: 1967 iface = 0; 1968 break; 1969 case 2: 1970 iface = 1; 1971 break; 1972 default: 1973 return; 1974 } 1975 1976 /* Find the version of the currently selected configuration 1977 * with the nearest sample rate. */ 1978 cfg = wm8994->retune_mobile_cfg[block]; 1979 best = 0; 1980 best_val = INT_MAX; 1981 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 1982 if (strcmp(pdata->retune_mobile_cfgs[i].name, 1983 wm8994->retune_mobile_texts[cfg]) == 0 && 1984 abs(pdata->retune_mobile_cfgs[i].rate 1985 - wm8994->dac_rates[iface]) < best_val) { 1986 best = i; 1987 best_val = abs(pdata->retune_mobile_cfgs[i].rate 1988 - wm8994->dac_rates[iface]); 1989 } 1990 } 1991 1992 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 1993 block, 1994 pdata->retune_mobile_cfgs[best].name, 1995 pdata->retune_mobile_cfgs[best].rate, 1996 wm8994->dac_rates[iface]); 1997 1998 /* The EQ will be disabled while reconfiguring it, remember the 1999 * current configuration. 2000 */ 2001 save = snd_soc_read(codec, base); 2002 save &= WM8994_AIF1DAC1_EQ_ENA; 2003 2004 for (i = 0; i < WM8994_EQ_REGS; i++) 2005 snd_soc_update_bits(codec, base + i, 0xffff, 2006 pdata->retune_mobile_cfgs[best].regs[i]); 2007 2008 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); 2009 } 2010 2011 /* Icky as hell but saves code duplication */ 2012 static int wm8994_get_retune_mobile_block(const char *name) 2013 { 2014 if (strcmp(name, "AIF1.1 EQ Mode") == 0) 2015 return 0; 2016 if (strcmp(name, "AIF1.2 EQ Mode") == 0) 2017 return 1; 2018 if (strcmp(name, "AIF2 EQ Mode") == 0) 2019 return 2; 2020 return -EINVAL; 2021 } 2022 2023 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 2024 struct snd_ctl_elem_value *ucontrol) 2025 { 2026 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2027 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2028 struct wm8994_pdata *pdata = wm8994->pdata; 2029 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 2030 int value = ucontrol->value.integer.value[0]; 2031 2032 if (block < 0) 2033 return block; 2034 2035 if (value >= pdata->num_retune_mobile_cfgs) 2036 return -EINVAL; 2037 2038 wm8994->retune_mobile_cfg[block] = value; 2039 2040 wm8994_set_retune_mobile(codec, block); 2041 2042 return 0; 2043 } 2044 2045 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 2046 struct snd_ctl_elem_value *ucontrol) 2047 { 2048 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2049 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2050 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 2051 2052 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; 2053 2054 return 0; 2055 } 2056 2057 static const struct snd_kcontrol_new wm8994_snd_controls[] = { 2058 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 2059 WM8994_AIF1_ADC1_RIGHT_VOLUME, 2060 1, 119, 0, digital_tlv), 2061 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, 2062 WM8994_AIF1_ADC2_RIGHT_VOLUME, 2063 1, 119, 0, digital_tlv), 2064 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, 2065 WM8994_AIF2_ADC_RIGHT_VOLUME, 2066 1, 119, 0, digital_tlv), 2067 2068 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 2069 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 2070 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, 2071 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 2072 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, 2073 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 2074 2075 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), 2076 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), 2077 2078 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), 2079 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), 2080 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), 2081 2082 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), 2083 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), 2084 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), 2085 2086 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), 2087 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), 2088 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), 2089 2090 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), 2091 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), 2092 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), 2093 2094 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 2095 5, 12, 0, st_tlv), 2096 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, 2097 0, 12, 0, st_tlv), 2098 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 2099 5, 12, 0, st_tlv), 2100 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, 2101 0, 12, 0, st_tlv), 2102 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 2103 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 2104 2105 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 2106 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 2107 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 2108 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), 2109 2110 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, 2111 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 2112 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, 2113 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), 2114 2115 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, 2116 6, 1, 1, wm_hubs_spkmix_tlv), 2117 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, 2118 2, 1, 1, wm_hubs_spkmix_tlv), 2119 2120 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, 2121 6, 1, 1, wm_hubs_spkmix_tlv), 2122 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, 2123 2, 1, 1, wm_hubs_spkmix_tlv), 2124 2125 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 2126 10, 15, 0, wm8994_3d_tlv), 2127 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 2128 8, 1, 0), 2129 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 2130 10, 15, 0, wm8994_3d_tlv), 2131 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 2132 8, 1, 0), 2133 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 2134 10, 15, 0, wm8994_3d_tlv), 2135 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 2136 8, 1, 0), 2137 }; 2138 2139 static const struct snd_kcontrol_new wm8994_eq_controls[] = { 2140 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, 2141 eq_tlv), 2142 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, 2143 eq_tlv), 2144 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, 2145 eq_tlv), 2146 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, 2147 eq_tlv), 2148 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, 2149 eq_tlv), 2150 2151 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, 2152 eq_tlv), 2153 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, 2154 eq_tlv), 2155 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, 2156 eq_tlv), 2157 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, 2158 eq_tlv), 2159 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, 2160 eq_tlv), 2161 2162 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, 2163 eq_tlv), 2164 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, 2165 eq_tlv), 2166 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, 2167 eq_tlv), 2168 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, 2169 eq_tlv), 2170 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, 2171 eq_tlv), 2172 }; 2173 2174 static int clk_sys_event(struct snd_soc_dapm_widget *w, 2175 struct snd_kcontrol *kcontrol, int event) 2176 { 2177 struct snd_soc_codec *codec = w->codec; 2178 2179 switch (event) { 2180 case SND_SOC_DAPM_PRE_PMU: 2181 return configure_clock(codec); 2182 2183 case SND_SOC_DAPM_POST_PMD: 2184 configure_clock(codec); 2185 break; 2186 } 2187 2188 return 0; 2189 } 2190 2191 static void wm8994_update_class_w(struct snd_soc_codec *codec) 2192 { 2193 int enable = 1; 2194 int source = 0; /* GCC flow analysis can't track enable */ 2195 int reg, reg_r; 2196 2197 /* Only support direct DAC->headphone paths */ 2198 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1); 2199 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) { 2200 dev_vdbg(codec->dev, "HPL connected to output mixer\n"); 2201 enable = 0; 2202 } 2203 2204 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2); 2205 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) { 2206 dev_vdbg(codec->dev, "HPR connected to output mixer\n"); 2207 enable = 0; 2208 } 2209 2210 /* We also need the same setting for L/R and only one path */ 2211 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 2212 switch (reg) { 2213 case WM8994_AIF2DACL_TO_DAC1L: 2214 dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); 2215 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; 2216 break; 2217 case WM8994_AIF1DAC2L_TO_DAC1L: 2218 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); 2219 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; 2220 break; 2221 case WM8994_AIF1DAC1L_TO_DAC1L: 2222 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); 2223 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; 2224 break; 2225 default: 2226 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 2227 enable = 0; 2228 break; 2229 } 2230 2231 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 2232 if (reg_r != reg) { 2233 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 2234 enable = 0; 2235 } 2236 2237 if (enable) { 2238 dev_dbg(codec->dev, "Class W enabled\n"); 2239 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 2240 WM8994_CP_DYN_PWR | 2241 WM8994_CP_DYN_SRC_SEL_MASK, 2242 source | WM8994_CP_DYN_PWR); 2243 2244 } else { 2245 dev_dbg(codec->dev, "Class W disabled\n"); 2246 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 2247 WM8994_CP_DYN_PWR, 0); 2248 } 2249 } 2250 2251 static const char *hp_mux_text[] = { 2252 "Mixer", 2253 "DAC", 2254 }; 2255 2256 #define WM8994_HP_ENUM(xname, xenum) \ 2257 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2258 .info = snd_soc_info_enum_double, \ 2259 .get = snd_soc_dapm_get_enum_double, \ 2260 .put = wm8994_put_hp_enum, \ 2261 .private_value = (unsigned long)&xenum } 2262 2263 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol, 2264 struct snd_ctl_elem_value *ucontrol) 2265 { 2266 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 2267 struct snd_soc_codec *codec = w->codec; 2268 int ret; 2269 2270 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 2271 2272 wm8994_update_class_w(codec); 2273 2274 return ret; 2275 } 2276 2277 static const struct soc_enum hpl_enum = 2278 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text); 2279 2280 static const struct snd_kcontrol_new hpl_mux = 2281 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum); 2282 2283 static const struct soc_enum hpr_enum = 2284 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text); 2285 2286 static const struct snd_kcontrol_new hpr_mux = 2287 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum); 2288 2289 static const char *adc_mux_text[] = { 2290 "ADC", 2291 "DMIC", 2292 }; 2293 2294 static const struct soc_enum adc_enum = 2295 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 2296 2297 static const struct snd_kcontrol_new adcl_mux = 2298 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 2299 2300 static const struct snd_kcontrol_new adcr_mux = 2301 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 2302 2303 static const struct snd_kcontrol_new left_speaker_mixer[] = { 2304 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 2305 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), 2306 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), 2307 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), 2308 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), 2309 }; 2310 2311 static const struct snd_kcontrol_new right_speaker_mixer[] = { 2312 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), 2313 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), 2314 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), 2315 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), 2316 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), 2317 }; 2318 2319 /* Debugging; dump chip status after DAPM transitions */ 2320 static int post_ev(struct snd_soc_dapm_widget *w, 2321 struct snd_kcontrol *kcontrol, int event) 2322 { 2323 struct snd_soc_codec *codec = w->codec; 2324 dev_dbg(codec->dev, "SRC status: %x\n", 2325 snd_soc_read(codec, 2326 WM8994_RATE_STATUS)); 2327 return 0; 2328 } 2329 2330 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 2331 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 2332 1, 1, 0), 2333 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, 2334 0, 1, 0), 2335 }; 2336 2337 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 2338 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 2339 1, 1, 0), 2340 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, 2341 0, 1, 0), 2342 }; 2343 2344 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 2345 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 2346 5, 1, 0), 2347 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 2348 4, 1, 0), 2349 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 2350 2, 1, 0), 2351 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 2352 1, 1, 0), 2353 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, 2354 0, 1, 0), 2355 }; 2356 2357 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 2358 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 2359 5, 1, 0), 2360 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 2361 4, 1, 0), 2362 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 2363 2, 1, 0), 2364 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 2365 1, 1, 0), 2366 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, 2367 0, 1, 0), 2368 }; 2369 2370 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 2371 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2372 .info = snd_soc_info_volsw, \ 2373 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ 2374 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 2375 2376 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, 2377 struct snd_ctl_elem_value *ucontrol) 2378 { 2379 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol); 2380 struct snd_soc_codec *codec = w->codec; 2381 int ret; 2382 2383 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 2384 2385 wm8994_update_class_w(codec); 2386 2387 return ret; 2388 } 2389 2390 static const struct snd_kcontrol_new dac1l_mix[] = { 2391 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 2392 5, 1, 0), 2393 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 2394 4, 1, 0), 2395 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 2396 2, 1, 0), 2397 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 2398 1, 1, 0), 2399 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, 2400 0, 1, 0), 2401 }; 2402 2403 static const struct snd_kcontrol_new dac1r_mix[] = { 2404 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 2405 5, 1, 0), 2406 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 2407 4, 1, 0), 2408 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 2409 2, 1, 0), 2410 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 2411 1, 1, 0), 2412 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, 2413 0, 1, 0), 2414 }; 2415 2416 static const char *sidetone_text[] = { 2417 "ADC/DMIC1", "DMIC2", 2418 }; 2419 2420 static const struct soc_enum sidetone1_enum = 2421 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); 2422 2423 static const struct snd_kcontrol_new sidetone1_mux = 2424 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 2425 2426 static const struct soc_enum sidetone2_enum = 2427 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); 2428 2429 static const struct snd_kcontrol_new sidetone2_mux = 2430 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 2431 2432 static const char *aif1dac_text[] = { 2433 "AIF1DACDAT", "AIF3DACDAT", 2434 }; 2435 2436 static const struct soc_enum aif1dac_enum = 2437 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); 2438 2439 static const struct snd_kcontrol_new aif1dac_mux = 2440 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); 2441 2442 static const char *aif2dac_text[] = { 2443 "AIF2DACDAT", "AIF3DACDAT", 2444 }; 2445 2446 static const struct soc_enum aif2dac_enum = 2447 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); 2448 2449 static const struct snd_kcontrol_new aif2dac_mux = 2450 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); 2451 2452 static const char *aif2adc_text[] = { 2453 "AIF2ADCDAT", "AIF3DACDAT", 2454 }; 2455 2456 static const struct soc_enum aif2adc_enum = 2457 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); 2458 2459 static const struct snd_kcontrol_new aif2adc_mux = 2460 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 2461 2462 static const char *aif3adc_text[] = { 2463 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", 2464 }; 2465 2466 static const struct soc_enum aif3adc_enum = 2467 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 2468 2469 static const struct snd_kcontrol_new aif3adc_mux = 2470 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum); 2471 2472 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 2473 SND_SOC_DAPM_INPUT("DMIC1DAT"), 2474 SND_SOC_DAPM_INPUT("DMIC2DAT"), 2475 2476 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 2477 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2478 2479 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0), 2480 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0), 2481 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0), 2482 2483 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0), 2484 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0), 2485 2486 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 2487 0, WM8994_POWER_MANAGEMENT_4, 9, 0), 2488 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 2489 0, WM8994_POWER_MANAGEMENT_4, 8, 0), 2490 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, 2491 WM8994_POWER_MANAGEMENT_5, 9, 0), 2492 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, 2493 WM8994_POWER_MANAGEMENT_5, 8, 0), 2494 2495 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 2496 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 2497 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 2498 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 2499 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, 2500 WM8994_POWER_MANAGEMENT_5, 11, 0), 2501 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, 2502 WM8994_POWER_MANAGEMENT_5, 10, 0), 2503 2504 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 2505 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 2506 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 2507 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 2508 2509 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 2510 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 2511 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 2512 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 2513 2514 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 2515 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 2516 2517 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 2518 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 2519 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 2520 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 2521 2522 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, 2523 WM8994_POWER_MANAGEMENT_4, 13, 0), 2524 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 2525 WM8994_POWER_MANAGEMENT_4, 12, 0), 2526 SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0, 2527 WM8994_POWER_MANAGEMENT_5, 13, 0), 2528 SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0, 2529 WM8994_POWER_MANAGEMENT_5, 12, 0), 2530 2531 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 2532 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 2533 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 2534 2535 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 2536 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 2537 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 2538 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux), 2539 2540 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 2541 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 2542 2543 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), 2544 2545 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), 2546 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), 2547 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), 2548 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), 2549 2550 /* Power is done with the muxes since the ADC power also controls the 2551 * downsampling chain, the chip will automatically manage the analogue 2552 * specific portions. 2553 */ 2554 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), 2555 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 2556 2557 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 2558 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 2559 2560 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), 2561 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), 2562 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), 2563 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), 2564 2565 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 2566 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 2567 2568 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, 2569 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 2570 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 2571 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 2572 2573 SND_SOC_DAPM_POST("Debug log", post_ev), 2574 }; 2575 2576 static const struct snd_soc_dapm_route intercon[] = { 2577 2578 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 2579 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 2580 2581 { "DSP1CLK", NULL, "CLK_SYS" }, 2582 { "DSP2CLK", NULL, "CLK_SYS" }, 2583 { "DSPINTCLK", NULL, "CLK_SYS" }, 2584 2585 { "AIF1ADC1L", NULL, "AIF1CLK" }, 2586 { "AIF1ADC1L", NULL, "DSP1CLK" }, 2587 { "AIF1ADC1R", NULL, "AIF1CLK" }, 2588 { "AIF1ADC1R", NULL, "DSP1CLK" }, 2589 { "AIF1ADC1R", NULL, "DSPINTCLK" }, 2590 2591 { "AIF1DAC1L", NULL, "AIF1CLK" }, 2592 { "AIF1DAC1L", NULL, "DSP1CLK" }, 2593 { "AIF1DAC1R", NULL, "AIF1CLK" }, 2594 { "AIF1DAC1R", NULL, "DSP1CLK" }, 2595 { "AIF1DAC1R", NULL, "DSPINTCLK" }, 2596 2597 { "AIF1ADC2L", NULL, "AIF1CLK" }, 2598 { "AIF1ADC2L", NULL, "DSP1CLK" }, 2599 { "AIF1ADC2R", NULL, "AIF1CLK" }, 2600 { "AIF1ADC2R", NULL, "DSP1CLK" }, 2601 { "AIF1ADC2R", NULL, "DSPINTCLK" }, 2602 2603 { "AIF1DAC2L", NULL, "AIF1CLK" }, 2604 { "AIF1DAC2L", NULL, "DSP1CLK" }, 2605 { "AIF1DAC2R", NULL, "AIF1CLK" }, 2606 { "AIF1DAC2R", NULL, "DSP1CLK" }, 2607 { "AIF1DAC2R", NULL, "DSPINTCLK" }, 2608 2609 { "AIF2ADCL", NULL, "AIF2CLK" }, 2610 { "AIF2ADCL", NULL, "DSP2CLK" }, 2611 { "AIF2ADCR", NULL, "AIF2CLK" }, 2612 { "AIF2ADCR", NULL, "DSP2CLK" }, 2613 { "AIF2ADCR", NULL, "DSPINTCLK" }, 2614 2615 { "AIF2DACL", NULL, "AIF2CLK" }, 2616 { "AIF2DACL", NULL, "DSP2CLK" }, 2617 { "AIF2DACR", NULL, "AIF2CLK" }, 2618 { "AIF2DACR", NULL, "DSP2CLK" }, 2619 { "AIF2DACR", NULL, "DSPINTCLK" }, 2620 2621 { "DMIC1L", NULL, "DMIC1DAT" }, 2622 { "DMIC1L", NULL, "CLK_SYS" }, 2623 { "DMIC1R", NULL, "DMIC1DAT" }, 2624 { "DMIC1R", NULL, "CLK_SYS" }, 2625 { "DMIC2L", NULL, "DMIC2DAT" }, 2626 { "DMIC2L", NULL, "CLK_SYS" }, 2627 { "DMIC2R", NULL, "DMIC2DAT" }, 2628 { "DMIC2R", NULL, "CLK_SYS" }, 2629 2630 { "ADCL", NULL, "AIF1CLK" }, 2631 { "ADCL", NULL, "DSP1CLK" }, 2632 { "ADCL", NULL, "DSPINTCLK" }, 2633 2634 { "ADCR", NULL, "AIF1CLK" }, 2635 { "ADCR", NULL, "DSP1CLK" }, 2636 { "ADCR", NULL, "DSPINTCLK" }, 2637 2638 { "ADCL Mux", "ADC", "ADCL" }, 2639 { "ADCL Mux", "DMIC", "DMIC1L" }, 2640 { "ADCR Mux", "ADC", "ADCR" }, 2641 { "ADCR Mux", "DMIC", "DMIC1R" }, 2642 2643 { "DAC1L", NULL, "AIF1CLK" }, 2644 { "DAC1L", NULL, "DSP1CLK" }, 2645 { "DAC1L", NULL, "DSPINTCLK" }, 2646 2647 { "DAC1R", NULL, "AIF1CLK" }, 2648 { "DAC1R", NULL, "DSP1CLK" }, 2649 { "DAC1R", NULL, "DSPINTCLK" }, 2650 2651 { "DAC2L", NULL, "AIF2CLK" }, 2652 { "DAC2L", NULL, "DSP2CLK" }, 2653 { "DAC2L", NULL, "DSPINTCLK" }, 2654 2655 { "DAC2R", NULL, "AIF2DACR" }, 2656 { "DAC2R", NULL, "AIF2CLK" }, 2657 { "DAC2R", NULL, "DSP2CLK" }, 2658 { "DAC2R", NULL, "DSPINTCLK" }, 2659 2660 { "TOCLK", NULL, "CLK_SYS" }, 2661 2662 /* AIF1 outputs */ 2663 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 2664 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 2665 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 2666 2667 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 2668 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 2669 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 2670 2671 /* Pin level routing for AIF3 */ 2672 { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, 2673 { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, 2674 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 2675 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 2676 2677 { "AIF2DACL", NULL, "AIF2DAC Mux" }, 2678 { "AIF2DACR", NULL, "AIF2DAC Mux" }, 2679 2680 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 2681 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 2682 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 2683 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 2684 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, 2685 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, 2686 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, 2687 2688 /* DAC1 inputs */ 2689 { "DAC1L", NULL, "DAC1L Mixer" }, 2690 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, 2691 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 2692 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 2693 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 2694 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 2695 2696 { "DAC1R", NULL, "DAC1R Mixer" }, 2697 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, 2698 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 2699 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 2700 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 2701 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 2702 2703 /* DAC2/AIF2 outputs */ 2704 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, 2705 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 2706 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, 2707 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 2708 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 2709 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 2710 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 2711 2712 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, 2713 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 2714 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, 2715 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 2716 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 2717 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 2718 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 2719 2720 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, 2721 2722 /* AIF3 output */ 2723 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, 2724 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, 2725 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, 2726 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, 2727 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, 2728 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, 2729 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, 2730 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, 2731 2732 /* Sidetone */ 2733 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, 2734 { "Left Sidetone", "DMIC2", "DMIC2L" }, 2735 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, 2736 { "Right Sidetone", "DMIC2", "DMIC2R" }, 2737 2738 /* Output stages */ 2739 { "Left Output Mixer", "DAC Switch", "DAC1L" }, 2740 { "Right Output Mixer", "DAC Switch", "DAC1R" }, 2741 2742 { "SPKL", "DAC1 Switch", "DAC1L" }, 2743 { "SPKL", "DAC2 Switch", "DAC2L" }, 2744 2745 { "SPKR", "DAC1 Switch", "DAC1R" }, 2746 { "SPKR", "DAC2 Switch", "DAC2R" }, 2747 2748 { "Left Headphone Mux", "DAC", "DAC1L" }, 2749 { "Right Headphone Mux", "DAC", "DAC1R" }, 2750 }; 2751 2752 /* The size in bits of the FLL divide multiplied by 10 2753 * to allow rounding later */ 2754 #define FIXED_FLL_SIZE ((1 << 16) * 10) 2755 2756 struct fll_div { 2757 u16 outdiv; 2758 u16 n; 2759 u16 k; 2760 u16 clk_ref_div; 2761 u16 fll_fratio; 2762 }; 2763 2764 static int wm8994_get_fll_config(struct fll_div *fll, 2765 int freq_in, int freq_out) 2766 { 2767 u64 Kpart; 2768 unsigned int K, Ndiv, Nmod; 2769 2770 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 2771 2772 /* Scale the input frequency down to <= 13.5MHz */ 2773 fll->clk_ref_div = 0; 2774 while (freq_in > 13500000) { 2775 fll->clk_ref_div++; 2776 freq_in /= 2; 2777 2778 if (fll->clk_ref_div > 3) 2779 return -EINVAL; 2780 } 2781 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 2782 2783 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 2784 fll->outdiv = 3; 2785 while (freq_out * (fll->outdiv + 1) < 90000000) { 2786 fll->outdiv++; 2787 if (fll->outdiv > 63) 2788 return -EINVAL; 2789 } 2790 freq_out *= fll->outdiv + 1; 2791 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 2792 2793 if (freq_in > 1000000) { 2794 fll->fll_fratio = 0; 2795 } else if (freq_in > 256000) { 2796 fll->fll_fratio = 1; 2797 freq_in *= 2; 2798 } else if (freq_in > 128000) { 2799 fll->fll_fratio = 2; 2800 freq_in *= 4; 2801 } else if (freq_in > 64000) { 2802 fll->fll_fratio = 3; 2803 freq_in *= 8; 2804 } else { 2805 fll->fll_fratio = 4; 2806 freq_in *= 16; 2807 } 2808 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 2809 2810 /* Now, calculate N.K */ 2811 Ndiv = freq_out / freq_in; 2812 2813 fll->n = Ndiv; 2814 Nmod = freq_out % freq_in; 2815 pr_debug("Nmod=%d\n", Nmod); 2816 2817 /* Calculate fractional part - scale up so we can round. */ 2818 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 2819 2820 do_div(Kpart, freq_in); 2821 2822 K = Kpart & 0xFFFFFFFF; 2823 2824 if ((K % 10) >= 5) 2825 K += 5; 2826 2827 /* Move down to proper range now rounding is done */ 2828 fll->k = K / 10; 2829 2830 pr_debug("N=%x K=%x\n", fll->n, fll->k); 2831 2832 return 0; 2833 } 2834 2835 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, 2836 unsigned int freq_in, unsigned int freq_out) 2837 { 2838 struct snd_soc_codec *codec = dai->codec; 2839 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2840 int reg_offset, ret; 2841 struct fll_div fll; 2842 u16 reg, aif1, aif2; 2843 2844 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1) 2845 & WM8994_AIF1CLK_ENA; 2846 2847 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1) 2848 & WM8994_AIF2CLK_ENA; 2849 2850 switch (id) { 2851 case WM8994_FLL1: 2852 reg_offset = 0; 2853 id = 0; 2854 break; 2855 case WM8994_FLL2: 2856 reg_offset = 0x20; 2857 id = 1; 2858 break; 2859 default: 2860 return -EINVAL; 2861 } 2862 2863 switch (src) { 2864 case 0: 2865 /* Allow no source specification when stopping */ 2866 if (freq_out) 2867 return -EINVAL; 2868 break; 2869 case WM8994_FLL_SRC_MCLK1: 2870 case WM8994_FLL_SRC_MCLK2: 2871 case WM8994_FLL_SRC_LRCLK: 2872 case WM8994_FLL_SRC_BCLK: 2873 break; 2874 default: 2875 return -EINVAL; 2876 } 2877 2878 /* Are we changing anything? */ 2879 if (wm8994->fll[id].src == src && 2880 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) 2881 return 0; 2882 2883 /* If we're stopping the FLL redo the old config - no 2884 * registers will actually be written but we avoid GCC flow 2885 * analysis bugs spewing warnings. 2886 */ 2887 if (freq_out) 2888 ret = wm8994_get_fll_config(&fll, freq_in, freq_out); 2889 else 2890 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, 2891 wm8994->fll[id].out); 2892 if (ret < 0) 2893 return ret; 2894 2895 /* Gate the AIF clocks while we reclock */ 2896 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 2897 WM8994_AIF1CLK_ENA, 0); 2898 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 2899 WM8994_AIF2CLK_ENA, 0); 2900 2901 /* We always need to disable the FLL while reconfiguring */ 2902 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2903 WM8994_FLL1_ENA, 0); 2904 2905 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2906 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2907 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 2908 WM8994_FLL1_OUTDIV_MASK | 2909 WM8994_FLL1_FRATIO_MASK, reg); 2910 2911 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k); 2912 2913 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, 2914 WM8994_FLL1_N_MASK, 2915 fll.n << WM8994_FLL1_N_SHIFT); 2916 2917 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2918 WM8994_FLL1_REFCLK_DIV_MASK | 2919 WM8994_FLL1_REFCLK_SRC_MASK, 2920 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2921 (src - 1)); 2922 2923 /* Enable (with fractional mode if required) */ 2924 if (freq_out) { 2925 if (fll.k) 2926 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC; 2927 else 2928 reg = WM8994_FLL1_ENA; 2929 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2930 WM8994_FLL1_ENA | WM8994_FLL1_FRAC, 2931 reg); 2932 } 2933 2934 wm8994->fll[id].in = freq_in; 2935 wm8994->fll[id].out = freq_out; 2936 wm8994->fll[id].src = src; 2937 2938 /* Enable any gated AIF clocks */ 2939 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 2940 WM8994_AIF1CLK_ENA, aif1); 2941 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 2942 WM8994_AIF2CLK_ENA, aif2); 2943 2944 configure_clock(codec); 2945 2946 return 0; 2947 } 2948 2949 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, 2950 int clk_id, unsigned int freq, int dir) 2951 { 2952 struct snd_soc_codec *codec = dai->codec; 2953 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2954 2955 switch (dai->id) { 2956 case 1: 2957 case 2: 2958 break; 2959 2960 default: 2961 /* AIF3 shares clocking with AIF1/2 */ 2962 return -EINVAL; 2963 } 2964 2965 switch (clk_id) { 2966 case WM8994_SYSCLK_MCLK1: 2967 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; 2968 wm8994->mclk[0] = freq; 2969 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 2970 dai->id, freq); 2971 break; 2972 2973 case WM8994_SYSCLK_MCLK2: 2974 /* TODO: Set GPIO AF */ 2975 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; 2976 wm8994->mclk[1] = freq; 2977 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 2978 dai->id, freq); 2979 break; 2980 2981 case WM8994_SYSCLK_FLL1: 2982 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; 2983 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); 2984 break; 2985 2986 case WM8994_SYSCLK_FLL2: 2987 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; 2988 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); 2989 break; 2990 2991 default: 2992 return -EINVAL; 2993 } 2994 2995 configure_clock(codec); 2996 2997 return 0; 2998 } 2999 3000 static int wm8994_set_bias_level(struct snd_soc_codec *codec, 3001 enum snd_soc_bias_level level) 3002 { 3003 switch (level) { 3004 case SND_SOC_BIAS_ON: 3005 break; 3006 3007 case SND_SOC_BIAS_PREPARE: 3008 /* VMID=2x40k */ 3009 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 3010 WM8994_VMID_SEL_MASK, 0x2); 3011 break; 3012 3013 case SND_SOC_BIAS_STANDBY: 3014 if (codec->bias_level == SND_SOC_BIAS_OFF) { 3015 /* Tweak DC servo configuration for improved 3016 * performance. */ 3017 snd_soc_write(codec, 0x102, 0x3); 3018 snd_soc_write(codec, 0x56, 0x3); 3019 snd_soc_write(codec, 0x102, 0); 3020 3021 /* Discharge LINEOUT1 & 2 */ 3022 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 3023 WM8994_LINEOUT1_DISCH | 3024 WM8994_LINEOUT2_DISCH, 3025 WM8994_LINEOUT1_DISCH | 3026 WM8994_LINEOUT2_DISCH); 3027 3028 /* Startup bias, VMID ramp & buffer */ 3029 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 3030 WM8994_STARTUP_BIAS_ENA | 3031 WM8994_VMID_BUF_ENA | 3032 WM8994_VMID_RAMP_MASK, 3033 WM8994_STARTUP_BIAS_ENA | 3034 WM8994_VMID_BUF_ENA | 3035 (0x11 << WM8994_VMID_RAMP_SHIFT)); 3036 3037 /* Main bias enable, VMID=2x40k */ 3038 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 3039 WM8994_BIAS_ENA | 3040 WM8994_VMID_SEL_MASK, 3041 WM8994_BIAS_ENA | 0x2); 3042 3043 msleep(20); 3044 } 3045 3046 /* VMID=2x500k */ 3047 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 3048 WM8994_VMID_SEL_MASK, 0x4); 3049 3050 break; 3051 3052 case SND_SOC_BIAS_OFF: 3053 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 3054 /* Switch over to startup biases */ 3055 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 3056 WM8994_BIAS_SRC | 3057 WM8994_STARTUP_BIAS_ENA | 3058 WM8994_VMID_BUF_ENA | 3059 WM8994_VMID_RAMP_MASK, 3060 WM8994_BIAS_SRC | 3061 WM8994_STARTUP_BIAS_ENA | 3062 WM8994_VMID_BUF_ENA | 3063 (1 << WM8994_VMID_RAMP_SHIFT)); 3064 3065 /* Disable main biases */ 3066 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, 3067 WM8994_BIAS_ENA | 3068 WM8994_VMID_SEL_MASK, 0); 3069 3070 /* Discharge line */ 3071 snd_soc_update_bits(codec, WM8994_ANTIPOP_1, 3072 WM8994_LINEOUT1_DISCH | 3073 WM8994_LINEOUT2_DISCH, 3074 WM8994_LINEOUT1_DISCH | 3075 WM8994_LINEOUT2_DISCH); 3076 3077 msleep(5); 3078 3079 /* Switch off startup biases */ 3080 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 3081 WM8994_BIAS_SRC | 3082 WM8994_STARTUP_BIAS_ENA | 3083 WM8994_VMID_BUF_ENA | 3084 WM8994_VMID_RAMP_MASK, 0); 3085 } 3086 break; 3087 } 3088 codec->bias_level = level; 3089 return 0; 3090 } 3091 3092 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 3093 { 3094 struct snd_soc_codec *codec = dai->codec; 3095 int ms_reg; 3096 int aif1_reg; 3097 int ms = 0; 3098 int aif1 = 0; 3099 3100 switch (dai->id) { 3101 case 1: 3102 ms_reg = WM8994_AIF1_MASTER_SLAVE; 3103 aif1_reg = WM8994_AIF1_CONTROL_1; 3104 break; 3105 case 2: 3106 ms_reg = WM8994_AIF2_MASTER_SLAVE; 3107 aif1_reg = WM8994_AIF2_CONTROL_1; 3108 break; 3109 default: 3110 return -EINVAL; 3111 } 3112 3113 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3114 case SND_SOC_DAIFMT_CBS_CFS: 3115 break; 3116 case SND_SOC_DAIFMT_CBM_CFM: 3117 ms = WM8994_AIF1_MSTR; 3118 break; 3119 default: 3120 return -EINVAL; 3121 } 3122 3123 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3124 case SND_SOC_DAIFMT_DSP_B: 3125 aif1 |= WM8994_AIF1_LRCLK_INV; 3126 case SND_SOC_DAIFMT_DSP_A: 3127 aif1 |= 0x18; 3128 break; 3129 case SND_SOC_DAIFMT_I2S: 3130 aif1 |= 0x10; 3131 break; 3132 case SND_SOC_DAIFMT_RIGHT_J: 3133 break; 3134 case SND_SOC_DAIFMT_LEFT_J: 3135 aif1 |= 0x8; 3136 break; 3137 default: 3138 return -EINVAL; 3139 } 3140 3141 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3142 case SND_SOC_DAIFMT_DSP_A: 3143 case SND_SOC_DAIFMT_DSP_B: 3144 /* frame inversion not valid for DSP modes */ 3145 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3146 case SND_SOC_DAIFMT_NB_NF: 3147 break; 3148 case SND_SOC_DAIFMT_IB_NF: 3149 aif1 |= WM8994_AIF1_BCLK_INV; 3150 break; 3151 default: 3152 return -EINVAL; 3153 } 3154 break; 3155 3156 case SND_SOC_DAIFMT_I2S: 3157 case SND_SOC_DAIFMT_RIGHT_J: 3158 case SND_SOC_DAIFMT_LEFT_J: 3159 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3160 case SND_SOC_DAIFMT_NB_NF: 3161 break; 3162 case SND_SOC_DAIFMT_IB_IF: 3163 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; 3164 break; 3165 case SND_SOC_DAIFMT_IB_NF: 3166 aif1 |= WM8994_AIF1_BCLK_INV; 3167 break; 3168 case SND_SOC_DAIFMT_NB_IF: 3169 aif1 |= WM8994_AIF1_LRCLK_INV; 3170 break; 3171 default: 3172 return -EINVAL; 3173 } 3174 break; 3175 default: 3176 return -EINVAL; 3177 } 3178 3179 snd_soc_update_bits(codec, aif1_reg, 3180 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 3181 WM8994_AIF1_FMT_MASK, 3182 aif1); 3183 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, 3184 ms); 3185 3186 return 0; 3187 } 3188 3189 static struct { 3190 int val, rate; 3191 } srs[] = { 3192 { 0, 8000 }, 3193 { 1, 11025 }, 3194 { 2, 12000 }, 3195 { 3, 16000 }, 3196 { 4, 22050 }, 3197 { 5, 24000 }, 3198 { 6, 32000 }, 3199 { 7, 44100 }, 3200 { 8, 48000 }, 3201 { 9, 88200 }, 3202 { 10, 96000 }, 3203 }; 3204 3205 static int fs_ratios[] = { 3206 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 3207 }; 3208 3209 static int bclk_divs[] = { 3210 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, 3211 640, 880, 960, 1280, 1760, 1920 3212 }; 3213 3214 static int wm8994_hw_params(struct snd_pcm_substream *substream, 3215 struct snd_pcm_hw_params *params, 3216 struct snd_soc_dai *dai) 3217 { 3218 struct snd_soc_codec *codec = dai->codec; 3219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3220 int aif1_reg; 3221 int bclk_reg; 3222 int lrclk_reg; 3223 int rate_reg; 3224 int aif1 = 0; 3225 int bclk = 0; 3226 int lrclk = 0; 3227 int rate_val = 0; 3228 int id = dai->id - 1; 3229 3230 int i, cur_val, best_val, bclk_rate, best; 3231 3232 switch (dai->id) { 3233 case 1: 3234 aif1_reg = WM8994_AIF1_CONTROL_1; 3235 bclk_reg = WM8994_AIF1_BCLK; 3236 rate_reg = WM8994_AIF1_RATE; 3237 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 3238 wm8994->lrclk_shared[0]) 3239 lrclk_reg = WM8994_AIF1DAC_LRCLK; 3240 else 3241 lrclk_reg = WM8994_AIF1ADC_LRCLK; 3242 break; 3243 case 2: 3244 aif1_reg = WM8994_AIF2_CONTROL_1; 3245 bclk_reg = WM8994_AIF2_BCLK; 3246 rate_reg = WM8994_AIF2_RATE; 3247 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 3248 wm8994->lrclk_shared[1]) 3249 lrclk_reg = WM8994_AIF2DAC_LRCLK; 3250 else 3251 lrclk_reg = WM8994_AIF2ADC_LRCLK; 3252 break; 3253 default: 3254 return -EINVAL; 3255 } 3256 3257 bclk_rate = params_rate(params) * 2; 3258 switch (params_format(params)) { 3259 case SNDRV_PCM_FORMAT_S16_LE: 3260 bclk_rate *= 16; 3261 break; 3262 case SNDRV_PCM_FORMAT_S20_3LE: 3263 bclk_rate *= 20; 3264 aif1 |= 0x20; 3265 break; 3266 case SNDRV_PCM_FORMAT_S24_LE: 3267 bclk_rate *= 24; 3268 aif1 |= 0x40; 3269 break; 3270 case SNDRV_PCM_FORMAT_S32_LE: 3271 bclk_rate *= 32; 3272 aif1 |= 0x60; 3273 break; 3274 default: 3275 return -EINVAL; 3276 } 3277 3278 /* Try to find an appropriate sample rate; look for an exact match. */ 3279 for (i = 0; i < ARRAY_SIZE(srs); i++) 3280 if (srs[i].rate == params_rate(params)) 3281 break; 3282 if (i == ARRAY_SIZE(srs)) 3283 return -EINVAL; 3284 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; 3285 3286 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); 3287 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 3288 dai->id, wm8994->aifclk[id], bclk_rate); 3289 3290 if (wm8994->aifclk[id] == 0) { 3291 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 3292 return -EINVAL; 3293 } 3294 3295 /* AIFCLK/fs ratio; look for a close match in either direction */ 3296 best = 0; 3297 best_val = abs((fs_ratios[0] * params_rate(params)) 3298 - wm8994->aifclk[id]); 3299 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { 3300 cur_val = abs((fs_ratios[i] * params_rate(params)) 3301 - wm8994->aifclk[id]); 3302 if (cur_val >= best_val) 3303 continue; 3304 best = i; 3305 best_val = cur_val; 3306 } 3307 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 3308 dai->id, fs_ratios[best]); 3309 rate_val |= best; 3310 3311 /* We may not get quite the right frequency if using 3312 * approximate clocks so look for the closest match that is 3313 * higher than the target (we need to ensure that there enough 3314 * BCLKs to clock out the samples). 3315 */ 3316 best = 0; 3317 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 3318 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; 3319 if (cur_val < 0) /* BCLK table is sorted */ 3320 break; 3321 best = i; 3322 } 3323 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; 3324 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 3325 bclk_divs[best], bclk_rate); 3326 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; 3327 3328 lrclk = bclk_rate / params_rate(params); 3329 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 3330 lrclk, bclk_rate / lrclk); 3331 3332 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 3333 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 3334 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 3335 lrclk); 3336 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | 3337 WM8994_AIF1CLK_RATE_MASK, rate_val); 3338 3339 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3340 switch (dai->id) { 3341 case 1: 3342 wm8994->dac_rates[0] = params_rate(params); 3343 wm8994_set_retune_mobile(codec, 0); 3344 wm8994_set_retune_mobile(codec, 1); 3345 break; 3346 case 2: 3347 wm8994->dac_rates[1] = params_rate(params); 3348 wm8994_set_retune_mobile(codec, 2); 3349 break; 3350 } 3351 } 3352 3353 return 0; 3354 } 3355 3356 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 3357 { 3358 struct snd_soc_codec *codec = codec_dai->codec; 3359 int mute_reg; 3360 int reg; 3361 3362 switch (codec_dai->id) { 3363 case 1: 3364 mute_reg = WM8994_AIF1_DAC1_FILTERS_1; 3365 break; 3366 case 2: 3367 mute_reg = WM8994_AIF2_DAC_FILTERS_1; 3368 break; 3369 default: 3370 return -EINVAL; 3371 } 3372 3373 if (mute) 3374 reg = WM8994_AIF1DAC1_MUTE; 3375 else 3376 reg = 0; 3377 3378 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); 3379 3380 return 0; 3381 } 3382 3383 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 3384 { 3385 struct snd_soc_codec *codec = codec_dai->codec; 3386 int reg, val, mask; 3387 3388 switch (codec_dai->id) { 3389 case 1: 3390 reg = WM8994_AIF1_MASTER_SLAVE; 3391 mask = WM8994_AIF1_TRI; 3392 break; 3393 case 2: 3394 reg = WM8994_AIF2_MASTER_SLAVE; 3395 mask = WM8994_AIF2_TRI; 3396 break; 3397 case 3: 3398 reg = WM8994_POWER_MANAGEMENT_6; 3399 mask = WM8994_AIF3_TRI; 3400 break; 3401 default: 3402 return -EINVAL; 3403 } 3404 3405 if (tristate) 3406 val = mask; 3407 else 3408 val = 0; 3409 3410 return snd_soc_update_bits(codec, reg, mask, reg); 3411 } 3412 3413 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 3414 3415 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3416 SNDRV_PCM_FMTBIT_S24_LE) 3417 3418 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = { 3419 .set_sysclk = wm8994_set_dai_sysclk, 3420 .set_fmt = wm8994_set_dai_fmt, 3421 .hw_params = wm8994_hw_params, 3422 .digital_mute = wm8994_aif_mute, 3423 .set_pll = wm8994_set_fll, 3424 .set_tristate = wm8994_set_tristate, 3425 }; 3426 3427 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = { 3428 .set_sysclk = wm8994_set_dai_sysclk, 3429 .set_fmt = wm8994_set_dai_fmt, 3430 .hw_params = wm8994_hw_params, 3431 .digital_mute = wm8994_aif_mute, 3432 .set_pll = wm8994_set_fll, 3433 .set_tristate = wm8994_set_tristate, 3434 }; 3435 3436 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 3437 .set_tristate = wm8994_set_tristate, 3438 }; 3439 3440 struct snd_soc_dai wm8994_dai[] = { 3441 { 3442 .name = "WM8994 AIF1", 3443 .id = 1, 3444 .playback = { 3445 .stream_name = "AIF1 Playback", 3446 .channels_min = 2, 3447 .channels_max = 2, 3448 .rates = WM8994_RATES, 3449 .formats = WM8994_FORMATS, 3450 }, 3451 .capture = { 3452 .stream_name = "AIF1 Capture", 3453 .channels_min = 2, 3454 .channels_max = 2, 3455 .rates = WM8994_RATES, 3456 .formats = WM8994_FORMATS, 3457 }, 3458 .ops = &wm8994_aif1_dai_ops, 3459 }, 3460 { 3461 .name = "WM8994 AIF2", 3462 .id = 2, 3463 .playback = { 3464 .stream_name = "AIF2 Playback", 3465 .channels_min = 2, 3466 .channels_max = 2, 3467 .rates = WM8994_RATES, 3468 .formats = WM8994_FORMATS, 3469 }, 3470 .capture = { 3471 .stream_name = "AIF2 Capture", 3472 .channels_min = 2, 3473 .channels_max = 2, 3474 .rates = WM8994_RATES, 3475 .formats = WM8994_FORMATS, 3476 }, 3477 .ops = &wm8994_aif2_dai_ops, 3478 }, 3479 { 3480 .name = "WM8994 AIF3", 3481 .id = 3, 3482 .playback = { 3483 .stream_name = "AIF3 Playback", 3484 .channels_min = 2, 3485 .channels_max = 2, 3486 .rates = WM8994_RATES, 3487 .formats = WM8994_FORMATS, 3488 }, 3489 .capture = { 3490 .stream_name = "AIF3 Capture", 3491 .channels_min = 2, 3492 .channels_max = 2, 3493 .rates = WM8994_RATES, 3494 .formats = WM8994_FORMATS, 3495 }, 3496 .ops = &wm8994_aif3_dai_ops, 3497 } 3498 }; 3499 EXPORT_SYMBOL_GPL(wm8994_dai); 3500 3501 #ifdef CONFIG_PM 3502 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state) 3503 { 3504 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 3505 struct snd_soc_codec *codec = socdev->card->codec; 3506 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3507 int i, ret; 3508 3509 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3510 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], 3511 sizeof(struct fll_config)); 3512 ret = wm8994_set_fll(&codec->dai[0], i + 1, 0, 0, 0); 3513 if (ret < 0) 3514 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", 3515 i + 1, ret); 3516 } 3517 3518 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3519 3520 return 0; 3521 } 3522 3523 static int wm8994_resume(struct platform_device *pdev) 3524 { 3525 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 3526 struct snd_soc_codec *codec = socdev->card->codec; 3527 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3528 u16 *reg_cache = codec->reg_cache; 3529 int i, ret; 3530 3531 /* Restore the registers */ 3532 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) { 3533 switch (i) { 3534 case WM8994_LDO_1: 3535 case WM8994_LDO_2: 3536 case WM8994_SOFTWARE_RESET: 3537 /* Handled by other MFD drivers */ 3538 continue; 3539 default: 3540 break; 3541 } 3542 3543 if (!access_masks[i].writable) 3544 continue; 3545 3546 wm8994_reg_write(codec->control_data, i, reg_cache[i]); 3547 } 3548 3549 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 3550 3551 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { 3552 if (!wm8994->fll_suspend[i].out) 3553 continue; 3554 3555 ret = wm8994_set_fll(&codec->dai[0], i + 1, 3556 wm8994->fll_suspend[i].src, 3557 wm8994->fll_suspend[i].in, 3558 wm8994->fll_suspend[i].out); 3559 if (ret < 0) 3560 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", 3561 i + 1, ret); 3562 } 3563 3564 return 0; 3565 } 3566 #else 3567 #define wm8994_suspend NULL 3568 #define wm8994_resume NULL 3569 #endif 3570 3571 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) 3572 { 3573 struct snd_soc_codec *codec = &wm8994->codec; 3574 struct wm8994_pdata *pdata = wm8994->pdata; 3575 struct snd_kcontrol_new controls[] = { 3576 SOC_ENUM_EXT("AIF1.1 EQ Mode", 3577 wm8994->retune_mobile_enum, 3578 wm8994_get_retune_mobile_enum, 3579 wm8994_put_retune_mobile_enum), 3580 SOC_ENUM_EXT("AIF1.2 EQ Mode", 3581 wm8994->retune_mobile_enum, 3582 wm8994_get_retune_mobile_enum, 3583 wm8994_put_retune_mobile_enum), 3584 SOC_ENUM_EXT("AIF2 EQ Mode", 3585 wm8994->retune_mobile_enum, 3586 wm8994_get_retune_mobile_enum, 3587 wm8994_put_retune_mobile_enum), 3588 }; 3589 int ret, i, j; 3590 const char **t; 3591 3592 /* We need an array of texts for the enum API but the number 3593 * of texts is likely to be less than the number of 3594 * configurations due to the sample rate dependency of the 3595 * configurations. */ 3596 wm8994->num_retune_mobile_texts = 0; 3597 wm8994->retune_mobile_texts = NULL; 3598 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 3599 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { 3600 if (strcmp(pdata->retune_mobile_cfgs[i].name, 3601 wm8994->retune_mobile_texts[j]) == 0) 3602 break; 3603 } 3604 3605 if (j != wm8994->num_retune_mobile_texts) 3606 continue; 3607 3608 /* Expand the array... */ 3609 t = krealloc(wm8994->retune_mobile_texts, 3610 sizeof(char *) * 3611 (wm8994->num_retune_mobile_texts + 1), 3612 GFP_KERNEL); 3613 if (t == NULL) 3614 continue; 3615 3616 /* ...store the new entry... */ 3617 t[wm8994->num_retune_mobile_texts] = 3618 pdata->retune_mobile_cfgs[i].name; 3619 3620 /* ...and remember the new version. */ 3621 wm8994->num_retune_mobile_texts++; 3622 wm8994->retune_mobile_texts = t; 3623 } 3624 3625 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 3626 wm8994->num_retune_mobile_texts); 3627 3628 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; 3629 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; 3630 3631 ret = snd_soc_add_controls(&wm8994->codec, controls, 3632 ARRAY_SIZE(controls)); 3633 if (ret != 0) 3634 dev_err(wm8994->codec.dev, 3635 "Failed to add ReTune Mobile controls: %d\n", ret); 3636 } 3637 3638 static void wm8994_handle_pdata(struct wm8994_priv *wm8994) 3639 { 3640 struct snd_soc_codec *codec = &wm8994->codec; 3641 struct wm8994_pdata *pdata = wm8994->pdata; 3642 int ret, i; 3643 3644 if (!pdata) 3645 return; 3646 3647 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, 3648 pdata->lineout2_diff, 3649 pdata->lineout1fb, 3650 pdata->lineout2fb, 3651 pdata->jd_scthr, 3652 pdata->jd_thr, 3653 pdata->micbias1_lvl, 3654 pdata->micbias2_lvl); 3655 3656 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 3657 3658 if (pdata->num_drc_cfgs) { 3659 struct snd_kcontrol_new controls[] = { 3660 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, 3661 wm8994_get_drc_enum, wm8994_put_drc_enum), 3662 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, 3663 wm8994_get_drc_enum, wm8994_put_drc_enum), 3664 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, 3665 wm8994_get_drc_enum, wm8994_put_drc_enum), 3666 }; 3667 3668 /* We need an array of texts for the enum API */ 3669 wm8994->drc_texts = kmalloc(sizeof(char *) 3670 * pdata->num_drc_cfgs, GFP_KERNEL); 3671 if (!wm8994->drc_texts) { 3672 dev_err(wm8994->codec.dev, 3673 "Failed to allocate %d DRC config texts\n", 3674 pdata->num_drc_cfgs); 3675 return; 3676 } 3677 3678 for (i = 0; i < pdata->num_drc_cfgs; i++) 3679 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; 3680 3681 wm8994->drc_enum.max = pdata->num_drc_cfgs; 3682 wm8994->drc_enum.texts = wm8994->drc_texts; 3683 3684 ret = snd_soc_add_controls(&wm8994->codec, controls, 3685 ARRAY_SIZE(controls)); 3686 if (ret != 0) 3687 dev_err(wm8994->codec.dev, 3688 "Failed to add DRC mode controls: %d\n", ret); 3689 3690 for (i = 0; i < WM8994_NUM_DRC; i++) 3691 wm8994_set_drc(codec, i); 3692 } 3693 3694 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 3695 pdata->num_retune_mobile_cfgs); 3696 3697 if (pdata->num_retune_mobile_cfgs) 3698 wm8994_handle_retune_mobile_pdata(wm8994); 3699 else 3700 snd_soc_add_controls(&wm8994->codec, wm8994_eq_controls, 3701 ARRAY_SIZE(wm8994_eq_controls)); 3702 } 3703 3704 static int wm8994_probe(struct platform_device *pdev) 3705 { 3706 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 3707 struct snd_soc_codec *codec; 3708 int ret = 0; 3709 3710 if (wm8994_codec == NULL) { 3711 dev_err(&pdev->dev, "Codec device not registered\n"); 3712 return -ENODEV; 3713 } 3714 3715 socdev->card->codec = wm8994_codec; 3716 codec = wm8994_codec; 3717 3718 /* register pcms */ 3719 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 3720 if (ret < 0) { 3721 dev_err(codec->dev, "failed to create pcms: %d\n", ret); 3722 return ret; 3723 } 3724 3725 wm8994_handle_pdata(snd_soc_codec_get_drvdata(codec)); 3726 3727 wm_hubs_add_analogue_controls(codec); 3728 snd_soc_add_controls(codec, wm8994_snd_controls, 3729 ARRAY_SIZE(wm8994_snd_controls)); 3730 snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets, 3731 ARRAY_SIZE(wm8994_dapm_widgets)); 3732 wm_hubs_add_analogue_routes(codec, 0, 0); 3733 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 3734 3735 return 0; 3736 } 3737 3738 static int wm8994_remove(struct platform_device *pdev) 3739 { 3740 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 3741 3742 snd_soc_free_pcms(socdev); 3743 snd_soc_dapm_free(socdev); 3744 3745 return 0; 3746 } 3747 3748 struct snd_soc_codec_device soc_codec_dev_wm8994 = { 3749 .probe = wm8994_probe, 3750 .remove = wm8994_remove, 3751 .suspend = wm8994_suspend, 3752 .resume = wm8994_resume, 3753 }; 3754 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994); 3755 3756 /** 3757 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ 3758 * 3759 * @codec: WM8994 codec 3760 * @jack: jack to report detection events on 3761 * @micbias: microphone bias to detect on 3762 * @det: value to report for presence detection 3763 * @shrt: value to report for short detection 3764 * 3765 * Enable microphone detection via IRQ on the WM8994. If GPIOs are 3766 * being used to bring out signals to the processor then only platform 3767 * data configuration is needed for WM8903 and processor GPIOs should 3768 * be configured using snd_soc_jack_add_gpios() instead. 3769 * 3770 * Configuration of detection levels is available via the micbias1_lvl 3771 * and micbias2_lvl platform data members. 3772 */ 3773 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 3774 int micbias, int det, int shrt) 3775 { 3776 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3777 struct wm8994_micdet *micdet; 3778 int reg; 3779 3780 switch (micbias) { 3781 case 1: 3782 micdet = &wm8994->micdet[0]; 3783 break; 3784 case 2: 3785 micdet = &wm8994->micdet[1]; 3786 break; 3787 default: 3788 return -EINVAL; 3789 } 3790 3791 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n", 3792 micbias, det, shrt); 3793 3794 /* Store the configuration */ 3795 micdet->jack = jack; 3796 micdet->det = det; 3797 micdet->shrt = shrt; 3798 3799 /* If either of the jacks is set up then enable detection */ 3800 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) 3801 reg = WM8994_MICD_ENA; 3802 else 3803 reg = 0; 3804 3805 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); 3806 3807 return 0; 3808 } 3809 EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3810 3811 static irqreturn_t wm8994_mic_irq(int irq, void *data) 3812 { 3813 struct wm8994_priv *priv = data; 3814 struct snd_soc_codec *codec = &priv->codec; 3815 int reg; 3816 int report; 3817 3818 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 3819 if (reg < 0) { 3820 dev_err(codec->dev, "Failed to read microphone status: %d\n", 3821 reg); 3822 return IRQ_HANDLED; 3823 } 3824 3825 dev_dbg(codec->dev, "Microphone status: %x\n", reg); 3826 3827 report = 0; 3828 if (reg & WM8994_MIC1_DET_STS) 3829 report |= priv->micdet[0].det; 3830 if (reg & WM8994_MIC1_SHRT_STS) 3831 report |= priv->micdet[0].shrt; 3832 snd_soc_jack_report(priv->micdet[0].jack, report, 3833 priv->micdet[0].det | priv->micdet[0].shrt); 3834 3835 report = 0; 3836 if (reg & WM8994_MIC2_DET_STS) 3837 report |= priv->micdet[1].det; 3838 if (reg & WM8994_MIC2_SHRT_STS) 3839 report |= priv->micdet[1].shrt; 3840 snd_soc_jack_report(priv->micdet[1].jack, report, 3841 priv->micdet[1].det | priv->micdet[1].shrt); 3842 3843 return IRQ_HANDLED; 3844 } 3845 3846 static int wm8994_codec_probe(struct platform_device *pdev) 3847 { 3848 int ret; 3849 struct wm8994_priv *wm8994; 3850 struct snd_soc_codec *codec; 3851 int i; 3852 u16 rev; 3853 3854 if (wm8994_codec) { 3855 dev_err(&pdev->dev, "Another WM8994 is registered\n"); 3856 return -EINVAL; 3857 } 3858 3859 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 3860 if (!wm8994) { 3861 dev_err(&pdev->dev, "Failed to allocate private data\n"); 3862 return -ENOMEM; 3863 } 3864 3865 codec = &wm8994->codec; 3866 3867 mutex_init(&codec->mutex); 3868 INIT_LIST_HEAD(&codec->dapm_widgets); 3869 INIT_LIST_HEAD(&codec->dapm_paths); 3870 3871 snd_soc_codec_set_drvdata(codec, wm8994); 3872 codec->control_data = dev_get_drvdata(pdev->dev.parent); 3873 codec->name = "WM8994"; 3874 codec->owner = THIS_MODULE; 3875 codec->read = wm8994_read; 3876 codec->write = wm8994_write; 3877 codec->readable_register = wm8994_readable; 3878 codec->bias_level = SND_SOC_BIAS_OFF; 3879 codec->set_bias_level = wm8994_set_bias_level; 3880 codec->dai = &wm8994_dai[0]; 3881 codec->num_dai = 3; 3882 codec->reg_cache_size = WM8994_MAX_REGISTER; 3883 codec->reg_cache = &wm8994->reg_cache; 3884 codec->dev = &pdev->dev; 3885 3886 wm8994->pdata = pdev->dev.parent->platform_data; 3887 3888 /* Fill the cache with physical values we inherited; don't reset */ 3889 ret = wm8994_bulk_read(codec->control_data, 0, 3890 ARRAY_SIZE(wm8994->reg_cache) - 1, 3891 codec->reg_cache); 3892 if (ret < 0) { 3893 dev_err(codec->dev, "Failed to fill register cache: %d\n", 3894 ret); 3895 goto err; 3896 } 3897 3898 /* Clear the cached values for unreadable/volatile registers to 3899 * avoid potential confusion. 3900 */ 3901 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++) 3902 if (wm8994_volatile(i) || !wm8994_readable(i)) 3903 wm8994->reg_cache[i] = 0; 3904 3905 /* Set revision-specific configuration */ 3906 rev = snd_soc_read(codec, WM8994_CHIP_REVISION); 3907 switch (rev) { 3908 case 2: 3909 case 3: 3910 wm8994->hubs.dcs_codes = -5; 3911 wm8994->hubs.hp_startup_mode = 1; 3912 wm8994->hubs.dcs_readback_mode = 1; 3913 break; 3914 default: 3915 wm8994->hubs.dcs_readback_mode = 1; 3916 break; 3917 } 3918 3919 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 3920 wm8994_mic_irq, "Mic 1 detect", wm8994); 3921 if (ret != 0) 3922 dev_warn(&pdev->dev, 3923 "Failed to request Mic1 detect IRQ: %d\n", ret); 3924 3925 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 3926 wm8994_mic_irq, "Mic 1 short", wm8994); 3927 if (ret != 0) 3928 dev_warn(&pdev->dev, 3929 "Failed to request Mic1 short IRQ: %d\n", ret); 3930 3931 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 3932 wm8994_mic_irq, "Mic 2 detect", wm8994); 3933 if (ret != 0) 3934 dev_warn(&pdev->dev, 3935 "Failed to request Mic2 detect IRQ: %d\n", ret); 3936 3937 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, 3938 wm8994_mic_irq, "Mic 2 short", wm8994); 3939 if (ret != 0) 3940 dev_warn(&pdev->dev, 3941 "Failed to request Mic2 short IRQ: %d\n", ret); 3942 3943 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 3944 * configured on init - if a system wants to do this dynamically 3945 * at runtime we can deal with that then. 3946 */ 3947 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1); 3948 if (ret < 0) { 3949 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); 3950 goto err_irq; 3951 } 3952 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3953 wm8994->lrclk_shared[0] = 1; 3954 wm8994_dai[0].symmetric_rates = 1; 3955 } else { 3956 wm8994->lrclk_shared[0] = 0; 3957 } 3958 3959 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6); 3960 if (ret < 0) { 3961 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); 3962 goto err_irq; 3963 } 3964 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { 3965 wm8994->lrclk_shared[1] = 1; 3966 wm8994_dai[1].symmetric_rates = 1; 3967 } else { 3968 wm8994->lrclk_shared[1] = 0; 3969 } 3970 3971 for (i = 0; i < ARRAY_SIZE(wm8994_dai); i++) 3972 wm8994_dai[i].dev = codec->dev; 3973 3974 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 3975 3976 wm8994_codec = codec; 3977 3978 /* Latch volume updates (right only; we always do left then right). */ 3979 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME, 3980 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU); 3981 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME, 3982 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU); 3983 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME, 3984 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU); 3985 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME, 3986 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU); 3987 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME, 3988 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU); 3989 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME, 3990 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU); 3991 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME, 3992 WM8994_DAC1_VU, WM8994_DAC1_VU); 3993 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME, 3994 WM8994_DAC2_VU, WM8994_DAC2_VU); 3995 3996 /* Set the low bit of the 3D stereo depth so TLV matches */ 3997 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, 3998 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, 3999 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); 4000 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, 4001 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, 4002 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); 4003 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, 4004 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, 4005 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); 4006 4007 wm8994_update_class_w(codec); 4008 4009 ret = snd_soc_register_codec(codec); 4010 if (ret != 0) { 4011 dev_err(codec->dev, "Failed to register codec: %d\n", ret); 4012 goto err_irq; 4013 } 4014 4015 ret = snd_soc_register_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4016 if (ret != 0) { 4017 dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); 4018 goto err_codec; 4019 } 4020 4021 platform_set_drvdata(pdev, wm8994); 4022 4023 return 0; 4024 4025 err_codec: 4026 snd_soc_unregister_codec(codec); 4027 err_irq: 4028 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 4029 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 4030 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 4031 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 4032 err: 4033 kfree(wm8994); 4034 return ret; 4035 } 4036 4037 static int __devexit wm8994_codec_remove(struct platform_device *pdev) 4038 { 4039 struct wm8994_priv *wm8994 = platform_get_drvdata(pdev); 4040 struct snd_soc_codec *codec = &wm8994->codec; 4041 4042 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 4043 snd_soc_unregister_dais(wm8994_dai, ARRAY_SIZE(wm8994_dai)); 4044 snd_soc_unregister_codec(&wm8994->codec); 4045 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 4046 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 4047 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 4048 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 4049 kfree(wm8994); 4050 wm8994_codec = NULL; 4051 4052 return 0; 4053 } 4054 4055 static struct platform_driver wm8994_codec_driver = { 4056 .driver = { 4057 .name = "wm8994-codec", 4058 .owner = THIS_MODULE, 4059 }, 4060 .probe = wm8994_codec_probe, 4061 .remove = __devexit_p(wm8994_codec_remove), 4062 }; 4063 4064 static __init int wm8994_init(void) 4065 { 4066 return platform_driver_register(&wm8994_codec_driver); 4067 } 4068 module_init(wm8994_init); 4069 4070 static __exit void wm8994_exit(void) 4071 { 4072 platform_driver_unregister(&wm8994_codec_driver); 4073 } 4074 module_exit(wm8994_exit); 4075 4076 4077 MODULE_DESCRIPTION("ASoC WM8994 driver"); 4078 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4079 MODULE_LICENSE("GPL"); 4080 MODULE_ALIAS("platform:wm8994-codec"); 4081