1 /* 2 * wm8993.c -- WM8993 ALSA SoC audio driver 3 * 4 * Copyright 2009, 2010 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/i2c.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/slab.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/tlv.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/wm8993.h> 29 30 #include "wm8993.h" 31 #include "wm_hubs.h" 32 33 #define WM8993_NUM_SUPPLIES 6 34 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = { 35 "DCVDD", 36 "DBVDD", 37 "AVDD1", 38 "AVDD2", 39 "CPVDD", 40 "SPKVDD", 41 }; 42 43 static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = { 44 0x8993, /* R0 - Software Reset */ 45 0x0000, /* R1 - Power Management (1) */ 46 0x6000, /* R2 - Power Management (2) */ 47 0x0000, /* R3 - Power Management (3) */ 48 0x4050, /* R4 - Audio Interface (1) */ 49 0x4000, /* R5 - Audio Interface (2) */ 50 0x01C8, /* R6 - Clocking 1 */ 51 0x0000, /* R7 - Clocking 2 */ 52 0x0000, /* R8 - Audio Interface (3) */ 53 0x0040, /* R9 - Audio Interface (4) */ 54 0x0004, /* R10 - DAC CTRL */ 55 0x00C0, /* R11 - Left DAC Digital Volume */ 56 0x00C0, /* R12 - Right DAC Digital Volume */ 57 0x0000, /* R13 - Digital Side Tone */ 58 0x0300, /* R14 - ADC CTRL */ 59 0x00C0, /* R15 - Left ADC Digital Volume */ 60 0x00C0, /* R16 - Right ADC Digital Volume */ 61 0x0000, /* R17 */ 62 0x0000, /* R18 - GPIO CTRL 1 */ 63 0x0010, /* R19 - GPIO1 */ 64 0x0000, /* R20 - IRQ_DEBOUNCE */ 65 0x0000, /* R21 */ 66 0x8000, /* R22 - GPIOCTRL 2 */ 67 0x0800, /* R23 - GPIO_POL */ 68 0x008B, /* R24 - Left Line Input 1&2 Volume */ 69 0x008B, /* R25 - Left Line Input 3&4 Volume */ 70 0x008B, /* R26 - Right Line Input 1&2 Volume */ 71 0x008B, /* R27 - Right Line Input 3&4 Volume */ 72 0x006D, /* R28 - Left Output Volume */ 73 0x006D, /* R29 - Right Output Volume */ 74 0x0066, /* R30 - Line Outputs Volume */ 75 0x0020, /* R31 - HPOUT2 Volume */ 76 0x0079, /* R32 - Left OPGA Volume */ 77 0x0079, /* R33 - Right OPGA Volume */ 78 0x0003, /* R34 - SPKMIXL Attenuation */ 79 0x0003, /* R35 - SPKMIXR Attenuation */ 80 0x0011, /* R36 - SPKOUT Mixers */ 81 0x0100, /* R37 - SPKOUT Boost */ 82 0x0079, /* R38 - Speaker Volume Left */ 83 0x0079, /* R39 - Speaker Volume Right */ 84 0x0000, /* R40 - Input Mixer2 */ 85 0x0000, /* R41 - Input Mixer3 */ 86 0x0000, /* R42 - Input Mixer4 */ 87 0x0000, /* R43 - Input Mixer5 */ 88 0x0000, /* R44 - Input Mixer6 */ 89 0x0000, /* R45 - Output Mixer1 */ 90 0x0000, /* R46 - Output Mixer2 */ 91 0x0000, /* R47 - Output Mixer3 */ 92 0x0000, /* R48 - Output Mixer4 */ 93 0x0000, /* R49 - Output Mixer5 */ 94 0x0000, /* R50 - Output Mixer6 */ 95 0x0000, /* R51 - HPOUT2 Mixer */ 96 0x0000, /* R52 - Line Mixer1 */ 97 0x0000, /* R53 - Line Mixer2 */ 98 0x0000, /* R54 - Speaker Mixer */ 99 0x0000, /* R55 - Additional Control */ 100 0x0000, /* R56 - AntiPOP1 */ 101 0x0000, /* R57 - AntiPOP2 */ 102 0x0000, /* R58 - MICBIAS */ 103 0x0000, /* R59 */ 104 0x0000, /* R60 - FLL Control 1 */ 105 0x0000, /* R61 - FLL Control 2 */ 106 0x0000, /* R62 - FLL Control 3 */ 107 0x2EE0, /* R63 - FLL Control 4 */ 108 0x0002, /* R64 - FLL Control 5 */ 109 0x2287, /* R65 - Clocking 3 */ 110 0x025F, /* R66 - Clocking 4 */ 111 0x0000, /* R67 - MW Slave Control */ 112 0x0000, /* R68 */ 113 0x0002, /* R69 - Bus Control 1 */ 114 0x0000, /* R70 - Write Sequencer 0 */ 115 0x0000, /* R71 - Write Sequencer 1 */ 116 0x0000, /* R72 - Write Sequencer 2 */ 117 0x0000, /* R73 - Write Sequencer 3 */ 118 0x0000, /* R74 - Write Sequencer 4 */ 119 0x0000, /* R75 - Write Sequencer 5 */ 120 0x1F25, /* R76 - Charge Pump 1 */ 121 0x0000, /* R77 */ 122 0x0000, /* R78 */ 123 0x0000, /* R79 */ 124 0x0000, /* R80 */ 125 0x0000, /* R81 - Class W 0 */ 126 0x0000, /* R82 */ 127 0x0000, /* R83 */ 128 0x0000, /* R84 - DC Servo 0 */ 129 0x054A, /* R85 - DC Servo 1 */ 130 0x0000, /* R86 */ 131 0x0000, /* R87 - DC Servo 3 */ 132 0x0000, /* R88 - DC Servo Readback 0 */ 133 0x0000, /* R89 - DC Servo Readback 1 */ 134 0x0000, /* R90 - DC Servo Readback 2 */ 135 0x0000, /* R91 */ 136 0x0000, /* R92 */ 137 0x0000, /* R93 */ 138 0x0000, /* R94 */ 139 0x0000, /* R95 */ 140 0x0100, /* R96 - Analogue HP 0 */ 141 0x0000, /* R97 */ 142 0x0000, /* R98 - EQ1 */ 143 0x000C, /* R99 - EQ2 */ 144 0x000C, /* R100 - EQ3 */ 145 0x000C, /* R101 - EQ4 */ 146 0x000C, /* R102 - EQ5 */ 147 0x000C, /* R103 - EQ6 */ 148 0x0FCA, /* R104 - EQ7 */ 149 0x0400, /* R105 - EQ8 */ 150 0x00D8, /* R106 - EQ9 */ 151 0x1EB5, /* R107 - EQ10 */ 152 0xF145, /* R108 - EQ11 */ 153 0x0B75, /* R109 - EQ12 */ 154 0x01C5, /* R110 - EQ13 */ 155 0x1C58, /* R111 - EQ14 */ 156 0xF373, /* R112 - EQ15 */ 157 0x0A54, /* R113 - EQ16 */ 158 0x0558, /* R114 - EQ17 */ 159 0x168E, /* R115 - EQ18 */ 160 0xF829, /* R116 - EQ19 */ 161 0x07AD, /* R117 - EQ20 */ 162 0x1103, /* R118 - EQ21 */ 163 0x0564, /* R119 - EQ22 */ 164 0x0559, /* R120 - EQ23 */ 165 0x4000, /* R121 - EQ24 */ 166 0x0000, /* R122 - Digital Pulls */ 167 0x0F08, /* R123 - DRC Control 1 */ 168 0x0000, /* R124 - DRC Control 2 */ 169 0x0080, /* R125 - DRC Control 3 */ 170 0x0000, /* R126 - DRC Control 4 */ 171 }; 172 173 static struct { 174 int ratio; 175 int clk_sys_rate; 176 } clk_sys_rates[] = { 177 { 64, 0 }, 178 { 128, 1 }, 179 { 192, 2 }, 180 { 256, 3 }, 181 { 384, 4 }, 182 { 512, 5 }, 183 { 768, 6 }, 184 { 1024, 7 }, 185 { 1408, 8 }, 186 { 1536, 9 }, 187 }; 188 189 static struct { 190 int rate; 191 int sample_rate; 192 } sample_rates[] = { 193 { 8000, 0 }, 194 { 11025, 1 }, 195 { 12000, 1 }, 196 { 16000, 2 }, 197 { 22050, 3 }, 198 { 24000, 3 }, 199 { 32000, 4 }, 200 { 44100, 5 }, 201 { 48000, 5 }, 202 }; 203 204 static struct { 205 int div; /* *10 due to .5s */ 206 int bclk_div; 207 } bclk_divs[] = { 208 { 10, 0 }, 209 { 15, 1 }, 210 { 20, 2 }, 211 { 30, 3 }, 212 { 40, 4 }, 213 { 55, 5 }, 214 { 60, 6 }, 215 { 80, 7 }, 216 { 110, 8 }, 217 { 120, 9 }, 218 { 160, 10 }, 219 { 220, 11 }, 220 { 240, 12 }, 221 { 320, 13 }, 222 { 440, 14 }, 223 { 480, 15 }, 224 }; 225 226 struct wm8993_priv { 227 struct wm_hubs_data hubs_data; 228 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; 229 struct wm8993_platform_data pdata; 230 enum snd_soc_control_type control_type; 231 int master; 232 int sysclk_source; 233 int tdm_slots; 234 int tdm_width; 235 unsigned int mclk_rate; 236 unsigned int sysclk_rate; 237 unsigned int fs; 238 unsigned int bclk; 239 int class_w_users; 240 unsigned int fll_fref; 241 unsigned int fll_fout; 242 int fll_src; 243 }; 244 245 static int wm8993_volatile(struct snd_soc_codec *codec, unsigned int reg) 246 { 247 switch (reg) { 248 case WM8993_SOFTWARE_RESET: 249 case WM8993_DC_SERVO_0: 250 case WM8993_DC_SERVO_READBACK_0: 251 case WM8993_DC_SERVO_READBACK_1: 252 case WM8993_DC_SERVO_READBACK_2: 253 return 1; 254 default: 255 return 0; 256 } 257 } 258 259 struct _fll_div { 260 u16 fll_fratio; 261 u16 fll_outdiv; 262 u16 fll_clk_ref_div; 263 u16 n; 264 u16 k; 265 }; 266 267 /* The size in bits of the FLL divide multiplied by 10 268 * to allow rounding later */ 269 #define FIXED_FLL_SIZE ((1 << 16) * 10) 270 271 static struct { 272 unsigned int min; 273 unsigned int max; 274 u16 fll_fratio; 275 int ratio; 276 } fll_fratios[] = { 277 { 0, 64000, 4, 16 }, 278 { 64000, 128000, 3, 8 }, 279 { 128000, 256000, 2, 4 }, 280 { 256000, 1000000, 1, 2 }, 281 { 1000000, 13500000, 0, 1 }, 282 }; 283 284 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 285 unsigned int Fout) 286 { 287 u64 Kpart; 288 unsigned int K, Ndiv, Nmod, target; 289 unsigned int div; 290 int i; 291 292 /* Fref must be <=13.5MHz */ 293 div = 1; 294 fll_div->fll_clk_ref_div = 0; 295 while ((Fref / div) > 13500000) { 296 div *= 2; 297 fll_div->fll_clk_ref_div++; 298 299 if (div > 8) { 300 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 301 Fref); 302 return -EINVAL; 303 } 304 } 305 306 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 307 308 /* Apply the division for our remaining calculations */ 309 Fref /= div; 310 311 /* Fvco should be 90-100MHz; don't check the upper bound */ 312 div = 0; 313 target = Fout * 2; 314 while (target < 90000000) { 315 div++; 316 target *= 2; 317 if (div > 7) { 318 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 319 Fout); 320 return -EINVAL; 321 } 322 } 323 fll_div->fll_outdiv = div; 324 325 pr_debug("Fvco=%dHz\n", target); 326 327 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 328 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 329 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 330 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 331 target /= fll_fratios[i].ratio; 332 break; 333 } 334 } 335 if (i == ARRAY_SIZE(fll_fratios)) { 336 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 337 return -EINVAL; 338 } 339 340 /* Now, calculate N.K */ 341 Ndiv = target / Fref; 342 343 fll_div->n = Ndiv; 344 Nmod = target % Fref; 345 pr_debug("Nmod=%d\n", Nmod); 346 347 /* Calculate fractional part - scale up so we can round. */ 348 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 349 350 do_div(Kpart, Fref); 351 352 K = Kpart & 0xFFFFFFFF; 353 354 if ((K % 10) >= 5) 355 K += 5; 356 357 /* Move down to proper range now rounding is done */ 358 fll_div->k = K / 10; 359 360 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 361 fll_div->n, fll_div->k, 362 fll_div->fll_fratio, fll_div->fll_outdiv, 363 fll_div->fll_clk_ref_div); 364 365 return 0; 366 } 367 368 static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 369 unsigned int Fref, unsigned int Fout) 370 { 371 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 372 u16 reg1, reg4, reg5; 373 struct _fll_div fll_div; 374 int ret; 375 376 /* Any change? */ 377 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout) 378 return 0; 379 380 /* Disable the FLL */ 381 if (Fout == 0) { 382 dev_dbg(codec->dev, "FLL disabled\n"); 383 wm8993->fll_fref = 0; 384 wm8993->fll_fout = 0; 385 386 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); 387 reg1 &= ~WM8993_FLL_ENA; 388 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 389 390 return 0; 391 } 392 393 ret = fll_factors(&fll_div, Fref, Fout); 394 if (ret != 0) 395 return ret; 396 397 reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5); 398 reg5 &= ~WM8993_FLL_CLK_SRC_MASK; 399 400 switch (fll_id) { 401 case WM8993_FLL_MCLK: 402 break; 403 404 case WM8993_FLL_LRCLK: 405 reg5 |= 1; 406 break; 407 408 case WM8993_FLL_BCLK: 409 reg5 |= 2; 410 break; 411 412 default: 413 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 414 return -EINVAL; 415 } 416 417 /* Any FLL configuration change requires that the FLL be 418 * disabled first. */ 419 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); 420 reg1 &= ~WM8993_FLL_ENA; 421 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 422 423 /* Apply the configuration */ 424 if (fll_div.k) 425 reg1 |= WM8993_FLL_FRAC_MASK; 426 else 427 reg1 &= ~WM8993_FLL_FRAC_MASK; 428 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); 429 430 snd_soc_write(codec, WM8993_FLL_CONTROL_2, 431 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) | 432 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT)); 433 snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k); 434 435 reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4); 436 reg4 &= ~WM8993_FLL_N_MASK; 437 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT; 438 snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4); 439 440 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK; 441 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT; 442 snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5); 443 444 /* Enable the FLL */ 445 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA); 446 447 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 448 449 wm8993->fll_fref = Fref; 450 wm8993->fll_fout = Fout; 451 wm8993->fll_src = source; 452 453 return 0; 454 } 455 456 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 457 unsigned int Fref, unsigned int Fout) 458 { 459 return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout); 460 } 461 462 static int configure_clock(struct snd_soc_codec *codec) 463 { 464 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 465 unsigned int reg; 466 467 /* This should be done on init() for bypass paths */ 468 switch (wm8993->sysclk_source) { 469 case WM8993_SYSCLK_MCLK: 470 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate); 471 472 reg = snd_soc_read(codec, WM8993_CLOCKING_2); 473 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC); 474 if (wm8993->mclk_rate > 13500000) { 475 reg |= WM8993_MCLK_DIV; 476 wm8993->sysclk_rate = wm8993->mclk_rate / 2; 477 } else { 478 reg &= ~WM8993_MCLK_DIV; 479 wm8993->sysclk_rate = wm8993->mclk_rate; 480 } 481 snd_soc_write(codec, WM8993_CLOCKING_2, reg); 482 break; 483 484 case WM8993_SYSCLK_FLL: 485 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 486 wm8993->fll_fout); 487 488 reg = snd_soc_read(codec, WM8993_CLOCKING_2); 489 reg |= WM8993_SYSCLK_SRC; 490 if (wm8993->fll_fout > 13500000) { 491 reg |= WM8993_MCLK_DIV; 492 wm8993->sysclk_rate = wm8993->fll_fout / 2; 493 } else { 494 reg &= ~WM8993_MCLK_DIV; 495 wm8993->sysclk_rate = wm8993->fll_fout; 496 } 497 snd_soc_write(codec, WM8993_CLOCKING_2, reg); 498 break; 499 500 default: 501 dev_err(codec->dev, "System clock not configured\n"); 502 return -EINVAL; 503 } 504 505 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate); 506 507 return 0; 508 } 509 510 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 511 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0); 512 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0); 513 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); 514 static const unsigned int drc_max_tlv[] = { 515 TLV_DB_RANGE_HEAD(4), 516 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0), 517 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0), 518 }; 519 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); 520 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0); 521 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 522 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 523 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 524 525 static const char *dac_deemph_text[] = { 526 "None", 527 "32kHz", 528 "44.1kHz", 529 "48kHz", 530 }; 531 532 static const struct soc_enum dac_deemph = 533 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text); 534 535 static const char *adc_hpf_text[] = { 536 "Hi-Fi", 537 "Voice 1", 538 "Voice 2", 539 "Voice 3", 540 }; 541 542 static const struct soc_enum adc_hpf = 543 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text); 544 545 static const char *drc_path_text[] = { 546 "ADC", 547 "DAC" 548 }; 549 550 static const struct soc_enum drc_path = 551 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text); 552 553 static const char *drc_r0_text[] = { 554 "1", 555 "1/2", 556 "1/4", 557 "1/8", 558 "1/16", 559 "0", 560 }; 561 562 static const struct soc_enum drc_r0 = 563 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text); 564 565 static const char *drc_r1_text[] = { 566 "1", 567 "1/2", 568 "1/4", 569 "1/8", 570 "0", 571 }; 572 573 static const struct soc_enum drc_r1 = 574 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text); 575 576 static const char *drc_attack_text[] = { 577 "Reserved", 578 "181us", 579 "363us", 580 "726us", 581 "1.45ms", 582 "2.9ms", 583 "5.8ms", 584 "11.6ms", 585 "23.2ms", 586 "46.4ms", 587 "92.8ms", 588 "185.6ms", 589 }; 590 591 static const struct soc_enum drc_attack = 592 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text); 593 594 static const char *drc_decay_text[] = { 595 "186ms", 596 "372ms", 597 "743ms", 598 "1.49s", 599 "2.97ms", 600 "5.94ms", 601 "11.89ms", 602 "23.78ms", 603 "47.56ms", 604 }; 605 606 static const struct soc_enum drc_decay = 607 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text); 608 609 static const char *drc_ff_text[] = { 610 "5 samples", 611 "9 samples", 612 }; 613 614 static const struct soc_enum drc_ff = 615 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text); 616 617 static const char *drc_qr_rate_text[] = { 618 "0.725ms", 619 "1.45ms", 620 "5.8ms", 621 }; 622 623 static const struct soc_enum drc_qr_rate = 624 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text); 625 626 static const char *drc_smooth_text[] = { 627 "Low", 628 "Medium", 629 "High", 630 }; 631 632 static const struct soc_enum drc_smooth = 633 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text); 634 635 static const struct snd_kcontrol_new wm8993_snd_controls[] = { 636 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE, 637 5, 9, 12, 0, sidetone_tlv), 638 639 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0), 640 SOC_ENUM("DRC Path", drc_path), 641 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2, 642 2, 60, 1, drc_comp_threash), 643 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3, 644 11, 30, 1, drc_comp_amp), 645 SOC_ENUM("DRC R0", drc_r0), 646 SOC_ENUM("DRC R1", drc_r1), 647 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1, 648 drc_min_tlv), 649 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0, 650 drc_max_tlv), 651 SOC_ENUM("DRC Attack Rate", drc_attack), 652 SOC_ENUM("DRC Decay Rate", drc_decay), 653 SOC_ENUM("DRC FF Delay", drc_ff), 654 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0), 655 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0), 656 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0, 657 drc_qr_tlv), 658 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate), 659 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0), 660 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0), 661 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth), 662 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0, 663 drc_startup_tlv), 664 665 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0), 666 667 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME, 668 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 669 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0), 670 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf), 671 672 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME, 673 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), 674 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0, 675 dac_boost_tlv), 676 SOC_ENUM("DAC Deemphasis", dac_deemph), 677 678 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION, 679 2, 1, 1, wm_hubs_spkmix_tlv), 680 681 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION, 682 2, 1, 1, wm_hubs_spkmix_tlv), 683 }; 684 685 static const struct snd_kcontrol_new wm8993_eq_controls[] = { 686 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv), 687 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv), 688 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv), 689 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv), 690 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv), 691 }; 692 693 static int clk_sys_event(struct snd_soc_dapm_widget *w, 694 struct snd_kcontrol *kcontrol, int event) 695 { 696 struct snd_soc_codec *codec = w->codec; 697 698 switch (event) { 699 case SND_SOC_DAPM_PRE_PMU: 700 return configure_clock(codec); 701 702 case SND_SOC_DAPM_POST_PMD: 703 break; 704 } 705 706 return 0; 707 } 708 709 /* 710 * When used with DAC outputs only the WM8993 charge pump supports 711 * operation in class W mode, providing very low power consumption 712 * when used with digital sources. Enable and disable this mode 713 * automatically depending on the mixer configuration. 714 * 715 * Currently the only supported paths are the direct DAC->headphone 716 * paths (which provide minimum power consumption anyway). 717 */ 718 static int class_w_put(struct snd_kcontrol *kcontrol, 719 struct snd_ctl_elem_value *ucontrol) 720 { 721 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 722 struct snd_soc_dapm_widget *widget = wlist->widgets[0]; 723 struct snd_soc_codec *codec = widget->codec; 724 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 725 int ret; 726 727 /* Turn it off if we're using the main output mixer */ 728 if (ucontrol->value.integer.value[0] == 0) { 729 if (wm8993->class_w_users == 0) { 730 dev_dbg(codec->dev, "Disabling Class W\n"); 731 snd_soc_update_bits(codec, WM8993_CLASS_W_0, 732 WM8993_CP_DYN_FREQ | 733 WM8993_CP_DYN_V, 734 0); 735 } 736 wm8993->class_w_users++; 737 wm8993->hubs_data.class_w = true; 738 } 739 740 /* Implement the change */ 741 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 742 743 /* Enable it if we're using the direct DAC path */ 744 if (ucontrol->value.integer.value[0] == 1) { 745 if (wm8993->class_w_users == 1) { 746 dev_dbg(codec->dev, "Enabling Class W\n"); 747 snd_soc_update_bits(codec, WM8993_CLASS_W_0, 748 WM8993_CP_DYN_FREQ | 749 WM8993_CP_DYN_V, 750 WM8993_CP_DYN_FREQ | 751 WM8993_CP_DYN_V); 752 } 753 wm8993->class_w_users--; 754 wm8993->hubs_data.class_w = false; 755 } 756 757 dev_dbg(codec->dev, "Indirect DAC use count now %d\n", 758 wm8993->class_w_users); 759 760 return ret; 761 } 762 763 #define SOC_DAPM_ENUM_W(xname, xenum) \ 764 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 765 .info = snd_soc_info_enum_double, \ 766 .get = snd_soc_dapm_get_enum_double, \ 767 .put = class_w_put, \ 768 .private_value = (unsigned long)&xenum } 769 770 static const char *hp_mux_text[] = { 771 "Mixer", 772 "DAC", 773 }; 774 775 static const struct soc_enum hpl_enum = 776 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text); 777 778 static const struct snd_kcontrol_new hpl_mux = 779 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum); 780 781 static const struct soc_enum hpr_enum = 782 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text); 783 784 static const struct snd_kcontrol_new hpr_mux = 785 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum); 786 787 static const struct snd_kcontrol_new left_speaker_mixer[] = { 788 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0), 789 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0), 790 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0), 791 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 792 }; 793 794 static const struct snd_kcontrol_new right_speaker_mixer[] = { 795 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), 796 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0), 797 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0), 798 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0), 799 }; 800 801 static const char *aif_text[] = { 802 "Left", "Right" 803 }; 804 805 static const struct soc_enum aifoutl_enum = 806 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text); 807 808 static const struct snd_kcontrol_new aifoutl_mux = 809 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 810 811 static const struct soc_enum aifoutr_enum = 812 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text); 813 814 static const struct snd_kcontrol_new aifoutr_mux = 815 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 816 817 static const struct soc_enum aifinl_enum = 818 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text); 819 820 static const struct snd_kcontrol_new aifinl_mux = 821 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 822 823 static const struct soc_enum aifinr_enum = 824 SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text); 825 826 static const struct snd_kcontrol_new aifinr_mux = 827 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 828 829 static const char *sidetone_text[] = { 830 "None", "Left", "Right" 831 }; 832 833 static const struct soc_enum sidetonel_enum = 834 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text); 835 836 static const struct snd_kcontrol_new sidetonel_mux = 837 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum); 838 839 static const struct soc_enum sidetoner_enum = 840 SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text); 841 842 static const struct snd_kcontrol_new sidetoner_mux = 843 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum); 844 845 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = { 846 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event, 847 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 848 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0), 849 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0), 850 851 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0), 852 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0), 853 854 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 855 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 856 857 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 858 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 859 860 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 861 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 862 863 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 864 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 865 866 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux), 867 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux), 868 869 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0), 870 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0), 871 872 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 873 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 874 875 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0, 876 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 877 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0, 878 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 879 880 }; 881 882 static const struct snd_soc_dapm_route routes[] = { 883 { "ADCL", NULL, "CLK_SYS" }, 884 { "ADCL", NULL, "CLK_DSP" }, 885 { "ADCR", NULL, "CLK_SYS" }, 886 { "ADCR", NULL, "CLK_DSP" }, 887 888 { "AIFOUTL Mux", "Left", "ADCL" }, 889 { "AIFOUTL Mux", "Right", "ADCR" }, 890 { "AIFOUTR Mux", "Left", "ADCL" }, 891 { "AIFOUTR Mux", "Right", "ADCR" }, 892 893 { "AIFOUTL", NULL, "AIFOUTL Mux" }, 894 { "AIFOUTR", NULL, "AIFOUTR Mux" }, 895 896 { "DACL Mux", "Left", "AIFINL" }, 897 { "DACL Mux", "Right", "AIFINR" }, 898 { "DACR Mux", "Left", "AIFINL" }, 899 { "DACR Mux", "Right", "AIFINR" }, 900 901 { "DACL Sidetone", "Left", "ADCL" }, 902 { "DACL Sidetone", "Right", "ADCR" }, 903 { "DACR Sidetone", "Left", "ADCL" }, 904 { "DACR Sidetone", "Right", "ADCR" }, 905 906 { "DACL", NULL, "CLK_SYS" }, 907 { "DACL", NULL, "CLK_DSP" }, 908 { "DACL", NULL, "DACL Mux" }, 909 { "DACL", NULL, "DACL Sidetone" }, 910 { "DACR", NULL, "CLK_SYS" }, 911 { "DACR", NULL, "CLK_DSP" }, 912 { "DACR", NULL, "DACR Mux" }, 913 { "DACR", NULL, "DACR Sidetone" }, 914 915 { "Left Output Mixer", "DAC Switch", "DACL" }, 916 917 { "Right Output Mixer", "DAC Switch", "DACR" }, 918 919 { "Left Output PGA", NULL, "CLK_SYS" }, 920 921 { "Right Output PGA", NULL, "CLK_SYS" }, 922 923 { "SPKL", "DAC Switch", "DACL" }, 924 { "SPKL", NULL, "CLK_SYS" }, 925 926 { "SPKR", "DAC Switch", "DACR" }, 927 { "SPKR", NULL, "CLK_SYS" }, 928 929 { "Left Headphone Mux", "DAC", "DACL" }, 930 { "Right Headphone Mux", "DAC", "DACR" }, 931 }; 932 933 static void wm8993_cache_restore(struct snd_soc_codec *codec) 934 { 935 u16 *cache = codec->reg_cache; 936 int i; 937 938 if (!codec->cache_sync) 939 return; 940 941 /* Reenable hardware writes */ 942 codec->cache_only = 0; 943 944 /* Restore the register settings */ 945 for (i = 1; i < WM8993_MAX_REGISTER; i++) { 946 if (cache[i] == wm8993_reg_defaults[i]) 947 continue; 948 snd_soc_write(codec, i, cache[i]); 949 } 950 951 /* We're in sync again */ 952 codec->cache_sync = 0; 953 } 954 955 static int wm8993_set_bias_level(struct snd_soc_codec *codec, 956 enum snd_soc_bias_level level) 957 { 958 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 959 int ret; 960 961 switch (level) { 962 case SND_SOC_BIAS_ON: 963 case SND_SOC_BIAS_PREPARE: 964 /* VMID=2*40k */ 965 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 966 WM8993_VMID_SEL_MASK, 0x2); 967 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 968 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA); 969 break; 970 971 case SND_SOC_BIAS_STANDBY: 972 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 973 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), 974 wm8993->supplies); 975 if (ret != 0) 976 return ret; 977 978 wm8993_cache_restore(codec); 979 980 /* Tune DC servo configuration */ 981 snd_soc_write(codec, 0x44, 3); 982 snd_soc_write(codec, 0x56, 3); 983 snd_soc_write(codec, 0x44, 0); 984 985 /* Bring up VMID with fast soft start */ 986 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 987 WM8993_STARTUP_BIAS_ENA | 988 WM8993_VMID_BUF_ENA | 989 WM8993_VMID_RAMP_MASK | 990 WM8993_BIAS_SRC, 991 WM8993_STARTUP_BIAS_ENA | 992 WM8993_VMID_BUF_ENA | 993 WM8993_VMID_RAMP_MASK | 994 WM8993_BIAS_SRC); 995 996 /* If either line output is single ended we 997 * need the VMID buffer */ 998 if (!wm8993->pdata.lineout1_diff || 999 !wm8993->pdata.lineout2_diff) 1000 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1001 WM8993_LINEOUT_VMID_BUF_ENA, 1002 WM8993_LINEOUT_VMID_BUF_ENA); 1003 1004 /* VMID=2*40k */ 1005 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1006 WM8993_VMID_SEL_MASK | 1007 WM8993_BIAS_ENA, 1008 WM8993_BIAS_ENA | 0x2); 1009 msleep(32); 1010 1011 /* Switch to normal bias */ 1012 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1013 WM8993_BIAS_SRC | 1014 WM8993_STARTUP_BIAS_ENA, 0); 1015 } 1016 1017 /* VMID=2*240k */ 1018 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1019 WM8993_VMID_SEL_MASK, 0x4); 1020 1021 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, 1022 WM8993_TSHUT_ENA, 0); 1023 break; 1024 1025 case SND_SOC_BIAS_OFF: 1026 snd_soc_update_bits(codec, WM8993_ANTIPOP1, 1027 WM8993_LINEOUT_VMID_BUF_ENA, 0); 1028 1029 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, 1030 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, 1031 0); 1032 1033 snd_soc_update_bits(codec, WM8993_ANTIPOP2, 1034 WM8993_STARTUP_BIAS_ENA | 1035 WM8993_VMID_BUF_ENA | 1036 WM8993_VMID_RAMP_MASK | 1037 WM8993_BIAS_SRC, 0); 1038 1039 #ifdef CONFIG_REGULATOR 1040 /* Post 2.6.34 we will be able to get a callback when 1041 * the regulators are disabled which we can use but 1042 * for now just assume that the power will be cut if 1043 * the regulator API is in use. 1044 */ 1045 codec->cache_sync = 1; 1046 #endif 1047 1048 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), 1049 wm8993->supplies); 1050 break; 1051 } 1052 1053 codec->dapm.bias_level = level; 1054 1055 return 0; 1056 } 1057 1058 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai, 1059 int clk_id, unsigned int freq, int dir) 1060 { 1061 struct snd_soc_codec *codec = codec_dai->codec; 1062 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1063 1064 switch (clk_id) { 1065 case WM8993_SYSCLK_MCLK: 1066 wm8993->mclk_rate = freq; 1067 case WM8993_SYSCLK_FLL: 1068 wm8993->sysclk_source = clk_id; 1069 break; 1070 1071 default: 1072 return -EINVAL; 1073 } 1074 1075 return 0; 1076 } 1077 1078 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai, 1079 unsigned int fmt) 1080 { 1081 struct snd_soc_codec *codec = dai->codec; 1082 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1083 unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); 1084 unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); 1085 1086 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV | 1087 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK); 1088 aif4 &= ~WM8993_LRCLK_DIR; 1089 1090 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1091 case SND_SOC_DAIFMT_CBS_CFS: 1092 wm8993->master = 0; 1093 break; 1094 case SND_SOC_DAIFMT_CBS_CFM: 1095 aif4 |= WM8993_LRCLK_DIR; 1096 wm8993->master = 1; 1097 break; 1098 case SND_SOC_DAIFMT_CBM_CFS: 1099 aif1 |= WM8993_BCLK_DIR; 1100 wm8993->master = 1; 1101 break; 1102 case SND_SOC_DAIFMT_CBM_CFM: 1103 aif1 |= WM8993_BCLK_DIR; 1104 aif4 |= WM8993_LRCLK_DIR; 1105 wm8993->master = 1; 1106 break; 1107 default: 1108 return -EINVAL; 1109 } 1110 1111 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1112 case SND_SOC_DAIFMT_DSP_B: 1113 aif1 |= WM8993_AIF_LRCLK_INV; 1114 case SND_SOC_DAIFMT_DSP_A: 1115 aif1 |= 0x18; 1116 break; 1117 case SND_SOC_DAIFMT_I2S: 1118 aif1 |= 0x10; 1119 break; 1120 case SND_SOC_DAIFMT_RIGHT_J: 1121 break; 1122 case SND_SOC_DAIFMT_LEFT_J: 1123 aif1 |= 0x8; 1124 break; 1125 default: 1126 return -EINVAL; 1127 } 1128 1129 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1130 case SND_SOC_DAIFMT_DSP_A: 1131 case SND_SOC_DAIFMT_DSP_B: 1132 /* frame inversion not valid for DSP modes */ 1133 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1134 case SND_SOC_DAIFMT_NB_NF: 1135 break; 1136 case SND_SOC_DAIFMT_IB_NF: 1137 aif1 |= WM8993_AIF_BCLK_INV; 1138 break; 1139 default: 1140 return -EINVAL; 1141 } 1142 break; 1143 1144 case SND_SOC_DAIFMT_I2S: 1145 case SND_SOC_DAIFMT_RIGHT_J: 1146 case SND_SOC_DAIFMT_LEFT_J: 1147 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1148 case SND_SOC_DAIFMT_NB_NF: 1149 break; 1150 case SND_SOC_DAIFMT_IB_IF: 1151 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV; 1152 break; 1153 case SND_SOC_DAIFMT_IB_NF: 1154 aif1 |= WM8993_AIF_BCLK_INV; 1155 break; 1156 case SND_SOC_DAIFMT_NB_IF: 1157 aif1 |= WM8993_AIF_LRCLK_INV; 1158 break; 1159 default: 1160 return -EINVAL; 1161 } 1162 break; 1163 default: 1164 return -EINVAL; 1165 } 1166 1167 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1168 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1169 1170 return 0; 1171 } 1172 1173 static int wm8993_hw_params(struct snd_pcm_substream *substream, 1174 struct snd_pcm_hw_params *params, 1175 struct snd_soc_dai *dai) 1176 { 1177 struct snd_soc_codec *codec = dai->codec; 1178 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1179 int ret, i, best, best_val, cur_val; 1180 unsigned int clocking1, clocking3, aif1, aif4; 1181 1182 clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1); 1183 clocking1 &= ~WM8993_BCLK_DIV_MASK; 1184 1185 clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3); 1186 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK); 1187 1188 aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); 1189 aif1 &= ~WM8993_AIF_WL_MASK; 1190 1191 aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); 1192 aif4 &= ~WM8993_LRCLK_RATE_MASK; 1193 1194 /* What BCLK do we need? */ 1195 wm8993->fs = params_rate(params); 1196 wm8993->bclk = 2 * wm8993->fs; 1197 if (wm8993->tdm_slots) { 1198 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1199 wm8993->tdm_slots, wm8993->tdm_width); 1200 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots; 1201 } else { 1202 switch (params_format(params)) { 1203 case SNDRV_PCM_FORMAT_S16_LE: 1204 wm8993->bclk *= 16; 1205 break; 1206 case SNDRV_PCM_FORMAT_S20_3LE: 1207 wm8993->bclk *= 20; 1208 aif1 |= 0x8; 1209 break; 1210 case SNDRV_PCM_FORMAT_S24_LE: 1211 wm8993->bclk *= 24; 1212 aif1 |= 0x10; 1213 break; 1214 case SNDRV_PCM_FORMAT_S32_LE: 1215 wm8993->bclk *= 32; 1216 aif1 |= 0x18; 1217 break; 1218 default: 1219 return -EINVAL; 1220 } 1221 } 1222 1223 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk); 1224 1225 ret = configure_clock(codec); 1226 if (ret != 0) 1227 return ret; 1228 1229 /* Select nearest CLK_SYS_RATE */ 1230 best = 0; 1231 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio) 1232 - wm8993->fs); 1233 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1234 cur_val = abs((wm8993->sysclk_rate / 1235 clk_sys_rates[i].ratio) - wm8993->fs); 1236 if (cur_val < best_val) { 1237 best = i; 1238 best_val = cur_val; 1239 } 1240 } 1241 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1242 clk_sys_rates[best].ratio); 1243 clocking3 |= (clk_sys_rates[best].clk_sys_rate 1244 << WM8993_CLK_SYS_RATE_SHIFT); 1245 1246 /* SAMPLE_RATE */ 1247 best = 0; 1248 best_val = abs(wm8993->fs - sample_rates[0].rate); 1249 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1250 /* Closest match */ 1251 cur_val = abs(wm8993->fs - sample_rates[i].rate); 1252 if (cur_val < best_val) { 1253 best = i; 1254 best_val = cur_val; 1255 } 1256 } 1257 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1258 sample_rates[best].rate); 1259 clocking3 |= (sample_rates[best].sample_rate 1260 << WM8993_SAMPLE_RATE_SHIFT); 1261 1262 /* BCLK_DIV */ 1263 best = 0; 1264 best_val = INT_MAX; 1265 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1266 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div) 1267 - wm8993->bclk; 1268 if (cur_val < 0) /* Table is sorted */ 1269 break; 1270 if (cur_val < best_val) { 1271 best = i; 1272 best_val = cur_val; 1273 } 1274 } 1275 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div; 1276 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1277 bclk_divs[best].div, wm8993->bclk); 1278 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT; 1279 1280 /* LRCLK is a simple fraction of BCLK */ 1281 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs); 1282 aif4 |= wm8993->bclk / wm8993->fs; 1283 1284 snd_soc_write(codec, WM8993_CLOCKING_1, clocking1); 1285 snd_soc_write(codec, WM8993_CLOCKING_3, clocking3); 1286 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); 1287 snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); 1288 1289 /* ReTune Mobile? */ 1290 if (wm8993->pdata.num_retune_configs) { 1291 u16 eq1 = snd_soc_read(codec, WM8993_EQ1); 1292 struct wm8993_retune_mobile_setting *s; 1293 1294 best = 0; 1295 best_val = abs(wm8993->pdata.retune_configs[0].rate 1296 - wm8993->fs); 1297 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) { 1298 cur_val = abs(wm8993->pdata.retune_configs[i].rate 1299 - wm8993->fs); 1300 if (cur_val < best_val) { 1301 best_val = cur_val; 1302 best = i; 1303 } 1304 } 1305 s = &wm8993->pdata.retune_configs[best]; 1306 1307 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n", 1308 s->name, s->rate); 1309 1310 /* Disable EQ while we reconfigure */ 1311 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0); 1312 1313 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1314 snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]); 1315 1316 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1323 { 1324 struct snd_soc_codec *codec = codec_dai->codec; 1325 unsigned int reg; 1326 1327 reg = snd_soc_read(codec, WM8993_DAC_CTRL); 1328 1329 if (mute) 1330 reg |= WM8993_DAC_MUTE; 1331 else 1332 reg &= ~WM8993_DAC_MUTE; 1333 1334 snd_soc_write(codec, WM8993_DAC_CTRL, reg); 1335 1336 return 0; 1337 } 1338 1339 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1340 unsigned int rx_mask, int slots, int slot_width) 1341 { 1342 struct snd_soc_codec *codec = dai->codec; 1343 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1344 int aif1 = 0; 1345 int aif2 = 0; 1346 1347 /* Don't need to validate anything if we're turning off TDM */ 1348 if (slots == 0) { 1349 wm8993->tdm_slots = 0; 1350 goto out; 1351 } 1352 1353 /* Note that we allow configurations we can't handle ourselves - 1354 * for example, we can generate clocks for slots 2 and up even if 1355 * we can't use those slots ourselves. 1356 */ 1357 aif1 |= WM8993_AIFADC_TDM; 1358 aif2 |= WM8993_AIFDAC_TDM; 1359 1360 switch (rx_mask) { 1361 case 3: 1362 break; 1363 case 0xc: 1364 aif1 |= WM8993_AIFADC_TDM_CHAN; 1365 break; 1366 default: 1367 return -EINVAL; 1368 } 1369 1370 1371 switch (tx_mask) { 1372 case 3: 1373 break; 1374 case 0xc: 1375 aif2 |= WM8993_AIFDAC_TDM_CHAN; 1376 break; 1377 default: 1378 return -EINVAL; 1379 } 1380 1381 out: 1382 wm8993->tdm_width = slot_width; 1383 wm8993->tdm_slots = slots / 2; 1384 1385 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1, 1386 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1); 1387 snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2, 1388 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2); 1389 1390 return 0; 1391 } 1392 1393 static struct snd_soc_dai_ops wm8993_ops = { 1394 .set_sysclk = wm8993_set_sysclk, 1395 .set_fmt = wm8993_set_dai_fmt, 1396 .hw_params = wm8993_hw_params, 1397 .digital_mute = wm8993_digital_mute, 1398 .set_pll = wm8993_set_fll, 1399 .set_tdm_slot = wm8993_set_tdm_slot, 1400 }; 1401 1402 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000 1403 1404 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1405 SNDRV_PCM_FMTBIT_S20_3LE |\ 1406 SNDRV_PCM_FMTBIT_S24_LE |\ 1407 SNDRV_PCM_FMTBIT_S32_LE) 1408 1409 static struct snd_soc_dai_driver wm8993_dai = { 1410 .name = "wm8993-hifi", 1411 .playback = { 1412 .stream_name = "Playback", 1413 .channels_min = 1, 1414 .channels_max = 2, 1415 .rates = WM8993_RATES, 1416 .formats = WM8993_FORMATS, 1417 }, 1418 .capture = { 1419 .stream_name = "Capture", 1420 .channels_min = 1, 1421 .channels_max = 2, 1422 .rates = WM8993_RATES, 1423 .formats = WM8993_FORMATS, 1424 }, 1425 .ops = &wm8993_ops, 1426 .symmetric_rates = 1, 1427 }; 1428 1429 static int wm8993_probe(struct snd_soc_codec *codec) 1430 { 1431 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1432 struct snd_soc_dapm_context *dapm = &codec->dapm; 1433 int ret, i, val; 1434 1435 wm8993->hubs_data.hp_startup_mode = 1; 1436 wm8993->hubs_data.dcs_codes = -2; 1437 1438 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1439 if (ret != 0) { 1440 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1441 return ret; 1442 } 1443 1444 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++) 1445 wm8993->supplies[i].supply = wm8993_supply_names[i]; 1446 1447 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies), 1448 wm8993->supplies); 1449 if (ret != 0) { 1450 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1451 return ret; 1452 } 1453 1454 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), 1455 wm8993->supplies); 1456 if (ret != 0) { 1457 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 1458 goto err_get; 1459 } 1460 1461 val = snd_soc_read(codec, WM8993_SOFTWARE_RESET); 1462 if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) { 1463 dev_err(codec->dev, "Invalid ID register value %x\n", val); 1464 ret = -EINVAL; 1465 goto err_enable; 1466 } 1467 1468 ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff); 1469 if (ret != 0) 1470 goto err_enable; 1471 1472 codec->cache_only = 1; 1473 1474 /* By default we're using the output mixers */ 1475 wm8993->class_w_users = 2; 1476 1477 /* Latch volume update bits and default ZC on */ 1478 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1479 WM8993_DAC_VU, WM8993_DAC_VU); 1480 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1481 WM8993_ADC_VU, WM8993_ADC_VU); 1482 1483 /* Manualy manage the HPOUT sequencing for independent stereo 1484 * control. */ 1485 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0, 1486 WM8993_HPOUT1_AUTO_PU, 0); 1487 1488 /* Use automatic clock configuration */ 1489 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0); 1490 1491 wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff, 1492 wm8993->pdata.lineout2_diff, 1493 wm8993->pdata.lineout1fb, 1494 wm8993->pdata.lineout2fb, 1495 wm8993->pdata.jd_scthr, 1496 wm8993->pdata.jd_thr, 1497 wm8993->pdata.micbias1_lvl, 1498 wm8993->pdata.micbias2_lvl); 1499 1500 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1501 if (ret != 0) 1502 goto err_enable; 1503 1504 snd_soc_add_controls(codec, wm8993_snd_controls, 1505 ARRAY_SIZE(wm8993_snd_controls)); 1506 if (wm8993->pdata.num_retune_configs != 0) { 1507 dev_dbg(codec->dev, "Using ReTune Mobile\n"); 1508 } else { 1509 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n"); 1510 snd_soc_add_controls(codec, wm8993_eq_controls, 1511 ARRAY_SIZE(wm8993_eq_controls)); 1512 } 1513 1514 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets, 1515 ARRAY_SIZE(wm8993_dapm_widgets)); 1516 wm_hubs_add_analogue_controls(codec); 1517 1518 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); 1519 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff, 1520 wm8993->pdata.lineout2_diff); 1521 1522 return 0; 1523 1524 err_enable: 1525 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1526 err_get: 1527 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1528 return ret; 1529 } 1530 1531 static int wm8993_remove(struct snd_soc_codec *codec) 1532 { 1533 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1534 1535 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF); 1536 regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); 1537 return 0; 1538 } 1539 1540 #ifdef CONFIG_PM 1541 static int wm8993_suspend(struct snd_soc_codec *codec, pm_message_t state) 1542 { 1543 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1544 int fll_fout = wm8993->fll_fout; 1545 int fll_fref = wm8993->fll_fref; 1546 int ret; 1547 1548 /* Stop the FLL in an orderly fashion */ 1549 ret = _wm8993_set_fll(codec, 0, 0, 0, 0); 1550 if (ret != 0) { 1551 dev_err(codec->dev, "Failed to stop FLL\n"); 1552 return ret; 1553 } 1554 1555 wm8993->fll_fout = fll_fout; 1556 wm8993->fll_fref = fll_fref; 1557 1558 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF); 1559 1560 return 0; 1561 } 1562 1563 static int wm8993_resume(struct snd_soc_codec *codec) 1564 { 1565 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1566 int ret; 1567 1568 wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1569 1570 /* Restart the FLL? */ 1571 if (wm8993->fll_fout) { 1572 int fll_fout = wm8993->fll_fout; 1573 int fll_fref = wm8993->fll_fref; 1574 1575 wm8993->fll_fref = 0; 1576 wm8993->fll_fout = 0; 1577 1578 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src, 1579 fll_fref, fll_fout); 1580 if (ret != 0) 1581 dev_err(codec->dev, "Failed to restart FLL\n"); 1582 } 1583 1584 return 0; 1585 } 1586 #else 1587 #define wm8993_suspend NULL 1588 #define wm8993_resume NULL 1589 #endif 1590 1591 static struct snd_soc_codec_driver soc_codec_dev_wm8993 = { 1592 .probe = wm8993_probe, 1593 .remove = wm8993_remove, 1594 .suspend = wm8993_suspend, 1595 .resume = wm8993_resume, 1596 .set_bias_level = wm8993_set_bias_level, 1597 .reg_cache_size = ARRAY_SIZE(wm8993_reg_defaults), 1598 .reg_word_size = sizeof(u16), 1599 .reg_cache_default = wm8993_reg_defaults, 1600 .volatile_register = wm8993_volatile, 1601 }; 1602 1603 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1604 static __devinit int wm8993_i2c_probe(struct i2c_client *i2c, 1605 const struct i2c_device_id *id) 1606 { 1607 struct wm8993_priv *wm8993; 1608 int ret; 1609 1610 wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL); 1611 if (wm8993 == NULL) 1612 return -ENOMEM; 1613 1614 i2c_set_clientdata(i2c, wm8993); 1615 1616 ret = snd_soc_register_codec(&i2c->dev, 1617 &soc_codec_dev_wm8993, &wm8993_dai, 1); 1618 if (ret < 0) 1619 kfree(wm8993); 1620 return ret; 1621 } 1622 1623 static __devexit int wm8993_i2c_remove(struct i2c_client *client) 1624 { 1625 snd_soc_unregister_codec(&client->dev); 1626 kfree(i2c_get_clientdata(client)); 1627 return 0; 1628 } 1629 1630 static const struct i2c_device_id wm8993_i2c_id[] = { 1631 { "wm8993", 0 }, 1632 { } 1633 }; 1634 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id); 1635 1636 static struct i2c_driver wm8993_i2c_driver = { 1637 .driver = { 1638 .name = "wm8993-codec", 1639 .owner = THIS_MODULE, 1640 }, 1641 .probe = wm8993_i2c_probe, 1642 .remove = __devexit_p(wm8993_i2c_remove), 1643 .id_table = wm8993_i2c_id, 1644 }; 1645 #endif 1646 1647 static int __init wm8993_modinit(void) 1648 { 1649 int ret = 0; 1650 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1651 ret = i2c_add_driver(&wm8993_i2c_driver); 1652 if (ret != 0) { 1653 pr_err("WM8993: Unable to register I2C driver: %d\n", 1654 ret); 1655 } 1656 #endif 1657 return ret; 1658 } 1659 module_init(wm8993_modinit); 1660 1661 static void __exit wm8993_exit(void) 1662 { 1663 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1664 i2c_del_driver(&wm8993_i2c_driver); 1665 #endif 1666 } 1667 module_exit(wm8993_exit); 1668 1669 1670 MODULE_DESCRIPTION("ASoC WM8993 driver"); 1671 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1672 MODULE_LICENSE("GPL"); 1673