1 /* 2 * wm8990.c -- WM8990 ALSA Soc Audio driver 3 * 4 * Copyright 2008 Wolfson Microelectronics PLC. 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <asm/div64.h> 29 30 #include "wm8990.h" 31 32 /* codec private data */ 33 struct wm8990_priv { 34 enum snd_soc_control_type control_type; 35 unsigned int sysclk; 36 unsigned int pcmclk; 37 }; 38 39 /* 40 * wm8990 register cache. Note that register 0 is not included in the 41 * cache. 42 */ 43 static const u16 wm8990_reg[] = { 44 0x8990, /* R0 - Reset */ 45 0x0000, /* R1 - Power Management (1) */ 46 0x6000, /* R2 - Power Management (2) */ 47 0x0000, /* R3 - Power Management (3) */ 48 0x4050, /* R4 - Audio Interface (1) */ 49 0x4000, /* R5 - Audio Interface (2) */ 50 0x01C8, /* R6 - Clocking (1) */ 51 0x0000, /* R7 - Clocking (2) */ 52 0x0040, /* R8 - Audio Interface (3) */ 53 0x0040, /* R9 - Audio Interface (4) */ 54 0x0004, /* R10 - DAC CTRL */ 55 0x00C0, /* R11 - Left DAC Digital Volume */ 56 0x00C0, /* R12 - Right DAC Digital Volume */ 57 0x0000, /* R13 - Digital Side Tone */ 58 0x0100, /* R14 - ADC CTRL */ 59 0x00C0, /* R15 - Left ADC Digital Volume */ 60 0x00C0, /* R16 - Right ADC Digital Volume */ 61 0x0000, /* R17 */ 62 0x0000, /* R18 - GPIO CTRL 1 */ 63 0x1000, /* R19 - GPIO1 & GPIO2 */ 64 0x1010, /* R20 - GPIO3 & GPIO4 */ 65 0x1010, /* R21 - GPIO5 & GPIO6 */ 66 0x8000, /* R22 - GPIOCTRL 2 */ 67 0x0800, /* R23 - GPIO_POL */ 68 0x008B, /* R24 - Left Line Input 1&2 Volume */ 69 0x008B, /* R25 - Left Line Input 3&4 Volume */ 70 0x008B, /* R26 - Right Line Input 1&2 Volume */ 71 0x008B, /* R27 - Right Line Input 3&4 Volume */ 72 0x0000, /* R28 - Left Output Volume */ 73 0x0000, /* R29 - Right Output Volume */ 74 0x0066, /* R30 - Line Outputs Volume */ 75 0x0022, /* R31 - Out3/4 Volume */ 76 0x0079, /* R32 - Left OPGA Volume */ 77 0x0079, /* R33 - Right OPGA Volume */ 78 0x0003, /* R34 - Speaker Volume */ 79 0x0003, /* R35 - ClassD1 */ 80 0x0000, /* R36 */ 81 0x0100, /* R37 - ClassD3 */ 82 0x0079, /* R38 - ClassD4 */ 83 0x0000, /* R39 - Input Mixer1 */ 84 0x0000, /* R40 - Input Mixer2 */ 85 0x0000, /* R41 - Input Mixer3 */ 86 0x0000, /* R42 - Input Mixer4 */ 87 0x0000, /* R43 - Input Mixer5 */ 88 0x0000, /* R44 - Input Mixer6 */ 89 0x0000, /* R45 - Output Mixer1 */ 90 0x0000, /* R46 - Output Mixer2 */ 91 0x0000, /* R47 - Output Mixer3 */ 92 0x0000, /* R48 - Output Mixer4 */ 93 0x0000, /* R49 - Output Mixer5 */ 94 0x0000, /* R50 - Output Mixer6 */ 95 0x0180, /* R51 - Out3/4 Mixer */ 96 0x0000, /* R52 - Line Mixer1 */ 97 0x0000, /* R53 - Line Mixer2 */ 98 0x0000, /* R54 - Speaker Mixer */ 99 0x0000, /* R55 - Additional Control */ 100 0x0000, /* R56 - AntiPOP1 */ 101 0x0000, /* R57 - AntiPOP2 */ 102 0x0000, /* R58 - MICBIAS */ 103 0x0000, /* R59 */ 104 0x0008, /* R60 - PLL1 */ 105 0x0031, /* R61 - PLL2 */ 106 0x0026, /* R62 - PLL3 */ 107 0x0000, /* R63 - Driver internal */ 108 }; 109 110 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0) 111 112 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); 113 114 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); 115 116 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0); 117 118 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); 119 120 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); 121 122 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); 123 124 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); 125 126 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); 127 128 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 129 struct snd_ctl_elem_value *ucontrol) 130 { 131 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 132 struct soc_mixer_control *mc = 133 (struct soc_mixer_control *)kcontrol->private_value; 134 int reg = mc->reg; 135 int ret; 136 u16 val; 137 138 ret = snd_soc_put_volsw(kcontrol, ucontrol); 139 if (ret < 0) 140 return ret; 141 142 /* now hit the volume update bits (always bit 8) */ 143 val = snd_soc_read(codec, reg); 144 return snd_soc_write(codec, reg, val | 0x0100); 145 } 146 147 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 148 tlv_array) {\ 149 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 150 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 151 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 152 .tlv.p = (tlv_array), \ 153 .info = snd_soc_info_volsw, \ 154 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ 155 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 156 157 158 static const char *wm8990_digital_sidetone[] = 159 {"None", "Left ADC", "Right ADC", "Reserved"}; 160 161 static const struct soc_enum wm8990_left_digital_sidetone_enum = 162 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 163 WM8990_ADC_TO_DACL_SHIFT, 164 WM8990_ADC_TO_DACL_MASK, 165 wm8990_digital_sidetone); 166 167 static const struct soc_enum wm8990_right_digital_sidetone_enum = 168 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 169 WM8990_ADC_TO_DACR_SHIFT, 170 WM8990_ADC_TO_DACR_MASK, 171 wm8990_digital_sidetone); 172 173 static const char *wm8990_adcmode[] = 174 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 175 176 static const struct soc_enum wm8990_right_adcmode_enum = 177 SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 178 WM8990_ADC_HPF_CUT_SHIFT, 179 WM8990_ADC_HPF_CUT_MASK, 180 wm8990_adcmode); 181 182 static const struct snd_kcontrol_new wm8990_snd_controls[] = { 183 /* INMIXL */ 184 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 185 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 186 /* INMIXR */ 187 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 188 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 189 190 /* LOMIX */ 191 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 192 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 193 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 194 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 195 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 196 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 197 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 198 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 199 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 200 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 201 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 202 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 203 204 /* ROMIX */ 205 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 206 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 207 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 208 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 209 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 210 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 211 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 212 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 213 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 214 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 215 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 216 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 217 218 /* LOUT */ 219 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 220 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 221 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 222 223 /* ROUT */ 224 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 225 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 226 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 227 228 /* LOPGA */ 229 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 230 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 231 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 232 WM8990_LOPGAZC_BIT, 1, 0), 233 234 /* ROPGA */ 235 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 236 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 237 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 238 WM8990_ROPGAZC_BIT, 1, 0), 239 240 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 241 WM8990_LONMUTE_BIT, 1, 0), 242 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 243 WM8990_LOPMUTE_BIT, 1, 0), 244 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 245 WM8990_LOATTN_BIT, 1, 0), 246 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 247 WM8990_RONMUTE_BIT, 1, 0), 248 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 249 WM8990_ROPMUTE_BIT, 1, 0), 250 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 251 WM8990_ROATTN_BIT, 1, 0), 252 253 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 254 WM8990_OUT3MUTE_BIT, 1, 0), 255 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 256 WM8990_OUT3ATTN_BIT, 1, 0), 257 258 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 259 WM8990_OUT4MUTE_BIT, 1, 0), 260 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 261 WM8990_OUT4ATTN_BIT, 1, 0), 262 263 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 264 WM8990_CDMODE_BIT, 1, 0), 265 266 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 267 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 268 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 269 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 270 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 271 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 272 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 273 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 274 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 275 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 276 277 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 278 WM8990_LEFT_DAC_DIGITAL_VOLUME, 279 WM8990_DACL_VOL_SHIFT, 280 WM8990_DACL_VOL_MASK, 281 0, 282 out_dac_tlv), 283 284 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 285 WM8990_RIGHT_DAC_DIGITAL_VOLUME, 286 WM8990_DACR_VOL_SHIFT, 287 WM8990_DACR_VOL_MASK, 288 0, 289 out_dac_tlv), 290 291 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 292 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 293 294 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 295 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 296 out_sidetone_tlv), 297 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 298 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 299 out_sidetone_tlv), 300 301 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 302 WM8990_ADC_HPF_ENA_BIT, 1, 0), 303 304 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 305 306 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 307 WM8990_LEFT_ADC_DIGITAL_VOLUME, 308 WM8990_ADCL_VOL_SHIFT, 309 WM8990_ADCL_VOL_MASK, 310 0, 311 in_adc_tlv), 312 313 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 314 WM8990_RIGHT_ADC_DIGITAL_VOLUME, 315 WM8990_ADCR_VOL_SHIFT, 316 WM8990_ADCR_VOL_MASK, 317 0, 318 in_adc_tlv), 319 320 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 321 WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 322 WM8990_LIN12VOL_SHIFT, 323 WM8990_LIN12VOL_MASK, 324 0, 325 in_pga_tlv), 326 327 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 328 WM8990_LI12ZC_BIT, 1, 0), 329 330 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 331 WM8990_LI12MUTE_BIT, 1, 0), 332 333 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 334 WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 335 WM8990_LIN34VOL_SHIFT, 336 WM8990_LIN34VOL_MASK, 337 0, 338 in_pga_tlv), 339 340 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 341 WM8990_LI34ZC_BIT, 1, 0), 342 343 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 344 WM8990_LI34MUTE_BIT, 1, 0), 345 346 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 347 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 348 WM8990_RIN12VOL_SHIFT, 349 WM8990_RIN12VOL_MASK, 350 0, 351 in_pga_tlv), 352 353 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 354 WM8990_RI12ZC_BIT, 1, 0), 355 356 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 357 WM8990_RI12MUTE_BIT, 1, 0), 358 359 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 360 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 361 WM8990_RIN34VOL_SHIFT, 362 WM8990_RIN34VOL_MASK, 363 0, 364 in_pga_tlv), 365 366 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 367 WM8990_RI34ZC_BIT, 1, 0), 368 369 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 370 WM8990_RI34MUTE_BIT, 1, 0), 371 372 }; 373 374 /* 375 * _DAPM_ Controls 376 */ 377 378 static int inmixer_event(struct snd_soc_dapm_widget *w, 379 struct snd_kcontrol *kcontrol, int event) 380 { 381 u16 reg, fakepower; 382 383 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2); 384 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS); 385 386 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 387 (1 << WM8990_AINLMUX_PWR_BIT))) { 388 reg |= WM8990_AINL_ENA; 389 } else { 390 reg &= ~WM8990_AINL_ENA; 391 } 392 393 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) | 394 (1 << WM8990_AINRMUX_PWR_BIT))) { 395 reg |= WM8990_AINR_ENA; 396 } else { 397 reg &= ~WM8990_AINL_ENA; 398 } 399 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 400 401 return 0; 402 } 403 404 static int outmixer_event(struct snd_soc_dapm_widget *w, 405 struct snd_kcontrol *kcontrol, int event) 406 { 407 u32 reg_shift = kcontrol->private_value & 0xfff; 408 int ret = 0; 409 u16 reg; 410 411 switch (reg_shift) { 412 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 413 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1); 414 if (reg & WM8990_LDLO) { 415 printk(KERN_WARNING 416 "Cannot set as Output Mixer 1 LDLO Set\n"); 417 ret = -1; 418 } 419 break; 420 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 421 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2); 422 if (reg & WM8990_RDRO) { 423 printk(KERN_WARNING 424 "Cannot set as Output Mixer 2 RDRO Set\n"); 425 ret = -1; 426 } 427 break; 428 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 429 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 430 if (reg & WM8990_LDSPK) { 431 printk(KERN_WARNING 432 "Cannot set as Speaker Mixer LDSPK Set\n"); 433 ret = -1; 434 } 435 break; 436 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 437 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 438 if (reg & WM8990_RDSPK) { 439 printk(KERN_WARNING 440 "Cannot set as Speaker Mixer RDSPK Set\n"); 441 ret = -1; 442 } 443 break; 444 } 445 446 return ret; 447 } 448 449 /* INMIX dB values */ 450 static const unsigned int in_mix_tlv[] = { 451 TLV_DB_RANGE_HEAD(1), 452 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0), 453 }; 454 455 /* Left In PGA Connections */ 456 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 457 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 458 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 459 }; 460 461 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 462 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 463 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 464 }; 465 466 /* Right In PGA Connections */ 467 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 468 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 469 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 470 }; 471 472 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 473 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 474 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 475 }; 476 477 /* INMIXL */ 478 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 479 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 480 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 481 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 482 7, 0, in_mix_tlv), 483 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 484 1, 0), 485 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 486 1, 0), 487 }; 488 489 /* INMIXR */ 490 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 491 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 492 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 493 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 494 7, 0, in_mix_tlv), 495 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 496 1, 0), 497 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 498 1, 0), 499 }; 500 501 /* AINLMUX */ 502 static const char *wm8990_ainlmux[] = 503 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 504 505 static const struct soc_enum wm8990_ainlmux_enum = 506 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 507 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 508 509 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 510 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 511 512 /* DIFFINL */ 513 514 /* AINRMUX */ 515 static const char *wm8990_ainrmux[] = 516 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 517 518 static const struct soc_enum wm8990_ainrmux_enum = 519 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 520 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 521 522 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 523 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 524 525 /* RXVOICE */ 526 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 527 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 528 WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 529 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 530 WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 531 }; 532 533 /* LOMIX */ 534 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 535 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 536 WM8990_LRBLO_BIT, 1, 0), 537 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 538 WM8990_LLBLO_BIT, 1, 0), 539 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 540 WM8990_LRI3LO_BIT, 1, 0), 541 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 542 WM8990_LLI3LO_BIT, 1, 0), 543 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 544 WM8990_LR12LO_BIT, 1, 0), 545 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 546 WM8990_LL12LO_BIT, 1, 0), 547 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 548 WM8990_LDLO_BIT, 1, 0), 549 }; 550 551 /* ROMIX */ 552 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 553 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 554 WM8990_RLBRO_BIT, 1, 0), 555 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 556 WM8990_RRBRO_BIT, 1, 0), 557 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 558 WM8990_RLI3RO_BIT, 1, 0), 559 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 560 WM8990_RRI3RO_BIT, 1, 0), 561 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 562 WM8990_RL12RO_BIT, 1, 0), 563 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 564 WM8990_RR12RO_BIT, 1, 0), 565 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 566 WM8990_RDRO_BIT, 1, 0), 567 }; 568 569 /* LONMIX */ 570 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 571 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 572 WM8990_LLOPGALON_BIT, 1, 0), 573 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 574 WM8990_LROPGALON_BIT, 1, 0), 575 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 576 WM8990_LOPLON_BIT, 1, 0), 577 }; 578 579 /* LOPMIX */ 580 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 581 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 582 WM8990_LR12LOP_BIT, 1, 0), 583 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 584 WM8990_LL12LOP_BIT, 1, 0), 585 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 586 WM8990_LLOPGALOP_BIT, 1, 0), 587 }; 588 589 /* RONMIX */ 590 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 591 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 592 WM8990_RROPGARON_BIT, 1, 0), 593 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 594 WM8990_RLOPGARON_BIT, 1, 0), 595 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 596 WM8990_ROPRON_BIT, 1, 0), 597 }; 598 599 /* ROPMIX */ 600 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 601 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 602 WM8990_RL12ROP_BIT, 1, 0), 603 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 604 WM8990_RR12ROP_BIT, 1, 0), 605 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 606 WM8990_RROPGAROP_BIT, 1, 0), 607 }; 608 609 /* OUT3MIX */ 610 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 611 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 612 WM8990_LI4O3_BIT, 1, 0), 613 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 614 WM8990_LPGAO3_BIT, 1, 0), 615 }; 616 617 /* OUT4MIX */ 618 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 619 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 620 WM8990_RPGAO4_BIT, 1, 0), 621 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 622 WM8990_RI4O4_BIT, 1, 0), 623 }; 624 625 /* SPKMIX */ 626 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 627 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 628 WM8990_LI2SPK_BIT, 1, 0), 629 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 630 WM8990_LB2SPK_BIT, 1, 0), 631 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 632 WM8990_LOPGASPK_BIT, 1, 0), 633 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 634 WM8990_LDSPK_BIT, 1, 0), 635 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 636 WM8990_RDSPK_BIT, 1, 0), 637 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 638 WM8990_ROPGASPK_BIT, 1, 0), 639 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 640 WM8990_RL12ROP_BIT, 1, 0), 641 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 642 WM8990_RI2SPK_BIT, 1, 0), 643 }; 644 645 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 646 /* Input Side */ 647 /* Input Lines */ 648 SND_SOC_DAPM_INPUT("LIN1"), 649 SND_SOC_DAPM_INPUT("LIN2"), 650 SND_SOC_DAPM_INPUT("LIN3"), 651 SND_SOC_DAPM_INPUT("LIN4/RXN"), 652 SND_SOC_DAPM_INPUT("RIN3"), 653 SND_SOC_DAPM_INPUT("RIN4/RXP"), 654 SND_SOC_DAPM_INPUT("RIN1"), 655 SND_SOC_DAPM_INPUT("RIN2"), 656 SND_SOC_DAPM_INPUT("Internal ADC Source"), 657 658 /* DACs */ 659 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 660 WM8990_ADCL_ENA_BIT, 0), 661 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 662 WM8990_ADCR_ENA_BIT, 0), 663 664 /* Input PGAs */ 665 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 666 0, &wm8990_dapm_lin12_pga_controls[0], 667 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 668 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 669 0, &wm8990_dapm_lin34_pga_controls[0], 670 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 671 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 672 0, &wm8990_dapm_rin12_pga_controls[0], 673 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 674 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 675 0, &wm8990_dapm_rin34_pga_controls[0], 676 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 677 678 /* INMIXL */ 679 SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0, 680 &wm8990_dapm_inmixl_controls[0], 681 ARRAY_SIZE(wm8990_dapm_inmixl_controls), 682 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 683 684 /* AINLMUX */ 685 SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0, 686 &wm8990_dapm_ainlmux_controls, inmixer_event, 687 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 688 689 /* INMIXR */ 690 SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0, 691 &wm8990_dapm_inmixr_controls[0], 692 ARRAY_SIZE(wm8990_dapm_inmixr_controls), 693 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 694 695 /* AINRMUX */ 696 SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0, 697 &wm8990_dapm_ainrmux_controls, inmixer_event, 698 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 699 700 /* Output Side */ 701 /* DACs */ 702 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 703 WM8990_DACL_ENA_BIT, 0), 704 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 705 WM8990_DACR_ENA_BIT, 0), 706 707 /* LOMIX */ 708 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 709 0, &wm8990_dapm_lomix_controls[0], 710 ARRAY_SIZE(wm8990_dapm_lomix_controls), 711 outmixer_event, SND_SOC_DAPM_PRE_REG), 712 713 /* LONMIX */ 714 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 715 &wm8990_dapm_lonmix_controls[0], 716 ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 717 718 /* LOPMIX */ 719 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 720 &wm8990_dapm_lopmix_controls[0], 721 ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 722 723 /* OUT3MIX */ 724 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 725 &wm8990_dapm_out3mix_controls[0], 726 ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 727 728 /* SPKMIX */ 729 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 730 &wm8990_dapm_spkmix_controls[0], 731 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 732 SND_SOC_DAPM_PRE_REG), 733 734 /* OUT4MIX */ 735 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 736 &wm8990_dapm_out4mix_controls[0], 737 ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 738 739 /* ROPMIX */ 740 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 741 &wm8990_dapm_ropmix_controls[0], 742 ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 743 744 /* RONMIX */ 745 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 746 &wm8990_dapm_ronmix_controls[0], 747 ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 748 749 /* ROMIX */ 750 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 751 0, &wm8990_dapm_romix_controls[0], 752 ARRAY_SIZE(wm8990_dapm_romix_controls), 753 outmixer_event, SND_SOC_DAPM_PRE_REG), 754 755 /* LOUT PGA */ 756 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 757 NULL, 0), 758 759 /* ROUT PGA */ 760 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 761 NULL, 0), 762 763 /* LOPGA */ 764 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 765 NULL, 0), 766 767 /* ROPGA */ 768 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 769 NULL, 0), 770 771 /* MICBIAS */ 772 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1, 773 WM8990_MICBIAS_ENA_BIT, 0), 774 775 SND_SOC_DAPM_OUTPUT("LON"), 776 SND_SOC_DAPM_OUTPUT("LOP"), 777 SND_SOC_DAPM_OUTPUT("OUT3"), 778 SND_SOC_DAPM_OUTPUT("LOUT"), 779 SND_SOC_DAPM_OUTPUT("SPKN"), 780 SND_SOC_DAPM_OUTPUT("SPKP"), 781 SND_SOC_DAPM_OUTPUT("ROUT"), 782 SND_SOC_DAPM_OUTPUT("OUT4"), 783 SND_SOC_DAPM_OUTPUT("ROP"), 784 SND_SOC_DAPM_OUTPUT("RON"), 785 786 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 787 }; 788 789 static const struct snd_soc_dapm_route audio_map[] = { 790 /* Make DACs turn on when playing even if not mixed into any outputs */ 791 {"Internal DAC Sink", NULL, "Left DAC"}, 792 {"Internal DAC Sink", NULL, "Right DAC"}, 793 794 /* Make ADCs turn on when recording even if not mixed from any inputs */ 795 {"Left ADC", NULL, "Internal ADC Source"}, 796 {"Right ADC", NULL, "Internal ADC Source"}, 797 798 /* Input Side */ 799 /* LIN12 PGA */ 800 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 801 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 802 /* LIN34 PGA */ 803 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 804 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 805 /* INMIXL */ 806 {"INMIXL", "Record Left Volume", "LOMIX"}, 807 {"INMIXL", "LIN2 Volume", "LIN2"}, 808 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 809 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 810 /* AINLMUX */ 811 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 812 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 813 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 814 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"}, 815 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"}, 816 /* ADC */ 817 {"Left ADC", NULL, "AINLMUX"}, 818 819 /* RIN12 PGA */ 820 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 821 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 822 /* RIN34 PGA */ 823 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 824 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 825 /* INMIXL */ 826 {"INMIXR", "Record Right Volume", "ROMIX"}, 827 {"INMIXR", "RIN2 Volume", "RIN2"}, 828 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 829 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 830 /* AINRMUX */ 831 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 832 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 833 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 834 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"}, 835 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"}, 836 /* ADC */ 837 {"Right ADC", NULL, "AINRMUX"}, 838 839 /* LOMIX */ 840 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 841 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 842 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 843 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 844 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 845 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 846 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 847 848 /* ROMIX */ 849 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 850 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 851 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 852 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 853 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 854 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 855 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 856 857 /* SPKMIX */ 858 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 859 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 860 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 861 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 862 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 863 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 864 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 865 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 866 867 /* LONMIX */ 868 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 869 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 870 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 871 872 /* LOPMIX */ 873 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 874 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 875 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 876 877 /* OUT3MIX */ 878 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 879 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 880 881 /* OUT4MIX */ 882 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 883 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 884 885 /* RONMIX */ 886 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 887 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 888 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 889 890 /* ROPMIX */ 891 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 892 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 893 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 894 895 /* Out Mixer PGAs */ 896 {"LOPGA", NULL, "LOMIX"}, 897 {"ROPGA", NULL, "ROMIX"}, 898 899 {"LOUT PGA", NULL, "LOMIX"}, 900 {"ROUT PGA", NULL, "ROMIX"}, 901 902 /* Output Pins */ 903 {"LON", NULL, "LONMIX"}, 904 {"LOP", NULL, "LOPMIX"}, 905 {"OUT3", NULL, "OUT3MIX"}, 906 {"LOUT", NULL, "LOUT PGA"}, 907 {"SPKN", NULL, "SPKMIX"}, 908 {"ROUT", NULL, "ROUT PGA"}, 909 {"OUT4", NULL, "OUT4MIX"}, 910 {"ROP", NULL, "ROPMIX"}, 911 {"RON", NULL, "RONMIX"}, 912 }; 913 914 static int wm8990_add_widgets(struct snd_soc_codec *codec) 915 { 916 struct snd_soc_dapm_context *dapm = &codec->dapm; 917 918 snd_soc_dapm_new_controls(dapm, wm8990_dapm_widgets, 919 ARRAY_SIZE(wm8990_dapm_widgets)); 920 /* set up the WM8990 audio map */ 921 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); 922 923 return 0; 924 } 925 926 /* PLL divisors */ 927 struct _pll_div { 928 u32 div2; 929 u32 n; 930 u32 k; 931 }; 932 933 /* The size in bits of the pll divide multiplied by 10 934 * to allow rounding later */ 935 #define FIXED_PLL_SIZE ((1 << 16) * 10) 936 937 static void pll_factors(struct _pll_div *pll_div, unsigned int target, 938 unsigned int source) 939 { 940 u64 Kpart; 941 unsigned int K, Ndiv, Nmod; 942 943 944 Ndiv = target / source; 945 if (Ndiv < 6) { 946 source >>= 1; 947 pll_div->div2 = 1; 948 Ndiv = target / source; 949 } else 950 pll_div->div2 = 0; 951 952 if ((Ndiv < 6) || (Ndiv > 12)) 953 printk(KERN_WARNING 954 "WM8990 N value outwith recommended range! N = %u\n", Ndiv); 955 956 pll_div->n = Ndiv; 957 Nmod = target % source; 958 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 959 960 do_div(Kpart, source); 961 962 K = Kpart & 0xFFFFFFFF; 963 964 /* Check if we need to round */ 965 if ((K % 10) >= 5) 966 K += 5; 967 968 /* Move down to proper range now rounding is done */ 969 K /= 10; 970 971 pll_div->k = K; 972 } 973 974 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 975 int source, unsigned int freq_in, unsigned int freq_out) 976 { 977 u16 reg; 978 struct snd_soc_codec *codec = codec_dai->codec; 979 struct _pll_div pll_div; 980 981 if (freq_in && freq_out) { 982 pll_factors(&pll_div, freq_out * 4, freq_in); 983 984 /* Turn on PLL */ 985 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 986 reg |= WM8990_PLL_ENA; 987 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 988 989 /* sysclk comes from PLL */ 990 reg = snd_soc_read(codec, WM8990_CLOCKING_2); 991 snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 992 993 /* set up N , fractional mode and pre-divisor if necessary */ 994 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 995 (pll_div.div2?WM8990_PRESCALE:0)); 996 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 997 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 998 } else { 999 /* Turn on PLL */ 1000 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 1001 reg &= ~WM8990_PLL_ENA; 1002 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1003 } 1004 return 0; 1005 } 1006 1007 /* 1008 * Clock after PLL and dividers 1009 */ 1010 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1011 int clk_id, unsigned int freq, int dir) 1012 { 1013 struct snd_soc_codec *codec = codec_dai->codec; 1014 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec); 1015 1016 wm8990->sysclk = freq; 1017 return 0; 1018 } 1019 1020 /* 1021 * Set's ADC and Voice DAC format. 1022 */ 1023 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 1024 unsigned int fmt) 1025 { 1026 struct snd_soc_codec *codec = codec_dai->codec; 1027 u16 audio1, audio3; 1028 1029 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1030 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3); 1031 1032 /* set master/slave audio interface */ 1033 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1034 case SND_SOC_DAIFMT_CBS_CFS: 1035 audio3 &= ~WM8990_AIF_MSTR1; 1036 break; 1037 case SND_SOC_DAIFMT_CBM_CFM: 1038 audio3 |= WM8990_AIF_MSTR1; 1039 break; 1040 default: 1041 return -EINVAL; 1042 } 1043 1044 audio1 &= ~WM8990_AIF_FMT_MASK; 1045 1046 /* interface format */ 1047 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1048 case SND_SOC_DAIFMT_I2S: 1049 audio1 |= WM8990_AIF_TMF_I2S; 1050 audio1 &= ~WM8990_AIF_LRCLK_INV; 1051 break; 1052 case SND_SOC_DAIFMT_RIGHT_J: 1053 audio1 |= WM8990_AIF_TMF_RIGHTJ; 1054 audio1 &= ~WM8990_AIF_LRCLK_INV; 1055 break; 1056 case SND_SOC_DAIFMT_LEFT_J: 1057 audio1 |= WM8990_AIF_TMF_LEFTJ; 1058 audio1 &= ~WM8990_AIF_LRCLK_INV; 1059 break; 1060 case SND_SOC_DAIFMT_DSP_A: 1061 audio1 |= WM8990_AIF_TMF_DSP; 1062 audio1 &= ~WM8990_AIF_LRCLK_INV; 1063 break; 1064 case SND_SOC_DAIFMT_DSP_B: 1065 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1066 break; 1067 default: 1068 return -EINVAL; 1069 } 1070 1071 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1072 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1073 return 0; 1074 } 1075 1076 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1077 int div_id, int div) 1078 { 1079 struct snd_soc_codec *codec = codec_dai->codec; 1080 u16 reg; 1081 1082 switch (div_id) { 1083 case WM8990_MCLK_DIV: 1084 reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1085 ~WM8990_MCLK_DIV_MASK; 1086 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1087 break; 1088 case WM8990_DACCLK_DIV: 1089 reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1090 ~WM8990_DAC_CLKDIV_MASK; 1091 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1092 break; 1093 case WM8990_ADCCLK_DIV: 1094 reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1095 ~WM8990_ADC_CLKDIV_MASK; 1096 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1097 break; 1098 case WM8990_BCLK_DIV: 1099 reg = snd_soc_read(codec, WM8990_CLOCKING_1) & 1100 ~WM8990_BCLK_DIV_MASK; 1101 snd_soc_write(codec, WM8990_CLOCKING_1, reg | div); 1102 break; 1103 default: 1104 return -EINVAL; 1105 } 1106 1107 return 0; 1108 } 1109 1110 /* 1111 * Set PCM DAI bit size and sample rate. 1112 */ 1113 static int wm8990_hw_params(struct snd_pcm_substream *substream, 1114 struct snd_pcm_hw_params *params, 1115 struct snd_soc_dai *dai) 1116 { 1117 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1118 struct snd_soc_codec *codec = rtd->codec; 1119 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1120 1121 audio1 &= ~WM8990_AIF_WL_MASK; 1122 /* bit size */ 1123 switch (params_format(params)) { 1124 case SNDRV_PCM_FORMAT_S16_LE: 1125 break; 1126 case SNDRV_PCM_FORMAT_S20_3LE: 1127 audio1 |= WM8990_AIF_WL_20BITS; 1128 break; 1129 case SNDRV_PCM_FORMAT_S24_LE: 1130 audio1 |= WM8990_AIF_WL_24BITS; 1131 break; 1132 case SNDRV_PCM_FORMAT_S32_LE: 1133 audio1 |= WM8990_AIF_WL_32BITS; 1134 break; 1135 } 1136 1137 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1138 return 0; 1139 } 1140 1141 static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1142 { 1143 struct snd_soc_codec *codec = dai->codec; 1144 u16 val; 1145 1146 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1147 1148 if (mute) 1149 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1150 else 1151 snd_soc_write(codec, WM8990_DAC_CTRL, val); 1152 1153 return 0; 1154 } 1155 1156 static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1157 enum snd_soc_bias_level level) 1158 { 1159 u16 val; 1160 1161 switch (level) { 1162 case SND_SOC_BIAS_ON: 1163 break; 1164 1165 case SND_SOC_BIAS_PREPARE: 1166 /* VMID=2*50k */ 1167 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) & 1168 ~WM8990_VMID_MODE_MASK; 1169 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1170 break; 1171 1172 case SND_SOC_BIAS_STANDBY: 1173 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1174 /* Enable all output discharge bits */ 1175 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1176 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1177 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1178 WM8990_DIS_ROUT); 1179 1180 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1181 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1182 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1183 WM8990_VMIDTOG); 1184 1185 /* Delay to allow output caps to discharge */ 1186 msleep(300); 1187 1188 /* Disable VMIDTOG */ 1189 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1190 WM8990_BUFDCOPEN | WM8990_POBCTRL); 1191 1192 /* disable all output discharge bits */ 1193 snd_soc_write(codec, WM8990_ANTIPOP1, 0); 1194 1195 /* Enable outputs */ 1196 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1197 1198 msleep(50); 1199 1200 /* Enable VMID at 2x50k */ 1201 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1202 1203 msleep(100); 1204 1205 /* Enable VREF */ 1206 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1207 1208 msleep(600); 1209 1210 /* Enable BUFIOEN */ 1211 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1212 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1213 WM8990_BUFIOEN); 1214 1215 /* Disable outputs */ 1216 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1217 1218 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1219 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1220 1221 /* Enable workaround for ADC clocking issue. */ 1222 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1223 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003); 1224 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1225 } 1226 1227 /* VMID=2*250k */ 1228 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) & 1229 ~WM8990_VMID_MODE_MASK; 1230 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1231 break; 1232 1233 case SND_SOC_BIAS_OFF: 1234 /* Enable POBCTRL and SOFT_ST */ 1235 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1236 WM8990_POBCTRL | WM8990_BUFIOEN); 1237 1238 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1239 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1240 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1241 WM8990_BUFIOEN); 1242 1243 /* mute DAC */ 1244 val = snd_soc_read(codec, WM8990_DAC_CTRL); 1245 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1246 1247 /* Enable any disabled outputs */ 1248 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1249 1250 /* Disable VMID */ 1251 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1252 1253 msleep(300); 1254 1255 /* Enable all output discharge bits */ 1256 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1257 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1258 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1259 WM8990_DIS_ROUT); 1260 1261 /* Disable VREF */ 1262 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1263 1264 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1265 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0); 1266 break; 1267 } 1268 1269 codec->dapm.bias_level = level; 1270 return 0; 1271 } 1272 1273 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1274 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1275 SNDRV_PCM_RATE_48000) 1276 1277 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1278 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1279 1280 /* 1281 * The WM8990 supports 2 different and mutually exclusive DAI 1282 * configurations. 1283 * 1284 * 1. ADC/DAC on Primary Interface 1285 * 2. ADC on Primary Interface/DAC on secondary 1286 */ 1287 static struct snd_soc_dai_ops wm8990_dai_ops = { 1288 .hw_params = wm8990_hw_params, 1289 .digital_mute = wm8990_mute, 1290 .set_fmt = wm8990_set_dai_fmt, 1291 .set_clkdiv = wm8990_set_dai_clkdiv, 1292 .set_pll = wm8990_set_dai_pll, 1293 .set_sysclk = wm8990_set_dai_sysclk, 1294 }; 1295 1296 static struct snd_soc_dai_driver wm8990_dai = { 1297 /* ADC/DAC on primary */ 1298 .name = "wm8990-hifi", 1299 .playback = { 1300 .stream_name = "Playback", 1301 .channels_min = 1, 1302 .channels_max = 2, 1303 .rates = WM8990_RATES, 1304 .formats = WM8990_FORMATS,}, 1305 .capture = { 1306 .stream_name = "Capture", 1307 .channels_min = 1, 1308 .channels_max = 2, 1309 .rates = WM8990_RATES, 1310 .formats = WM8990_FORMATS,}, 1311 .ops = &wm8990_dai_ops, 1312 }; 1313 1314 static int wm8990_suspend(struct snd_soc_codec *codec, pm_message_t state) 1315 { 1316 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1317 return 0; 1318 } 1319 1320 static int wm8990_resume(struct snd_soc_codec *codec) 1321 { 1322 int i; 1323 u8 data[2]; 1324 u16 *cache = codec->reg_cache; 1325 1326 /* Sync reg_cache with the hardware */ 1327 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) { 1328 if (i + 1 == WM8990_RESET) 1329 continue; 1330 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); 1331 data[1] = cache[i] & 0x00ff; 1332 codec->hw_write(codec->control_data, data, 2); 1333 } 1334 1335 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1336 return 0; 1337 } 1338 1339 /* 1340 * initialise the WM8990 driver 1341 * register the mixer and dsp interfaces with the kernel 1342 */ 1343 static int wm8990_probe(struct snd_soc_codec *codec) 1344 { 1345 int ret; 1346 u16 reg; 1347 1348 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1349 if (ret < 0) { 1350 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret); 1351 return ret; 1352 } 1353 1354 wm8990_reset(codec); 1355 1356 /* charge output caps */ 1357 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1358 1359 reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4); 1360 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1361 1362 reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) & 1363 ~WM8990_GPIO1_SEL_MASK; 1364 snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1365 1366 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 1367 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1368 1369 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1370 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1371 1372 snd_soc_add_controls(codec, wm8990_snd_controls, 1373 ARRAY_SIZE(wm8990_snd_controls)); 1374 wm8990_add_widgets(codec); 1375 1376 return 0; 1377 } 1378 1379 /* power down chip */ 1380 static int wm8990_remove(struct snd_soc_codec *codec) 1381 { 1382 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1383 return 0; 1384 } 1385 1386 static struct snd_soc_codec_driver soc_codec_dev_wm8990 = { 1387 .probe = wm8990_probe, 1388 .remove = wm8990_remove, 1389 .suspend = wm8990_suspend, 1390 .resume = wm8990_resume, 1391 .set_bias_level = wm8990_set_bias_level, 1392 .reg_cache_size = ARRAY_SIZE(wm8990_reg), 1393 .reg_word_size = sizeof(u16), 1394 .reg_cache_default = wm8990_reg, 1395 }; 1396 1397 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1398 static __devinit int wm8990_i2c_probe(struct i2c_client *i2c, 1399 const struct i2c_device_id *id) 1400 { 1401 struct wm8990_priv *wm8990; 1402 int ret; 1403 1404 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL); 1405 if (wm8990 == NULL) 1406 return -ENOMEM; 1407 1408 i2c_set_clientdata(i2c, wm8990); 1409 1410 ret = snd_soc_register_codec(&i2c->dev, 1411 &soc_codec_dev_wm8990, &wm8990_dai, 1); 1412 if (ret < 0) 1413 kfree(wm8990); 1414 return ret; 1415 } 1416 1417 static __devexit int wm8990_i2c_remove(struct i2c_client *client) 1418 { 1419 snd_soc_unregister_codec(&client->dev); 1420 kfree(i2c_get_clientdata(client)); 1421 return 0; 1422 } 1423 1424 static const struct i2c_device_id wm8990_i2c_id[] = { 1425 { "wm8990", 0 }, 1426 { } 1427 }; 1428 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1429 1430 static struct i2c_driver wm8990_i2c_driver = { 1431 .driver = { 1432 .name = "wm8990-codec", 1433 .owner = THIS_MODULE, 1434 }, 1435 .probe = wm8990_i2c_probe, 1436 .remove = __devexit_p(wm8990_i2c_remove), 1437 .id_table = wm8990_i2c_id, 1438 }; 1439 #endif 1440 1441 static int __init wm8990_modinit(void) 1442 { 1443 int ret = 0; 1444 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1445 ret = i2c_add_driver(&wm8990_i2c_driver); 1446 if (ret != 0) { 1447 printk(KERN_ERR "Failed to register wm8990 I2C driver: %d\n", 1448 ret); 1449 } 1450 #endif 1451 return ret; 1452 } 1453 module_init(wm8990_modinit); 1454 1455 static void __exit wm8990_exit(void) 1456 { 1457 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1458 i2c_del_driver(&wm8990_i2c_driver); 1459 #endif 1460 } 1461 module_exit(wm8990_exit); 1462 1463 MODULE_DESCRIPTION("ASoC WM8990 driver"); 1464 MODULE_AUTHOR("Liam Girdwood"); 1465 MODULE_LICENSE("GPL"); 1466