1f10485e7SMark Brown /* 2f10485e7SMark Brown * wm8990.c -- WM8990 ALSA Soc Audio driver 3f10485e7SMark Brown * 4f10485e7SMark Brown * Copyright 2008 Wolfson Microelectronics PLC. 564ca0404SLiam Girdwood * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6f10485e7SMark Brown * 7f10485e7SMark Brown * This program is free software; you can redistribute it and/or modify it 8f10485e7SMark Brown * under the terms of the GNU General Public License as published by the 9f10485e7SMark Brown * Free Software Foundation; either version 2 of the License, or (at your 10f10485e7SMark Brown * option) any later version. 11f10485e7SMark Brown */ 12f10485e7SMark Brown 13f10485e7SMark Brown #include <linux/module.h> 14f10485e7SMark Brown #include <linux/moduleparam.h> 15f10485e7SMark Brown #include <linux/kernel.h> 16f10485e7SMark Brown #include <linux/init.h> 17f10485e7SMark Brown #include <linux/delay.h> 18f10485e7SMark Brown #include <linux/pm.h> 19f10485e7SMark Brown #include <linux/i2c.h> 20f10485e7SMark Brown #include <linux/platform_device.h> 215a0e3ad6STejun Heo #include <linux/slab.h> 22f10485e7SMark Brown #include <sound/core.h> 23f10485e7SMark Brown #include <sound/pcm.h> 24f10485e7SMark Brown #include <sound/pcm_params.h> 25f10485e7SMark Brown #include <sound/soc.h> 26f10485e7SMark Brown #include <sound/soc-dapm.h> 27f10485e7SMark Brown #include <sound/initval.h> 28f10485e7SMark Brown #include <sound/tlv.h> 29f10485e7SMark Brown #include <asm/div64.h> 30f10485e7SMark Brown 31f10485e7SMark Brown #include "wm8990.h" 32f10485e7SMark Brown 33f10485e7SMark Brown /* codec private data */ 34f10485e7SMark Brown struct wm8990_priv { 35*f0fba2adSLiam Girdwood enum snd_soc_control_type control_type; 36*f0fba2adSLiam Girdwood void *control_data; 37f10485e7SMark Brown unsigned int sysclk; 38f10485e7SMark Brown unsigned int pcmclk; 39f10485e7SMark Brown }; 40f10485e7SMark Brown 41f10485e7SMark Brown /* 42f10485e7SMark Brown * wm8990 register cache. Note that register 0 is not included in the 43f10485e7SMark Brown * cache. 44f10485e7SMark Brown */ 45f10485e7SMark Brown static const u16 wm8990_reg[] = { 46f10485e7SMark Brown 0x8990, /* R0 - Reset */ 47f10485e7SMark Brown 0x0000, /* R1 - Power Management (1) */ 48f10485e7SMark Brown 0x6000, /* R2 - Power Management (2) */ 49f10485e7SMark Brown 0x0000, /* R3 - Power Management (3) */ 50f10485e7SMark Brown 0x4050, /* R4 - Audio Interface (1) */ 51f10485e7SMark Brown 0x4000, /* R5 - Audio Interface (2) */ 52f10485e7SMark Brown 0x01C8, /* R6 - Clocking (1) */ 53f10485e7SMark Brown 0x0000, /* R7 - Clocking (2) */ 54f10485e7SMark Brown 0x0040, /* R8 - Audio Interface (3) */ 55f10485e7SMark Brown 0x0040, /* R9 - Audio Interface (4) */ 56f10485e7SMark Brown 0x0004, /* R10 - DAC CTRL */ 57f10485e7SMark Brown 0x00C0, /* R11 - Left DAC Digital Volume */ 58f10485e7SMark Brown 0x00C0, /* R12 - Right DAC Digital Volume */ 59f10485e7SMark Brown 0x0000, /* R13 - Digital Side Tone */ 60f10485e7SMark Brown 0x0100, /* R14 - ADC CTRL */ 61f10485e7SMark Brown 0x00C0, /* R15 - Left ADC Digital Volume */ 62f10485e7SMark Brown 0x00C0, /* R16 - Right ADC Digital Volume */ 63f10485e7SMark Brown 0x0000, /* R17 */ 64f10485e7SMark Brown 0x0000, /* R18 - GPIO CTRL 1 */ 65f10485e7SMark Brown 0x1000, /* R19 - GPIO1 & GPIO2 */ 66f10485e7SMark Brown 0x1010, /* R20 - GPIO3 & GPIO4 */ 67f10485e7SMark Brown 0x1010, /* R21 - GPIO5 & GPIO6 */ 68f10485e7SMark Brown 0x8000, /* R22 - GPIOCTRL 2 */ 69f10485e7SMark Brown 0x0800, /* R23 - GPIO_POL */ 70f10485e7SMark Brown 0x008B, /* R24 - Left Line Input 1&2 Volume */ 71f10485e7SMark Brown 0x008B, /* R25 - Left Line Input 3&4 Volume */ 72f10485e7SMark Brown 0x008B, /* R26 - Right Line Input 1&2 Volume */ 73f10485e7SMark Brown 0x008B, /* R27 - Right Line Input 3&4 Volume */ 74f10485e7SMark Brown 0x0000, /* R28 - Left Output Volume */ 75f10485e7SMark Brown 0x0000, /* R29 - Right Output Volume */ 76f10485e7SMark Brown 0x0066, /* R30 - Line Outputs Volume */ 77f10485e7SMark Brown 0x0022, /* R31 - Out3/4 Volume */ 78f10485e7SMark Brown 0x0079, /* R32 - Left OPGA Volume */ 79f10485e7SMark Brown 0x0079, /* R33 - Right OPGA Volume */ 80f10485e7SMark Brown 0x0003, /* R34 - Speaker Volume */ 81f10485e7SMark Brown 0x0003, /* R35 - ClassD1 */ 82f10485e7SMark Brown 0x0000, /* R36 */ 83f10485e7SMark Brown 0x0100, /* R37 - ClassD3 */ 8497bb8129SMark Brown 0x0079, /* R38 - ClassD4 */ 85f10485e7SMark Brown 0x0000, /* R39 - Input Mixer1 */ 86f10485e7SMark Brown 0x0000, /* R40 - Input Mixer2 */ 87f10485e7SMark Brown 0x0000, /* R41 - Input Mixer3 */ 88f10485e7SMark Brown 0x0000, /* R42 - Input Mixer4 */ 89f10485e7SMark Brown 0x0000, /* R43 - Input Mixer5 */ 90f10485e7SMark Brown 0x0000, /* R44 - Input Mixer6 */ 91f10485e7SMark Brown 0x0000, /* R45 - Output Mixer1 */ 92f10485e7SMark Brown 0x0000, /* R46 - Output Mixer2 */ 93f10485e7SMark Brown 0x0000, /* R47 - Output Mixer3 */ 94f10485e7SMark Brown 0x0000, /* R48 - Output Mixer4 */ 95f10485e7SMark Brown 0x0000, /* R49 - Output Mixer5 */ 96f10485e7SMark Brown 0x0000, /* R50 - Output Mixer6 */ 97f10485e7SMark Brown 0x0180, /* R51 - Out3/4 Mixer */ 98f10485e7SMark Brown 0x0000, /* R52 - Line Mixer1 */ 99f10485e7SMark Brown 0x0000, /* R53 - Line Mixer2 */ 100f10485e7SMark Brown 0x0000, /* R54 - Speaker Mixer */ 101f10485e7SMark Brown 0x0000, /* R55 - Additional Control */ 102f10485e7SMark Brown 0x0000, /* R56 - AntiPOP1 */ 103f10485e7SMark Brown 0x0000, /* R57 - AntiPOP2 */ 104f10485e7SMark Brown 0x0000, /* R58 - MICBIAS */ 105f10485e7SMark Brown 0x0000, /* R59 */ 106f10485e7SMark Brown 0x0008, /* R60 - PLL1 */ 107f10485e7SMark Brown 0x0031, /* R61 - PLL2 */ 108f10485e7SMark Brown 0x0026, /* R62 - PLL3 */ 109ba533e95SMark Brown 0x0000, /* R63 - Driver internal */ 110f10485e7SMark Brown }; 111f10485e7SMark Brown 1128d50e447SMark Brown #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0) 113f10485e7SMark Brown 114021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); 115f10485e7SMark Brown 116021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); 117f10485e7SMark Brown 118021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0); 119f10485e7SMark Brown 120021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); 121f10485e7SMark Brown 122021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); 123f10485e7SMark Brown 124021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); 125f10485e7SMark Brown 126021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); 127f10485e7SMark Brown 128021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); 129f10485e7SMark Brown 130f10485e7SMark Brown static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 131f10485e7SMark Brown struct snd_ctl_elem_value *ucontrol) 132f10485e7SMark Brown { 133f10485e7SMark Brown struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 134397d5aeeSJarkko Nikula struct soc_mixer_control *mc = 135397d5aeeSJarkko Nikula (struct soc_mixer_control *)kcontrol->private_value; 136397d5aeeSJarkko Nikula int reg = mc->reg; 137f10485e7SMark Brown int ret; 138f10485e7SMark Brown u16 val; 139f10485e7SMark Brown 140f10485e7SMark Brown ret = snd_soc_put_volsw(kcontrol, ucontrol); 141f10485e7SMark Brown if (ret < 0) 142f10485e7SMark Brown return ret; 143f10485e7SMark Brown 144f10485e7SMark Brown /* now hit the volume update bits (always bit 8) */ 1458d50e447SMark Brown val = snd_soc_read(codec, reg); 1468d50e447SMark Brown return snd_soc_write(codec, reg, val | 0x0100); 147f10485e7SMark Brown } 148f10485e7SMark Brown 149f10485e7SMark Brown #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 150f10485e7SMark Brown tlv_array) {\ 151f10485e7SMark Brown .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 152f10485e7SMark Brown .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 153f10485e7SMark Brown SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 154f10485e7SMark Brown .tlv.p = (tlv_array), \ 155f10485e7SMark Brown .info = snd_soc_info_volsw, \ 156f10485e7SMark Brown .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ 157f10485e7SMark Brown .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 158f10485e7SMark Brown 159f10485e7SMark Brown 160f10485e7SMark Brown static const char *wm8990_digital_sidetone[] = 161f10485e7SMark Brown {"None", "Left ADC", "Right ADC", "Reserved"}; 162f10485e7SMark Brown 163f10485e7SMark Brown static const struct soc_enum wm8990_left_digital_sidetone_enum = 164f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 165f10485e7SMark Brown WM8990_ADC_TO_DACL_SHIFT, 166f10485e7SMark Brown WM8990_ADC_TO_DACL_MASK, 167f10485e7SMark Brown wm8990_digital_sidetone); 168f10485e7SMark Brown 169f10485e7SMark Brown static const struct soc_enum wm8990_right_digital_sidetone_enum = 170f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 171f10485e7SMark Brown WM8990_ADC_TO_DACR_SHIFT, 172f10485e7SMark Brown WM8990_ADC_TO_DACR_MASK, 173f10485e7SMark Brown wm8990_digital_sidetone); 174f10485e7SMark Brown 175f10485e7SMark Brown static const char *wm8990_adcmode[] = 176f10485e7SMark Brown {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 177f10485e7SMark Brown 178f10485e7SMark Brown static const struct soc_enum wm8990_right_adcmode_enum = 179f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 180f10485e7SMark Brown WM8990_ADC_HPF_CUT_SHIFT, 181f10485e7SMark Brown WM8990_ADC_HPF_CUT_MASK, 182f10485e7SMark Brown wm8990_adcmode); 183f10485e7SMark Brown 184f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_snd_controls[] = { 185f10485e7SMark Brown /* INMIXL */ 186f10485e7SMark Brown SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 187f10485e7SMark Brown SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 188f10485e7SMark Brown /* INMIXR */ 189f10485e7SMark Brown SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 190f10485e7SMark Brown SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 191f10485e7SMark Brown 192f10485e7SMark Brown /* LOMIX */ 193f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 194f10485e7SMark Brown WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 195f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 196f10485e7SMark Brown WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 197f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 198f10485e7SMark Brown WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 199f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 200f10485e7SMark Brown WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 201f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 202f10485e7SMark Brown WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 203f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 204f10485e7SMark Brown WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 205f10485e7SMark Brown 206f10485e7SMark Brown /* ROMIX */ 207f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 208f10485e7SMark Brown WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 209f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 210f10485e7SMark Brown WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 211f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 212f10485e7SMark Brown WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 213f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 214f10485e7SMark Brown WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 215f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 216f10485e7SMark Brown WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 217f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 218f10485e7SMark Brown WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 219f10485e7SMark Brown 220f10485e7SMark Brown /* LOUT */ 221f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 222f10485e7SMark Brown WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 223f10485e7SMark Brown SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 224f10485e7SMark Brown 225f10485e7SMark Brown /* ROUT */ 226f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 227f10485e7SMark Brown WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 228f10485e7SMark Brown SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 229f10485e7SMark Brown 230f10485e7SMark Brown /* LOPGA */ 231f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 232f10485e7SMark Brown WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 233f10485e7SMark Brown SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 234f10485e7SMark Brown WM8990_LOPGAZC_BIT, 1, 0), 235f10485e7SMark Brown 236f10485e7SMark Brown /* ROPGA */ 237f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 238f10485e7SMark Brown WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 239f10485e7SMark Brown SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 240f10485e7SMark Brown WM8990_ROPGAZC_BIT, 1, 0), 241f10485e7SMark Brown 242f10485e7SMark Brown SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 243f10485e7SMark Brown WM8990_LONMUTE_BIT, 1, 0), 244f10485e7SMark Brown SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 245f10485e7SMark Brown WM8990_LOPMUTE_BIT, 1, 0), 246f10485e7SMark Brown SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 247f10485e7SMark Brown WM8990_LOATTN_BIT, 1, 0), 248f10485e7SMark Brown SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 249f10485e7SMark Brown WM8990_RONMUTE_BIT, 1, 0), 250f10485e7SMark Brown SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 251f10485e7SMark Brown WM8990_ROPMUTE_BIT, 1, 0), 252f10485e7SMark Brown SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 253f10485e7SMark Brown WM8990_ROATTN_BIT, 1, 0), 254f10485e7SMark Brown 255f10485e7SMark Brown SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 256f10485e7SMark Brown WM8990_OUT3MUTE_BIT, 1, 0), 257f10485e7SMark Brown SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 258f10485e7SMark Brown WM8990_OUT3ATTN_BIT, 1, 0), 259f10485e7SMark Brown 260f10485e7SMark Brown SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 261f10485e7SMark Brown WM8990_OUT4MUTE_BIT, 1, 0), 262f10485e7SMark Brown SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 263f10485e7SMark Brown WM8990_OUT4ATTN_BIT, 1, 0), 264f10485e7SMark Brown 265f10485e7SMark Brown SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 266f10485e7SMark Brown WM8990_CDMODE_BIT, 1, 0), 267f10485e7SMark Brown 268f10485e7SMark Brown SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 26997bb8129SMark Brown WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 270f10485e7SMark Brown SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 271f10485e7SMark Brown WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 272f10485e7SMark Brown SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 273f10485e7SMark Brown WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 27497bb8129SMark Brown SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 27597bb8129SMark Brown WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 27697bb8129SMark Brown SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 27797bb8129SMark Brown WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 278f10485e7SMark Brown 279f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 280f10485e7SMark Brown WM8990_LEFT_DAC_DIGITAL_VOLUME, 281f10485e7SMark Brown WM8990_DACL_VOL_SHIFT, 282f10485e7SMark Brown WM8990_DACL_VOL_MASK, 283f10485e7SMark Brown 0, 284f10485e7SMark Brown out_dac_tlv), 285f10485e7SMark Brown 286f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 287f10485e7SMark Brown WM8990_RIGHT_DAC_DIGITAL_VOLUME, 288f10485e7SMark Brown WM8990_DACR_VOL_SHIFT, 289f10485e7SMark Brown WM8990_DACR_VOL_MASK, 290f10485e7SMark Brown 0, 291f10485e7SMark Brown out_dac_tlv), 292f10485e7SMark Brown 293f10485e7SMark Brown SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 294f10485e7SMark Brown SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 295f10485e7SMark Brown 296f10485e7SMark Brown SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 297f10485e7SMark Brown WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 298f10485e7SMark Brown out_sidetone_tlv), 299f10485e7SMark Brown SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 300f10485e7SMark Brown WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 301f10485e7SMark Brown out_sidetone_tlv), 302f10485e7SMark Brown 303f10485e7SMark Brown SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 304f10485e7SMark Brown WM8990_ADC_HPF_ENA_BIT, 1, 0), 305f10485e7SMark Brown 306f10485e7SMark Brown SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 307f10485e7SMark Brown 308f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 309f10485e7SMark Brown WM8990_LEFT_ADC_DIGITAL_VOLUME, 310f10485e7SMark Brown WM8990_ADCL_VOL_SHIFT, 311f10485e7SMark Brown WM8990_ADCL_VOL_MASK, 312f10485e7SMark Brown 0, 313f10485e7SMark Brown in_adc_tlv), 314f10485e7SMark Brown 315f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 316f10485e7SMark Brown WM8990_RIGHT_ADC_DIGITAL_VOLUME, 317f10485e7SMark Brown WM8990_ADCR_VOL_SHIFT, 318f10485e7SMark Brown WM8990_ADCR_VOL_MASK, 319f10485e7SMark Brown 0, 320f10485e7SMark Brown in_adc_tlv), 321f10485e7SMark Brown 322f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 323f10485e7SMark Brown WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 324f10485e7SMark Brown WM8990_LIN12VOL_SHIFT, 325f10485e7SMark Brown WM8990_LIN12VOL_MASK, 326f10485e7SMark Brown 0, 327f10485e7SMark Brown in_pga_tlv), 328f10485e7SMark Brown 329f10485e7SMark Brown SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 330f10485e7SMark Brown WM8990_LI12ZC_BIT, 1, 0), 331f10485e7SMark Brown 332f10485e7SMark Brown SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 333f10485e7SMark Brown WM8990_LI12MUTE_BIT, 1, 0), 334f10485e7SMark Brown 335f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 336f10485e7SMark Brown WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 337f10485e7SMark Brown WM8990_LIN34VOL_SHIFT, 338f10485e7SMark Brown WM8990_LIN34VOL_MASK, 339f10485e7SMark Brown 0, 340f10485e7SMark Brown in_pga_tlv), 341f10485e7SMark Brown 342f10485e7SMark Brown SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 343f10485e7SMark Brown WM8990_LI34ZC_BIT, 1, 0), 344f10485e7SMark Brown 345f10485e7SMark Brown SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 346f10485e7SMark Brown WM8990_LI34MUTE_BIT, 1, 0), 347f10485e7SMark Brown 348f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 349f10485e7SMark Brown WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 350f10485e7SMark Brown WM8990_RIN12VOL_SHIFT, 351f10485e7SMark Brown WM8990_RIN12VOL_MASK, 352f10485e7SMark Brown 0, 353f10485e7SMark Brown in_pga_tlv), 354f10485e7SMark Brown 355f10485e7SMark Brown SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 356f10485e7SMark Brown WM8990_RI12ZC_BIT, 1, 0), 357f10485e7SMark Brown 358f10485e7SMark Brown SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 359f10485e7SMark Brown WM8990_RI12MUTE_BIT, 1, 0), 360f10485e7SMark Brown 361f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 362f10485e7SMark Brown WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 363f10485e7SMark Brown WM8990_RIN34VOL_SHIFT, 364f10485e7SMark Brown WM8990_RIN34VOL_MASK, 365f10485e7SMark Brown 0, 366f10485e7SMark Brown in_pga_tlv), 367f10485e7SMark Brown 368f10485e7SMark Brown SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 369f10485e7SMark Brown WM8990_RI34ZC_BIT, 1, 0), 370f10485e7SMark Brown 371f10485e7SMark Brown SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 372f10485e7SMark Brown WM8990_RI34MUTE_BIT, 1, 0), 373f10485e7SMark Brown 374f10485e7SMark Brown }; 375f10485e7SMark Brown 376f10485e7SMark Brown /* 377f10485e7SMark Brown * _DAPM_ Controls 378f10485e7SMark Brown */ 379f10485e7SMark Brown 380f10485e7SMark Brown static int inmixer_event(struct snd_soc_dapm_widget *w, 381f10485e7SMark Brown struct snd_kcontrol *kcontrol, int event) 382f10485e7SMark Brown { 383f10485e7SMark Brown u16 reg, fakepower; 384f10485e7SMark Brown 3858d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2); 3868d50e447SMark Brown fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS); 387f10485e7SMark Brown 388f10485e7SMark Brown if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 389f10485e7SMark Brown (1 << WM8990_AINLMUX_PWR_BIT))) { 390f10485e7SMark Brown reg |= WM8990_AINL_ENA; 391f10485e7SMark Brown } else { 392f10485e7SMark Brown reg &= ~WM8990_AINL_ENA; 393f10485e7SMark Brown } 394f10485e7SMark Brown 395f10485e7SMark Brown if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) | 396f10485e7SMark Brown (1 << WM8990_AINRMUX_PWR_BIT))) { 397f10485e7SMark Brown reg |= WM8990_AINR_ENA; 398f10485e7SMark Brown } else { 399f10485e7SMark Brown reg &= ~WM8990_AINL_ENA; 400f10485e7SMark Brown } 4018d50e447SMark Brown snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 402f10485e7SMark Brown 403f10485e7SMark Brown return 0; 404f10485e7SMark Brown } 405f10485e7SMark Brown 406f10485e7SMark Brown static int outmixer_event(struct snd_soc_dapm_widget *w, 407f10485e7SMark Brown struct snd_kcontrol *kcontrol, int event) 408f10485e7SMark Brown { 409f10485e7SMark Brown u32 reg_shift = kcontrol->private_value & 0xfff; 410f10485e7SMark Brown int ret = 0; 411f10485e7SMark Brown u16 reg; 412f10485e7SMark Brown 413f10485e7SMark Brown switch (reg_shift) { 414f10485e7SMark Brown case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 4158d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1); 416f10485e7SMark Brown if (reg & WM8990_LDLO) { 417f10485e7SMark Brown printk(KERN_WARNING 418f10485e7SMark Brown "Cannot set as Output Mixer 1 LDLO Set\n"); 419f10485e7SMark Brown ret = -1; 420f10485e7SMark Brown } 421f10485e7SMark Brown break; 422f10485e7SMark Brown case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 4238d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2); 424f10485e7SMark Brown if (reg & WM8990_RDRO) { 425f10485e7SMark Brown printk(KERN_WARNING 426f10485e7SMark Brown "Cannot set as Output Mixer 2 RDRO Set\n"); 427f10485e7SMark Brown ret = -1; 428f10485e7SMark Brown } 429f10485e7SMark Brown break; 430f10485e7SMark Brown case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 4318d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 432f10485e7SMark Brown if (reg & WM8990_LDSPK) { 433f10485e7SMark Brown printk(KERN_WARNING 434f10485e7SMark Brown "Cannot set as Speaker Mixer LDSPK Set\n"); 435f10485e7SMark Brown ret = -1; 436f10485e7SMark Brown } 437f10485e7SMark Brown break; 438f10485e7SMark Brown case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 4398d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 440f10485e7SMark Brown if (reg & WM8990_RDSPK) { 441f10485e7SMark Brown printk(KERN_WARNING 442f10485e7SMark Brown "Cannot set as Speaker Mixer RDSPK Set\n"); 443f10485e7SMark Brown ret = -1; 444f10485e7SMark Brown } 445f10485e7SMark Brown break; 446f10485e7SMark Brown } 447f10485e7SMark Brown 448f10485e7SMark Brown return ret; 449f10485e7SMark Brown } 450f10485e7SMark Brown 451f10485e7SMark Brown /* INMIX dB values */ 452f10485e7SMark Brown static const unsigned int in_mix_tlv[] = { 453f10485e7SMark Brown TLV_DB_RANGE_HEAD(1), 454021f80ccSMark Brown 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0), 455f10485e7SMark Brown }; 456f10485e7SMark Brown 457f10485e7SMark Brown /* Left In PGA Connections */ 458f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 459f10485e7SMark Brown SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 460f10485e7SMark Brown SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 461f10485e7SMark Brown }; 462f10485e7SMark Brown 463f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 464f10485e7SMark Brown SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 465f10485e7SMark Brown SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 466f10485e7SMark Brown }; 467f10485e7SMark Brown 468f10485e7SMark Brown /* Right In PGA Connections */ 469f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 470f10485e7SMark Brown SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 471f10485e7SMark Brown SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 472f10485e7SMark Brown }; 473f10485e7SMark Brown 474f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 475f10485e7SMark Brown SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 476f10485e7SMark Brown SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 477f10485e7SMark Brown }; 478f10485e7SMark Brown 479f10485e7SMark Brown /* INMIXL */ 480f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 481f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 482f10485e7SMark Brown WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 483f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 484f10485e7SMark Brown 7, 0, in_mix_tlv), 485f10485e7SMark Brown SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 486f10485e7SMark Brown 1, 0), 487f10485e7SMark Brown SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 488f10485e7SMark Brown 1, 0), 489f10485e7SMark Brown }; 490f10485e7SMark Brown 491f10485e7SMark Brown /* INMIXR */ 492f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 493f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 494f10485e7SMark Brown WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 495f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 496f10485e7SMark Brown 7, 0, in_mix_tlv), 497f10485e7SMark Brown SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 498f10485e7SMark Brown 1, 0), 499f10485e7SMark Brown SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 500f10485e7SMark Brown 1, 0), 501f10485e7SMark Brown }; 502f10485e7SMark Brown 503f10485e7SMark Brown /* AINLMUX */ 504f10485e7SMark Brown static const char *wm8990_ainlmux[] = 505f10485e7SMark Brown {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 506f10485e7SMark Brown 507f10485e7SMark Brown static const struct soc_enum wm8990_ainlmux_enum = 508f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 509f10485e7SMark Brown ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 510f10485e7SMark Brown 511f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 512f10485e7SMark Brown SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 513f10485e7SMark Brown 514f10485e7SMark Brown /* DIFFINL */ 515f10485e7SMark Brown 516f10485e7SMark Brown /* AINRMUX */ 517f10485e7SMark Brown static const char *wm8990_ainrmux[] = 518f10485e7SMark Brown {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 519f10485e7SMark Brown 520f10485e7SMark Brown static const struct soc_enum wm8990_ainrmux_enum = 521f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 522f10485e7SMark Brown ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 523f10485e7SMark Brown 524f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 525f10485e7SMark Brown SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 526f10485e7SMark Brown 527f10485e7SMark Brown /* RXVOICE */ 528f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 529f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 530f10485e7SMark Brown WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 531f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 532f10485e7SMark Brown WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 533f10485e7SMark Brown }; 534f10485e7SMark Brown 535f10485e7SMark Brown /* LOMIX */ 536f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 537f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 538f10485e7SMark Brown WM8990_LRBLO_BIT, 1, 0), 539f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 540f10485e7SMark Brown WM8990_LLBLO_BIT, 1, 0), 541f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 542f10485e7SMark Brown WM8990_LRI3LO_BIT, 1, 0), 543f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 544f10485e7SMark Brown WM8990_LLI3LO_BIT, 1, 0), 545f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 546f10485e7SMark Brown WM8990_LR12LO_BIT, 1, 0), 547f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 548f10485e7SMark Brown WM8990_LL12LO_BIT, 1, 0), 549f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 550f10485e7SMark Brown WM8990_LDLO_BIT, 1, 0), 551f10485e7SMark Brown }; 552f10485e7SMark Brown 553f10485e7SMark Brown /* ROMIX */ 554f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 555f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 556f10485e7SMark Brown WM8990_RLBRO_BIT, 1, 0), 557f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 558f10485e7SMark Brown WM8990_RRBRO_BIT, 1, 0), 559f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 560f10485e7SMark Brown WM8990_RLI3RO_BIT, 1, 0), 561f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 562f10485e7SMark Brown WM8990_RRI3RO_BIT, 1, 0), 563f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 564f10485e7SMark Brown WM8990_RL12RO_BIT, 1, 0), 565f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 566f10485e7SMark Brown WM8990_RR12RO_BIT, 1, 0), 567f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 568f10485e7SMark Brown WM8990_RDRO_BIT, 1, 0), 569f10485e7SMark Brown }; 570f10485e7SMark Brown 571f10485e7SMark Brown /* LONMIX */ 572f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 573f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 574f10485e7SMark Brown WM8990_LLOPGALON_BIT, 1, 0), 575f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 576f10485e7SMark Brown WM8990_LROPGALON_BIT, 1, 0), 577f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 578f10485e7SMark Brown WM8990_LOPLON_BIT, 1, 0), 579f10485e7SMark Brown }; 580f10485e7SMark Brown 581f10485e7SMark Brown /* LOPMIX */ 582f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 583f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 584f10485e7SMark Brown WM8990_LR12LOP_BIT, 1, 0), 585f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 586f10485e7SMark Brown WM8990_LL12LOP_BIT, 1, 0), 587f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 588f10485e7SMark Brown WM8990_LLOPGALOP_BIT, 1, 0), 589f10485e7SMark Brown }; 590f10485e7SMark Brown 591f10485e7SMark Brown /* RONMIX */ 592f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 593f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 594f10485e7SMark Brown WM8990_RROPGARON_BIT, 1, 0), 595f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 596f10485e7SMark Brown WM8990_RLOPGARON_BIT, 1, 0), 597f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 598f10485e7SMark Brown WM8990_ROPRON_BIT, 1, 0), 599f10485e7SMark Brown }; 600f10485e7SMark Brown 601f10485e7SMark Brown /* ROPMIX */ 602f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 603f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 604f10485e7SMark Brown WM8990_RL12ROP_BIT, 1, 0), 605f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 606f10485e7SMark Brown WM8990_RR12ROP_BIT, 1, 0), 607f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 608f10485e7SMark Brown WM8990_RROPGAROP_BIT, 1, 0), 609f10485e7SMark Brown }; 610f10485e7SMark Brown 611f10485e7SMark Brown /* OUT3MIX */ 612f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 613f10485e7SMark Brown SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 614f10485e7SMark Brown WM8990_LI4O3_BIT, 1, 0), 615f10485e7SMark Brown SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 616f10485e7SMark Brown WM8990_LPGAO3_BIT, 1, 0), 617f10485e7SMark Brown }; 618f10485e7SMark Brown 619f10485e7SMark Brown /* OUT4MIX */ 620f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 621f10485e7SMark Brown SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 622f10485e7SMark Brown WM8990_RPGAO4_BIT, 1, 0), 623f10485e7SMark Brown SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 624f10485e7SMark Brown WM8990_RI4O4_BIT, 1, 0), 625f10485e7SMark Brown }; 626f10485e7SMark Brown 627f10485e7SMark Brown /* SPKMIX */ 628f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 629f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 630f10485e7SMark Brown WM8990_LI2SPK_BIT, 1, 0), 631f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 632f10485e7SMark Brown WM8990_LB2SPK_BIT, 1, 0), 633f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 634f10485e7SMark Brown WM8990_LOPGASPK_BIT, 1, 0), 635f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 636f10485e7SMark Brown WM8990_LDSPK_BIT, 1, 0), 637f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 638f10485e7SMark Brown WM8990_RDSPK_BIT, 1, 0), 639f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 640f10485e7SMark Brown WM8990_ROPGASPK_BIT, 1, 0), 641f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 642f10485e7SMark Brown WM8990_RL12ROP_BIT, 1, 0), 643f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 644f10485e7SMark Brown WM8990_RI2SPK_BIT, 1, 0), 645f10485e7SMark Brown }; 646f10485e7SMark Brown 647f10485e7SMark Brown static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 648f10485e7SMark Brown /* Input Side */ 649f10485e7SMark Brown /* Input Lines */ 650f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN1"), 651f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN2"), 652f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN3"), 653f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN4/RXN"), 654f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN3"), 655f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN4/RXP"), 656f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN1"), 657f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN2"), 658f10485e7SMark Brown SND_SOC_DAPM_INPUT("Internal ADC Source"), 659f10485e7SMark Brown 660f10485e7SMark Brown /* DACs */ 661f10485e7SMark Brown SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 662f10485e7SMark Brown WM8990_ADCL_ENA_BIT, 0), 663f10485e7SMark Brown SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 664f10485e7SMark Brown WM8990_ADCR_ENA_BIT, 0), 665f10485e7SMark Brown 666f10485e7SMark Brown /* Input PGAs */ 667f10485e7SMark Brown SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 668f10485e7SMark Brown 0, &wm8990_dapm_lin12_pga_controls[0], 669f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 670f10485e7SMark Brown SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 671f10485e7SMark Brown 0, &wm8990_dapm_lin34_pga_controls[0], 672f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 673f10485e7SMark Brown SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 674f10485e7SMark Brown 0, &wm8990_dapm_rin12_pga_controls[0], 675f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 676f10485e7SMark Brown SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 677f10485e7SMark Brown 0, &wm8990_dapm_rin34_pga_controls[0], 678f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 679f10485e7SMark Brown 680f10485e7SMark Brown /* INMIXL */ 681f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0, 682f10485e7SMark Brown &wm8990_dapm_inmixl_controls[0], 683f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_inmixl_controls), 684f10485e7SMark Brown inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 685f10485e7SMark Brown 686f10485e7SMark Brown /* AINLMUX */ 68797a775c4SJinyoung Park SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0, 688f10485e7SMark Brown &wm8990_dapm_ainlmux_controls, inmixer_event, 689f10485e7SMark Brown SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 690f10485e7SMark Brown 691f10485e7SMark Brown /* INMIXR */ 692f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0, 693f10485e7SMark Brown &wm8990_dapm_inmixr_controls[0], 694f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_inmixr_controls), 695f10485e7SMark Brown inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 696f10485e7SMark Brown 697f10485e7SMark Brown /* AINRMUX */ 69897a775c4SJinyoung Park SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0, 699f10485e7SMark Brown &wm8990_dapm_ainrmux_controls, inmixer_event, 700f10485e7SMark Brown SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 701f10485e7SMark Brown 702f10485e7SMark Brown /* Output Side */ 703f10485e7SMark Brown /* DACs */ 704f10485e7SMark Brown SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 705f10485e7SMark Brown WM8990_DACL_ENA_BIT, 0), 706f10485e7SMark Brown SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 707f10485e7SMark Brown WM8990_DACR_ENA_BIT, 0), 708f10485e7SMark Brown 709f10485e7SMark Brown /* LOMIX */ 710f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 711f10485e7SMark Brown 0, &wm8990_dapm_lomix_controls[0], 712f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lomix_controls), 713f10485e7SMark Brown outmixer_event, SND_SOC_DAPM_PRE_REG), 714f10485e7SMark Brown 715f10485e7SMark Brown /* LONMIX */ 716f10485e7SMark Brown SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 717f10485e7SMark Brown &wm8990_dapm_lonmix_controls[0], 718f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 719f10485e7SMark Brown 720f10485e7SMark Brown /* LOPMIX */ 721f10485e7SMark Brown SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 722f10485e7SMark Brown &wm8990_dapm_lopmix_controls[0], 723f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 724f10485e7SMark Brown 725f10485e7SMark Brown /* OUT3MIX */ 726f10485e7SMark Brown SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 727f10485e7SMark Brown &wm8990_dapm_out3mix_controls[0], 728f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 729f10485e7SMark Brown 730f10485e7SMark Brown /* SPKMIX */ 731f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 732f10485e7SMark Brown &wm8990_dapm_spkmix_controls[0], 733f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 734f10485e7SMark Brown SND_SOC_DAPM_PRE_REG), 735f10485e7SMark Brown 736f10485e7SMark Brown /* OUT4MIX */ 737f10485e7SMark Brown SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 738f10485e7SMark Brown &wm8990_dapm_out4mix_controls[0], 739f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 740f10485e7SMark Brown 741f10485e7SMark Brown /* ROPMIX */ 742f10485e7SMark Brown SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 743f10485e7SMark Brown &wm8990_dapm_ropmix_controls[0], 744f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 745f10485e7SMark Brown 746f10485e7SMark Brown /* RONMIX */ 747f10485e7SMark Brown SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 748f10485e7SMark Brown &wm8990_dapm_ronmix_controls[0], 749f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 750f10485e7SMark Brown 751f10485e7SMark Brown /* ROMIX */ 752f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 753f10485e7SMark Brown 0, &wm8990_dapm_romix_controls[0], 754f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_romix_controls), 755f10485e7SMark Brown outmixer_event, SND_SOC_DAPM_PRE_REG), 756f10485e7SMark Brown 757f10485e7SMark Brown /* LOUT PGA */ 758f10485e7SMark Brown SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 759f10485e7SMark Brown NULL, 0), 760f10485e7SMark Brown 761f10485e7SMark Brown /* ROUT PGA */ 762f10485e7SMark Brown SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 763f10485e7SMark Brown NULL, 0), 764f10485e7SMark Brown 765f10485e7SMark Brown /* LOPGA */ 766f10485e7SMark Brown SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 767f10485e7SMark Brown NULL, 0), 768f10485e7SMark Brown 769f10485e7SMark Brown /* ROPGA */ 770f10485e7SMark Brown SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 771f10485e7SMark Brown NULL, 0), 772f10485e7SMark Brown 773f10485e7SMark Brown /* MICBIAS */ 774f10485e7SMark Brown SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1, 775f10485e7SMark Brown WM8990_MICBIAS_ENA_BIT, 0), 776f10485e7SMark Brown 777f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LON"), 778f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LOP"), 779f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("OUT3"), 780f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LOUT"), 781f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("SPKN"), 782f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("SPKP"), 783f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("ROUT"), 784f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("OUT4"), 785f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("ROP"), 786f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("RON"), 787f10485e7SMark Brown 788f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 789f10485e7SMark Brown }; 790f10485e7SMark Brown 791f10485e7SMark Brown static const struct snd_soc_dapm_route audio_map[] = { 792f10485e7SMark Brown /* Make DACs turn on when playing even if not mixed into any outputs */ 793f10485e7SMark Brown {"Internal DAC Sink", NULL, "Left DAC"}, 794f10485e7SMark Brown {"Internal DAC Sink", NULL, "Right DAC"}, 795f10485e7SMark Brown 796f10485e7SMark Brown /* Make ADCs turn on when recording even if not mixed from any inputs */ 797f10485e7SMark Brown {"Left ADC", NULL, "Internal ADC Source"}, 798f10485e7SMark Brown {"Right ADC", NULL, "Internal ADC Source"}, 799f10485e7SMark Brown 800f10485e7SMark Brown /* Input Side */ 801f10485e7SMark Brown /* LIN12 PGA */ 802f10485e7SMark Brown {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 803f10485e7SMark Brown {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 804f10485e7SMark Brown /* LIN34 PGA */ 805f10485e7SMark Brown {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 80697a775c4SJinyoung Park {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 807f10485e7SMark Brown /* INMIXL */ 808f10485e7SMark Brown {"INMIXL", "Record Left Volume", "LOMIX"}, 809f10485e7SMark Brown {"INMIXL", "LIN2 Volume", "LIN2"}, 810f10485e7SMark Brown {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 811f10485e7SMark Brown {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 81297a775c4SJinyoung Park /* AINLMUX */ 81397a775c4SJinyoung Park {"AINLMUX", "INMIXL Mix", "INMIXL"}, 81497a775c4SJinyoung Park {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 81597a775c4SJinyoung Park {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 81697a775c4SJinyoung Park {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"}, 81797a775c4SJinyoung Park {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"}, 818f10485e7SMark Brown /* ADC */ 81997a775c4SJinyoung Park {"Left ADC", NULL, "AINLMUX"}, 820f10485e7SMark Brown 821f10485e7SMark Brown /* RIN12 PGA */ 822f10485e7SMark Brown {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 823f10485e7SMark Brown {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 824f10485e7SMark Brown /* RIN34 PGA */ 825f10485e7SMark Brown {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 82697a775c4SJinyoung Park {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 827f10485e7SMark Brown /* INMIXL */ 828f10485e7SMark Brown {"INMIXR", "Record Right Volume", "ROMIX"}, 829f10485e7SMark Brown {"INMIXR", "RIN2 Volume", "RIN2"}, 830f10485e7SMark Brown {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 831f10485e7SMark Brown {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 83297a775c4SJinyoung Park /* AINRMUX */ 83397a775c4SJinyoung Park {"AINRMUX", "INMIXR Mix", "INMIXR"}, 83497a775c4SJinyoung Park {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 83597a775c4SJinyoung Park {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 83697a775c4SJinyoung Park {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"}, 83797a775c4SJinyoung Park {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"}, 838f10485e7SMark Brown /* ADC */ 83997a775c4SJinyoung Park {"Right ADC", NULL, "AINRMUX"}, 840f10485e7SMark Brown 841f10485e7SMark Brown /* LOMIX */ 842f10485e7SMark Brown {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 843f10485e7SMark Brown {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 844f10485e7SMark Brown {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 845f10485e7SMark Brown {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 846f10485e7SMark Brown {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 847f10485e7SMark Brown {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 848f10485e7SMark Brown {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 849f10485e7SMark Brown 850f10485e7SMark Brown /* ROMIX */ 851f10485e7SMark Brown {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 852f10485e7SMark Brown {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 853f10485e7SMark Brown {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 854f10485e7SMark Brown {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 855f10485e7SMark Brown {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 856f10485e7SMark Brown {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 857f10485e7SMark Brown {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 858f10485e7SMark Brown 859f10485e7SMark Brown /* SPKMIX */ 860f10485e7SMark Brown {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 861f10485e7SMark Brown {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 862f10485e7SMark Brown {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 863f10485e7SMark Brown {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 864f10485e7SMark Brown {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 865f10485e7SMark Brown {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 866f10485e7SMark Brown {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 867436a7459SMark Brown {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 868f10485e7SMark Brown 869f10485e7SMark Brown /* LONMIX */ 870f10485e7SMark Brown {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 871f10485e7SMark Brown {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 872f10485e7SMark Brown {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 873f10485e7SMark Brown 874f10485e7SMark Brown /* LOPMIX */ 875f10485e7SMark Brown {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 876f10485e7SMark Brown {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 877f10485e7SMark Brown {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 878f10485e7SMark Brown 879f10485e7SMark Brown /* OUT3MIX */ 88097a775c4SJinyoung Park {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 881f10485e7SMark Brown {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 882f10485e7SMark Brown 883f10485e7SMark Brown /* OUT4MIX */ 884f10485e7SMark Brown {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 885f10485e7SMark Brown {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 886f10485e7SMark Brown 887f10485e7SMark Brown /* RONMIX */ 888f10485e7SMark Brown {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 889f10485e7SMark Brown {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 890f10485e7SMark Brown {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 891f10485e7SMark Brown 892f10485e7SMark Brown /* ROPMIX */ 893f10485e7SMark Brown {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 894f10485e7SMark Brown {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 895f10485e7SMark Brown {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 896f10485e7SMark Brown 897f10485e7SMark Brown /* Out Mixer PGAs */ 898f10485e7SMark Brown {"LOPGA", NULL, "LOMIX"}, 899f10485e7SMark Brown {"ROPGA", NULL, "ROMIX"}, 900f10485e7SMark Brown 901f10485e7SMark Brown {"LOUT PGA", NULL, "LOMIX"}, 902f10485e7SMark Brown {"ROUT PGA", NULL, "ROMIX"}, 903f10485e7SMark Brown 904f10485e7SMark Brown /* Output Pins */ 905f10485e7SMark Brown {"LON", NULL, "LONMIX"}, 906f10485e7SMark Brown {"LOP", NULL, "LOPMIX"}, 90797a775c4SJinyoung Park {"OUT3", NULL, "OUT3MIX"}, 908f10485e7SMark Brown {"LOUT", NULL, "LOUT PGA"}, 909f10485e7SMark Brown {"SPKN", NULL, "SPKMIX"}, 910f10485e7SMark Brown {"ROUT", NULL, "ROUT PGA"}, 911f10485e7SMark Brown {"OUT4", NULL, "OUT4MIX"}, 912f10485e7SMark Brown {"ROP", NULL, "ROPMIX"}, 913f10485e7SMark Brown {"RON", NULL, "RONMIX"}, 914f10485e7SMark Brown }; 915f10485e7SMark Brown 916f10485e7SMark Brown static int wm8990_add_widgets(struct snd_soc_codec *codec) 917f10485e7SMark Brown { 918f10485e7SMark Brown snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, 919f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_widgets)); 920f10485e7SMark Brown 921f10485e7SMark Brown /* set up the WM8990 audio map */ 922f10485e7SMark Brown snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 923f10485e7SMark Brown 924f10485e7SMark Brown return 0; 925f10485e7SMark Brown } 926f10485e7SMark Brown 927f10485e7SMark Brown /* PLL divisors */ 928f10485e7SMark Brown struct _pll_div { 929f10485e7SMark Brown u32 div2; 930f10485e7SMark Brown u32 n; 931f10485e7SMark Brown u32 k; 932f10485e7SMark Brown }; 933f10485e7SMark Brown 934f10485e7SMark Brown /* The size in bits of the pll divide multiplied by 10 935f10485e7SMark Brown * to allow rounding later */ 936f10485e7SMark Brown #define FIXED_PLL_SIZE ((1 << 16) * 10) 937f10485e7SMark Brown 938f10485e7SMark Brown static void pll_factors(struct _pll_div *pll_div, unsigned int target, 939f10485e7SMark Brown unsigned int source) 940f10485e7SMark Brown { 941f10485e7SMark Brown u64 Kpart; 942f10485e7SMark Brown unsigned int K, Ndiv, Nmod; 943f10485e7SMark Brown 944f10485e7SMark Brown 945f10485e7SMark Brown Ndiv = target / source; 946f10485e7SMark Brown if (Ndiv < 6) { 947f10485e7SMark Brown source >>= 1; 948f10485e7SMark Brown pll_div->div2 = 1; 949f10485e7SMark Brown Ndiv = target / source; 950f10485e7SMark Brown } else 951f10485e7SMark Brown pll_div->div2 = 0; 952f10485e7SMark Brown 953f10485e7SMark Brown if ((Ndiv < 6) || (Ndiv > 12)) 954f10485e7SMark Brown printk(KERN_WARNING 955449bd54dSRoel Kluin "WM8990 N value outwith recommended range! N = %u\n", Ndiv); 956f10485e7SMark Brown 957f10485e7SMark Brown pll_div->n = Ndiv; 958f10485e7SMark Brown Nmod = target % source; 959f10485e7SMark Brown Kpart = FIXED_PLL_SIZE * (long long)Nmod; 960f10485e7SMark Brown 961f10485e7SMark Brown do_div(Kpart, source); 962f10485e7SMark Brown 963f10485e7SMark Brown K = Kpart & 0xFFFFFFFF; 964f10485e7SMark Brown 965f10485e7SMark Brown /* Check if we need to round */ 966f10485e7SMark Brown if ((K % 10) >= 5) 967f10485e7SMark Brown K += 5; 968f10485e7SMark Brown 969f10485e7SMark Brown /* Move down to proper range now rounding is done */ 970f10485e7SMark Brown K /= 10; 971f10485e7SMark Brown 972f10485e7SMark Brown pll_div->k = K; 973f10485e7SMark Brown } 974f10485e7SMark Brown 97585488037SMark Brown static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 97685488037SMark Brown int source, unsigned int freq_in, unsigned int freq_out) 977f10485e7SMark Brown { 978f10485e7SMark Brown u16 reg; 979f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 980f10485e7SMark Brown struct _pll_div pll_div; 981f10485e7SMark Brown 982f10485e7SMark Brown if (freq_in && freq_out) { 983f10485e7SMark Brown pll_factors(&pll_div, freq_out * 4, freq_in); 984f10485e7SMark Brown 985f10485e7SMark Brown /* Turn on PLL */ 9868d50e447SMark Brown reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 987f10485e7SMark Brown reg |= WM8990_PLL_ENA; 9888d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 989f10485e7SMark Brown 990f10485e7SMark Brown /* sysclk comes from PLL */ 9918d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2); 9928d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 993f10485e7SMark Brown 9943ad2f3fbSDaniel Mack /* set up N , fractional mode and pre-divisor if necessary */ 9958d50e447SMark Brown snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 996f10485e7SMark Brown (pll_div.div2?WM8990_PRESCALE:0)); 9978d50e447SMark Brown snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 9988d50e447SMark Brown snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 999f10485e7SMark Brown } else { 1000f10485e7SMark Brown /* Turn on PLL */ 10018d50e447SMark Brown reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 1002f10485e7SMark Brown reg &= ~WM8990_PLL_ENA; 10038d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1004f10485e7SMark Brown } 1005f10485e7SMark Brown return 0; 1006f10485e7SMark Brown } 1007f10485e7SMark Brown 1008f10485e7SMark Brown /* 1009f10485e7SMark Brown * Clock after PLL and dividers 1010f10485e7SMark Brown */ 1011e550e17fSLiam Girdwood static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1012f10485e7SMark Brown int clk_id, unsigned int freq, int dir) 1013f10485e7SMark Brown { 1014f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1015b2c812e2SMark Brown struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec); 1016f10485e7SMark Brown 1017f10485e7SMark Brown wm8990->sysclk = freq; 1018f10485e7SMark Brown return 0; 1019f10485e7SMark Brown } 1020f10485e7SMark Brown 1021f10485e7SMark Brown /* 1022f10485e7SMark Brown * Set's ADC and Voice DAC format. 1023f10485e7SMark Brown */ 1024e550e17fSLiam Girdwood static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 1025f10485e7SMark Brown unsigned int fmt) 1026f10485e7SMark Brown { 1027f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1028f10485e7SMark Brown u16 audio1, audio3; 1029f10485e7SMark Brown 10308d50e447SMark Brown audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 10318d50e447SMark Brown audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3); 1032f10485e7SMark Brown 1033f10485e7SMark Brown /* set master/slave audio interface */ 1034f10485e7SMark Brown switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1035f10485e7SMark Brown case SND_SOC_DAIFMT_CBS_CFS: 1036f10485e7SMark Brown audio3 &= ~WM8990_AIF_MSTR1; 1037f10485e7SMark Brown break; 1038f10485e7SMark Brown case SND_SOC_DAIFMT_CBM_CFM: 1039f10485e7SMark Brown audio3 |= WM8990_AIF_MSTR1; 1040f10485e7SMark Brown break; 1041f10485e7SMark Brown default: 1042f10485e7SMark Brown return -EINVAL; 1043f10485e7SMark Brown } 1044f10485e7SMark Brown 1045f10485e7SMark Brown audio1 &= ~WM8990_AIF_FMT_MASK; 1046f10485e7SMark Brown 1047f10485e7SMark Brown /* interface format */ 1048f10485e7SMark Brown switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1049f10485e7SMark Brown case SND_SOC_DAIFMT_I2S: 1050f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_I2S; 1051f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1052f10485e7SMark Brown break; 1053f10485e7SMark Brown case SND_SOC_DAIFMT_RIGHT_J: 1054f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_RIGHTJ; 1055f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1056f10485e7SMark Brown break; 1057f10485e7SMark Brown case SND_SOC_DAIFMT_LEFT_J: 1058f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_LEFTJ; 1059f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1060f10485e7SMark Brown break; 1061f10485e7SMark Brown case SND_SOC_DAIFMT_DSP_A: 1062f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_DSP; 1063f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1064f10485e7SMark Brown break; 1065f10485e7SMark Brown case SND_SOC_DAIFMT_DSP_B: 1066f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1067f10485e7SMark Brown break; 1068f10485e7SMark Brown default: 1069f10485e7SMark Brown return -EINVAL; 1070f10485e7SMark Brown } 1071f10485e7SMark Brown 10728d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 10738d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1074f10485e7SMark Brown return 0; 1075f10485e7SMark Brown } 1076f10485e7SMark Brown 1077e550e17fSLiam Girdwood static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1078f10485e7SMark Brown int div_id, int div) 1079f10485e7SMark Brown { 1080f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1081f10485e7SMark Brown u16 reg; 1082f10485e7SMark Brown 1083f10485e7SMark Brown switch (div_id) { 1084f10485e7SMark Brown case WM8990_MCLK_DIV: 10858d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1086f10485e7SMark Brown ~WM8990_MCLK_DIV_MASK; 10878d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1088f10485e7SMark Brown break; 1089f10485e7SMark Brown case WM8990_DACCLK_DIV: 10908d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1091f10485e7SMark Brown ~WM8990_DAC_CLKDIV_MASK; 10928d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1093f10485e7SMark Brown break; 1094f10485e7SMark Brown case WM8990_ADCCLK_DIV: 10958d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1096f10485e7SMark Brown ~WM8990_ADC_CLKDIV_MASK; 10978d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1098f10485e7SMark Brown break; 1099f10485e7SMark Brown case WM8990_BCLK_DIV: 11008d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_1) & 1101f10485e7SMark Brown ~WM8990_BCLK_DIV_MASK; 11028d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_1, reg | div); 1103f10485e7SMark Brown break; 1104f10485e7SMark Brown default: 1105f10485e7SMark Brown return -EINVAL; 1106f10485e7SMark Brown } 1107f10485e7SMark Brown 1108f10485e7SMark Brown return 0; 1109f10485e7SMark Brown } 1110f10485e7SMark Brown 1111f10485e7SMark Brown /* 1112f10485e7SMark Brown * Set PCM DAI bit size and sample rate. 1113f10485e7SMark Brown */ 1114f10485e7SMark Brown static int wm8990_hw_params(struct snd_pcm_substream *substream, 1115dee89c4dSMark Brown struct snd_pcm_hw_params *params, 1116dee89c4dSMark Brown struct snd_soc_dai *dai) 1117f10485e7SMark Brown { 1118f10485e7SMark Brown struct snd_soc_pcm_runtime *rtd = substream->private_data; 1119*f0fba2adSLiam Girdwood struct snd_soc_codec *codec = rtd->codec; 11208d50e447SMark Brown u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1121f10485e7SMark Brown 1122f10485e7SMark Brown audio1 &= ~WM8990_AIF_WL_MASK; 1123f10485e7SMark Brown /* bit size */ 1124f10485e7SMark Brown switch (params_format(params)) { 1125f10485e7SMark Brown case SNDRV_PCM_FORMAT_S16_LE: 1126f10485e7SMark Brown break; 1127f10485e7SMark Brown case SNDRV_PCM_FORMAT_S20_3LE: 1128f10485e7SMark Brown audio1 |= WM8990_AIF_WL_20BITS; 1129f10485e7SMark Brown break; 1130f10485e7SMark Brown case SNDRV_PCM_FORMAT_S24_LE: 1131f10485e7SMark Brown audio1 |= WM8990_AIF_WL_24BITS; 1132f10485e7SMark Brown break; 1133f10485e7SMark Brown case SNDRV_PCM_FORMAT_S32_LE: 1134f10485e7SMark Brown audio1 |= WM8990_AIF_WL_32BITS; 1135f10485e7SMark Brown break; 1136f10485e7SMark Brown } 1137f10485e7SMark Brown 11388d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1139f10485e7SMark Brown return 0; 1140f10485e7SMark Brown } 1141f10485e7SMark Brown 1142e550e17fSLiam Girdwood static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1143f10485e7SMark Brown { 1144f10485e7SMark Brown struct snd_soc_codec *codec = dai->codec; 1145f10485e7SMark Brown u16 val; 1146f10485e7SMark Brown 11478d50e447SMark Brown val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1148f10485e7SMark Brown 1149f10485e7SMark Brown if (mute) 11508d50e447SMark Brown snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1151f10485e7SMark Brown else 11528d50e447SMark Brown snd_soc_write(codec, WM8990_DAC_CTRL, val); 1153f10485e7SMark Brown 1154f10485e7SMark Brown return 0; 1155f10485e7SMark Brown } 1156f10485e7SMark Brown 1157f10485e7SMark Brown static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1158f10485e7SMark Brown enum snd_soc_bias_level level) 1159f10485e7SMark Brown { 1160f10485e7SMark Brown u16 val; 1161f10485e7SMark Brown 1162f10485e7SMark Brown switch (level) { 1163f10485e7SMark Brown case SND_SOC_BIAS_ON: 1164f10485e7SMark Brown break; 11652adb9833SMark Brown 1166f10485e7SMark Brown case SND_SOC_BIAS_PREPARE: 11672adb9833SMark Brown /* VMID=2*50k */ 11688d50e447SMark Brown val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) & 11692adb9833SMark Brown ~WM8990_VMID_MODE_MASK; 11708d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1171f10485e7SMark Brown break; 11722adb9833SMark Brown 1173f10485e7SMark Brown case SND_SOC_BIAS_STANDBY: 1174f10485e7SMark Brown if (codec->bias_level == SND_SOC_BIAS_OFF) { 1175f10485e7SMark Brown /* Enable all output discharge bits */ 11768d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1177f10485e7SMark Brown WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1178f10485e7SMark Brown WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1179f10485e7SMark Brown WM8990_DIS_ROUT); 1180f10485e7SMark Brown 1181f10485e7SMark Brown /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 11828d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1183f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1184f10485e7SMark Brown WM8990_VMIDTOG); 1185f10485e7SMark Brown 1186f10485e7SMark Brown /* Delay to allow output caps to discharge */ 1187f10485e7SMark Brown msleep(msecs_to_jiffies(300)); 1188f10485e7SMark Brown 1189f10485e7SMark Brown /* Disable VMIDTOG */ 11908d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1191f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL); 1192f10485e7SMark Brown 1193f10485e7SMark Brown /* disable all output discharge bits */ 11948d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP1, 0); 1195f10485e7SMark Brown 1196f10485e7SMark Brown /* Enable outputs */ 11978d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1198f10485e7SMark Brown 1199f10485e7SMark Brown msleep(msecs_to_jiffies(50)); 1200f10485e7SMark Brown 1201f10485e7SMark Brown /* Enable VMID at 2x50k */ 12028d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1203f10485e7SMark Brown 1204f10485e7SMark Brown msleep(msecs_to_jiffies(100)); 1205f10485e7SMark Brown 1206f10485e7SMark Brown /* Enable VREF */ 12078d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1208f10485e7SMark Brown 1209f10485e7SMark Brown msleep(msecs_to_jiffies(600)); 1210f10485e7SMark Brown 1211f10485e7SMark Brown /* Enable BUFIOEN */ 12128d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1213f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1214f10485e7SMark Brown WM8990_BUFIOEN); 1215f10485e7SMark Brown 1216f10485e7SMark Brown /* Disable outputs */ 12178d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1218f10485e7SMark Brown 1219f10485e7SMark Brown /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 12208d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1221f10485e7SMark Brown 1222be1b87c7SMark Brown /* Enable workaround for ADC clocking issue. */ 12238d50e447SMark Brown snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 12248d50e447SMark Brown snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003); 12258d50e447SMark Brown snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1226f10485e7SMark Brown } 12272adb9833SMark Brown 12282adb9833SMark Brown /* VMID=2*250k */ 12298d50e447SMark Brown val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) & 12302adb9833SMark Brown ~WM8990_VMID_MODE_MASK; 12318d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1232f10485e7SMark Brown break; 1233f10485e7SMark Brown 1234f10485e7SMark Brown case SND_SOC_BIAS_OFF: 1235f10485e7SMark Brown /* Enable POBCTRL and SOFT_ST */ 12368d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1237f10485e7SMark Brown WM8990_POBCTRL | WM8990_BUFIOEN); 1238f10485e7SMark Brown 1239f10485e7SMark Brown /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 12408d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1241f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1242f10485e7SMark Brown WM8990_BUFIOEN); 1243f10485e7SMark Brown 1244f10485e7SMark Brown /* mute DAC */ 12458d50e447SMark Brown val = snd_soc_read(codec, WM8990_DAC_CTRL); 12468d50e447SMark Brown snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1247f10485e7SMark Brown 1248f10485e7SMark Brown /* Enable any disabled outputs */ 12498d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1250f10485e7SMark Brown 1251f10485e7SMark Brown /* Disable VMID */ 12528d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1253f10485e7SMark Brown 1254f10485e7SMark Brown msleep(msecs_to_jiffies(300)); 1255f10485e7SMark Brown 1256f10485e7SMark Brown /* Enable all output discharge bits */ 12578d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1258f10485e7SMark Brown WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1259f10485e7SMark Brown WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1260f10485e7SMark Brown WM8990_DIS_ROUT); 1261f10485e7SMark Brown 1262f10485e7SMark Brown /* Disable VREF */ 12638d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1264f10485e7SMark Brown 1265f10485e7SMark Brown /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 12668d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, 0x0); 1267f10485e7SMark Brown break; 1268f10485e7SMark Brown } 1269f10485e7SMark Brown 1270f10485e7SMark Brown codec->bias_level = level; 1271f10485e7SMark Brown return 0; 1272f10485e7SMark Brown } 1273f10485e7SMark Brown 1274f10485e7SMark Brown #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1275f10485e7SMark Brown SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1276f10485e7SMark Brown SNDRV_PCM_RATE_48000) 1277f10485e7SMark Brown 1278f10485e7SMark Brown #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1279f10485e7SMark Brown SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1280f10485e7SMark Brown 1281f10485e7SMark Brown /* 1282f10485e7SMark Brown * The WM8990 supports 2 different and mutually exclusive DAI 1283f10485e7SMark Brown * configurations. 1284f10485e7SMark Brown * 1285f10485e7SMark Brown * 1. ADC/DAC on Primary Interface 1286f10485e7SMark Brown * 2. ADC on Primary Interface/DAC on secondary 1287f10485e7SMark Brown */ 12886335d055SEric Miao static struct snd_soc_dai_ops wm8990_dai_ops = { 12896335d055SEric Miao .hw_params = wm8990_hw_params, 12906335d055SEric Miao .digital_mute = wm8990_mute, 12916335d055SEric Miao .set_fmt = wm8990_set_dai_fmt, 12926335d055SEric Miao .set_clkdiv = wm8990_set_dai_clkdiv, 12936335d055SEric Miao .set_pll = wm8990_set_dai_pll, 12946335d055SEric Miao .set_sysclk = wm8990_set_dai_sysclk, 12956335d055SEric Miao }; 12966335d055SEric Miao 1297*f0fba2adSLiam Girdwood static struct snd_soc_dai_driver wm8990_dai = { 1298f10485e7SMark Brown /* ADC/DAC on primary */ 1299*f0fba2adSLiam Girdwood .name = "wm8990-hifi", 1300f10485e7SMark Brown .playback = { 1301f10485e7SMark Brown .stream_name = "Playback", 1302f10485e7SMark Brown .channels_min = 1, 1303f10485e7SMark Brown .channels_max = 2, 1304f10485e7SMark Brown .rates = WM8990_RATES, 1305f10485e7SMark Brown .formats = WM8990_FORMATS,}, 1306f10485e7SMark Brown .capture = { 1307f10485e7SMark Brown .stream_name = "Capture", 1308f10485e7SMark Brown .channels_min = 1, 1309f10485e7SMark Brown .channels_max = 2, 1310f10485e7SMark Brown .rates = WM8990_RATES, 1311f10485e7SMark Brown .formats = WM8990_FORMATS,}, 13126335d055SEric Miao .ops = &wm8990_dai_ops, 1313f10485e7SMark Brown }; 1314f10485e7SMark Brown 1315*f0fba2adSLiam Girdwood static int wm8990_suspend(struct snd_soc_codec *codec, pm_message_t state) 1316f10485e7SMark Brown { 1317f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1318f10485e7SMark Brown return 0; 1319f10485e7SMark Brown } 1320f10485e7SMark Brown 1321*f0fba2adSLiam Girdwood static int wm8990_resume(struct snd_soc_codec *codec) 1322f10485e7SMark Brown { 1323f10485e7SMark Brown int i; 1324f10485e7SMark Brown u8 data[2]; 1325f10485e7SMark Brown u16 *cache = codec->reg_cache; 1326f10485e7SMark Brown 1327f10485e7SMark Brown /* Sync reg_cache with the hardware */ 1328f10485e7SMark Brown for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) { 1329f10485e7SMark Brown if (i + 1 == WM8990_RESET) 1330f10485e7SMark Brown continue; 1331f10485e7SMark Brown data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); 1332f10485e7SMark Brown data[1] = cache[i] & 0x00ff; 1333f10485e7SMark Brown codec->hw_write(codec->control_data, data, 2); 1334f10485e7SMark Brown } 1335f10485e7SMark Brown 1336f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1337f10485e7SMark Brown return 0; 1338f10485e7SMark Brown } 1339f10485e7SMark Brown 1340f10485e7SMark Brown /* 1341f10485e7SMark Brown * initialise the WM8990 driver 1342f10485e7SMark Brown * register the mixer and dsp interfaces with the kernel 1343f10485e7SMark Brown */ 1344*f0fba2adSLiam Girdwood static int wm8990_probe(struct snd_soc_codec *codec) 1345f10485e7SMark Brown { 1346*f0fba2adSLiam Girdwood struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec); 1347*f0fba2adSLiam Girdwood int ret; 1348f10485e7SMark Brown u16 reg; 1349f10485e7SMark Brown 1350*f0fba2adSLiam Girdwood codec->control_data = wm8990->control_data; 13518d50e447SMark Brown ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 13528d50e447SMark Brown if (ret < 0) { 13538d50e447SMark Brown printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret); 1354*f0fba2adSLiam Girdwood return ret; 13558d50e447SMark Brown } 13568d50e447SMark Brown 1357f10485e7SMark Brown wm8990_reset(codec); 1358f10485e7SMark Brown 1359f10485e7SMark Brown /* charge output caps */ 1360f10485e7SMark Brown codec->bias_level = SND_SOC_BIAS_OFF; 1361f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1362f10485e7SMark Brown 13638d50e447SMark Brown reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4); 13648d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1365f10485e7SMark Brown 13668d50e447SMark Brown reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) & 1367f10485e7SMark Brown ~WM8990_GPIO1_SEL_MASK; 13688d50e447SMark Brown snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1369f10485e7SMark Brown 13708d50e447SMark Brown reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 13718d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1372f10485e7SMark Brown 13738d50e447SMark Brown snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 13748d50e447SMark Brown snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1375f10485e7SMark Brown 13763e8e1952SIan Molton snd_soc_add_controls(codec, wm8990_snd_controls, 13773e8e1952SIan Molton ARRAY_SIZE(wm8990_snd_controls)); 1378f10485e7SMark Brown wm8990_add_widgets(codec); 1379fe3e78e0SMark Brown 1380*f0fba2adSLiam Girdwood return 0; 1381f10485e7SMark Brown } 1382f10485e7SMark Brown 1383*f0fba2adSLiam Girdwood /* power down chip */ 1384*f0fba2adSLiam Girdwood static int wm8990_remove(struct snd_soc_codec *codec) 1385*f0fba2adSLiam Girdwood { 1386*f0fba2adSLiam Girdwood wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1387*f0fba2adSLiam Girdwood return 0; 1388*f0fba2adSLiam Girdwood } 1389*f0fba2adSLiam Girdwood 1390*f0fba2adSLiam Girdwood static struct snd_soc_codec_driver soc_codec_dev_wm8990 = { 1391*f0fba2adSLiam Girdwood .probe = wm8990_probe, 1392*f0fba2adSLiam Girdwood .remove = wm8990_remove, 1393*f0fba2adSLiam Girdwood .suspend = wm8990_suspend, 1394*f0fba2adSLiam Girdwood .resume = wm8990_resume, 1395*f0fba2adSLiam Girdwood .set_bias_level = wm8990_set_bias_level, 1396*f0fba2adSLiam Girdwood .reg_cache_size = ARRAY_SIZE(wm8990_reg), 1397*f0fba2adSLiam Girdwood .reg_word_size = sizeof(u16), 1398*f0fba2adSLiam Girdwood .reg_cache_default = wm8990_reg, 1399*f0fba2adSLiam Girdwood }; 1400f10485e7SMark Brown 1401f10485e7SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1402*f0fba2adSLiam Girdwood static __devinit int wm8990_i2c_probe(struct i2c_client *i2c, 1403e5d3fd38SJean Delvare const struct i2c_device_id *id) 1404f10485e7SMark Brown { 1405*f0fba2adSLiam Girdwood struct wm8990_priv *wm8990; 1406f10485e7SMark Brown int ret; 1407f10485e7SMark Brown 1408*f0fba2adSLiam Girdwood wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL); 1409*f0fba2adSLiam Girdwood if (wm8990 == NULL) 1410*f0fba2adSLiam Girdwood return -ENOMEM; 1411f10485e7SMark Brown 1412*f0fba2adSLiam Girdwood i2c_set_clientdata(i2c, wm8990); 1413*f0fba2adSLiam Girdwood wm8990->control_data = i2c; 1414*f0fba2adSLiam Girdwood 1415*f0fba2adSLiam Girdwood ret = snd_soc_register_codec(&i2c->dev, 1416*f0fba2adSLiam Girdwood &soc_codec_dev_wm8990, &wm8990_dai, 1); 1417e5d3fd38SJean Delvare if (ret < 0) 1418*f0fba2adSLiam Girdwood kfree(wm8990); 1419f10485e7SMark Brown return ret; 1420f10485e7SMark Brown } 1421f10485e7SMark Brown 1422*f0fba2adSLiam Girdwood static __devexit int wm8990_i2c_remove(struct i2c_client *client) 1423f10485e7SMark Brown { 1424*f0fba2adSLiam Girdwood snd_soc_unregister_codec(&client->dev); 1425*f0fba2adSLiam Girdwood kfree(i2c_get_clientdata(client)); 1426f10485e7SMark Brown return 0; 1427f10485e7SMark Brown } 1428f10485e7SMark Brown 1429e5d3fd38SJean Delvare static const struct i2c_device_id wm8990_i2c_id[] = { 1430e5d3fd38SJean Delvare { "wm8990", 0 }, 1431e5d3fd38SJean Delvare { } 1432e5d3fd38SJean Delvare }; 1433e5d3fd38SJean Delvare MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1434f10485e7SMark Brown 1435f10485e7SMark Brown static struct i2c_driver wm8990_i2c_driver = { 1436f10485e7SMark Brown .driver = { 1437*f0fba2adSLiam Girdwood .name = "wm8990-codec", 1438f10485e7SMark Brown .owner = THIS_MODULE, 1439f10485e7SMark Brown }, 1440e5d3fd38SJean Delvare .probe = wm8990_i2c_probe, 1441*f0fba2adSLiam Girdwood .remove = __devexit_p(wm8990_i2c_remove), 1442e5d3fd38SJean Delvare .id_table = wm8990_i2c_id, 1443f10485e7SMark Brown }; 1444f10485e7SMark Brown #endif 1445f10485e7SMark Brown 1446c9b3a40fSTakashi Iwai static int __init wm8990_modinit(void) 144764089b84SMark Brown { 1448*f0fba2adSLiam Girdwood int ret = 0; 1449*f0fba2adSLiam Girdwood #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1450*f0fba2adSLiam Girdwood ret = i2c_add_driver(&wm8990_i2c_driver); 1451*f0fba2adSLiam Girdwood if (ret != 0) { 1452*f0fba2adSLiam Girdwood printk(KERN_ERR "Failed to register wm8990 I2C driver: %d\n", 1453*f0fba2adSLiam Girdwood ret); 1454*f0fba2adSLiam Girdwood } 1455*f0fba2adSLiam Girdwood #endif 1456*f0fba2adSLiam Girdwood return ret; 145764089b84SMark Brown } 145864089b84SMark Brown module_init(wm8990_modinit); 145964089b84SMark Brown 146064089b84SMark Brown static void __exit wm8990_exit(void) 146164089b84SMark Brown { 1462*f0fba2adSLiam Girdwood #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1463*f0fba2adSLiam Girdwood i2c_del_driver(&wm8990_i2c_driver); 1464*f0fba2adSLiam Girdwood #endif 146564089b84SMark Brown } 146664089b84SMark Brown module_exit(wm8990_exit); 146764089b84SMark Brown 1468f10485e7SMark Brown MODULE_DESCRIPTION("ASoC WM8990 driver"); 1469f10485e7SMark Brown MODULE_AUTHOR("Liam Girdwood"); 1470f10485e7SMark Brown MODULE_LICENSE("GPL"); 1471