1f10485e7SMark Brown /* 2f10485e7SMark Brown * wm8990.c -- WM8990 ALSA Soc Audio driver 3f10485e7SMark Brown * 4f10485e7SMark Brown * Copyright 2008 Wolfson Microelectronics PLC. 564ca0404SLiam Girdwood * Author: Liam Girdwood <lrg@slimlogic.co.uk> 6f10485e7SMark Brown * 7f10485e7SMark Brown * This program is free software; you can redistribute it and/or modify it 8f10485e7SMark Brown * under the terms of the GNU General Public License as published by the 9f10485e7SMark Brown * Free Software Foundation; either version 2 of the License, or (at your 10f10485e7SMark Brown * option) any later version. 11f10485e7SMark Brown */ 12f10485e7SMark Brown 13f10485e7SMark Brown #include <linux/module.h> 14f10485e7SMark Brown #include <linux/moduleparam.h> 15f10485e7SMark Brown #include <linux/kernel.h> 16f10485e7SMark Brown #include <linux/init.h> 17f10485e7SMark Brown #include <linux/delay.h> 18f10485e7SMark Brown #include <linux/pm.h> 19f10485e7SMark Brown #include <linux/i2c.h> 20f10485e7SMark Brown #include <linux/platform_device.h> 215a0e3ad6STejun Heo #include <linux/slab.h> 22f10485e7SMark Brown #include <sound/core.h> 23f10485e7SMark Brown #include <sound/pcm.h> 24f10485e7SMark Brown #include <sound/pcm_params.h> 25f10485e7SMark Brown #include <sound/soc.h> 26f10485e7SMark Brown #include <sound/initval.h> 27f10485e7SMark Brown #include <sound/tlv.h> 28f10485e7SMark Brown #include <asm/div64.h> 29f10485e7SMark Brown 30f10485e7SMark Brown #include "wm8990.h" 31f10485e7SMark Brown 32f10485e7SMark Brown /* codec private data */ 33f10485e7SMark Brown struct wm8990_priv { 34f0fba2adSLiam Girdwood enum snd_soc_control_type control_type; 35f10485e7SMark Brown unsigned int sysclk; 36f10485e7SMark Brown unsigned int pcmclk; 37f10485e7SMark Brown }; 38f10485e7SMark Brown 39416a0ce5SAxel Lin static int wm8990_volatile_register(struct snd_soc_codec *codec, 40416a0ce5SAxel Lin unsigned int reg) 41416a0ce5SAxel Lin { 42416a0ce5SAxel Lin switch (reg) { 43416a0ce5SAxel Lin case WM8990_RESET: 44416a0ce5SAxel Lin return 1; 45416a0ce5SAxel Lin default: 46416a0ce5SAxel Lin return 0; 47416a0ce5SAxel Lin } 48416a0ce5SAxel Lin } 49416a0ce5SAxel Lin 50f10485e7SMark Brown static const u16 wm8990_reg[] = { 51f10485e7SMark Brown 0x8990, /* R0 - Reset */ 52f10485e7SMark Brown 0x0000, /* R1 - Power Management (1) */ 53f10485e7SMark Brown 0x6000, /* R2 - Power Management (2) */ 54f10485e7SMark Brown 0x0000, /* R3 - Power Management (3) */ 55f10485e7SMark Brown 0x4050, /* R4 - Audio Interface (1) */ 56f10485e7SMark Brown 0x4000, /* R5 - Audio Interface (2) */ 57f10485e7SMark Brown 0x01C8, /* R6 - Clocking (1) */ 58f10485e7SMark Brown 0x0000, /* R7 - Clocking (2) */ 59f10485e7SMark Brown 0x0040, /* R8 - Audio Interface (3) */ 60f10485e7SMark Brown 0x0040, /* R9 - Audio Interface (4) */ 61f10485e7SMark Brown 0x0004, /* R10 - DAC CTRL */ 62f10485e7SMark Brown 0x00C0, /* R11 - Left DAC Digital Volume */ 63f10485e7SMark Brown 0x00C0, /* R12 - Right DAC Digital Volume */ 64f10485e7SMark Brown 0x0000, /* R13 - Digital Side Tone */ 65f10485e7SMark Brown 0x0100, /* R14 - ADC CTRL */ 66f10485e7SMark Brown 0x00C0, /* R15 - Left ADC Digital Volume */ 67f10485e7SMark Brown 0x00C0, /* R16 - Right ADC Digital Volume */ 68f10485e7SMark Brown 0x0000, /* R17 */ 69f10485e7SMark Brown 0x0000, /* R18 - GPIO CTRL 1 */ 70f10485e7SMark Brown 0x1000, /* R19 - GPIO1 & GPIO2 */ 71f10485e7SMark Brown 0x1010, /* R20 - GPIO3 & GPIO4 */ 72f10485e7SMark Brown 0x1010, /* R21 - GPIO5 & GPIO6 */ 73f10485e7SMark Brown 0x8000, /* R22 - GPIOCTRL 2 */ 74f10485e7SMark Brown 0x0800, /* R23 - GPIO_POL */ 75f10485e7SMark Brown 0x008B, /* R24 - Left Line Input 1&2 Volume */ 76f10485e7SMark Brown 0x008B, /* R25 - Left Line Input 3&4 Volume */ 77f10485e7SMark Brown 0x008B, /* R26 - Right Line Input 1&2 Volume */ 78f10485e7SMark Brown 0x008B, /* R27 - Right Line Input 3&4 Volume */ 79f10485e7SMark Brown 0x0000, /* R28 - Left Output Volume */ 80f10485e7SMark Brown 0x0000, /* R29 - Right Output Volume */ 81f10485e7SMark Brown 0x0066, /* R30 - Line Outputs Volume */ 82f10485e7SMark Brown 0x0022, /* R31 - Out3/4 Volume */ 83f10485e7SMark Brown 0x0079, /* R32 - Left OPGA Volume */ 84f10485e7SMark Brown 0x0079, /* R33 - Right OPGA Volume */ 85f10485e7SMark Brown 0x0003, /* R34 - Speaker Volume */ 86f10485e7SMark Brown 0x0003, /* R35 - ClassD1 */ 87f10485e7SMark Brown 0x0000, /* R36 */ 88f10485e7SMark Brown 0x0100, /* R37 - ClassD3 */ 8997bb8129SMark Brown 0x0079, /* R38 - ClassD4 */ 90f10485e7SMark Brown 0x0000, /* R39 - Input Mixer1 */ 91f10485e7SMark Brown 0x0000, /* R40 - Input Mixer2 */ 92f10485e7SMark Brown 0x0000, /* R41 - Input Mixer3 */ 93f10485e7SMark Brown 0x0000, /* R42 - Input Mixer4 */ 94f10485e7SMark Brown 0x0000, /* R43 - Input Mixer5 */ 95f10485e7SMark Brown 0x0000, /* R44 - Input Mixer6 */ 96f10485e7SMark Brown 0x0000, /* R45 - Output Mixer1 */ 97f10485e7SMark Brown 0x0000, /* R46 - Output Mixer2 */ 98f10485e7SMark Brown 0x0000, /* R47 - Output Mixer3 */ 99f10485e7SMark Brown 0x0000, /* R48 - Output Mixer4 */ 100f10485e7SMark Brown 0x0000, /* R49 - Output Mixer5 */ 101f10485e7SMark Brown 0x0000, /* R50 - Output Mixer6 */ 102f10485e7SMark Brown 0x0180, /* R51 - Out3/4 Mixer */ 103f10485e7SMark Brown 0x0000, /* R52 - Line Mixer1 */ 104f10485e7SMark Brown 0x0000, /* R53 - Line Mixer2 */ 105f10485e7SMark Brown 0x0000, /* R54 - Speaker Mixer */ 106f10485e7SMark Brown 0x0000, /* R55 - Additional Control */ 107f10485e7SMark Brown 0x0000, /* R56 - AntiPOP1 */ 108f10485e7SMark Brown 0x0000, /* R57 - AntiPOP2 */ 109f10485e7SMark Brown 0x0000, /* R58 - MICBIAS */ 110f10485e7SMark Brown 0x0000, /* R59 */ 111f10485e7SMark Brown 0x0008, /* R60 - PLL1 */ 112f10485e7SMark Brown 0x0031, /* R61 - PLL2 */ 113f10485e7SMark Brown 0x0026, /* R62 - PLL3 */ 114ba533e95SMark Brown 0x0000, /* R63 - Driver internal */ 115f10485e7SMark Brown }; 116f10485e7SMark Brown 1178d50e447SMark Brown #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0) 118f10485e7SMark Brown 119021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); 120f10485e7SMark Brown 121021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); 122f10485e7SMark Brown 123021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0); 124f10485e7SMark Brown 125021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); 126f10485e7SMark Brown 127021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); 128f10485e7SMark Brown 129021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); 130f10485e7SMark Brown 131021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); 132f10485e7SMark Brown 133021f80ccSMark Brown static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); 134f10485e7SMark Brown 135f10485e7SMark Brown static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 136f10485e7SMark Brown struct snd_ctl_elem_value *ucontrol) 137f10485e7SMark Brown { 138f10485e7SMark Brown struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 139397d5aeeSJarkko Nikula struct soc_mixer_control *mc = 140397d5aeeSJarkko Nikula (struct soc_mixer_control *)kcontrol->private_value; 141397d5aeeSJarkko Nikula int reg = mc->reg; 142f10485e7SMark Brown int ret; 143f10485e7SMark Brown u16 val; 144f10485e7SMark Brown 145f10485e7SMark Brown ret = snd_soc_put_volsw(kcontrol, ucontrol); 146f10485e7SMark Brown if (ret < 0) 147f10485e7SMark Brown return ret; 148f10485e7SMark Brown 149f10485e7SMark Brown /* now hit the volume update bits (always bit 8) */ 1508d50e447SMark Brown val = snd_soc_read(codec, reg); 1518d50e447SMark Brown return snd_soc_write(codec, reg, val | 0x0100); 152f10485e7SMark Brown } 153f10485e7SMark Brown 154f10485e7SMark Brown #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 155f10485e7SMark Brown tlv_array) {\ 156f10485e7SMark Brown .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 157f10485e7SMark Brown .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 158f10485e7SMark Brown SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 159f10485e7SMark Brown .tlv.p = (tlv_array), \ 160f10485e7SMark Brown .info = snd_soc_info_volsw, \ 161f10485e7SMark Brown .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ 162f10485e7SMark Brown .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 163f10485e7SMark Brown 164f10485e7SMark Brown 165f10485e7SMark Brown static const char *wm8990_digital_sidetone[] = 166f10485e7SMark Brown {"None", "Left ADC", "Right ADC", "Reserved"}; 167f10485e7SMark Brown 168f10485e7SMark Brown static const struct soc_enum wm8990_left_digital_sidetone_enum = 169f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 170f10485e7SMark Brown WM8990_ADC_TO_DACL_SHIFT, 171f10485e7SMark Brown WM8990_ADC_TO_DACL_MASK, 172f10485e7SMark Brown wm8990_digital_sidetone); 173f10485e7SMark Brown 174f10485e7SMark Brown static const struct soc_enum wm8990_right_digital_sidetone_enum = 175f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 176f10485e7SMark Brown WM8990_ADC_TO_DACR_SHIFT, 177f10485e7SMark Brown WM8990_ADC_TO_DACR_MASK, 178f10485e7SMark Brown wm8990_digital_sidetone); 179f10485e7SMark Brown 180f10485e7SMark Brown static const char *wm8990_adcmode[] = 181f10485e7SMark Brown {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 182f10485e7SMark Brown 183f10485e7SMark Brown static const struct soc_enum wm8990_right_adcmode_enum = 184f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 185f10485e7SMark Brown WM8990_ADC_HPF_CUT_SHIFT, 186f10485e7SMark Brown WM8990_ADC_HPF_CUT_MASK, 187f10485e7SMark Brown wm8990_adcmode); 188f10485e7SMark Brown 189f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_snd_controls[] = { 190f10485e7SMark Brown /* INMIXL */ 191f10485e7SMark Brown SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 192f10485e7SMark Brown SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 193f10485e7SMark Brown /* INMIXR */ 194f10485e7SMark Brown SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 195f10485e7SMark Brown SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 196f10485e7SMark Brown 197f10485e7SMark Brown /* LOMIX */ 198f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 199f10485e7SMark Brown WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 200f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 201f10485e7SMark Brown WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 202f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 203f10485e7SMark Brown WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 204f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 205f10485e7SMark Brown WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 206f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 207f10485e7SMark Brown WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 208f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 209f10485e7SMark Brown WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 210f10485e7SMark Brown 211f10485e7SMark Brown /* ROMIX */ 212f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 213f10485e7SMark Brown WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 214f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 215f10485e7SMark Brown WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 216f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 217f10485e7SMark Brown WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 218f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 219f10485e7SMark Brown WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 220f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 221f10485e7SMark Brown WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 222f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 223f10485e7SMark Brown WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 224f10485e7SMark Brown 225f10485e7SMark Brown /* LOUT */ 226f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 227f10485e7SMark Brown WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 228f10485e7SMark Brown SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 229f10485e7SMark Brown 230f10485e7SMark Brown /* ROUT */ 231f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 232f10485e7SMark Brown WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 233f10485e7SMark Brown SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 234f10485e7SMark Brown 235f10485e7SMark Brown /* LOPGA */ 236f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 237f10485e7SMark Brown WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 238f10485e7SMark Brown SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 239f10485e7SMark Brown WM8990_LOPGAZC_BIT, 1, 0), 240f10485e7SMark Brown 241f10485e7SMark Brown /* ROPGA */ 242f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 243f10485e7SMark Brown WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 244f10485e7SMark Brown SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 245f10485e7SMark Brown WM8990_ROPGAZC_BIT, 1, 0), 246f10485e7SMark Brown 247f10485e7SMark Brown SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 248f10485e7SMark Brown WM8990_LONMUTE_BIT, 1, 0), 249f10485e7SMark Brown SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 250f10485e7SMark Brown WM8990_LOPMUTE_BIT, 1, 0), 251f10485e7SMark Brown SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 252f10485e7SMark Brown WM8990_LOATTN_BIT, 1, 0), 253f10485e7SMark Brown SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 254f10485e7SMark Brown WM8990_RONMUTE_BIT, 1, 0), 255f10485e7SMark Brown SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 256f10485e7SMark Brown WM8990_ROPMUTE_BIT, 1, 0), 257f10485e7SMark Brown SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 258f10485e7SMark Brown WM8990_ROATTN_BIT, 1, 0), 259f10485e7SMark Brown 260f10485e7SMark Brown SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 261f10485e7SMark Brown WM8990_OUT3MUTE_BIT, 1, 0), 262f10485e7SMark Brown SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 263f10485e7SMark Brown WM8990_OUT3ATTN_BIT, 1, 0), 264f10485e7SMark Brown 265f10485e7SMark Brown SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 266f10485e7SMark Brown WM8990_OUT4MUTE_BIT, 1, 0), 267f10485e7SMark Brown SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 268f10485e7SMark Brown WM8990_OUT4ATTN_BIT, 1, 0), 269f10485e7SMark Brown 270f10485e7SMark Brown SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 271f10485e7SMark Brown WM8990_CDMODE_BIT, 1, 0), 272f10485e7SMark Brown 273f10485e7SMark Brown SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 27497bb8129SMark Brown WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 275f10485e7SMark Brown SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 276f10485e7SMark Brown WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 277f10485e7SMark Brown SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 278f10485e7SMark Brown WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 27997bb8129SMark Brown SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 28097bb8129SMark Brown WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 28197bb8129SMark Brown SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 28297bb8129SMark Brown WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 283f10485e7SMark Brown 284f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 285f10485e7SMark Brown WM8990_LEFT_DAC_DIGITAL_VOLUME, 286f10485e7SMark Brown WM8990_DACL_VOL_SHIFT, 287f10485e7SMark Brown WM8990_DACL_VOL_MASK, 288f10485e7SMark Brown 0, 289f10485e7SMark Brown out_dac_tlv), 290f10485e7SMark Brown 291f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 292f10485e7SMark Brown WM8990_RIGHT_DAC_DIGITAL_VOLUME, 293f10485e7SMark Brown WM8990_DACR_VOL_SHIFT, 294f10485e7SMark Brown WM8990_DACR_VOL_MASK, 295f10485e7SMark Brown 0, 296f10485e7SMark Brown out_dac_tlv), 297f10485e7SMark Brown 298f10485e7SMark Brown SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 299f10485e7SMark Brown SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 300f10485e7SMark Brown 301f10485e7SMark Brown SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 302f10485e7SMark Brown WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 303f10485e7SMark Brown out_sidetone_tlv), 304f10485e7SMark Brown SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 305f10485e7SMark Brown WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 306f10485e7SMark Brown out_sidetone_tlv), 307f10485e7SMark Brown 308f10485e7SMark Brown SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 309f10485e7SMark Brown WM8990_ADC_HPF_ENA_BIT, 1, 0), 310f10485e7SMark Brown 311f10485e7SMark Brown SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 312f10485e7SMark Brown 313f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 314f10485e7SMark Brown WM8990_LEFT_ADC_DIGITAL_VOLUME, 315f10485e7SMark Brown WM8990_ADCL_VOL_SHIFT, 316f10485e7SMark Brown WM8990_ADCL_VOL_MASK, 317f10485e7SMark Brown 0, 318f10485e7SMark Brown in_adc_tlv), 319f10485e7SMark Brown 320f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 321f10485e7SMark Brown WM8990_RIGHT_ADC_DIGITAL_VOLUME, 322f10485e7SMark Brown WM8990_ADCR_VOL_SHIFT, 323f10485e7SMark Brown WM8990_ADCR_VOL_MASK, 324f10485e7SMark Brown 0, 325f10485e7SMark Brown in_adc_tlv), 326f10485e7SMark Brown 327f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 328f10485e7SMark Brown WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 329f10485e7SMark Brown WM8990_LIN12VOL_SHIFT, 330f10485e7SMark Brown WM8990_LIN12VOL_MASK, 331f10485e7SMark Brown 0, 332f10485e7SMark Brown in_pga_tlv), 333f10485e7SMark Brown 334f10485e7SMark Brown SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 335f10485e7SMark Brown WM8990_LI12ZC_BIT, 1, 0), 336f10485e7SMark Brown 337f10485e7SMark Brown SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 338f10485e7SMark Brown WM8990_LI12MUTE_BIT, 1, 0), 339f10485e7SMark Brown 340f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 341f10485e7SMark Brown WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 342f10485e7SMark Brown WM8990_LIN34VOL_SHIFT, 343f10485e7SMark Brown WM8990_LIN34VOL_MASK, 344f10485e7SMark Brown 0, 345f10485e7SMark Brown in_pga_tlv), 346f10485e7SMark Brown 347f10485e7SMark Brown SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 348f10485e7SMark Brown WM8990_LI34ZC_BIT, 1, 0), 349f10485e7SMark Brown 350f10485e7SMark Brown SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 351f10485e7SMark Brown WM8990_LI34MUTE_BIT, 1, 0), 352f10485e7SMark Brown 353f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 354f10485e7SMark Brown WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 355f10485e7SMark Brown WM8990_RIN12VOL_SHIFT, 356f10485e7SMark Brown WM8990_RIN12VOL_MASK, 357f10485e7SMark Brown 0, 358f10485e7SMark Brown in_pga_tlv), 359f10485e7SMark Brown 360f10485e7SMark Brown SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 361f10485e7SMark Brown WM8990_RI12ZC_BIT, 1, 0), 362f10485e7SMark Brown 363f10485e7SMark Brown SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 364f10485e7SMark Brown WM8990_RI12MUTE_BIT, 1, 0), 365f10485e7SMark Brown 366f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 367f10485e7SMark Brown WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 368f10485e7SMark Brown WM8990_RIN34VOL_SHIFT, 369f10485e7SMark Brown WM8990_RIN34VOL_MASK, 370f10485e7SMark Brown 0, 371f10485e7SMark Brown in_pga_tlv), 372f10485e7SMark Brown 373f10485e7SMark Brown SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 374f10485e7SMark Brown WM8990_RI34ZC_BIT, 1, 0), 375f10485e7SMark Brown 376f10485e7SMark Brown SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 377f10485e7SMark Brown WM8990_RI34MUTE_BIT, 1, 0), 378f10485e7SMark Brown 379f10485e7SMark Brown }; 380f10485e7SMark Brown 381f10485e7SMark Brown /* 382f10485e7SMark Brown * _DAPM_ Controls 383f10485e7SMark Brown */ 384f10485e7SMark Brown 385f10485e7SMark Brown static int inmixer_event(struct snd_soc_dapm_widget *w, 386f10485e7SMark Brown struct snd_kcontrol *kcontrol, int event) 387f10485e7SMark Brown { 388f10485e7SMark Brown u16 reg, fakepower; 389f10485e7SMark Brown 3908d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2); 3918d50e447SMark Brown fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS); 392f10485e7SMark Brown 393f10485e7SMark Brown if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 394f10485e7SMark Brown (1 << WM8990_AINLMUX_PWR_BIT))) { 395f10485e7SMark Brown reg |= WM8990_AINL_ENA; 396f10485e7SMark Brown } else { 397f10485e7SMark Brown reg &= ~WM8990_AINL_ENA; 398f10485e7SMark Brown } 399f10485e7SMark Brown 400f10485e7SMark Brown if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) | 401f10485e7SMark Brown (1 << WM8990_AINRMUX_PWR_BIT))) { 402f10485e7SMark Brown reg |= WM8990_AINR_ENA; 403f10485e7SMark Brown } else { 404*790f9325SAxel Lin reg &= ~WM8990_AINR_ENA; 405f10485e7SMark Brown } 4068d50e447SMark Brown snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 407f10485e7SMark Brown 408f10485e7SMark Brown return 0; 409f10485e7SMark Brown } 410f10485e7SMark Brown 411f10485e7SMark Brown static int outmixer_event(struct snd_soc_dapm_widget *w, 412f10485e7SMark Brown struct snd_kcontrol *kcontrol, int event) 413f10485e7SMark Brown { 414f10485e7SMark Brown u32 reg_shift = kcontrol->private_value & 0xfff; 415f10485e7SMark Brown int ret = 0; 416f10485e7SMark Brown u16 reg; 417f10485e7SMark Brown 418f10485e7SMark Brown switch (reg_shift) { 419f10485e7SMark Brown case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 4208d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1); 421f10485e7SMark Brown if (reg & WM8990_LDLO) { 422f10485e7SMark Brown printk(KERN_WARNING 423f10485e7SMark Brown "Cannot set as Output Mixer 1 LDLO Set\n"); 424f10485e7SMark Brown ret = -1; 425f10485e7SMark Brown } 426f10485e7SMark Brown break; 427f10485e7SMark Brown case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 4288d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2); 429f10485e7SMark Brown if (reg & WM8990_RDRO) { 430f10485e7SMark Brown printk(KERN_WARNING 431f10485e7SMark Brown "Cannot set as Output Mixer 2 RDRO Set\n"); 432f10485e7SMark Brown ret = -1; 433f10485e7SMark Brown } 434f10485e7SMark Brown break; 435f10485e7SMark Brown case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 4368d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 437f10485e7SMark Brown if (reg & WM8990_LDSPK) { 438f10485e7SMark Brown printk(KERN_WARNING 439f10485e7SMark Brown "Cannot set as Speaker Mixer LDSPK Set\n"); 440f10485e7SMark Brown ret = -1; 441f10485e7SMark Brown } 442f10485e7SMark Brown break; 443f10485e7SMark Brown case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 4448d50e447SMark Brown reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER); 445f10485e7SMark Brown if (reg & WM8990_RDSPK) { 446f10485e7SMark Brown printk(KERN_WARNING 447f10485e7SMark Brown "Cannot set as Speaker Mixer RDSPK Set\n"); 448f10485e7SMark Brown ret = -1; 449f10485e7SMark Brown } 450f10485e7SMark Brown break; 451f10485e7SMark Brown } 452f10485e7SMark Brown 453f10485e7SMark Brown return ret; 454f10485e7SMark Brown } 455f10485e7SMark Brown 456f10485e7SMark Brown /* INMIX dB values */ 457f10485e7SMark Brown static const unsigned int in_mix_tlv[] = { 458f10485e7SMark Brown TLV_DB_RANGE_HEAD(1), 459021f80ccSMark Brown 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0), 460f10485e7SMark Brown }; 461f10485e7SMark Brown 462f10485e7SMark Brown /* Left In PGA Connections */ 463f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 464f10485e7SMark Brown SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 465f10485e7SMark Brown SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 466f10485e7SMark Brown }; 467f10485e7SMark Brown 468f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 469f10485e7SMark Brown SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 470f10485e7SMark Brown SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 471f10485e7SMark Brown }; 472f10485e7SMark Brown 473f10485e7SMark Brown /* Right In PGA Connections */ 474f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 475f10485e7SMark Brown SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 476f10485e7SMark Brown SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 477f10485e7SMark Brown }; 478f10485e7SMark Brown 479f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 480f10485e7SMark Brown SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 481f10485e7SMark Brown SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 482f10485e7SMark Brown }; 483f10485e7SMark Brown 484f10485e7SMark Brown /* INMIXL */ 485f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 486f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 487f10485e7SMark Brown WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 488f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 489f10485e7SMark Brown 7, 0, in_mix_tlv), 490f10485e7SMark Brown SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 491f10485e7SMark Brown 1, 0), 492f10485e7SMark Brown SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 493f10485e7SMark Brown 1, 0), 494f10485e7SMark Brown }; 495f10485e7SMark Brown 496f10485e7SMark Brown /* INMIXR */ 497f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 498f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 499f10485e7SMark Brown WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 500f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 501f10485e7SMark Brown 7, 0, in_mix_tlv), 502f10485e7SMark Brown SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 503f10485e7SMark Brown 1, 0), 504f10485e7SMark Brown SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 505f10485e7SMark Brown 1, 0), 506f10485e7SMark Brown }; 507f10485e7SMark Brown 508f10485e7SMark Brown /* AINLMUX */ 509f10485e7SMark Brown static const char *wm8990_ainlmux[] = 510f10485e7SMark Brown {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 511f10485e7SMark Brown 512f10485e7SMark Brown static const struct soc_enum wm8990_ainlmux_enum = 513f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 514f10485e7SMark Brown ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 515f10485e7SMark Brown 516f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 517f10485e7SMark Brown SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 518f10485e7SMark Brown 519f10485e7SMark Brown /* DIFFINL */ 520f10485e7SMark Brown 521f10485e7SMark Brown /* AINRMUX */ 522f10485e7SMark Brown static const char *wm8990_ainrmux[] = 523f10485e7SMark Brown {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 524f10485e7SMark Brown 525f10485e7SMark Brown static const struct soc_enum wm8990_ainrmux_enum = 526f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 527f10485e7SMark Brown ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 528f10485e7SMark Brown 529f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 530f10485e7SMark Brown SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 531f10485e7SMark Brown 532f10485e7SMark Brown /* RXVOICE */ 533f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 534f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 535f10485e7SMark Brown WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 536f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 537f10485e7SMark Brown WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 538f10485e7SMark Brown }; 539f10485e7SMark Brown 540f10485e7SMark Brown /* LOMIX */ 541f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 542f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 543f10485e7SMark Brown WM8990_LRBLO_BIT, 1, 0), 544f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 545f10485e7SMark Brown WM8990_LLBLO_BIT, 1, 0), 546f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 547f10485e7SMark Brown WM8990_LRI3LO_BIT, 1, 0), 548f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 549f10485e7SMark Brown WM8990_LLI3LO_BIT, 1, 0), 550f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 551f10485e7SMark Brown WM8990_LR12LO_BIT, 1, 0), 552f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 553f10485e7SMark Brown WM8990_LL12LO_BIT, 1, 0), 554f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 555f10485e7SMark Brown WM8990_LDLO_BIT, 1, 0), 556f10485e7SMark Brown }; 557f10485e7SMark Brown 558f10485e7SMark Brown /* ROMIX */ 559f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 560f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 561f10485e7SMark Brown WM8990_RLBRO_BIT, 1, 0), 562f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 563f10485e7SMark Brown WM8990_RRBRO_BIT, 1, 0), 564f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 565f10485e7SMark Brown WM8990_RLI3RO_BIT, 1, 0), 566f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 567f10485e7SMark Brown WM8990_RRI3RO_BIT, 1, 0), 568f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 569f10485e7SMark Brown WM8990_RL12RO_BIT, 1, 0), 570f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 571f10485e7SMark Brown WM8990_RR12RO_BIT, 1, 0), 572f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 573f10485e7SMark Brown WM8990_RDRO_BIT, 1, 0), 574f10485e7SMark Brown }; 575f10485e7SMark Brown 576f10485e7SMark Brown /* LONMIX */ 577f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 578f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 579f10485e7SMark Brown WM8990_LLOPGALON_BIT, 1, 0), 580f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 581f10485e7SMark Brown WM8990_LROPGALON_BIT, 1, 0), 582f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 583f10485e7SMark Brown WM8990_LOPLON_BIT, 1, 0), 584f10485e7SMark Brown }; 585f10485e7SMark Brown 586f10485e7SMark Brown /* LOPMIX */ 587f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 588f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 589f10485e7SMark Brown WM8990_LR12LOP_BIT, 1, 0), 590f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 591f10485e7SMark Brown WM8990_LL12LOP_BIT, 1, 0), 592f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 593f10485e7SMark Brown WM8990_LLOPGALOP_BIT, 1, 0), 594f10485e7SMark Brown }; 595f10485e7SMark Brown 596f10485e7SMark Brown /* RONMIX */ 597f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 598f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 599f10485e7SMark Brown WM8990_RROPGARON_BIT, 1, 0), 600f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 601f10485e7SMark Brown WM8990_RLOPGARON_BIT, 1, 0), 602f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 603f10485e7SMark Brown WM8990_ROPRON_BIT, 1, 0), 604f10485e7SMark Brown }; 605f10485e7SMark Brown 606f10485e7SMark Brown /* ROPMIX */ 607f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 608f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 609f10485e7SMark Brown WM8990_RL12ROP_BIT, 1, 0), 610f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 611f10485e7SMark Brown WM8990_RR12ROP_BIT, 1, 0), 612f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 613f10485e7SMark Brown WM8990_RROPGAROP_BIT, 1, 0), 614f10485e7SMark Brown }; 615f10485e7SMark Brown 616f10485e7SMark Brown /* OUT3MIX */ 617f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 618f10485e7SMark Brown SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 619f10485e7SMark Brown WM8990_LI4O3_BIT, 1, 0), 620f10485e7SMark Brown SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 621f10485e7SMark Brown WM8990_LPGAO3_BIT, 1, 0), 622f10485e7SMark Brown }; 623f10485e7SMark Brown 624f10485e7SMark Brown /* OUT4MIX */ 625f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 626f10485e7SMark Brown SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 627f10485e7SMark Brown WM8990_RPGAO4_BIT, 1, 0), 628f10485e7SMark Brown SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 629f10485e7SMark Brown WM8990_RI4O4_BIT, 1, 0), 630f10485e7SMark Brown }; 631f10485e7SMark Brown 632f10485e7SMark Brown /* SPKMIX */ 633f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 634f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 635f10485e7SMark Brown WM8990_LI2SPK_BIT, 1, 0), 636f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 637f10485e7SMark Brown WM8990_LB2SPK_BIT, 1, 0), 638f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 639f10485e7SMark Brown WM8990_LOPGASPK_BIT, 1, 0), 640f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 641f10485e7SMark Brown WM8990_LDSPK_BIT, 1, 0), 642f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 643f10485e7SMark Brown WM8990_RDSPK_BIT, 1, 0), 644f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 645f10485e7SMark Brown WM8990_ROPGASPK_BIT, 1, 0), 646f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 647f10485e7SMark Brown WM8990_RL12ROP_BIT, 1, 0), 648f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 649f10485e7SMark Brown WM8990_RI2SPK_BIT, 1, 0), 650f10485e7SMark Brown }; 651f10485e7SMark Brown 652f10485e7SMark Brown static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 653f10485e7SMark Brown /* Input Side */ 654f10485e7SMark Brown /* Input Lines */ 655f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN1"), 656f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN2"), 657f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN3"), 658f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN4/RXN"), 659f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN3"), 660f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN4/RXP"), 661f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN1"), 662f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN2"), 663f10485e7SMark Brown SND_SOC_DAPM_INPUT("Internal ADC Source"), 664f10485e7SMark Brown 665f10485e7SMark Brown /* DACs */ 666f10485e7SMark Brown SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 667f10485e7SMark Brown WM8990_ADCL_ENA_BIT, 0), 668f10485e7SMark Brown SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 669f10485e7SMark Brown WM8990_ADCR_ENA_BIT, 0), 670f10485e7SMark Brown 671f10485e7SMark Brown /* Input PGAs */ 672f10485e7SMark Brown SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 673f10485e7SMark Brown 0, &wm8990_dapm_lin12_pga_controls[0], 674f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 675f10485e7SMark Brown SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 676f10485e7SMark Brown 0, &wm8990_dapm_lin34_pga_controls[0], 677f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 678f10485e7SMark Brown SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 679f10485e7SMark Brown 0, &wm8990_dapm_rin12_pga_controls[0], 680f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 681f10485e7SMark Brown SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 682f10485e7SMark Brown 0, &wm8990_dapm_rin34_pga_controls[0], 683f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 684f10485e7SMark Brown 685f10485e7SMark Brown /* INMIXL */ 686f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0, 687f10485e7SMark Brown &wm8990_dapm_inmixl_controls[0], 688f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_inmixl_controls), 689f10485e7SMark Brown inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 690f10485e7SMark Brown 691f10485e7SMark Brown /* AINLMUX */ 69297a775c4SJinyoung Park SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0, 693f10485e7SMark Brown &wm8990_dapm_ainlmux_controls, inmixer_event, 694f10485e7SMark Brown SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 695f10485e7SMark Brown 696f10485e7SMark Brown /* INMIXR */ 697f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0, 698f10485e7SMark Brown &wm8990_dapm_inmixr_controls[0], 699f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_inmixr_controls), 700f10485e7SMark Brown inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 701f10485e7SMark Brown 702f10485e7SMark Brown /* AINRMUX */ 70397a775c4SJinyoung Park SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0, 704f10485e7SMark Brown &wm8990_dapm_ainrmux_controls, inmixer_event, 705f10485e7SMark Brown SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 706f10485e7SMark Brown 707f10485e7SMark Brown /* Output Side */ 708f10485e7SMark Brown /* DACs */ 709f10485e7SMark Brown SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 710f10485e7SMark Brown WM8990_DACL_ENA_BIT, 0), 711f10485e7SMark Brown SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 712f10485e7SMark Brown WM8990_DACR_ENA_BIT, 0), 713f10485e7SMark Brown 714f10485e7SMark Brown /* LOMIX */ 715f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 716f10485e7SMark Brown 0, &wm8990_dapm_lomix_controls[0], 717f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lomix_controls), 718f10485e7SMark Brown outmixer_event, SND_SOC_DAPM_PRE_REG), 719f10485e7SMark Brown 720f10485e7SMark Brown /* LONMIX */ 721f10485e7SMark Brown SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 722f10485e7SMark Brown &wm8990_dapm_lonmix_controls[0], 723f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 724f10485e7SMark Brown 725f10485e7SMark Brown /* LOPMIX */ 726f10485e7SMark Brown SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 727f10485e7SMark Brown &wm8990_dapm_lopmix_controls[0], 728f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 729f10485e7SMark Brown 730f10485e7SMark Brown /* OUT3MIX */ 731f10485e7SMark Brown SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 732f10485e7SMark Brown &wm8990_dapm_out3mix_controls[0], 733f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 734f10485e7SMark Brown 735f10485e7SMark Brown /* SPKMIX */ 736f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 737f10485e7SMark Brown &wm8990_dapm_spkmix_controls[0], 738f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 739f10485e7SMark Brown SND_SOC_DAPM_PRE_REG), 740f10485e7SMark Brown 741f10485e7SMark Brown /* OUT4MIX */ 742f10485e7SMark Brown SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 743f10485e7SMark Brown &wm8990_dapm_out4mix_controls[0], 744f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 745f10485e7SMark Brown 746f10485e7SMark Brown /* ROPMIX */ 747f10485e7SMark Brown SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 748f10485e7SMark Brown &wm8990_dapm_ropmix_controls[0], 749f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 750f10485e7SMark Brown 751f10485e7SMark Brown /* RONMIX */ 752f10485e7SMark Brown SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 753f10485e7SMark Brown &wm8990_dapm_ronmix_controls[0], 754f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 755f10485e7SMark Brown 756f10485e7SMark Brown /* ROMIX */ 757f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 758f10485e7SMark Brown 0, &wm8990_dapm_romix_controls[0], 759f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_romix_controls), 760f10485e7SMark Brown outmixer_event, SND_SOC_DAPM_PRE_REG), 761f10485e7SMark Brown 762f10485e7SMark Brown /* LOUT PGA */ 763f10485e7SMark Brown SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 764f10485e7SMark Brown NULL, 0), 765f10485e7SMark Brown 766f10485e7SMark Brown /* ROUT PGA */ 767f10485e7SMark Brown SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 768f10485e7SMark Brown NULL, 0), 769f10485e7SMark Brown 770f10485e7SMark Brown /* LOPGA */ 771f10485e7SMark Brown SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 772f10485e7SMark Brown NULL, 0), 773f10485e7SMark Brown 774f10485e7SMark Brown /* ROPGA */ 775f10485e7SMark Brown SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 776f10485e7SMark Brown NULL, 0), 777f10485e7SMark Brown 778f10485e7SMark Brown /* MICBIAS */ 779f10485e7SMark Brown SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1, 780f10485e7SMark Brown WM8990_MICBIAS_ENA_BIT, 0), 781f10485e7SMark Brown 782f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LON"), 783f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LOP"), 784f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("OUT3"), 785f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LOUT"), 786f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("SPKN"), 787f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("SPKP"), 788f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("ROUT"), 789f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("OUT4"), 790f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("ROP"), 791f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("RON"), 792f10485e7SMark Brown 793f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 794f10485e7SMark Brown }; 795f10485e7SMark Brown 796f10485e7SMark Brown static const struct snd_soc_dapm_route audio_map[] = { 797f10485e7SMark Brown /* Make DACs turn on when playing even if not mixed into any outputs */ 798f10485e7SMark Brown {"Internal DAC Sink", NULL, "Left DAC"}, 799f10485e7SMark Brown {"Internal DAC Sink", NULL, "Right DAC"}, 800f10485e7SMark Brown 801f10485e7SMark Brown /* Make ADCs turn on when recording even if not mixed from any inputs */ 802f10485e7SMark Brown {"Left ADC", NULL, "Internal ADC Source"}, 803f10485e7SMark Brown {"Right ADC", NULL, "Internal ADC Source"}, 804f10485e7SMark Brown 805f10485e7SMark Brown /* Input Side */ 806f10485e7SMark Brown /* LIN12 PGA */ 807f10485e7SMark Brown {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 808f10485e7SMark Brown {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 809f10485e7SMark Brown /* LIN34 PGA */ 810f10485e7SMark Brown {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 81197a775c4SJinyoung Park {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 812f10485e7SMark Brown /* INMIXL */ 813f10485e7SMark Brown {"INMIXL", "Record Left Volume", "LOMIX"}, 814f10485e7SMark Brown {"INMIXL", "LIN2 Volume", "LIN2"}, 815f10485e7SMark Brown {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 816f10485e7SMark Brown {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 81797a775c4SJinyoung Park /* AINLMUX */ 81897a775c4SJinyoung Park {"AINLMUX", "INMIXL Mix", "INMIXL"}, 81997a775c4SJinyoung Park {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 82097a775c4SJinyoung Park {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 82197a775c4SJinyoung Park {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"}, 82297a775c4SJinyoung Park {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"}, 823f10485e7SMark Brown /* ADC */ 82497a775c4SJinyoung Park {"Left ADC", NULL, "AINLMUX"}, 825f10485e7SMark Brown 826f10485e7SMark Brown /* RIN12 PGA */ 827f10485e7SMark Brown {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 828f10485e7SMark Brown {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 829f10485e7SMark Brown /* RIN34 PGA */ 830f10485e7SMark Brown {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 83197a775c4SJinyoung Park {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 832f10485e7SMark Brown /* INMIXL */ 833f10485e7SMark Brown {"INMIXR", "Record Right Volume", "ROMIX"}, 834f10485e7SMark Brown {"INMIXR", "RIN2 Volume", "RIN2"}, 835f10485e7SMark Brown {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 836f10485e7SMark Brown {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 83797a775c4SJinyoung Park /* AINRMUX */ 83897a775c4SJinyoung Park {"AINRMUX", "INMIXR Mix", "INMIXR"}, 83997a775c4SJinyoung Park {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 84097a775c4SJinyoung Park {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 84197a775c4SJinyoung Park {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"}, 84297a775c4SJinyoung Park {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"}, 843f10485e7SMark Brown /* ADC */ 84497a775c4SJinyoung Park {"Right ADC", NULL, "AINRMUX"}, 845f10485e7SMark Brown 846f10485e7SMark Brown /* LOMIX */ 847f10485e7SMark Brown {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 848f10485e7SMark Brown {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 849f10485e7SMark Brown {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 850f10485e7SMark Brown {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 851f10485e7SMark Brown {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 852f10485e7SMark Brown {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 853f10485e7SMark Brown {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 854f10485e7SMark Brown 855f10485e7SMark Brown /* ROMIX */ 856f10485e7SMark Brown {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 857f10485e7SMark Brown {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 858f10485e7SMark Brown {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 859f10485e7SMark Brown {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 860f10485e7SMark Brown {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 861f10485e7SMark Brown {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 862f10485e7SMark Brown {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 863f10485e7SMark Brown 864f10485e7SMark Brown /* SPKMIX */ 865f10485e7SMark Brown {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 866f10485e7SMark Brown {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 867f10485e7SMark Brown {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 868f10485e7SMark Brown {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 869f10485e7SMark Brown {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 870f10485e7SMark Brown {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 871f10485e7SMark Brown {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 872436a7459SMark Brown {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 873f10485e7SMark Brown 874f10485e7SMark Brown /* LONMIX */ 875f10485e7SMark Brown {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 876f10485e7SMark Brown {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 877f10485e7SMark Brown {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 878f10485e7SMark Brown 879f10485e7SMark Brown /* LOPMIX */ 880f10485e7SMark Brown {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 881f10485e7SMark Brown {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 882f10485e7SMark Brown {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 883f10485e7SMark Brown 884f10485e7SMark Brown /* OUT3MIX */ 88597a775c4SJinyoung Park {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 886f10485e7SMark Brown {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 887f10485e7SMark Brown 888f10485e7SMark Brown /* OUT4MIX */ 889f10485e7SMark Brown {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 890f10485e7SMark Brown {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 891f10485e7SMark Brown 892f10485e7SMark Brown /* RONMIX */ 893f10485e7SMark Brown {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 894f10485e7SMark Brown {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 895f10485e7SMark Brown {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 896f10485e7SMark Brown 897f10485e7SMark Brown /* ROPMIX */ 898f10485e7SMark Brown {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 899f10485e7SMark Brown {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 900f10485e7SMark Brown {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 901f10485e7SMark Brown 902f10485e7SMark Brown /* Out Mixer PGAs */ 903f10485e7SMark Brown {"LOPGA", NULL, "LOMIX"}, 904f10485e7SMark Brown {"ROPGA", NULL, "ROMIX"}, 905f10485e7SMark Brown 906f10485e7SMark Brown {"LOUT PGA", NULL, "LOMIX"}, 907f10485e7SMark Brown {"ROUT PGA", NULL, "ROMIX"}, 908f10485e7SMark Brown 909f10485e7SMark Brown /* Output Pins */ 910f10485e7SMark Brown {"LON", NULL, "LONMIX"}, 911f10485e7SMark Brown {"LOP", NULL, "LOPMIX"}, 91297a775c4SJinyoung Park {"OUT3", NULL, "OUT3MIX"}, 913f10485e7SMark Brown {"LOUT", NULL, "LOUT PGA"}, 914f10485e7SMark Brown {"SPKN", NULL, "SPKMIX"}, 915f10485e7SMark Brown {"ROUT", NULL, "ROUT PGA"}, 916f10485e7SMark Brown {"OUT4", NULL, "OUT4MIX"}, 917f10485e7SMark Brown {"ROP", NULL, "ROPMIX"}, 918f10485e7SMark Brown {"RON", NULL, "RONMIX"}, 919f10485e7SMark Brown }; 920f10485e7SMark Brown 921f10485e7SMark Brown static int wm8990_add_widgets(struct snd_soc_codec *codec) 922f10485e7SMark Brown { 923ce6120ccSLiam Girdwood struct snd_soc_dapm_context *dapm = &codec->dapm; 924f10485e7SMark Brown 925ce6120ccSLiam Girdwood snd_soc_dapm_new_controls(dapm, wm8990_dapm_widgets, 926ce6120ccSLiam Girdwood ARRAY_SIZE(wm8990_dapm_widgets)); 927f10485e7SMark Brown /* set up the WM8990 audio map */ 928ce6120ccSLiam Girdwood snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); 929f10485e7SMark Brown 930f10485e7SMark Brown return 0; 931f10485e7SMark Brown } 932f10485e7SMark Brown 933f10485e7SMark Brown /* PLL divisors */ 934f10485e7SMark Brown struct _pll_div { 935f10485e7SMark Brown u32 div2; 936f10485e7SMark Brown u32 n; 937f10485e7SMark Brown u32 k; 938f10485e7SMark Brown }; 939f10485e7SMark Brown 940f10485e7SMark Brown /* The size in bits of the pll divide multiplied by 10 941f10485e7SMark Brown * to allow rounding later */ 942f10485e7SMark Brown #define FIXED_PLL_SIZE ((1 << 16) * 10) 943f10485e7SMark Brown 944f10485e7SMark Brown static void pll_factors(struct _pll_div *pll_div, unsigned int target, 945f10485e7SMark Brown unsigned int source) 946f10485e7SMark Brown { 947f10485e7SMark Brown u64 Kpart; 948f10485e7SMark Brown unsigned int K, Ndiv, Nmod; 949f10485e7SMark Brown 950f10485e7SMark Brown 951f10485e7SMark Brown Ndiv = target / source; 952f10485e7SMark Brown if (Ndiv < 6) { 953f10485e7SMark Brown source >>= 1; 954f10485e7SMark Brown pll_div->div2 = 1; 955f10485e7SMark Brown Ndiv = target / source; 956f10485e7SMark Brown } else 957f10485e7SMark Brown pll_div->div2 = 0; 958f10485e7SMark Brown 959f10485e7SMark Brown if ((Ndiv < 6) || (Ndiv > 12)) 960f10485e7SMark Brown printk(KERN_WARNING 961449bd54dSRoel Kluin "WM8990 N value outwith recommended range! N = %u\n", Ndiv); 962f10485e7SMark Brown 963f10485e7SMark Brown pll_div->n = Ndiv; 964f10485e7SMark Brown Nmod = target % source; 965f10485e7SMark Brown Kpart = FIXED_PLL_SIZE * (long long)Nmod; 966f10485e7SMark Brown 967f10485e7SMark Brown do_div(Kpart, source); 968f10485e7SMark Brown 969f10485e7SMark Brown K = Kpart & 0xFFFFFFFF; 970f10485e7SMark Brown 971f10485e7SMark Brown /* Check if we need to round */ 972f10485e7SMark Brown if ((K % 10) >= 5) 973f10485e7SMark Brown K += 5; 974f10485e7SMark Brown 975f10485e7SMark Brown /* Move down to proper range now rounding is done */ 976f10485e7SMark Brown K /= 10; 977f10485e7SMark Brown 978f10485e7SMark Brown pll_div->k = K; 979f10485e7SMark Brown } 980f10485e7SMark Brown 98185488037SMark Brown static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 98285488037SMark Brown int source, unsigned int freq_in, unsigned int freq_out) 983f10485e7SMark Brown { 984f10485e7SMark Brown u16 reg; 985f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 986f10485e7SMark Brown struct _pll_div pll_div; 987f10485e7SMark Brown 988f10485e7SMark Brown if (freq_in && freq_out) { 989f10485e7SMark Brown pll_factors(&pll_div, freq_out * 4, freq_in); 990f10485e7SMark Brown 991f10485e7SMark Brown /* Turn on PLL */ 9928d50e447SMark Brown reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 993f10485e7SMark Brown reg |= WM8990_PLL_ENA; 9948d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 995f10485e7SMark Brown 996f10485e7SMark Brown /* sysclk comes from PLL */ 9978d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2); 9988d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 999f10485e7SMark Brown 10003ad2f3fbSDaniel Mack /* set up N , fractional mode and pre-divisor if necessary */ 10018d50e447SMark Brown snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 1002f10485e7SMark Brown (pll_div.div2?WM8990_PRESCALE:0)); 10038d50e447SMark Brown snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 10048d50e447SMark Brown snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 1005f10485e7SMark Brown } else { 1006f10485e7SMark Brown /* Turn on PLL */ 10078d50e447SMark Brown reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 1008f10485e7SMark Brown reg &= ~WM8990_PLL_ENA; 10098d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1010f10485e7SMark Brown } 1011f10485e7SMark Brown return 0; 1012f10485e7SMark Brown } 1013f10485e7SMark Brown 1014f10485e7SMark Brown /* 1015f10485e7SMark Brown * Clock after PLL and dividers 1016f10485e7SMark Brown */ 1017e550e17fSLiam Girdwood static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1018f10485e7SMark Brown int clk_id, unsigned int freq, int dir) 1019f10485e7SMark Brown { 1020f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1021b2c812e2SMark Brown struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec); 1022f10485e7SMark Brown 1023f10485e7SMark Brown wm8990->sysclk = freq; 1024f10485e7SMark Brown return 0; 1025f10485e7SMark Brown } 1026f10485e7SMark Brown 1027f10485e7SMark Brown /* 1028f10485e7SMark Brown * Set's ADC and Voice DAC format. 1029f10485e7SMark Brown */ 1030e550e17fSLiam Girdwood static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 1031f10485e7SMark Brown unsigned int fmt) 1032f10485e7SMark Brown { 1033f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1034f10485e7SMark Brown u16 audio1, audio3; 1035f10485e7SMark Brown 10368d50e447SMark Brown audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 10378d50e447SMark Brown audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3); 1038f10485e7SMark Brown 1039f10485e7SMark Brown /* set master/slave audio interface */ 1040f10485e7SMark Brown switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1041f10485e7SMark Brown case SND_SOC_DAIFMT_CBS_CFS: 1042f10485e7SMark Brown audio3 &= ~WM8990_AIF_MSTR1; 1043f10485e7SMark Brown break; 1044f10485e7SMark Brown case SND_SOC_DAIFMT_CBM_CFM: 1045f10485e7SMark Brown audio3 |= WM8990_AIF_MSTR1; 1046f10485e7SMark Brown break; 1047f10485e7SMark Brown default: 1048f10485e7SMark Brown return -EINVAL; 1049f10485e7SMark Brown } 1050f10485e7SMark Brown 1051f10485e7SMark Brown audio1 &= ~WM8990_AIF_FMT_MASK; 1052f10485e7SMark Brown 1053f10485e7SMark Brown /* interface format */ 1054f10485e7SMark Brown switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1055f10485e7SMark Brown case SND_SOC_DAIFMT_I2S: 1056f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_I2S; 1057f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1058f10485e7SMark Brown break; 1059f10485e7SMark Brown case SND_SOC_DAIFMT_RIGHT_J: 1060f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_RIGHTJ; 1061f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1062f10485e7SMark Brown break; 1063f10485e7SMark Brown case SND_SOC_DAIFMT_LEFT_J: 1064f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_LEFTJ; 1065f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1066f10485e7SMark Brown break; 1067f10485e7SMark Brown case SND_SOC_DAIFMT_DSP_A: 1068f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_DSP; 1069f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1070f10485e7SMark Brown break; 1071f10485e7SMark Brown case SND_SOC_DAIFMT_DSP_B: 1072f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1073f10485e7SMark Brown break; 1074f10485e7SMark Brown default: 1075f10485e7SMark Brown return -EINVAL; 1076f10485e7SMark Brown } 1077f10485e7SMark Brown 10788d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 10798d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1080f10485e7SMark Brown return 0; 1081f10485e7SMark Brown } 1082f10485e7SMark Brown 1083e550e17fSLiam Girdwood static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1084f10485e7SMark Brown int div_id, int div) 1085f10485e7SMark Brown { 1086f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1087f10485e7SMark Brown u16 reg; 1088f10485e7SMark Brown 1089f10485e7SMark Brown switch (div_id) { 1090f10485e7SMark Brown case WM8990_MCLK_DIV: 10918d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1092f10485e7SMark Brown ~WM8990_MCLK_DIV_MASK; 10938d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1094f10485e7SMark Brown break; 1095f10485e7SMark Brown case WM8990_DACCLK_DIV: 10968d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1097f10485e7SMark Brown ~WM8990_DAC_CLKDIV_MASK; 10988d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1099f10485e7SMark Brown break; 1100f10485e7SMark Brown case WM8990_ADCCLK_DIV: 11018d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_2) & 1102f10485e7SMark Brown ~WM8990_ADC_CLKDIV_MASK; 11038d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_2, reg | div); 1104f10485e7SMark Brown break; 1105f10485e7SMark Brown case WM8990_BCLK_DIV: 11068d50e447SMark Brown reg = snd_soc_read(codec, WM8990_CLOCKING_1) & 1107f10485e7SMark Brown ~WM8990_BCLK_DIV_MASK; 11088d50e447SMark Brown snd_soc_write(codec, WM8990_CLOCKING_1, reg | div); 1109f10485e7SMark Brown break; 1110f10485e7SMark Brown default: 1111f10485e7SMark Brown return -EINVAL; 1112f10485e7SMark Brown } 1113f10485e7SMark Brown 1114f10485e7SMark Brown return 0; 1115f10485e7SMark Brown } 1116f10485e7SMark Brown 1117f10485e7SMark Brown /* 1118f10485e7SMark Brown * Set PCM DAI bit size and sample rate. 1119f10485e7SMark Brown */ 1120f10485e7SMark Brown static int wm8990_hw_params(struct snd_pcm_substream *substream, 1121dee89c4dSMark Brown struct snd_pcm_hw_params *params, 1122dee89c4dSMark Brown struct snd_soc_dai *dai) 1123f10485e7SMark Brown { 1124f10485e7SMark Brown struct snd_soc_pcm_runtime *rtd = substream->private_data; 1125f0fba2adSLiam Girdwood struct snd_soc_codec *codec = rtd->codec; 11268d50e447SMark Brown u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1127f10485e7SMark Brown 1128f10485e7SMark Brown audio1 &= ~WM8990_AIF_WL_MASK; 1129f10485e7SMark Brown /* bit size */ 1130f10485e7SMark Brown switch (params_format(params)) { 1131f10485e7SMark Brown case SNDRV_PCM_FORMAT_S16_LE: 1132f10485e7SMark Brown break; 1133f10485e7SMark Brown case SNDRV_PCM_FORMAT_S20_3LE: 1134f10485e7SMark Brown audio1 |= WM8990_AIF_WL_20BITS; 1135f10485e7SMark Brown break; 1136f10485e7SMark Brown case SNDRV_PCM_FORMAT_S24_LE: 1137f10485e7SMark Brown audio1 |= WM8990_AIF_WL_24BITS; 1138f10485e7SMark Brown break; 1139f10485e7SMark Brown case SNDRV_PCM_FORMAT_S32_LE: 1140f10485e7SMark Brown audio1 |= WM8990_AIF_WL_32BITS; 1141f10485e7SMark Brown break; 1142f10485e7SMark Brown } 1143f10485e7SMark Brown 11448d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1145f10485e7SMark Brown return 0; 1146f10485e7SMark Brown } 1147f10485e7SMark Brown 1148e550e17fSLiam Girdwood static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1149f10485e7SMark Brown { 1150f10485e7SMark Brown struct snd_soc_codec *codec = dai->codec; 1151f10485e7SMark Brown u16 val; 1152f10485e7SMark Brown 11538d50e447SMark Brown val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1154f10485e7SMark Brown 1155f10485e7SMark Brown if (mute) 11568d50e447SMark Brown snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1157f10485e7SMark Brown else 11588d50e447SMark Brown snd_soc_write(codec, WM8990_DAC_CTRL, val); 1159f10485e7SMark Brown 1160f10485e7SMark Brown return 0; 1161f10485e7SMark Brown } 1162f10485e7SMark Brown 1163f10485e7SMark Brown static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1164f10485e7SMark Brown enum snd_soc_bias_level level) 1165f10485e7SMark Brown { 1166416a0ce5SAxel Lin int ret; 1167f10485e7SMark Brown u16 val; 1168f10485e7SMark Brown 1169f10485e7SMark Brown switch (level) { 1170f10485e7SMark Brown case SND_SOC_BIAS_ON: 1171f10485e7SMark Brown break; 11722adb9833SMark Brown 1173f10485e7SMark Brown case SND_SOC_BIAS_PREPARE: 11742adb9833SMark Brown /* VMID=2*50k */ 11758d50e447SMark Brown val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) & 11762adb9833SMark Brown ~WM8990_VMID_MODE_MASK; 11778d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1178f10485e7SMark Brown break; 11792adb9833SMark Brown 1180f10485e7SMark Brown case SND_SOC_BIAS_STANDBY: 1181ce6120ccSLiam Girdwood if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1182416a0ce5SAxel Lin ret = snd_soc_cache_sync(codec); 1183416a0ce5SAxel Lin if (ret < 0) { 1184416a0ce5SAxel Lin dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1185416a0ce5SAxel Lin return ret; 1186416a0ce5SAxel Lin } 1187416a0ce5SAxel Lin 1188f10485e7SMark Brown /* Enable all output discharge bits */ 11898d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1190f10485e7SMark Brown WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1191f10485e7SMark Brown WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1192f10485e7SMark Brown WM8990_DIS_ROUT); 1193f10485e7SMark Brown 1194f10485e7SMark Brown /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 11958d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1196f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1197f10485e7SMark Brown WM8990_VMIDTOG); 1198f10485e7SMark Brown 1199f10485e7SMark Brown /* Delay to allow output caps to discharge */ 12007ebcf5d6SDimitris Papastamos msleep(300); 1201f10485e7SMark Brown 1202f10485e7SMark Brown /* Disable VMIDTOG */ 12038d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1204f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL); 1205f10485e7SMark Brown 1206f10485e7SMark Brown /* disable all output discharge bits */ 12078d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP1, 0); 1208f10485e7SMark Brown 1209f10485e7SMark Brown /* Enable outputs */ 12108d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1211f10485e7SMark Brown 12127ebcf5d6SDimitris Papastamos msleep(50); 1213f10485e7SMark Brown 1214f10485e7SMark Brown /* Enable VMID at 2x50k */ 12158d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1216f10485e7SMark Brown 12177ebcf5d6SDimitris Papastamos msleep(100); 1218f10485e7SMark Brown 1219f10485e7SMark Brown /* Enable VREF */ 12208d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1221f10485e7SMark Brown 12227ebcf5d6SDimitris Papastamos msleep(600); 1223f10485e7SMark Brown 1224f10485e7SMark Brown /* Enable BUFIOEN */ 12258d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1226f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1227f10485e7SMark Brown WM8990_BUFIOEN); 1228f10485e7SMark Brown 1229f10485e7SMark Brown /* Disable outputs */ 12308d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1231f10485e7SMark Brown 1232f10485e7SMark Brown /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 12338d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1234f10485e7SMark Brown 1235be1b87c7SMark Brown /* Enable workaround for ADC clocking issue. */ 12368d50e447SMark Brown snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 12378d50e447SMark Brown snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003); 12388d50e447SMark Brown snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1239f10485e7SMark Brown } 12402adb9833SMark Brown 12412adb9833SMark Brown /* VMID=2*250k */ 12428d50e447SMark Brown val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) & 12432adb9833SMark Brown ~WM8990_VMID_MODE_MASK; 12448d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1245f10485e7SMark Brown break; 1246f10485e7SMark Brown 1247f10485e7SMark Brown case SND_SOC_BIAS_OFF: 1248f10485e7SMark Brown /* Enable POBCTRL and SOFT_ST */ 12498d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1250f10485e7SMark Brown WM8990_POBCTRL | WM8990_BUFIOEN); 1251f10485e7SMark Brown 1252f10485e7SMark Brown /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 12538d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1254f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1255f10485e7SMark Brown WM8990_BUFIOEN); 1256f10485e7SMark Brown 1257f10485e7SMark Brown /* mute DAC */ 12588d50e447SMark Brown val = snd_soc_read(codec, WM8990_DAC_CTRL); 12598d50e447SMark Brown snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1260f10485e7SMark Brown 1261f10485e7SMark Brown /* Enable any disabled outputs */ 12628d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1263f10485e7SMark Brown 1264f10485e7SMark Brown /* Disable VMID */ 12658d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1266f10485e7SMark Brown 12677ebcf5d6SDimitris Papastamos msleep(300); 1268f10485e7SMark Brown 1269f10485e7SMark Brown /* Enable all output discharge bits */ 12708d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1271f10485e7SMark Brown WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1272f10485e7SMark Brown WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1273f10485e7SMark Brown WM8990_DIS_ROUT); 1274f10485e7SMark Brown 1275f10485e7SMark Brown /* Disable VREF */ 12768d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1277f10485e7SMark Brown 1278f10485e7SMark Brown /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 12798d50e447SMark Brown snd_soc_write(codec, WM8990_ANTIPOP2, 0x0); 1280f10485e7SMark Brown break; 1281f10485e7SMark Brown } 1282f10485e7SMark Brown 1283ce6120ccSLiam Girdwood codec->dapm.bias_level = level; 1284f10485e7SMark Brown return 0; 1285f10485e7SMark Brown } 1286f10485e7SMark Brown 1287f10485e7SMark Brown #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1288f10485e7SMark Brown SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1289f10485e7SMark Brown SNDRV_PCM_RATE_48000) 1290f10485e7SMark Brown 1291f10485e7SMark Brown #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1292f10485e7SMark Brown SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1293f10485e7SMark Brown 1294f10485e7SMark Brown /* 1295f10485e7SMark Brown * The WM8990 supports 2 different and mutually exclusive DAI 1296f10485e7SMark Brown * configurations. 1297f10485e7SMark Brown * 1298f10485e7SMark Brown * 1. ADC/DAC on Primary Interface 1299f10485e7SMark Brown * 2. ADC on Primary Interface/DAC on secondary 1300f10485e7SMark Brown */ 13016335d055SEric Miao static struct snd_soc_dai_ops wm8990_dai_ops = { 13026335d055SEric Miao .hw_params = wm8990_hw_params, 13036335d055SEric Miao .digital_mute = wm8990_mute, 13046335d055SEric Miao .set_fmt = wm8990_set_dai_fmt, 13056335d055SEric Miao .set_clkdiv = wm8990_set_dai_clkdiv, 13066335d055SEric Miao .set_pll = wm8990_set_dai_pll, 13076335d055SEric Miao .set_sysclk = wm8990_set_dai_sysclk, 13086335d055SEric Miao }; 13096335d055SEric Miao 1310f0fba2adSLiam Girdwood static struct snd_soc_dai_driver wm8990_dai = { 1311f10485e7SMark Brown /* ADC/DAC on primary */ 1312f0fba2adSLiam Girdwood .name = "wm8990-hifi", 1313f10485e7SMark Brown .playback = { 1314f10485e7SMark Brown .stream_name = "Playback", 1315f10485e7SMark Brown .channels_min = 1, 1316f10485e7SMark Brown .channels_max = 2, 1317f10485e7SMark Brown .rates = WM8990_RATES, 1318f10485e7SMark Brown .formats = WM8990_FORMATS,}, 1319f10485e7SMark Brown .capture = { 1320f10485e7SMark Brown .stream_name = "Capture", 1321f10485e7SMark Brown .channels_min = 1, 1322f10485e7SMark Brown .channels_max = 2, 1323f10485e7SMark Brown .rates = WM8990_RATES, 1324f10485e7SMark Brown .formats = WM8990_FORMATS,}, 13256335d055SEric Miao .ops = &wm8990_dai_ops, 1326f10485e7SMark Brown }; 1327f10485e7SMark Brown 1328f0fba2adSLiam Girdwood static int wm8990_suspend(struct snd_soc_codec *codec, pm_message_t state) 1329f10485e7SMark Brown { 1330f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1331f10485e7SMark Brown return 0; 1332f10485e7SMark Brown } 1333f10485e7SMark Brown 1334f0fba2adSLiam Girdwood static int wm8990_resume(struct snd_soc_codec *codec) 1335f10485e7SMark Brown { 1336f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1337f10485e7SMark Brown return 0; 1338f10485e7SMark Brown } 1339f10485e7SMark Brown 1340f10485e7SMark Brown /* 1341f10485e7SMark Brown * initialise the WM8990 driver 1342f10485e7SMark Brown * register the mixer and dsp interfaces with the kernel 1343f10485e7SMark Brown */ 1344f0fba2adSLiam Girdwood static int wm8990_probe(struct snd_soc_codec *codec) 1345f10485e7SMark Brown { 1346f0fba2adSLiam Girdwood int ret; 1347f10485e7SMark Brown u16 reg; 1348f10485e7SMark Brown 13498d50e447SMark Brown ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 13508d50e447SMark Brown if (ret < 0) { 13518d50e447SMark Brown printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret); 1352f0fba2adSLiam Girdwood return ret; 13538d50e447SMark Brown } 13548d50e447SMark Brown 1355f10485e7SMark Brown wm8990_reset(codec); 1356f10485e7SMark Brown 1357f10485e7SMark Brown /* charge output caps */ 1358f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1359f10485e7SMark Brown 13608d50e447SMark Brown reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4); 13618d50e447SMark Brown snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1362f10485e7SMark Brown 13638d50e447SMark Brown reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) & 1364f10485e7SMark Brown ~WM8990_GPIO1_SEL_MASK; 13658d50e447SMark Brown snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1366f10485e7SMark Brown 13678d50e447SMark Brown reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2); 13688d50e447SMark Brown snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1369f10485e7SMark Brown 13708d50e447SMark Brown snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 13718d50e447SMark Brown snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1372f10485e7SMark Brown 13733e8e1952SIan Molton snd_soc_add_controls(codec, wm8990_snd_controls, 13743e8e1952SIan Molton ARRAY_SIZE(wm8990_snd_controls)); 1375f10485e7SMark Brown wm8990_add_widgets(codec); 1376fe3e78e0SMark Brown 1377f0fba2adSLiam Girdwood return 0; 1378f10485e7SMark Brown } 1379f10485e7SMark Brown 1380f0fba2adSLiam Girdwood /* power down chip */ 1381f0fba2adSLiam Girdwood static int wm8990_remove(struct snd_soc_codec *codec) 1382f0fba2adSLiam Girdwood { 1383f0fba2adSLiam Girdwood wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1384f0fba2adSLiam Girdwood return 0; 1385f0fba2adSLiam Girdwood } 1386f0fba2adSLiam Girdwood 1387f0fba2adSLiam Girdwood static struct snd_soc_codec_driver soc_codec_dev_wm8990 = { 1388f0fba2adSLiam Girdwood .probe = wm8990_probe, 1389f0fba2adSLiam Girdwood .remove = wm8990_remove, 1390f0fba2adSLiam Girdwood .suspend = wm8990_suspend, 1391f0fba2adSLiam Girdwood .resume = wm8990_resume, 1392f0fba2adSLiam Girdwood .set_bias_level = wm8990_set_bias_level, 1393f0fba2adSLiam Girdwood .reg_cache_size = ARRAY_SIZE(wm8990_reg), 1394f0fba2adSLiam Girdwood .reg_word_size = sizeof(u16), 1395f0fba2adSLiam Girdwood .reg_cache_default = wm8990_reg, 1396416a0ce5SAxel Lin .volatile_register = wm8990_volatile_register, 1397f0fba2adSLiam Girdwood }; 1398f10485e7SMark Brown 1399f10485e7SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1400f0fba2adSLiam Girdwood static __devinit int wm8990_i2c_probe(struct i2c_client *i2c, 1401e5d3fd38SJean Delvare const struct i2c_device_id *id) 1402f10485e7SMark Brown { 1403f0fba2adSLiam Girdwood struct wm8990_priv *wm8990; 1404f10485e7SMark Brown int ret; 1405f10485e7SMark Brown 1406f0fba2adSLiam Girdwood wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL); 1407f0fba2adSLiam Girdwood if (wm8990 == NULL) 1408f0fba2adSLiam Girdwood return -ENOMEM; 1409f10485e7SMark Brown 1410f0fba2adSLiam Girdwood i2c_set_clientdata(i2c, wm8990); 1411f0fba2adSLiam Girdwood 1412f0fba2adSLiam Girdwood ret = snd_soc_register_codec(&i2c->dev, 1413f0fba2adSLiam Girdwood &soc_codec_dev_wm8990, &wm8990_dai, 1); 1414e5d3fd38SJean Delvare if (ret < 0) 1415f0fba2adSLiam Girdwood kfree(wm8990); 1416f10485e7SMark Brown return ret; 1417f10485e7SMark Brown } 1418f10485e7SMark Brown 1419f0fba2adSLiam Girdwood static __devexit int wm8990_i2c_remove(struct i2c_client *client) 1420f10485e7SMark Brown { 1421f0fba2adSLiam Girdwood snd_soc_unregister_codec(&client->dev); 1422f0fba2adSLiam Girdwood kfree(i2c_get_clientdata(client)); 1423f10485e7SMark Brown return 0; 1424f10485e7SMark Brown } 1425f10485e7SMark Brown 1426e5d3fd38SJean Delvare static const struct i2c_device_id wm8990_i2c_id[] = { 1427e5d3fd38SJean Delvare { "wm8990", 0 }, 1428e5d3fd38SJean Delvare { } 1429e5d3fd38SJean Delvare }; 1430e5d3fd38SJean Delvare MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1431f10485e7SMark Brown 1432f10485e7SMark Brown static struct i2c_driver wm8990_i2c_driver = { 1433f10485e7SMark Brown .driver = { 1434f0fba2adSLiam Girdwood .name = "wm8990-codec", 1435f10485e7SMark Brown .owner = THIS_MODULE, 1436f10485e7SMark Brown }, 1437e5d3fd38SJean Delvare .probe = wm8990_i2c_probe, 1438f0fba2adSLiam Girdwood .remove = __devexit_p(wm8990_i2c_remove), 1439e5d3fd38SJean Delvare .id_table = wm8990_i2c_id, 1440f10485e7SMark Brown }; 1441f10485e7SMark Brown #endif 1442f10485e7SMark Brown 1443c9b3a40fSTakashi Iwai static int __init wm8990_modinit(void) 144464089b84SMark Brown { 1445f0fba2adSLiam Girdwood int ret = 0; 1446f0fba2adSLiam Girdwood #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1447f0fba2adSLiam Girdwood ret = i2c_add_driver(&wm8990_i2c_driver); 1448f0fba2adSLiam Girdwood if (ret != 0) { 1449f0fba2adSLiam Girdwood printk(KERN_ERR "Failed to register wm8990 I2C driver: %d\n", 1450f0fba2adSLiam Girdwood ret); 1451f0fba2adSLiam Girdwood } 1452f0fba2adSLiam Girdwood #endif 1453f0fba2adSLiam Girdwood return ret; 145464089b84SMark Brown } 145564089b84SMark Brown module_init(wm8990_modinit); 145664089b84SMark Brown 145764089b84SMark Brown static void __exit wm8990_exit(void) 145864089b84SMark Brown { 1459f0fba2adSLiam Girdwood #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1460f0fba2adSLiam Girdwood i2c_del_driver(&wm8990_i2c_driver); 1461f0fba2adSLiam Girdwood #endif 146264089b84SMark Brown } 146364089b84SMark Brown module_exit(wm8990_exit); 146464089b84SMark Brown 1465f10485e7SMark Brown MODULE_DESCRIPTION("ASoC WM8990 driver"); 1466f10485e7SMark Brown MODULE_AUTHOR("Liam Girdwood"); 1467f10485e7SMark Brown MODULE_LICENSE("GPL"); 1468