1f10485e7SMark Brown /* 2f10485e7SMark Brown * wm8990.c -- WM8990 ALSA Soc Audio driver 3f10485e7SMark Brown * 4f10485e7SMark Brown * Copyright 2008 Wolfson Microelectronics PLC. 5f10485e7SMark Brown * Author: Liam Girdwood 6f10485e7SMark Brown * lg@opensource.wolfsonmicro.com or linux@wolfsonmicro.com 7f10485e7SMark Brown * 8f10485e7SMark Brown * This program is free software; you can redistribute it and/or modify it 9f10485e7SMark Brown * under the terms of the GNU General Public License as published by the 10f10485e7SMark Brown * Free Software Foundation; either version 2 of the License, or (at your 11f10485e7SMark Brown * option) any later version. 12f10485e7SMark Brown */ 13f10485e7SMark Brown 14f10485e7SMark Brown #include <linux/module.h> 15f10485e7SMark Brown #include <linux/moduleparam.h> 16f10485e7SMark Brown #include <linux/kernel.h> 17f10485e7SMark Brown #include <linux/init.h> 18f10485e7SMark Brown #include <linux/delay.h> 19f10485e7SMark Brown #include <linux/pm.h> 20f10485e7SMark Brown #include <linux/i2c.h> 21f10485e7SMark Brown #include <linux/platform_device.h> 22f10485e7SMark Brown #include <sound/core.h> 23f10485e7SMark Brown #include <sound/pcm.h> 24f10485e7SMark Brown #include <sound/pcm_params.h> 25f10485e7SMark Brown #include <sound/soc.h> 26f10485e7SMark Brown #include <sound/soc-dapm.h> 27f10485e7SMark Brown #include <sound/initval.h> 28f10485e7SMark Brown #include <sound/tlv.h> 29f10485e7SMark Brown #include <asm/div64.h> 30f10485e7SMark Brown 31f10485e7SMark Brown #include "wm8990.h" 32f10485e7SMark Brown 33f10485e7SMark Brown #define WM8990_VERSION "0.2" 34f10485e7SMark Brown 35f10485e7SMark Brown /* codec private data */ 36f10485e7SMark Brown struct wm8990_priv { 37f10485e7SMark Brown unsigned int sysclk; 38f10485e7SMark Brown unsigned int pcmclk; 39f10485e7SMark Brown }; 40f10485e7SMark Brown 41f10485e7SMark Brown /* 42f10485e7SMark Brown * wm8990 register cache. Note that register 0 is not included in the 43f10485e7SMark Brown * cache. 44f10485e7SMark Brown */ 45f10485e7SMark Brown static const u16 wm8990_reg[] = { 46f10485e7SMark Brown 0x8990, /* R0 - Reset */ 47f10485e7SMark Brown 0x0000, /* R1 - Power Management (1) */ 48f10485e7SMark Brown 0x6000, /* R2 - Power Management (2) */ 49f10485e7SMark Brown 0x0000, /* R3 - Power Management (3) */ 50f10485e7SMark Brown 0x4050, /* R4 - Audio Interface (1) */ 51f10485e7SMark Brown 0x4000, /* R5 - Audio Interface (2) */ 52f10485e7SMark Brown 0x01C8, /* R6 - Clocking (1) */ 53f10485e7SMark Brown 0x0000, /* R7 - Clocking (2) */ 54f10485e7SMark Brown 0x0040, /* R8 - Audio Interface (3) */ 55f10485e7SMark Brown 0x0040, /* R9 - Audio Interface (4) */ 56f10485e7SMark Brown 0x0004, /* R10 - DAC CTRL */ 57f10485e7SMark Brown 0x00C0, /* R11 - Left DAC Digital Volume */ 58f10485e7SMark Brown 0x00C0, /* R12 - Right DAC Digital Volume */ 59f10485e7SMark Brown 0x0000, /* R13 - Digital Side Tone */ 60f10485e7SMark Brown 0x0100, /* R14 - ADC CTRL */ 61f10485e7SMark Brown 0x00C0, /* R15 - Left ADC Digital Volume */ 62f10485e7SMark Brown 0x00C0, /* R16 - Right ADC Digital Volume */ 63f10485e7SMark Brown 0x0000, /* R17 */ 64f10485e7SMark Brown 0x0000, /* R18 - GPIO CTRL 1 */ 65f10485e7SMark Brown 0x1000, /* R19 - GPIO1 & GPIO2 */ 66f10485e7SMark Brown 0x1010, /* R20 - GPIO3 & GPIO4 */ 67f10485e7SMark Brown 0x1010, /* R21 - GPIO5 & GPIO6 */ 68f10485e7SMark Brown 0x8000, /* R22 - GPIOCTRL 2 */ 69f10485e7SMark Brown 0x0800, /* R23 - GPIO_POL */ 70f10485e7SMark Brown 0x008B, /* R24 - Left Line Input 1&2 Volume */ 71f10485e7SMark Brown 0x008B, /* R25 - Left Line Input 3&4 Volume */ 72f10485e7SMark Brown 0x008B, /* R26 - Right Line Input 1&2 Volume */ 73f10485e7SMark Brown 0x008B, /* R27 - Right Line Input 3&4 Volume */ 74f10485e7SMark Brown 0x0000, /* R28 - Left Output Volume */ 75f10485e7SMark Brown 0x0000, /* R29 - Right Output Volume */ 76f10485e7SMark Brown 0x0066, /* R30 - Line Outputs Volume */ 77f10485e7SMark Brown 0x0022, /* R31 - Out3/4 Volume */ 78f10485e7SMark Brown 0x0079, /* R32 - Left OPGA Volume */ 79f10485e7SMark Brown 0x0079, /* R33 - Right OPGA Volume */ 80f10485e7SMark Brown 0x0003, /* R34 - Speaker Volume */ 81f10485e7SMark Brown 0x0003, /* R35 - ClassD1 */ 82f10485e7SMark Brown 0x0000, /* R36 */ 83f10485e7SMark Brown 0x0100, /* R37 - ClassD3 */ 8497bb8129SMark Brown 0x0079, /* R38 - ClassD4 */ 85f10485e7SMark Brown 0x0000, /* R39 - Input Mixer1 */ 86f10485e7SMark Brown 0x0000, /* R40 - Input Mixer2 */ 87f10485e7SMark Brown 0x0000, /* R41 - Input Mixer3 */ 88f10485e7SMark Brown 0x0000, /* R42 - Input Mixer4 */ 89f10485e7SMark Brown 0x0000, /* R43 - Input Mixer5 */ 90f10485e7SMark Brown 0x0000, /* R44 - Input Mixer6 */ 91f10485e7SMark Brown 0x0000, /* R45 - Output Mixer1 */ 92f10485e7SMark Brown 0x0000, /* R46 - Output Mixer2 */ 93f10485e7SMark Brown 0x0000, /* R47 - Output Mixer3 */ 94f10485e7SMark Brown 0x0000, /* R48 - Output Mixer4 */ 95f10485e7SMark Brown 0x0000, /* R49 - Output Mixer5 */ 96f10485e7SMark Brown 0x0000, /* R50 - Output Mixer6 */ 97f10485e7SMark Brown 0x0180, /* R51 - Out3/4 Mixer */ 98f10485e7SMark Brown 0x0000, /* R52 - Line Mixer1 */ 99f10485e7SMark Brown 0x0000, /* R53 - Line Mixer2 */ 100f10485e7SMark Brown 0x0000, /* R54 - Speaker Mixer */ 101f10485e7SMark Brown 0x0000, /* R55 - Additional Control */ 102f10485e7SMark Brown 0x0000, /* R56 - AntiPOP1 */ 103f10485e7SMark Brown 0x0000, /* R57 - AntiPOP2 */ 104f10485e7SMark Brown 0x0000, /* R58 - MICBIAS */ 105f10485e7SMark Brown 0x0000, /* R59 */ 106f10485e7SMark Brown 0x0008, /* R60 - PLL1 */ 107f10485e7SMark Brown 0x0031, /* R61 - PLL2 */ 108f10485e7SMark Brown 0x0026, /* R62 - PLL3 */ 109ba533e95SMark Brown 0x0000, /* R63 - Driver internal */ 110f10485e7SMark Brown }; 111f10485e7SMark Brown 112f10485e7SMark Brown /* 113f10485e7SMark Brown * read wm8990 register cache 114f10485e7SMark Brown */ 115f10485e7SMark Brown static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec, 116f10485e7SMark Brown unsigned int reg) 117f10485e7SMark Brown { 118f10485e7SMark Brown u16 *cache = codec->reg_cache; 119f10485e7SMark Brown BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1); 120f10485e7SMark Brown return cache[reg]; 121f10485e7SMark Brown } 122f10485e7SMark Brown 123f10485e7SMark Brown /* 124f10485e7SMark Brown * write wm8990 register cache 125f10485e7SMark Brown */ 126f10485e7SMark Brown static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec, 127f10485e7SMark Brown unsigned int reg, unsigned int value) 128f10485e7SMark Brown { 129f10485e7SMark Brown u16 *cache = codec->reg_cache; 130f10485e7SMark Brown 131ba533e95SMark Brown /* Reset register and reserved registers are uncached */ 132ba533e95SMark Brown if (reg == 0 || reg > ARRAY_SIZE(wm8990_reg) - 1) 133f10485e7SMark Brown return; 134f10485e7SMark Brown 135f10485e7SMark Brown cache[reg] = value; 136f10485e7SMark Brown } 137f10485e7SMark Brown 138f10485e7SMark Brown /* 139f10485e7SMark Brown * write to the wm8990 register space 140f10485e7SMark Brown */ 141f10485e7SMark Brown static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg, 142f10485e7SMark Brown unsigned int value) 143f10485e7SMark Brown { 144f10485e7SMark Brown u8 data[3]; 145f10485e7SMark Brown 146f10485e7SMark Brown data[0] = reg & 0xFF; 147f10485e7SMark Brown data[1] = (value >> 8) & 0xFF; 148f10485e7SMark Brown data[2] = value & 0xFF; 149f10485e7SMark Brown 150f10485e7SMark Brown wm8990_write_reg_cache(codec, reg, value); 151f10485e7SMark Brown 152f10485e7SMark Brown if (codec->hw_write(codec->control_data, data, 3) == 2) 153f10485e7SMark Brown return 0; 154f10485e7SMark Brown else 155f10485e7SMark Brown return -EIO; 156f10485e7SMark Brown } 157f10485e7SMark Brown 158f10485e7SMark Brown #define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0) 159f10485e7SMark Brown 160f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600); 161f10485e7SMark Brown 162f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000); 163f10485e7SMark Brown 164f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100); 165f10485e7SMark Brown 166f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600); 167f10485e7SMark Brown 168f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0); 169f10485e7SMark Brown 170f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0); 171f10485e7SMark Brown 172f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763); 173f10485e7SMark Brown 174f10485e7SMark Brown static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0); 175f10485e7SMark Brown 176f10485e7SMark Brown static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 177f10485e7SMark Brown struct snd_ctl_elem_value *ucontrol) 178f10485e7SMark Brown { 179f10485e7SMark Brown struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 180f10485e7SMark Brown int reg = kcontrol->private_value & 0xff; 181f10485e7SMark Brown int ret; 182f10485e7SMark Brown u16 val; 183f10485e7SMark Brown 184f10485e7SMark Brown ret = snd_soc_put_volsw(kcontrol, ucontrol); 185f10485e7SMark Brown if (ret < 0) 186f10485e7SMark Brown return ret; 187f10485e7SMark Brown 188f10485e7SMark Brown /* now hit the volume update bits (always bit 8) */ 189f10485e7SMark Brown val = wm8990_read_reg_cache(codec, reg); 190f10485e7SMark Brown return wm8990_write(codec, reg, val | 0x0100); 191f10485e7SMark Brown } 192f10485e7SMark Brown 193f10485e7SMark Brown #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 194f10485e7SMark Brown tlv_array) {\ 195f10485e7SMark Brown .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 196f10485e7SMark Brown .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 197f10485e7SMark Brown SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 198f10485e7SMark Brown .tlv.p = (tlv_array), \ 199f10485e7SMark Brown .info = snd_soc_info_volsw, \ 200f10485e7SMark Brown .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ 201f10485e7SMark Brown .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 202f10485e7SMark Brown 203f10485e7SMark Brown 204f10485e7SMark Brown static const char *wm8990_digital_sidetone[] = 205f10485e7SMark Brown {"None", "Left ADC", "Right ADC", "Reserved"}; 206f10485e7SMark Brown 207f10485e7SMark Brown static const struct soc_enum wm8990_left_digital_sidetone_enum = 208f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 209f10485e7SMark Brown WM8990_ADC_TO_DACL_SHIFT, 210f10485e7SMark Brown WM8990_ADC_TO_DACL_MASK, 211f10485e7SMark Brown wm8990_digital_sidetone); 212f10485e7SMark Brown 213f10485e7SMark Brown static const struct soc_enum wm8990_right_digital_sidetone_enum = 214f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE, 215f10485e7SMark Brown WM8990_ADC_TO_DACR_SHIFT, 216f10485e7SMark Brown WM8990_ADC_TO_DACR_MASK, 217f10485e7SMark Brown wm8990_digital_sidetone); 218f10485e7SMark Brown 219f10485e7SMark Brown static const char *wm8990_adcmode[] = 220f10485e7SMark Brown {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 221f10485e7SMark Brown 222f10485e7SMark Brown static const struct soc_enum wm8990_right_adcmode_enum = 223f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_ADC_CTRL, 224f10485e7SMark Brown WM8990_ADC_HPF_CUT_SHIFT, 225f10485e7SMark Brown WM8990_ADC_HPF_CUT_MASK, 226f10485e7SMark Brown wm8990_adcmode); 227f10485e7SMark Brown 228f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_snd_controls[] = { 229f10485e7SMark Brown /* INMIXL */ 230f10485e7SMark Brown SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0), 231f10485e7SMark Brown SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0), 232f10485e7SMark Brown /* INMIXR */ 233f10485e7SMark Brown SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0), 234f10485e7SMark Brown SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0), 235f10485e7SMark Brown 236f10485e7SMark Brown /* LOMIX */ 237f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3, 238f10485e7SMark Brown WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv), 239f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 240f10485e7SMark Brown WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv), 241f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3, 242f10485e7SMark Brown WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv), 243f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5, 244f10485e7SMark Brown WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv), 245f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 246f10485e7SMark Brown WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 247f10485e7SMark Brown SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5, 248f10485e7SMark Brown WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv), 249f10485e7SMark Brown 250f10485e7SMark Brown /* ROMIX */ 251f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4, 252f10485e7SMark Brown WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv), 253f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 254f10485e7SMark Brown WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv), 255f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4, 256f10485e7SMark Brown WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv), 257f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6, 258f10485e7SMark Brown WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv), 259f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 260f10485e7SMark Brown WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv), 261f10485e7SMark Brown SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6, 262f10485e7SMark Brown WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv), 263f10485e7SMark Brown 264f10485e7SMark Brown /* LOUT */ 265f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME, 266f10485e7SMark Brown WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv), 267f10485e7SMark Brown SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0), 268f10485e7SMark Brown 269f10485e7SMark Brown /* ROUT */ 270f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME, 271f10485e7SMark Brown WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv), 272f10485e7SMark Brown SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0), 273f10485e7SMark Brown 274f10485e7SMark Brown /* LOPGA */ 275f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME, 276f10485e7SMark Brown WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv), 277f10485e7SMark Brown SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME, 278f10485e7SMark Brown WM8990_LOPGAZC_BIT, 1, 0), 279f10485e7SMark Brown 280f10485e7SMark Brown /* ROPGA */ 281f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME, 282f10485e7SMark Brown WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv), 283f10485e7SMark Brown SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME, 284f10485e7SMark Brown WM8990_ROPGAZC_BIT, 1, 0), 285f10485e7SMark Brown 286f10485e7SMark Brown SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 287f10485e7SMark Brown WM8990_LONMUTE_BIT, 1, 0), 288f10485e7SMark Brown SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 289f10485e7SMark Brown WM8990_LOPMUTE_BIT, 1, 0), 290f10485e7SMark Brown SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 291f10485e7SMark Brown WM8990_LOATTN_BIT, 1, 0), 292f10485e7SMark Brown SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 293f10485e7SMark Brown WM8990_RONMUTE_BIT, 1, 0), 294f10485e7SMark Brown SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME, 295f10485e7SMark Brown WM8990_ROPMUTE_BIT, 1, 0), 296f10485e7SMark Brown SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME, 297f10485e7SMark Brown WM8990_ROATTN_BIT, 1, 0), 298f10485e7SMark Brown 299f10485e7SMark Brown SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME, 300f10485e7SMark Brown WM8990_OUT3MUTE_BIT, 1, 0), 301f10485e7SMark Brown SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME, 302f10485e7SMark Brown WM8990_OUT3ATTN_BIT, 1, 0), 303f10485e7SMark Brown 304f10485e7SMark Brown SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME, 305f10485e7SMark Brown WM8990_OUT4MUTE_BIT, 1, 0), 306f10485e7SMark Brown SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME, 307f10485e7SMark Brown WM8990_OUT4ATTN_BIT, 1, 0), 308f10485e7SMark Brown 309f10485e7SMark Brown SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1, 310f10485e7SMark Brown WM8990_CDMODE_BIT, 1, 0), 311f10485e7SMark Brown 312f10485e7SMark Brown SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, 31397bb8129SMark Brown WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), 314f10485e7SMark Brown SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, 315f10485e7SMark Brown WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), 316f10485e7SMark Brown SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, 317f10485e7SMark Brown WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), 31897bb8129SMark Brown SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, 31997bb8129SMark Brown WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), 32097bb8129SMark Brown SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, 32197bb8129SMark Brown WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), 322f10485e7SMark Brown 323f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 324f10485e7SMark Brown WM8990_LEFT_DAC_DIGITAL_VOLUME, 325f10485e7SMark Brown WM8990_DACL_VOL_SHIFT, 326f10485e7SMark Brown WM8990_DACL_VOL_MASK, 327f10485e7SMark Brown 0, 328f10485e7SMark Brown out_dac_tlv), 329f10485e7SMark Brown 330f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 331f10485e7SMark Brown WM8990_RIGHT_DAC_DIGITAL_VOLUME, 332f10485e7SMark Brown WM8990_DACR_VOL_SHIFT, 333f10485e7SMark Brown WM8990_DACR_VOL_MASK, 334f10485e7SMark Brown 0, 335f10485e7SMark Brown out_dac_tlv), 336f10485e7SMark Brown 337f10485e7SMark Brown SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum), 338f10485e7SMark Brown SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum), 339f10485e7SMark Brown 340f10485e7SMark Brown SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 341f10485e7SMark Brown WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0, 342f10485e7SMark Brown out_sidetone_tlv), 343f10485e7SMark Brown SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE, 344f10485e7SMark Brown WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0, 345f10485e7SMark Brown out_sidetone_tlv), 346f10485e7SMark Brown 347f10485e7SMark Brown SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL, 348f10485e7SMark Brown WM8990_ADC_HPF_ENA_BIT, 1, 0), 349f10485e7SMark Brown 350f10485e7SMark Brown SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum), 351f10485e7SMark Brown 352f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 353f10485e7SMark Brown WM8990_LEFT_ADC_DIGITAL_VOLUME, 354f10485e7SMark Brown WM8990_ADCL_VOL_SHIFT, 355f10485e7SMark Brown WM8990_ADCL_VOL_MASK, 356f10485e7SMark Brown 0, 357f10485e7SMark Brown in_adc_tlv), 358f10485e7SMark Brown 359f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 360f10485e7SMark Brown WM8990_RIGHT_ADC_DIGITAL_VOLUME, 361f10485e7SMark Brown WM8990_ADCR_VOL_SHIFT, 362f10485e7SMark Brown WM8990_ADCR_VOL_MASK, 363f10485e7SMark Brown 0, 364f10485e7SMark Brown in_adc_tlv), 365f10485e7SMark Brown 366f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 367f10485e7SMark Brown WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 368f10485e7SMark Brown WM8990_LIN12VOL_SHIFT, 369f10485e7SMark Brown WM8990_LIN12VOL_MASK, 370f10485e7SMark Brown 0, 371f10485e7SMark Brown in_pga_tlv), 372f10485e7SMark Brown 373f10485e7SMark Brown SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 374f10485e7SMark Brown WM8990_LI12ZC_BIT, 1, 0), 375f10485e7SMark Brown 376f10485e7SMark Brown SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME, 377f10485e7SMark Brown WM8990_LI12MUTE_BIT, 1, 0), 378f10485e7SMark Brown 379f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 380f10485e7SMark Brown WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 381f10485e7SMark Brown WM8990_LIN34VOL_SHIFT, 382f10485e7SMark Brown WM8990_LIN34VOL_MASK, 383f10485e7SMark Brown 0, 384f10485e7SMark Brown in_pga_tlv), 385f10485e7SMark Brown 386f10485e7SMark Brown SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 387f10485e7SMark Brown WM8990_LI34ZC_BIT, 1, 0), 388f10485e7SMark Brown 389f10485e7SMark Brown SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME, 390f10485e7SMark Brown WM8990_LI34MUTE_BIT, 1, 0), 391f10485e7SMark Brown 392f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 393f10485e7SMark Brown WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 394f10485e7SMark Brown WM8990_RIN12VOL_SHIFT, 395f10485e7SMark Brown WM8990_RIN12VOL_MASK, 396f10485e7SMark Brown 0, 397f10485e7SMark Brown in_pga_tlv), 398f10485e7SMark Brown 399f10485e7SMark Brown SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 400f10485e7SMark Brown WM8990_RI12ZC_BIT, 1, 0), 401f10485e7SMark Brown 402f10485e7SMark Brown SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME, 403f10485e7SMark Brown WM8990_RI12MUTE_BIT, 1, 0), 404f10485e7SMark Brown 405f10485e7SMark Brown SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 406f10485e7SMark Brown WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 407f10485e7SMark Brown WM8990_RIN34VOL_SHIFT, 408f10485e7SMark Brown WM8990_RIN34VOL_MASK, 409f10485e7SMark Brown 0, 410f10485e7SMark Brown in_pga_tlv), 411f10485e7SMark Brown 412f10485e7SMark Brown SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 413f10485e7SMark Brown WM8990_RI34ZC_BIT, 1, 0), 414f10485e7SMark Brown 415f10485e7SMark Brown SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME, 416f10485e7SMark Brown WM8990_RI34MUTE_BIT, 1, 0), 417f10485e7SMark Brown 418f10485e7SMark Brown }; 419f10485e7SMark Brown 420f10485e7SMark Brown /* add non dapm controls */ 421f10485e7SMark Brown static int wm8990_add_controls(struct snd_soc_codec *codec) 422f10485e7SMark Brown { 423f10485e7SMark Brown int err, i; 424f10485e7SMark Brown 425f10485e7SMark Brown for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) { 426f10485e7SMark Brown err = snd_ctl_add(codec->card, 427f10485e7SMark Brown snd_soc_cnew(&wm8990_snd_controls[i], codec, 428f10485e7SMark Brown NULL)); 429f10485e7SMark Brown if (err < 0) 430f10485e7SMark Brown return err; 431f10485e7SMark Brown } 432f10485e7SMark Brown return 0; 433f10485e7SMark Brown } 434f10485e7SMark Brown 435f10485e7SMark Brown /* 436f10485e7SMark Brown * _DAPM_ Controls 437f10485e7SMark Brown */ 438f10485e7SMark Brown 439f10485e7SMark Brown static int inmixer_event(struct snd_soc_dapm_widget *w, 440f10485e7SMark Brown struct snd_kcontrol *kcontrol, int event) 441f10485e7SMark Brown { 442f10485e7SMark Brown u16 reg, fakepower; 443f10485e7SMark Brown 444f10485e7SMark Brown reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2); 445f10485e7SMark Brown fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS); 446f10485e7SMark Brown 447f10485e7SMark Brown if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 448f10485e7SMark Brown (1 << WM8990_AINLMUX_PWR_BIT))) { 449f10485e7SMark Brown reg |= WM8990_AINL_ENA; 450f10485e7SMark Brown } else { 451f10485e7SMark Brown reg &= ~WM8990_AINL_ENA; 452f10485e7SMark Brown } 453f10485e7SMark Brown 454f10485e7SMark Brown if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) | 455f10485e7SMark Brown (1 << WM8990_AINRMUX_PWR_BIT))) { 456f10485e7SMark Brown reg |= WM8990_AINR_ENA; 457f10485e7SMark Brown } else { 458f10485e7SMark Brown reg &= ~WM8990_AINL_ENA; 459f10485e7SMark Brown } 460f10485e7SMark Brown wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 461f10485e7SMark Brown 462f10485e7SMark Brown return 0; 463f10485e7SMark Brown } 464f10485e7SMark Brown 465f10485e7SMark Brown static int outmixer_event(struct snd_soc_dapm_widget *w, 466f10485e7SMark Brown struct snd_kcontrol *kcontrol, int event) 467f10485e7SMark Brown { 468f10485e7SMark Brown u32 reg_shift = kcontrol->private_value & 0xfff; 469f10485e7SMark Brown int ret = 0; 470f10485e7SMark Brown u16 reg; 471f10485e7SMark Brown 472f10485e7SMark Brown switch (reg_shift) { 473f10485e7SMark Brown case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 474f10485e7SMark Brown reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1); 475f10485e7SMark Brown if (reg & WM8990_LDLO) { 476f10485e7SMark Brown printk(KERN_WARNING 477f10485e7SMark Brown "Cannot set as Output Mixer 1 LDLO Set\n"); 478f10485e7SMark Brown ret = -1; 479f10485e7SMark Brown } 480f10485e7SMark Brown break; 481f10485e7SMark Brown case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 482f10485e7SMark Brown reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2); 483f10485e7SMark Brown if (reg & WM8990_RDRO) { 484f10485e7SMark Brown printk(KERN_WARNING 485f10485e7SMark Brown "Cannot set as Output Mixer 2 RDRO Set\n"); 486f10485e7SMark Brown ret = -1; 487f10485e7SMark Brown } 488f10485e7SMark Brown break; 489f10485e7SMark Brown case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 490f10485e7SMark Brown reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 491f10485e7SMark Brown if (reg & WM8990_LDSPK) { 492f10485e7SMark Brown printk(KERN_WARNING 493f10485e7SMark Brown "Cannot set as Speaker Mixer LDSPK Set\n"); 494f10485e7SMark Brown ret = -1; 495f10485e7SMark Brown } 496f10485e7SMark Brown break; 497f10485e7SMark Brown case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 498f10485e7SMark Brown reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 499f10485e7SMark Brown if (reg & WM8990_RDSPK) { 500f10485e7SMark Brown printk(KERN_WARNING 501f10485e7SMark Brown "Cannot set as Speaker Mixer RDSPK Set\n"); 502f10485e7SMark Brown ret = -1; 503f10485e7SMark Brown } 504f10485e7SMark Brown break; 505f10485e7SMark Brown } 506f10485e7SMark Brown 507f10485e7SMark Brown return ret; 508f10485e7SMark Brown } 509f10485e7SMark Brown 510f10485e7SMark Brown /* INMIX dB values */ 511f10485e7SMark Brown static const unsigned int in_mix_tlv[] = { 512f10485e7SMark Brown TLV_DB_RANGE_HEAD(1), 513f10485e7SMark Brown 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600), 514f10485e7SMark Brown }; 515f10485e7SMark Brown 516f10485e7SMark Brown /* Left In PGA Connections */ 517f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = { 518f10485e7SMark Brown SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0), 519f10485e7SMark Brown SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0), 520f10485e7SMark Brown }; 521f10485e7SMark Brown 522f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = { 523f10485e7SMark Brown SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0), 524f10485e7SMark Brown SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0), 525f10485e7SMark Brown }; 526f10485e7SMark Brown 527f10485e7SMark Brown /* Right In PGA Connections */ 528f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = { 529f10485e7SMark Brown SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0), 530f10485e7SMark Brown SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0), 531f10485e7SMark Brown }; 532f10485e7SMark Brown 533f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = { 534f10485e7SMark Brown SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0), 535f10485e7SMark Brown SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0), 536f10485e7SMark Brown }; 537f10485e7SMark Brown 538f10485e7SMark Brown /* INMIXL */ 539f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = { 540f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3, 541f10485e7SMark Brown WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), 542f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, 543f10485e7SMark Brown 7, 0, in_mix_tlv), 544f10485e7SMark Brown SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 545f10485e7SMark Brown 1, 0), 546f10485e7SMark Brown SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 547f10485e7SMark Brown 1, 0), 548f10485e7SMark Brown }; 549f10485e7SMark Brown 550f10485e7SMark Brown /* INMIXR */ 551f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = { 552f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4, 553f10485e7SMark Brown WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv), 554f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT, 555f10485e7SMark Brown 7, 0, in_mix_tlv), 556f10485e7SMark Brown SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 557f10485e7SMark Brown 1, 0), 558f10485e7SMark Brown SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 559f10485e7SMark Brown 1, 0), 560f10485e7SMark Brown }; 561f10485e7SMark Brown 562f10485e7SMark Brown /* AINLMUX */ 563f10485e7SMark Brown static const char *wm8990_ainlmux[] = 564f10485e7SMark Brown {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 565f10485e7SMark Brown 566f10485e7SMark Brown static const struct soc_enum wm8990_ainlmux_enum = 567f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, 568f10485e7SMark Brown ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); 569f10485e7SMark Brown 570f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = 571f10485e7SMark Brown SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum); 572f10485e7SMark Brown 573f10485e7SMark Brown /* DIFFINL */ 574f10485e7SMark Brown 575f10485e7SMark Brown /* AINRMUX */ 576f10485e7SMark Brown static const char *wm8990_ainrmux[] = 577f10485e7SMark Brown {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 578f10485e7SMark Brown 579f10485e7SMark Brown static const struct soc_enum wm8990_ainrmux_enum = 580f10485e7SMark Brown SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, 581f10485e7SMark Brown ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); 582f10485e7SMark Brown 583f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = 584f10485e7SMark Brown SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum); 585f10485e7SMark Brown 586f10485e7SMark Brown /* RXVOICE */ 587f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = { 588f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT, 589f10485e7SMark Brown WM8990_LR4BVOL_MASK, 0, in_mix_tlv), 590f10485e7SMark Brown SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT, 591f10485e7SMark Brown WM8990_RL4BVOL_MASK, 0, in_mix_tlv), 592f10485e7SMark Brown }; 593f10485e7SMark Brown 594f10485e7SMark Brown /* LOMIX */ 595f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = { 596f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 597f10485e7SMark Brown WM8990_LRBLO_BIT, 1, 0), 598f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1, 599f10485e7SMark Brown WM8990_LLBLO_BIT, 1, 0), 600f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 601f10485e7SMark Brown WM8990_LRI3LO_BIT, 1, 0), 602f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1, 603f10485e7SMark Brown WM8990_LLI3LO_BIT, 1, 0), 604f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 605f10485e7SMark Brown WM8990_LR12LO_BIT, 1, 0), 606f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1, 607f10485e7SMark Brown WM8990_LL12LO_BIT, 1, 0), 608f10485e7SMark Brown SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1, 609f10485e7SMark Brown WM8990_LDLO_BIT, 1, 0), 610f10485e7SMark Brown }; 611f10485e7SMark Brown 612f10485e7SMark Brown /* ROMIX */ 613f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = { 614f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 615f10485e7SMark Brown WM8990_RLBRO_BIT, 1, 0), 616f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2, 617f10485e7SMark Brown WM8990_RRBRO_BIT, 1, 0), 618f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 619f10485e7SMark Brown WM8990_RLI3RO_BIT, 1, 0), 620f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2, 621f10485e7SMark Brown WM8990_RRI3RO_BIT, 1, 0), 622f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 623f10485e7SMark Brown WM8990_RL12RO_BIT, 1, 0), 624f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2, 625f10485e7SMark Brown WM8990_RR12RO_BIT, 1, 0), 626f10485e7SMark Brown SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2, 627f10485e7SMark Brown WM8990_RDRO_BIT, 1, 0), 628f10485e7SMark Brown }; 629f10485e7SMark Brown 630f10485e7SMark Brown /* LONMIX */ 631f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = { 632f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 633f10485e7SMark Brown WM8990_LLOPGALON_BIT, 1, 0), 634f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1, 635f10485e7SMark Brown WM8990_LROPGALON_BIT, 1, 0), 636f10485e7SMark Brown SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1, 637f10485e7SMark Brown WM8990_LOPLON_BIT, 1, 0), 638f10485e7SMark Brown }; 639f10485e7SMark Brown 640f10485e7SMark Brown /* LOPMIX */ 641f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = { 642f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1, 643f10485e7SMark Brown WM8990_LR12LOP_BIT, 1, 0), 644f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1, 645f10485e7SMark Brown WM8990_LL12LOP_BIT, 1, 0), 646f10485e7SMark Brown SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1, 647f10485e7SMark Brown WM8990_LLOPGALOP_BIT, 1, 0), 648f10485e7SMark Brown }; 649f10485e7SMark Brown 650f10485e7SMark Brown /* RONMIX */ 651f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = { 652f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 653f10485e7SMark Brown WM8990_RROPGARON_BIT, 1, 0), 654f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2, 655f10485e7SMark Brown WM8990_RLOPGARON_BIT, 1, 0), 656f10485e7SMark Brown SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2, 657f10485e7SMark Brown WM8990_ROPRON_BIT, 1, 0), 658f10485e7SMark Brown }; 659f10485e7SMark Brown 660f10485e7SMark Brown /* ROPMIX */ 661f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = { 662f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2, 663f10485e7SMark Brown WM8990_RL12ROP_BIT, 1, 0), 664f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2, 665f10485e7SMark Brown WM8990_RR12ROP_BIT, 1, 0), 666f10485e7SMark Brown SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2, 667f10485e7SMark Brown WM8990_RROPGAROP_BIT, 1, 0), 668f10485e7SMark Brown }; 669f10485e7SMark Brown 670f10485e7SMark Brown /* OUT3MIX */ 671f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = { 672f10485e7SMark Brown SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 673f10485e7SMark Brown WM8990_LI4O3_BIT, 1, 0), 674f10485e7SMark Brown SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER, 675f10485e7SMark Brown WM8990_LPGAO3_BIT, 1, 0), 676f10485e7SMark Brown }; 677f10485e7SMark Brown 678f10485e7SMark Brown /* OUT4MIX */ 679f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = { 680f10485e7SMark Brown SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER, 681f10485e7SMark Brown WM8990_RPGAO4_BIT, 1, 0), 682f10485e7SMark Brown SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER, 683f10485e7SMark Brown WM8990_RI4O4_BIT, 1, 0), 684f10485e7SMark Brown }; 685f10485e7SMark Brown 686f10485e7SMark Brown /* SPKMIX */ 687f10485e7SMark Brown static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = { 688f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 689f10485e7SMark Brown WM8990_LI2SPK_BIT, 1, 0), 690f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER, 691f10485e7SMark Brown WM8990_LB2SPK_BIT, 1, 0), 692f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER, 693f10485e7SMark Brown WM8990_LOPGASPK_BIT, 1, 0), 694f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER, 695f10485e7SMark Brown WM8990_LDSPK_BIT, 1, 0), 696f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER, 697f10485e7SMark Brown WM8990_RDSPK_BIT, 1, 0), 698f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER, 699f10485e7SMark Brown WM8990_ROPGASPK_BIT, 1, 0), 700f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER, 701f10485e7SMark Brown WM8990_RL12ROP_BIT, 1, 0), 702f10485e7SMark Brown SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER, 703f10485e7SMark Brown WM8990_RI2SPK_BIT, 1, 0), 704f10485e7SMark Brown }; 705f10485e7SMark Brown 706f10485e7SMark Brown static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { 707f10485e7SMark Brown /* Input Side */ 708f10485e7SMark Brown /* Input Lines */ 709f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN1"), 710f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN2"), 711f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN3"), 712f10485e7SMark Brown SND_SOC_DAPM_INPUT("LIN4/RXN"), 713f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN3"), 714f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN4/RXP"), 715f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN1"), 716f10485e7SMark Brown SND_SOC_DAPM_INPUT("RIN2"), 717f10485e7SMark Brown SND_SOC_DAPM_INPUT("Internal ADC Source"), 718f10485e7SMark Brown 719f10485e7SMark Brown /* DACs */ 720f10485e7SMark Brown SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2, 721f10485e7SMark Brown WM8990_ADCL_ENA_BIT, 0), 722f10485e7SMark Brown SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2, 723f10485e7SMark Brown WM8990_ADCR_ENA_BIT, 0), 724f10485e7SMark Brown 725f10485e7SMark Brown /* Input PGAs */ 726f10485e7SMark Brown SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT, 727f10485e7SMark Brown 0, &wm8990_dapm_lin12_pga_controls[0], 728f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)), 729f10485e7SMark Brown SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT, 730f10485e7SMark Brown 0, &wm8990_dapm_lin34_pga_controls[0], 731f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)), 732f10485e7SMark Brown SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT, 733f10485e7SMark Brown 0, &wm8990_dapm_rin12_pga_controls[0], 734f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)), 735f10485e7SMark Brown SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT, 736f10485e7SMark Brown 0, &wm8990_dapm_rin34_pga_controls[0], 737f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)), 738f10485e7SMark Brown 739f10485e7SMark Brown /* INMIXL */ 740f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0, 741f10485e7SMark Brown &wm8990_dapm_inmixl_controls[0], 742f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_inmixl_controls), 743f10485e7SMark Brown inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 744f10485e7SMark Brown 745f10485e7SMark Brown /* AINLMUX */ 746f10485e7SMark Brown SND_SOC_DAPM_MUX_E("AILNMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0, 747f10485e7SMark Brown &wm8990_dapm_ainlmux_controls, inmixer_event, 748f10485e7SMark Brown SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 749f10485e7SMark Brown 750f10485e7SMark Brown /* INMIXR */ 751f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0, 752f10485e7SMark Brown &wm8990_dapm_inmixr_controls[0], 753f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_inmixr_controls), 754f10485e7SMark Brown inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 755f10485e7SMark Brown 756f10485e7SMark Brown /* AINRMUX */ 757f10485e7SMark Brown SND_SOC_DAPM_MUX_E("AIRNMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0, 758f10485e7SMark Brown &wm8990_dapm_ainrmux_controls, inmixer_event, 759f10485e7SMark Brown SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 760f10485e7SMark Brown 761f10485e7SMark Brown /* Output Side */ 762f10485e7SMark Brown /* DACs */ 763f10485e7SMark Brown SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3, 764f10485e7SMark Brown WM8990_DACL_ENA_BIT, 0), 765f10485e7SMark Brown SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3, 766f10485e7SMark Brown WM8990_DACR_ENA_BIT, 0), 767f10485e7SMark Brown 768f10485e7SMark Brown /* LOMIX */ 769f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT, 770f10485e7SMark Brown 0, &wm8990_dapm_lomix_controls[0], 771f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lomix_controls), 772f10485e7SMark Brown outmixer_event, SND_SOC_DAPM_PRE_REG), 773f10485e7SMark Brown 774f10485e7SMark Brown /* LONMIX */ 775f10485e7SMark Brown SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0, 776f10485e7SMark Brown &wm8990_dapm_lonmix_controls[0], 777f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lonmix_controls)), 778f10485e7SMark Brown 779f10485e7SMark Brown /* LOPMIX */ 780f10485e7SMark Brown SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0, 781f10485e7SMark Brown &wm8990_dapm_lopmix_controls[0], 782f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_lopmix_controls)), 783f10485e7SMark Brown 784f10485e7SMark Brown /* OUT3MIX */ 785f10485e7SMark Brown SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0, 786f10485e7SMark Brown &wm8990_dapm_out3mix_controls[0], 787f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_out3mix_controls)), 788f10485e7SMark Brown 789f10485e7SMark Brown /* SPKMIX */ 790f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0, 791f10485e7SMark Brown &wm8990_dapm_spkmix_controls[0], 792f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event, 793f10485e7SMark Brown SND_SOC_DAPM_PRE_REG), 794f10485e7SMark Brown 795f10485e7SMark Brown /* OUT4MIX */ 796f10485e7SMark Brown SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0, 797f10485e7SMark Brown &wm8990_dapm_out4mix_controls[0], 798f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_out4mix_controls)), 799f10485e7SMark Brown 800f10485e7SMark Brown /* ROPMIX */ 801f10485e7SMark Brown SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0, 802f10485e7SMark Brown &wm8990_dapm_ropmix_controls[0], 803f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_ropmix_controls)), 804f10485e7SMark Brown 805f10485e7SMark Brown /* RONMIX */ 806f10485e7SMark Brown SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0, 807f10485e7SMark Brown &wm8990_dapm_ronmix_controls[0], 808f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_ronmix_controls)), 809f10485e7SMark Brown 810f10485e7SMark Brown /* ROMIX */ 811f10485e7SMark Brown SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT, 812f10485e7SMark Brown 0, &wm8990_dapm_romix_controls[0], 813f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_romix_controls), 814f10485e7SMark Brown outmixer_event, SND_SOC_DAPM_PRE_REG), 815f10485e7SMark Brown 816f10485e7SMark Brown /* LOUT PGA */ 817f10485e7SMark Brown SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0, 818f10485e7SMark Brown NULL, 0), 819f10485e7SMark Brown 820f10485e7SMark Brown /* ROUT PGA */ 821f10485e7SMark Brown SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0, 822f10485e7SMark Brown NULL, 0), 823f10485e7SMark Brown 824f10485e7SMark Brown /* LOPGA */ 825f10485e7SMark Brown SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0, 826f10485e7SMark Brown NULL, 0), 827f10485e7SMark Brown 828f10485e7SMark Brown /* ROPGA */ 829f10485e7SMark Brown SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0, 830f10485e7SMark Brown NULL, 0), 831f10485e7SMark Brown 832f10485e7SMark Brown /* MICBIAS */ 833f10485e7SMark Brown SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1, 834f10485e7SMark Brown WM8990_MICBIAS_ENA_BIT, 0), 835f10485e7SMark Brown 836f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LON"), 837f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LOP"), 838f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("OUT3"), 839f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("LOUT"), 840f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("SPKN"), 841f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("SPKP"), 842f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("ROUT"), 843f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("OUT4"), 844f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("ROP"), 845f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("RON"), 846f10485e7SMark Brown 847f10485e7SMark Brown SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 848f10485e7SMark Brown }; 849f10485e7SMark Brown 850f10485e7SMark Brown static const struct snd_soc_dapm_route audio_map[] = { 851f10485e7SMark Brown /* Make DACs turn on when playing even if not mixed into any outputs */ 852f10485e7SMark Brown {"Internal DAC Sink", NULL, "Left DAC"}, 853f10485e7SMark Brown {"Internal DAC Sink", NULL, "Right DAC"}, 854f10485e7SMark Brown 855f10485e7SMark Brown /* Make ADCs turn on when recording even if not mixed from any inputs */ 856f10485e7SMark Brown {"Left ADC", NULL, "Internal ADC Source"}, 857f10485e7SMark Brown {"Right ADC", NULL, "Internal ADC Source"}, 858f10485e7SMark Brown 859f10485e7SMark Brown /* Input Side */ 860f10485e7SMark Brown /* LIN12 PGA */ 861f10485e7SMark Brown {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 862f10485e7SMark Brown {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 863f10485e7SMark Brown /* LIN34 PGA */ 864f10485e7SMark Brown {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 865f10485e7SMark Brown {"LIN34 PGA", "LIN4 Switch", "LIN4"}, 866f10485e7SMark Brown /* INMIXL */ 867f10485e7SMark Brown {"INMIXL", "Record Left Volume", "LOMIX"}, 868f10485e7SMark Brown {"INMIXL", "LIN2 Volume", "LIN2"}, 869f10485e7SMark Brown {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 870f10485e7SMark Brown {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 871f10485e7SMark Brown /* AILNMUX */ 872f10485e7SMark Brown {"AILNMUX", "INMIXL Mix", "INMIXL"}, 873f10485e7SMark Brown {"AILNMUX", "DIFFINL Mix", "LIN12PGA"}, 874f10485e7SMark Brown {"AILNMUX", "DIFFINL Mix", "LIN34PGA"}, 875f10485e7SMark Brown {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"}, 876f10485e7SMark Brown {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"}, 877f10485e7SMark Brown /* ADC */ 878f10485e7SMark Brown {"Left ADC", NULL, "AILNMUX"}, 879f10485e7SMark Brown 880f10485e7SMark Brown /* RIN12 PGA */ 881f10485e7SMark Brown {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 882f10485e7SMark Brown {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 883f10485e7SMark Brown /* RIN34 PGA */ 884f10485e7SMark Brown {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 885f10485e7SMark Brown {"RIN34 PGA", "RIN4 Switch", "RIN4"}, 886f10485e7SMark Brown /* INMIXL */ 887f10485e7SMark Brown {"INMIXR", "Record Right Volume", "ROMIX"}, 888f10485e7SMark Brown {"INMIXR", "RIN2 Volume", "RIN2"}, 889f10485e7SMark Brown {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 890f10485e7SMark Brown {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 891f10485e7SMark Brown /* AIRNMUX */ 892f10485e7SMark Brown {"AIRNMUX", "INMIXR Mix", "INMIXR"}, 893f10485e7SMark Brown {"AIRNMUX", "DIFFINR Mix", "RIN12PGA"}, 894f10485e7SMark Brown {"AIRNMUX", "DIFFINR Mix", "RIN34PGA"}, 895f10485e7SMark Brown {"AIRNMUX", "RXVOICE Mix", "RIN4/RXN"}, 896f10485e7SMark Brown {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"}, 897f10485e7SMark Brown /* ADC */ 898f10485e7SMark Brown {"Right ADC", NULL, "AIRNMUX"}, 899f10485e7SMark Brown 900f10485e7SMark Brown /* LOMIX */ 901f10485e7SMark Brown {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 902f10485e7SMark Brown {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 903f10485e7SMark Brown {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 904f10485e7SMark Brown {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 905f10485e7SMark Brown {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 906f10485e7SMark Brown {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 907f10485e7SMark Brown {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 908f10485e7SMark Brown 909f10485e7SMark Brown /* ROMIX */ 910f10485e7SMark Brown {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 911f10485e7SMark Brown {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 912f10485e7SMark Brown {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 913f10485e7SMark Brown {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 914f10485e7SMark Brown {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 915f10485e7SMark Brown {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 916f10485e7SMark Brown {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 917f10485e7SMark Brown 918f10485e7SMark Brown /* SPKMIX */ 919f10485e7SMark Brown {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 920f10485e7SMark Brown {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 921f10485e7SMark Brown {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 922f10485e7SMark Brown {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 923f10485e7SMark Brown {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 924f10485e7SMark Brown {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 925f10485e7SMark Brown {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 926436a7459SMark Brown {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, 927f10485e7SMark Brown 928f10485e7SMark Brown /* LONMIX */ 929f10485e7SMark Brown {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 930f10485e7SMark Brown {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 931f10485e7SMark Brown {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 932f10485e7SMark Brown 933f10485e7SMark Brown /* LOPMIX */ 934f10485e7SMark Brown {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 935f10485e7SMark Brown {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 936f10485e7SMark Brown {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 937f10485e7SMark Brown 938f10485e7SMark Brown /* OUT3MIX */ 939f10485e7SMark Brown {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXP"}, 940f10485e7SMark Brown {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 941f10485e7SMark Brown 942f10485e7SMark Brown /* OUT4MIX */ 943f10485e7SMark Brown {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 944f10485e7SMark Brown {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 945f10485e7SMark Brown 946f10485e7SMark Brown /* RONMIX */ 947f10485e7SMark Brown {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 948f10485e7SMark Brown {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 949f10485e7SMark Brown {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 950f10485e7SMark Brown 951f10485e7SMark Brown /* ROPMIX */ 952f10485e7SMark Brown {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 953f10485e7SMark Brown {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 954f10485e7SMark Brown {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 955f10485e7SMark Brown 956f10485e7SMark Brown /* Out Mixer PGAs */ 957f10485e7SMark Brown {"LOPGA", NULL, "LOMIX"}, 958f10485e7SMark Brown {"ROPGA", NULL, "ROMIX"}, 959f10485e7SMark Brown 960f10485e7SMark Brown {"LOUT PGA", NULL, "LOMIX"}, 961f10485e7SMark Brown {"ROUT PGA", NULL, "ROMIX"}, 962f10485e7SMark Brown 963f10485e7SMark Brown /* Output Pins */ 964f10485e7SMark Brown {"LON", NULL, "LONMIX"}, 965f10485e7SMark Brown {"LOP", NULL, "LOPMIX"}, 966f10485e7SMark Brown {"OUT", NULL, "OUT3MIX"}, 967f10485e7SMark Brown {"LOUT", NULL, "LOUT PGA"}, 968f10485e7SMark Brown {"SPKN", NULL, "SPKMIX"}, 969f10485e7SMark Brown {"ROUT", NULL, "ROUT PGA"}, 970f10485e7SMark Brown {"OUT4", NULL, "OUT4MIX"}, 971f10485e7SMark Brown {"ROP", NULL, "ROPMIX"}, 972f10485e7SMark Brown {"RON", NULL, "RONMIX"}, 973f10485e7SMark Brown }; 974f10485e7SMark Brown 975f10485e7SMark Brown static int wm8990_add_widgets(struct snd_soc_codec *codec) 976f10485e7SMark Brown { 977f10485e7SMark Brown snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, 978f10485e7SMark Brown ARRAY_SIZE(wm8990_dapm_widgets)); 979f10485e7SMark Brown 980f10485e7SMark Brown /* set up the WM8990 audio map */ 981f10485e7SMark Brown snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 982f10485e7SMark Brown 983f10485e7SMark Brown snd_soc_dapm_new_widgets(codec); 984f10485e7SMark Brown return 0; 985f10485e7SMark Brown } 986f10485e7SMark Brown 987f10485e7SMark Brown /* PLL divisors */ 988f10485e7SMark Brown struct _pll_div { 989f10485e7SMark Brown u32 div2; 990f10485e7SMark Brown u32 n; 991f10485e7SMark Brown u32 k; 992f10485e7SMark Brown }; 993f10485e7SMark Brown 994f10485e7SMark Brown /* The size in bits of the pll divide multiplied by 10 995f10485e7SMark Brown * to allow rounding later */ 996f10485e7SMark Brown #define FIXED_PLL_SIZE ((1 << 16) * 10) 997f10485e7SMark Brown 998f10485e7SMark Brown static void pll_factors(struct _pll_div *pll_div, unsigned int target, 999f10485e7SMark Brown unsigned int source) 1000f10485e7SMark Brown { 1001f10485e7SMark Brown u64 Kpart; 1002f10485e7SMark Brown unsigned int K, Ndiv, Nmod; 1003f10485e7SMark Brown 1004f10485e7SMark Brown 1005f10485e7SMark Brown Ndiv = target / source; 1006f10485e7SMark Brown if (Ndiv < 6) { 1007f10485e7SMark Brown source >>= 1; 1008f10485e7SMark Brown pll_div->div2 = 1; 1009f10485e7SMark Brown Ndiv = target / source; 1010f10485e7SMark Brown } else 1011f10485e7SMark Brown pll_div->div2 = 0; 1012f10485e7SMark Brown 1013f10485e7SMark Brown if ((Ndiv < 6) || (Ndiv > 12)) 1014f10485e7SMark Brown printk(KERN_WARNING 1015f10485e7SMark Brown "WM8990 N value outwith recommended range! N = %d\n", Ndiv); 1016f10485e7SMark Brown 1017f10485e7SMark Brown pll_div->n = Ndiv; 1018f10485e7SMark Brown Nmod = target % source; 1019f10485e7SMark Brown Kpart = FIXED_PLL_SIZE * (long long)Nmod; 1020f10485e7SMark Brown 1021f10485e7SMark Brown do_div(Kpart, source); 1022f10485e7SMark Brown 1023f10485e7SMark Brown K = Kpart & 0xFFFFFFFF; 1024f10485e7SMark Brown 1025f10485e7SMark Brown /* Check if we need to round */ 1026f10485e7SMark Brown if ((K % 10) >= 5) 1027f10485e7SMark Brown K += 5; 1028f10485e7SMark Brown 1029f10485e7SMark Brown /* Move down to proper range now rounding is done */ 1030f10485e7SMark Brown K /= 10; 1031f10485e7SMark Brown 1032f10485e7SMark Brown pll_div->k = K; 1033f10485e7SMark Brown } 1034f10485e7SMark Brown 1035e550e17fSLiam Girdwood static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, 1036f10485e7SMark Brown int pll_id, unsigned int freq_in, unsigned int freq_out) 1037f10485e7SMark Brown { 1038f10485e7SMark Brown u16 reg; 1039f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1040f10485e7SMark Brown struct _pll_div pll_div; 1041f10485e7SMark Brown 1042f10485e7SMark Brown if (freq_in && freq_out) { 1043f10485e7SMark Brown pll_factors(&pll_div, freq_out * 4, freq_in); 1044f10485e7SMark Brown 1045f10485e7SMark Brown /* Turn on PLL */ 1046f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1047f10485e7SMark Brown reg |= WM8990_PLL_ENA; 1048f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1049f10485e7SMark Brown 1050f10485e7SMark Brown /* sysclk comes from PLL */ 1051f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2); 1052f10485e7SMark Brown wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 1053f10485e7SMark Brown 1054f10485e7SMark Brown /* set up N , fractional mode and pre-divisor if neccessary */ 1055f10485e7SMark Brown wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 1056f10485e7SMark Brown (pll_div.div2?WM8990_PRESCALE:0)); 1057f10485e7SMark Brown wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 1058f10485e7SMark Brown wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 1059f10485e7SMark Brown } else { 1060f10485e7SMark Brown /* Turn on PLL */ 1061f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1062f10485e7SMark Brown reg &= ~WM8990_PLL_ENA; 1063f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1064f10485e7SMark Brown } 1065f10485e7SMark Brown return 0; 1066f10485e7SMark Brown } 1067f10485e7SMark Brown 1068f10485e7SMark Brown /* 1069f10485e7SMark Brown * Clock after PLL and dividers 1070f10485e7SMark Brown */ 1071e550e17fSLiam Girdwood static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1072f10485e7SMark Brown int clk_id, unsigned int freq, int dir) 1073f10485e7SMark Brown { 1074f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1075f10485e7SMark Brown struct wm8990_priv *wm8990 = codec->private_data; 1076f10485e7SMark Brown 1077f10485e7SMark Brown wm8990->sysclk = freq; 1078f10485e7SMark Brown return 0; 1079f10485e7SMark Brown } 1080f10485e7SMark Brown 1081f10485e7SMark Brown /* 1082f10485e7SMark Brown * Set's ADC and Voice DAC format. 1083f10485e7SMark Brown */ 1084e550e17fSLiam Girdwood static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai, 1085f10485e7SMark Brown unsigned int fmt) 1086f10485e7SMark Brown { 1087f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1088f10485e7SMark Brown u16 audio1, audio3; 1089f10485e7SMark Brown 1090f10485e7SMark Brown audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1091f10485e7SMark Brown audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3); 1092f10485e7SMark Brown 1093f10485e7SMark Brown /* set master/slave audio interface */ 1094f10485e7SMark Brown switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1095f10485e7SMark Brown case SND_SOC_DAIFMT_CBS_CFS: 1096f10485e7SMark Brown audio3 &= ~WM8990_AIF_MSTR1; 1097f10485e7SMark Brown break; 1098f10485e7SMark Brown case SND_SOC_DAIFMT_CBM_CFM: 1099f10485e7SMark Brown audio3 |= WM8990_AIF_MSTR1; 1100f10485e7SMark Brown break; 1101f10485e7SMark Brown default: 1102f10485e7SMark Brown return -EINVAL; 1103f10485e7SMark Brown } 1104f10485e7SMark Brown 1105f10485e7SMark Brown audio1 &= ~WM8990_AIF_FMT_MASK; 1106f10485e7SMark Brown 1107f10485e7SMark Brown /* interface format */ 1108f10485e7SMark Brown switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1109f10485e7SMark Brown case SND_SOC_DAIFMT_I2S: 1110f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_I2S; 1111f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1112f10485e7SMark Brown break; 1113f10485e7SMark Brown case SND_SOC_DAIFMT_RIGHT_J: 1114f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_RIGHTJ; 1115f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1116f10485e7SMark Brown break; 1117f10485e7SMark Brown case SND_SOC_DAIFMT_LEFT_J: 1118f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_LEFTJ; 1119f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1120f10485e7SMark Brown break; 1121f10485e7SMark Brown case SND_SOC_DAIFMT_DSP_A: 1122f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_DSP; 1123f10485e7SMark Brown audio1 &= ~WM8990_AIF_LRCLK_INV; 1124f10485e7SMark Brown break; 1125f10485e7SMark Brown case SND_SOC_DAIFMT_DSP_B: 1126f10485e7SMark Brown audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV; 1127f10485e7SMark Brown break; 1128f10485e7SMark Brown default: 1129f10485e7SMark Brown return -EINVAL; 1130f10485e7SMark Brown } 1131f10485e7SMark Brown 1132f10485e7SMark Brown wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1133f10485e7SMark Brown wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1134f10485e7SMark Brown return 0; 1135f10485e7SMark Brown } 1136f10485e7SMark Brown 1137e550e17fSLiam Girdwood static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1138f10485e7SMark Brown int div_id, int div) 1139f10485e7SMark Brown { 1140f10485e7SMark Brown struct snd_soc_codec *codec = codec_dai->codec; 1141f10485e7SMark Brown u16 reg; 1142f10485e7SMark Brown 1143f10485e7SMark Brown switch (div_id) { 1144f10485e7SMark Brown case WM8990_MCLK_DIV: 1145f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1146f10485e7SMark Brown ~WM8990_MCLK_DIV_MASK; 1147f10485e7SMark Brown wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1148f10485e7SMark Brown break; 1149f10485e7SMark Brown case WM8990_DACCLK_DIV: 1150f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1151f10485e7SMark Brown ~WM8990_DAC_CLKDIV_MASK; 1152f10485e7SMark Brown wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1153f10485e7SMark Brown break; 1154f10485e7SMark Brown case WM8990_ADCCLK_DIV: 1155f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1156f10485e7SMark Brown ~WM8990_ADC_CLKDIV_MASK; 1157f10485e7SMark Brown wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1158f10485e7SMark Brown break; 1159f10485e7SMark Brown case WM8990_BCLK_DIV: 1160f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) & 1161f10485e7SMark Brown ~WM8990_BCLK_DIV_MASK; 1162f10485e7SMark Brown wm8990_write(codec, WM8990_CLOCKING_1, reg | div); 1163f10485e7SMark Brown break; 1164f10485e7SMark Brown default: 1165f10485e7SMark Brown return -EINVAL; 1166f10485e7SMark Brown } 1167f10485e7SMark Brown 1168f10485e7SMark Brown return 0; 1169f10485e7SMark Brown } 1170f10485e7SMark Brown 1171f10485e7SMark Brown /* 1172f10485e7SMark Brown * Set PCM DAI bit size and sample rate. 1173f10485e7SMark Brown */ 1174f10485e7SMark Brown static int wm8990_hw_params(struct snd_pcm_substream *substream, 1175f10485e7SMark Brown struct snd_pcm_hw_params *params) 1176f10485e7SMark Brown { 1177f10485e7SMark Brown struct snd_soc_pcm_runtime *rtd = substream->private_data; 1178f10485e7SMark Brown struct snd_soc_device *socdev = rtd->socdev; 1179f10485e7SMark Brown struct snd_soc_codec *codec = socdev->codec; 1180f10485e7SMark Brown u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1181f10485e7SMark Brown 1182f10485e7SMark Brown audio1 &= ~WM8990_AIF_WL_MASK; 1183f10485e7SMark Brown /* bit size */ 1184f10485e7SMark Brown switch (params_format(params)) { 1185f10485e7SMark Brown case SNDRV_PCM_FORMAT_S16_LE: 1186f10485e7SMark Brown break; 1187f10485e7SMark Brown case SNDRV_PCM_FORMAT_S20_3LE: 1188f10485e7SMark Brown audio1 |= WM8990_AIF_WL_20BITS; 1189f10485e7SMark Brown break; 1190f10485e7SMark Brown case SNDRV_PCM_FORMAT_S24_LE: 1191f10485e7SMark Brown audio1 |= WM8990_AIF_WL_24BITS; 1192f10485e7SMark Brown break; 1193f10485e7SMark Brown case SNDRV_PCM_FORMAT_S32_LE: 1194f10485e7SMark Brown audio1 |= WM8990_AIF_WL_32BITS; 1195f10485e7SMark Brown break; 1196f10485e7SMark Brown } 1197f10485e7SMark Brown 1198f10485e7SMark Brown wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1199f10485e7SMark Brown return 0; 1200f10485e7SMark Brown } 1201f10485e7SMark Brown 1202e550e17fSLiam Girdwood static int wm8990_mute(struct snd_soc_dai *dai, int mute) 1203f10485e7SMark Brown { 1204f10485e7SMark Brown struct snd_soc_codec *codec = dai->codec; 1205f10485e7SMark Brown u16 val; 1206f10485e7SMark Brown 1207f10485e7SMark Brown val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1208f10485e7SMark Brown 1209f10485e7SMark Brown if (mute) 1210f10485e7SMark Brown wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1211f10485e7SMark Brown else 1212f10485e7SMark Brown wm8990_write(codec, WM8990_DAC_CTRL, val); 1213f10485e7SMark Brown 1214f10485e7SMark Brown return 0; 1215f10485e7SMark Brown } 1216f10485e7SMark Brown 1217f10485e7SMark Brown static int wm8990_set_bias_level(struct snd_soc_codec *codec, 1218f10485e7SMark Brown enum snd_soc_bias_level level) 1219f10485e7SMark Brown { 1220f10485e7SMark Brown u16 val; 1221f10485e7SMark Brown 1222f10485e7SMark Brown switch (level) { 1223f10485e7SMark Brown case SND_SOC_BIAS_ON: 1224f10485e7SMark Brown break; 1225*2adb9833SMark Brown 1226f10485e7SMark Brown case SND_SOC_BIAS_PREPARE: 1227*2adb9833SMark Brown /* VMID=2*50k */ 1228*2adb9833SMark Brown val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1229*2adb9833SMark Brown ~WM8990_VMID_MODE_MASK; 1230*2adb9833SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1231f10485e7SMark Brown break; 1232*2adb9833SMark Brown 1233f10485e7SMark Brown case SND_SOC_BIAS_STANDBY: 1234f10485e7SMark Brown if (codec->bias_level == SND_SOC_BIAS_OFF) { 1235f10485e7SMark Brown /* Enable all output discharge bits */ 1236f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1237f10485e7SMark Brown WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1238f10485e7SMark Brown WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1239f10485e7SMark Brown WM8990_DIS_ROUT); 1240f10485e7SMark Brown 1241f10485e7SMark Brown /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1242f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1243f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1244f10485e7SMark Brown WM8990_VMIDTOG); 1245f10485e7SMark Brown 1246f10485e7SMark Brown /* Delay to allow output caps to discharge */ 1247f10485e7SMark Brown msleep(msecs_to_jiffies(300)); 1248f10485e7SMark Brown 1249f10485e7SMark Brown /* Disable VMIDTOG */ 1250f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1251f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL); 1252f10485e7SMark Brown 1253f10485e7SMark Brown /* disable all output discharge bits */ 1254f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP1, 0); 1255f10485e7SMark Brown 1256f10485e7SMark Brown /* Enable outputs */ 1257f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1258f10485e7SMark Brown 1259f10485e7SMark Brown msleep(msecs_to_jiffies(50)); 1260f10485e7SMark Brown 1261f10485e7SMark Brown /* Enable VMID at 2x50k */ 1262f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1263f10485e7SMark Brown 1264f10485e7SMark Brown msleep(msecs_to_jiffies(100)); 1265f10485e7SMark Brown 1266f10485e7SMark Brown /* Enable VREF */ 1267f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1268f10485e7SMark Brown 1269f10485e7SMark Brown msleep(msecs_to_jiffies(600)); 1270f10485e7SMark Brown 1271f10485e7SMark Brown /* Enable BUFIOEN */ 1272f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1273f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1274f10485e7SMark Brown WM8990_BUFIOEN); 1275f10485e7SMark Brown 1276f10485e7SMark Brown /* Disable outputs */ 1277f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1278f10485e7SMark Brown 1279f10485e7SMark Brown /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1280f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1281f10485e7SMark Brown 1282be1b87c7SMark Brown /* Enable workaround for ADC clocking issue. */ 1283be1b87c7SMark Brown wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1284be1b87c7SMark Brown wm8990_write(codec, WM8990_EXT_CTL1, 0xa003); 1285be1b87c7SMark Brown wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1286f10485e7SMark Brown } 1287*2adb9833SMark Brown 1288*2adb9833SMark Brown /* VMID=2*250k */ 1289*2adb9833SMark Brown val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1290*2adb9833SMark Brown ~WM8990_VMID_MODE_MASK; 1291*2adb9833SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1292f10485e7SMark Brown break; 1293f10485e7SMark Brown 1294f10485e7SMark Brown case SND_SOC_BIAS_OFF: 1295f10485e7SMark Brown /* Enable POBCTRL and SOFT_ST */ 1296f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1297f10485e7SMark Brown WM8990_POBCTRL | WM8990_BUFIOEN); 1298f10485e7SMark Brown 1299f10485e7SMark Brown /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1300f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1301f10485e7SMark Brown WM8990_BUFDCOPEN | WM8990_POBCTRL | 1302f10485e7SMark Brown WM8990_BUFIOEN); 1303f10485e7SMark Brown 1304f10485e7SMark Brown /* mute DAC */ 1305f10485e7SMark Brown val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL); 1306f10485e7SMark Brown wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1307f10485e7SMark Brown 1308f10485e7SMark Brown /* Enable any disabled outputs */ 1309f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1310f10485e7SMark Brown 1311f10485e7SMark Brown /* Disable VMID */ 1312f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1313f10485e7SMark Brown 1314f10485e7SMark Brown msleep(msecs_to_jiffies(300)); 1315f10485e7SMark Brown 1316f10485e7SMark Brown /* Enable all output discharge bits */ 1317f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1318f10485e7SMark Brown WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1319f10485e7SMark Brown WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1320f10485e7SMark Brown WM8990_DIS_ROUT); 1321f10485e7SMark Brown 1322f10485e7SMark Brown /* Disable VREF */ 1323f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1324f10485e7SMark Brown 1325f10485e7SMark Brown /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1326f10485e7SMark Brown wm8990_write(codec, WM8990_ANTIPOP2, 0x0); 1327f10485e7SMark Brown break; 1328f10485e7SMark Brown } 1329f10485e7SMark Brown 1330f10485e7SMark Brown codec->bias_level = level; 1331f10485e7SMark Brown return 0; 1332f10485e7SMark Brown } 1333f10485e7SMark Brown 1334f10485e7SMark Brown #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 1335f10485e7SMark Brown SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ 1336f10485e7SMark Brown SNDRV_PCM_RATE_48000) 1337f10485e7SMark Brown 1338f10485e7SMark Brown #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1339f10485e7SMark Brown SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1340f10485e7SMark Brown 1341f10485e7SMark Brown /* 1342f10485e7SMark Brown * The WM8990 supports 2 different and mutually exclusive DAI 1343f10485e7SMark Brown * configurations. 1344f10485e7SMark Brown * 1345f10485e7SMark Brown * 1. ADC/DAC on Primary Interface 1346f10485e7SMark Brown * 2. ADC on Primary Interface/DAC on secondary 1347f10485e7SMark Brown */ 1348e550e17fSLiam Girdwood struct snd_soc_dai wm8990_dai = { 1349f10485e7SMark Brown /* ADC/DAC on primary */ 1350f10485e7SMark Brown .name = "WM8990 ADC/DAC Primary", 1351f10485e7SMark Brown .id = 1, 1352f10485e7SMark Brown .playback = { 1353f10485e7SMark Brown .stream_name = "Playback", 1354f10485e7SMark Brown .channels_min = 1, 1355f10485e7SMark Brown .channels_max = 2, 1356f10485e7SMark Brown .rates = WM8990_RATES, 1357f10485e7SMark Brown .formats = WM8990_FORMATS,}, 1358f10485e7SMark Brown .capture = { 1359f10485e7SMark Brown .stream_name = "Capture", 1360f10485e7SMark Brown .channels_min = 1, 1361f10485e7SMark Brown .channels_max = 2, 1362f10485e7SMark Brown .rates = WM8990_RATES, 1363f10485e7SMark Brown .formats = WM8990_FORMATS,}, 1364f10485e7SMark Brown .ops = { 1365f10485e7SMark Brown .hw_params = wm8990_hw_params,}, 1366f10485e7SMark Brown .dai_ops = { 1367f10485e7SMark Brown .digital_mute = wm8990_mute, 1368f10485e7SMark Brown .set_fmt = wm8990_set_dai_fmt, 1369f10485e7SMark Brown .set_clkdiv = wm8990_set_dai_clkdiv, 1370f10485e7SMark Brown .set_pll = wm8990_set_dai_pll, 1371f10485e7SMark Brown .set_sysclk = wm8990_set_dai_sysclk, 1372f10485e7SMark Brown }, 1373f10485e7SMark Brown }; 1374f10485e7SMark Brown EXPORT_SYMBOL_GPL(wm8990_dai); 1375f10485e7SMark Brown 1376f10485e7SMark Brown static int wm8990_suspend(struct platform_device *pdev, pm_message_t state) 1377f10485e7SMark Brown { 1378f10485e7SMark Brown struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1379f10485e7SMark Brown struct snd_soc_codec *codec = socdev->codec; 1380f10485e7SMark Brown 1381f10485e7SMark Brown /* we only need to suspend if we are a valid card */ 1382f10485e7SMark Brown if (!codec->card) 1383f10485e7SMark Brown return 0; 1384f10485e7SMark Brown 1385f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1386f10485e7SMark Brown return 0; 1387f10485e7SMark Brown } 1388f10485e7SMark Brown 1389f10485e7SMark Brown static int wm8990_resume(struct platform_device *pdev) 1390f10485e7SMark Brown { 1391f10485e7SMark Brown struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1392f10485e7SMark Brown struct snd_soc_codec *codec = socdev->codec; 1393f10485e7SMark Brown int i; 1394f10485e7SMark Brown u8 data[2]; 1395f10485e7SMark Brown u16 *cache = codec->reg_cache; 1396f10485e7SMark Brown 1397f10485e7SMark Brown /* we only need to resume if we are a valid card */ 1398f10485e7SMark Brown if (!codec->card) 1399f10485e7SMark Brown return 0; 1400f10485e7SMark Brown 1401f10485e7SMark Brown /* Sync reg_cache with the hardware */ 1402f10485e7SMark Brown for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) { 1403f10485e7SMark Brown if (i + 1 == WM8990_RESET) 1404f10485e7SMark Brown continue; 1405f10485e7SMark Brown data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001); 1406f10485e7SMark Brown data[1] = cache[i] & 0x00ff; 1407f10485e7SMark Brown codec->hw_write(codec->control_data, data, 2); 1408f10485e7SMark Brown } 1409f10485e7SMark Brown 1410f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1411f10485e7SMark Brown return 0; 1412f10485e7SMark Brown } 1413f10485e7SMark Brown 1414f10485e7SMark Brown /* 1415f10485e7SMark Brown * initialise the WM8990 driver 1416f10485e7SMark Brown * register the mixer and dsp interfaces with the kernel 1417f10485e7SMark Brown */ 1418f10485e7SMark Brown static int wm8990_init(struct snd_soc_device *socdev) 1419f10485e7SMark Brown { 1420f10485e7SMark Brown struct snd_soc_codec *codec = socdev->codec; 1421f10485e7SMark Brown u16 reg; 1422f10485e7SMark Brown int ret = 0; 1423f10485e7SMark Brown 1424f10485e7SMark Brown codec->name = "WM8990"; 1425f10485e7SMark Brown codec->owner = THIS_MODULE; 1426f10485e7SMark Brown codec->read = wm8990_read_reg_cache; 1427f10485e7SMark Brown codec->write = wm8990_write; 1428f10485e7SMark Brown codec->set_bias_level = wm8990_set_bias_level; 1429f10485e7SMark Brown codec->dai = &wm8990_dai; 1430f10485e7SMark Brown codec->num_dai = 2; 1431f10485e7SMark Brown codec->reg_cache_size = ARRAY_SIZE(wm8990_reg); 1432f10485e7SMark Brown codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL); 1433f10485e7SMark Brown 1434f10485e7SMark Brown if (codec->reg_cache == NULL) 1435f10485e7SMark Brown return -ENOMEM; 1436f10485e7SMark Brown 1437f10485e7SMark Brown wm8990_reset(codec); 1438f10485e7SMark Brown 1439f10485e7SMark Brown /* register pcms */ 1440f10485e7SMark Brown ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1441f10485e7SMark Brown if (ret < 0) { 1442f10485e7SMark Brown printk(KERN_ERR "wm8990: failed to create pcms\n"); 1443f10485e7SMark Brown goto pcm_err; 1444f10485e7SMark Brown } 1445f10485e7SMark Brown 1446f10485e7SMark Brown /* charge output caps */ 1447f10485e7SMark Brown codec->bias_level = SND_SOC_BIAS_OFF; 1448f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1449f10485e7SMark Brown 1450f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4); 1451f10485e7SMark Brown wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1452f10485e7SMark Brown 1453f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) & 1454f10485e7SMark Brown ~WM8990_GPIO1_SEL_MASK; 1455f10485e7SMark Brown wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1456f10485e7SMark Brown 1457f10485e7SMark Brown reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1458f10485e7SMark Brown wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1459f10485e7SMark Brown 1460f10485e7SMark Brown wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1461f10485e7SMark Brown wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1462f10485e7SMark Brown 1463f10485e7SMark Brown wm8990_add_controls(codec); 1464f10485e7SMark Brown wm8990_add_widgets(codec); 1465f10485e7SMark Brown ret = snd_soc_register_card(socdev); 1466f10485e7SMark Brown if (ret < 0) { 1467f10485e7SMark Brown printk(KERN_ERR "wm8990: failed to register card\n"); 1468f10485e7SMark Brown goto card_err; 1469f10485e7SMark Brown } 1470f10485e7SMark Brown return ret; 1471f10485e7SMark Brown 1472f10485e7SMark Brown card_err: 1473f10485e7SMark Brown snd_soc_free_pcms(socdev); 1474f10485e7SMark Brown snd_soc_dapm_free(socdev); 1475f10485e7SMark Brown pcm_err: 1476f10485e7SMark Brown kfree(codec->reg_cache); 1477f10485e7SMark Brown return ret; 1478f10485e7SMark Brown } 1479f10485e7SMark Brown 1480f10485e7SMark Brown /* If the i2c layer weren't so broken, we could pass this kind of data 1481f10485e7SMark Brown around */ 1482f10485e7SMark Brown static struct snd_soc_device *wm8990_socdev; 1483f10485e7SMark Brown 1484f10485e7SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1485f10485e7SMark Brown 1486f10485e7SMark Brown /* 1487f10485e7SMark Brown * WM891 2 wire address is determined by GPIO5 1488f10485e7SMark Brown * state during powerup. 1489f10485e7SMark Brown * low = 0x34 1490f10485e7SMark Brown * high = 0x36 1491f10485e7SMark Brown */ 1492f10485e7SMark Brown 1493e5d3fd38SJean Delvare static int wm8990_i2c_probe(struct i2c_client *i2c, 1494e5d3fd38SJean Delvare const struct i2c_device_id *id) 1495f10485e7SMark Brown { 1496f10485e7SMark Brown struct snd_soc_device *socdev = wm8990_socdev; 1497f10485e7SMark Brown struct snd_soc_codec *codec = socdev->codec; 1498f10485e7SMark Brown int ret; 1499f10485e7SMark Brown 1500f10485e7SMark Brown i2c_set_clientdata(i2c, codec); 1501f10485e7SMark Brown codec->control_data = i2c; 1502f10485e7SMark Brown 1503f10485e7SMark Brown ret = wm8990_init(socdev); 1504e5d3fd38SJean Delvare if (ret < 0) 1505a5c95e90SMark Brown pr_err("failed to initialise WM8990\n"); 1506f10485e7SMark Brown 1507f10485e7SMark Brown return ret; 1508f10485e7SMark Brown } 1509f10485e7SMark Brown 1510e5d3fd38SJean Delvare static int wm8990_i2c_remove(struct i2c_client *client) 1511f10485e7SMark Brown { 1512f10485e7SMark Brown struct snd_soc_codec *codec = i2c_get_clientdata(client); 1513f10485e7SMark Brown kfree(codec->reg_cache); 1514f10485e7SMark Brown return 0; 1515f10485e7SMark Brown } 1516f10485e7SMark Brown 1517e5d3fd38SJean Delvare static const struct i2c_device_id wm8990_i2c_id[] = { 1518e5d3fd38SJean Delvare { "wm8990", 0 }, 1519e5d3fd38SJean Delvare { } 1520e5d3fd38SJean Delvare }; 1521e5d3fd38SJean Delvare MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); 1522f10485e7SMark Brown 1523f10485e7SMark Brown static struct i2c_driver wm8990_i2c_driver = { 1524f10485e7SMark Brown .driver = { 1525f10485e7SMark Brown .name = "WM8990 I2C Codec", 1526f10485e7SMark Brown .owner = THIS_MODULE, 1527f10485e7SMark Brown }, 1528e5d3fd38SJean Delvare .probe = wm8990_i2c_probe, 1529e5d3fd38SJean Delvare .remove = wm8990_i2c_remove, 1530e5d3fd38SJean Delvare .id_table = wm8990_i2c_id, 1531f10485e7SMark Brown }; 1532f10485e7SMark Brown 1533e5d3fd38SJean Delvare static int wm8990_add_i2c_device(struct platform_device *pdev, 1534e5d3fd38SJean Delvare const struct wm8990_setup_data *setup) 1535e5d3fd38SJean Delvare { 1536e5d3fd38SJean Delvare struct i2c_board_info info; 1537e5d3fd38SJean Delvare struct i2c_adapter *adapter; 1538e5d3fd38SJean Delvare struct i2c_client *client; 1539e5d3fd38SJean Delvare int ret; 1540e5d3fd38SJean Delvare 1541e5d3fd38SJean Delvare ret = i2c_add_driver(&wm8990_i2c_driver); 1542e5d3fd38SJean Delvare if (ret != 0) { 1543e5d3fd38SJean Delvare dev_err(&pdev->dev, "can't add i2c driver\n"); 1544e5d3fd38SJean Delvare return ret; 1545e5d3fd38SJean Delvare } 1546e5d3fd38SJean Delvare 1547e5d3fd38SJean Delvare memset(&info, 0, sizeof(struct i2c_board_info)); 1548e5d3fd38SJean Delvare info.addr = setup->i2c_address; 1549e5d3fd38SJean Delvare strlcpy(info.type, "wm8990", I2C_NAME_SIZE); 1550e5d3fd38SJean Delvare 1551e5d3fd38SJean Delvare adapter = i2c_get_adapter(setup->i2c_bus); 1552e5d3fd38SJean Delvare if (!adapter) { 1553e5d3fd38SJean Delvare dev_err(&pdev->dev, "can't get i2c adapter %d\n", 1554e5d3fd38SJean Delvare setup->i2c_bus); 1555e5d3fd38SJean Delvare goto err_driver; 1556e5d3fd38SJean Delvare } 1557e5d3fd38SJean Delvare 1558e5d3fd38SJean Delvare client = i2c_new_device(adapter, &info); 1559e5d3fd38SJean Delvare i2c_put_adapter(adapter); 1560e5d3fd38SJean Delvare if (!client) { 1561e5d3fd38SJean Delvare dev_err(&pdev->dev, "can't add i2c device at 0x%x\n", 1562e5d3fd38SJean Delvare (unsigned int)info.addr); 1563e5d3fd38SJean Delvare goto err_driver; 1564e5d3fd38SJean Delvare } 1565e5d3fd38SJean Delvare 1566e5d3fd38SJean Delvare return 0; 1567e5d3fd38SJean Delvare 1568e5d3fd38SJean Delvare err_driver: 1569e5d3fd38SJean Delvare i2c_del_driver(&wm8990_i2c_driver); 1570e5d3fd38SJean Delvare return -ENODEV; 1571e5d3fd38SJean Delvare } 1572f10485e7SMark Brown #endif 1573f10485e7SMark Brown 1574f10485e7SMark Brown static int wm8990_probe(struct platform_device *pdev) 1575f10485e7SMark Brown { 1576f10485e7SMark Brown struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1577f10485e7SMark Brown struct wm8990_setup_data *setup; 1578f10485e7SMark Brown struct snd_soc_codec *codec; 1579f10485e7SMark Brown struct wm8990_priv *wm8990; 1580b7c9d852SMark Brown int ret; 1581f10485e7SMark Brown 1582a5c95e90SMark Brown pr_info("WM8990 Audio Codec %s\n", WM8990_VERSION); 1583f10485e7SMark Brown 1584f10485e7SMark Brown setup = socdev->codec_data; 1585f10485e7SMark Brown codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); 1586f10485e7SMark Brown if (codec == NULL) 1587f10485e7SMark Brown return -ENOMEM; 1588f10485e7SMark Brown 1589f10485e7SMark Brown wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL); 1590f10485e7SMark Brown if (wm8990 == NULL) { 1591f10485e7SMark Brown kfree(codec); 1592f10485e7SMark Brown return -ENOMEM; 1593f10485e7SMark Brown } 1594f10485e7SMark Brown 1595f10485e7SMark Brown codec->private_data = wm8990; 1596f10485e7SMark Brown socdev->codec = codec; 1597f10485e7SMark Brown mutex_init(&codec->mutex); 1598f10485e7SMark Brown INIT_LIST_HEAD(&codec->dapm_widgets); 1599f10485e7SMark Brown INIT_LIST_HEAD(&codec->dapm_paths); 1600f10485e7SMark Brown wm8990_socdev = socdev; 1601f10485e7SMark Brown 1602b7c9d852SMark Brown ret = -ENODEV; 1603b7c9d852SMark Brown 1604f10485e7SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1605f10485e7SMark Brown if (setup->i2c_address) { 1606f10485e7SMark Brown codec->hw_write = (hw_write_t)i2c_master_send; 1607e5d3fd38SJean Delvare ret = wm8990_add_i2c_device(pdev, setup); 1608f10485e7SMark Brown } 1609f10485e7SMark Brown #endif 16103051e41aSJean Delvare 16113051e41aSJean Delvare if (ret != 0) { 16123051e41aSJean Delvare kfree(codec->private_data); 16133051e41aSJean Delvare kfree(codec); 16143051e41aSJean Delvare } 1615f10485e7SMark Brown return ret; 1616f10485e7SMark Brown } 1617f10485e7SMark Brown 1618f10485e7SMark Brown /* power down chip */ 1619f10485e7SMark Brown static int wm8990_remove(struct platform_device *pdev) 1620f10485e7SMark Brown { 1621f10485e7SMark Brown struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1622f10485e7SMark Brown struct snd_soc_codec *codec = socdev->codec; 1623f10485e7SMark Brown 1624f10485e7SMark Brown if (codec->control_data) 1625f10485e7SMark Brown wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); 1626f10485e7SMark Brown snd_soc_free_pcms(socdev); 1627f10485e7SMark Brown snd_soc_dapm_free(socdev); 1628f10485e7SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1629e5d3fd38SJean Delvare i2c_unregister_device(codec->control_data); 1630f10485e7SMark Brown i2c_del_driver(&wm8990_i2c_driver); 1631f10485e7SMark Brown #endif 1632f10485e7SMark Brown kfree(codec->private_data); 1633f10485e7SMark Brown kfree(codec); 1634f10485e7SMark Brown 1635f10485e7SMark Brown return 0; 1636f10485e7SMark Brown } 1637f10485e7SMark Brown 1638f10485e7SMark Brown struct snd_soc_codec_device soc_codec_dev_wm8990 = { 1639f10485e7SMark Brown .probe = wm8990_probe, 1640f10485e7SMark Brown .remove = wm8990_remove, 1641f10485e7SMark Brown .suspend = wm8990_suspend, 1642f10485e7SMark Brown .resume = wm8990_resume, 1643f10485e7SMark Brown }; 1644f10485e7SMark Brown EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990); 1645f10485e7SMark Brown 1646f10485e7SMark Brown MODULE_DESCRIPTION("ASoC WM8990 driver"); 1647f10485e7SMark Brown MODULE_AUTHOR("Liam Girdwood"); 1648f10485e7SMark Brown MODULE_LICENSE("GPL"); 1649