xref: /linux/sound/soc/codecs/wm8983.c (revision 60e13231561b3a4c5269bfa1ef6c0569ad6f28ec)
1 /*
2  * wm8983.c  --  WM8983 ALSA SoC Audio driver
3  *
4  * Copyright 2011 Wolfson Microelectronics plc
5  *
6  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/spi/spi.h>
20 #include <linux/slab.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/initval.h>
26 #include <sound/tlv.h>
27 
28 #include "wm8983.h"
29 
30 static const u16 wm8983_reg_defs[WM8983_MAX_REGISTER + 1] = {
31 	[0x00] = 0x0000,     /* R0  - Software Reset */
32 	[0x01] = 0x0000,     /* R1  - Power management 1 */
33 	[0x02] = 0x0000,     /* R2  - Power management 2 */
34 	[0x03] = 0x0000,     /* R3  - Power management 3 */
35 	[0x04] = 0x0050,     /* R4  - Audio Interface */
36 	[0x05] = 0x0000,     /* R5  - Companding control */
37 	[0x06] = 0x0140,     /* R6  - Clock Gen control */
38 	[0x07] = 0x0000,     /* R7  - Additional control */
39 	[0x08] = 0x0000,     /* R8  - GPIO Control */
40 	[0x09] = 0x0000,     /* R9  - Jack Detect Control 1 */
41 	[0x0A] = 0x0000,     /* R10 - DAC Control */
42 	[0x0B] = 0x00FF,     /* R11 - Left DAC digital Vol */
43 	[0x0C] = 0x00FF,     /* R12 - Right DAC digital vol */
44 	[0x0D] = 0x0000,     /* R13 - Jack Detect Control 2 */
45 	[0x0E] = 0x0100,     /* R14 - ADC Control */
46 	[0x0F] = 0x00FF,     /* R15 - Left ADC Digital Vol */
47 	[0x10] = 0x00FF,     /* R16 - Right ADC Digital Vol */
48 	[0x12] = 0x012C,     /* R18 - EQ1 - low shelf */
49 	[0x13] = 0x002C,     /* R19 - EQ2 - peak 1 */
50 	[0x14] = 0x002C,     /* R20 - EQ3 - peak 2 */
51 	[0x15] = 0x002C,     /* R21 - EQ4 - peak 3 */
52 	[0x16] = 0x002C,     /* R22 - EQ5 - high shelf */
53 	[0x18] = 0x0032,     /* R24 - DAC Limiter 1 */
54 	[0x19] = 0x0000,     /* R25 - DAC Limiter 2 */
55 	[0x1B] = 0x0000,     /* R27 - Notch Filter 1 */
56 	[0x1C] = 0x0000,     /* R28 - Notch Filter 2 */
57 	[0x1D] = 0x0000,     /* R29 - Notch Filter 3 */
58 	[0x1E] = 0x0000,     /* R30 - Notch Filter 4 */
59 	[0x20] = 0x0038,     /* R32 - ALC control 1 */
60 	[0x21] = 0x000B,     /* R33 - ALC control 2 */
61 	[0x22] = 0x0032,     /* R34 - ALC control 3 */
62 	[0x23] = 0x0000,     /* R35 - Noise Gate */
63 	[0x24] = 0x0008,     /* R36 - PLL N */
64 	[0x25] = 0x000C,     /* R37 - PLL K 1 */
65 	[0x26] = 0x0093,     /* R38 - PLL K 2 */
66 	[0x27] = 0x00E9,     /* R39 - PLL K 3 */
67 	[0x29] = 0x0000,     /* R41 - 3D control */
68 	[0x2A] = 0x0000,     /* R42 - OUT4 to ADC */
69 	[0x2B] = 0x0000,     /* R43 - Beep control */
70 	[0x2C] = 0x0033,     /* R44 - Input ctrl */
71 	[0x2D] = 0x0010,     /* R45 - Left INP PGA gain ctrl */
72 	[0x2E] = 0x0010,     /* R46 - Right INP PGA gain ctrl */
73 	[0x2F] = 0x0100,     /* R47 - Left ADC BOOST ctrl */
74 	[0x30] = 0x0100,     /* R48 - Right ADC BOOST ctrl */
75 	[0x31] = 0x0002,     /* R49 - Output ctrl */
76 	[0x32] = 0x0001,     /* R50 - Left mixer ctrl */
77 	[0x33] = 0x0001,     /* R51 - Right mixer ctrl */
78 	[0x34] = 0x0039,     /* R52 - LOUT1 (HP) volume ctrl */
79 	[0x35] = 0x0039,     /* R53 - ROUT1 (HP) volume ctrl */
80 	[0x36] = 0x0039,     /* R54 - LOUT2 (SPK) volume ctrl */
81 	[0x37] = 0x0039,     /* R55 - ROUT2 (SPK) volume ctrl */
82 	[0x38] = 0x0001,     /* R56 - OUT3 mixer ctrl */
83 	[0x39] = 0x0001,     /* R57 - OUT4 (MONO) mix ctrl */
84 	[0x3D] = 0x0000      /* R61 - BIAS CTRL */
85 };
86 
87 static const struct wm8983_reg_access {
88 	u16 read; /* Mask of readable bits */
89 	u16 write; /* Mask of writable bits */
90 } wm8983_access_masks[WM8983_MAX_REGISTER + 1] = {
91 	[0x00] = { 0x0000, 0x01FF }, /* R0  - Software Reset */
92 	[0x01] = { 0x0000, 0x01FF }, /* R1  - Power management 1 */
93 	[0x02] = { 0x0000, 0x01FF }, /* R2  - Power management 2 */
94 	[0x03] = { 0x0000, 0x01EF }, /* R3  - Power management 3 */
95 	[0x04] = { 0x0000, 0x01FF }, /* R4  - Audio Interface */
96 	[0x05] = { 0x0000, 0x003F }, /* R5  - Companding control */
97 	[0x06] = { 0x0000, 0x01FD }, /* R6  - Clock Gen control */
98 	[0x07] = { 0x0000, 0x000F }, /* R7  - Additional control */
99 	[0x08] = { 0x0000, 0x003F }, /* R8  - GPIO Control */
100 	[0x09] = { 0x0000, 0x0070 }, /* R9  - Jack Detect Control 1 */
101 	[0x0A] = { 0x0000, 0x004F }, /* R10 - DAC Control */
102 	[0x0B] = { 0x0000, 0x01FF }, /* R11 - Left DAC digital Vol */
103 	[0x0C] = { 0x0000, 0x01FF }, /* R12 - Right DAC digital vol */
104 	[0x0D] = { 0x0000, 0x00FF }, /* R13 - Jack Detect Control 2 */
105 	[0x0E] = { 0x0000, 0x01FB }, /* R14 - ADC Control */
106 	[0x0F] = { 0x0000, 0x01FF }, /* R15 - Left ADC Digital Vol */
107 	[0x10] = { 0x0000, 0x01FF }, /* R16 - Right ADC Digital Vol */
108 	[0x12] = { 0x0000, 0x017F }, /* R18 - EQ1 - low shelf */
109 	[0x13] = { 0x0000, 0x017F }, /* R19 - EQ2 - peak 1 */
110 	[0x14] = { 0x0000, 0x017F }, /* R20 - EQ3 - peak 2 */
111 	[0x15] = { 0x0000, 0x017F }, /* R21 - EQ4 - peak 3 */
112 	[0x16] = { 0x0000, 0x007F }, /* R22 - EQ5 - high shelf */
113 	[0x18] = { 0x0000, 0x01FF }, /* R24 - DAC Limiter 1 */
114 	[0x19] = { 0x0000, 0x007F }, /* R25 - DAC Limiter 2 */
115 	[0x1B] = { 0x0000, 0x01FF }, /* R27 - Notch Filter 1 */
116 	[0x1C] = { 0x0000, 0x017F }, /* R28 - Notch Filter 2 */
117 	[0x1D] = { 0x0000, 0x017F }, /* R29 - Notch Filter 3 */
118 	[0x1E] = { 0x0000, 0x017F }, /* R30 - Notch Filter 4 */
119 	[0x20] = { 0x0000, 0x01BF }, /* R32 - ALC control 1 */
120 	[0x21] = { 0x0000, 0x00FF }, /* R33 - ALC control 2 */
121 	[0x22] = { 0x0000, 0x01FF }, /* R34 - ALC control 3 */
122 	[0x23] = { 0x0000, 0x000F }, /* R35 - Noise Gate */
123 	[0x24] = { 0x0000, 0x001F }, /* R36 - PLL N */
124 	[0x25] = { 0x0000, 0x003F }, /* R37 - PLL K 1 */
125 	[0x26] = { 0x0000, 0x01FF }, /* R38 - PLL K 2 */
126 	[0x27] = { 0x0000, 0x01FF }, /* R39 - PLL K 3 */
127 	[0x29] = { 0x0000, 0x000F }, /* R41 - 3D control */
128 	[0x2A] = { 0x0000, 0x01E7 }, /* R42 - OUT4 to ADC */
129 	[0x2B] = { 0x0000, 0x01BF }, /* R43 - Beep control */
130 	[0x2C] = { 0x0000, 0x0177 }, /* R44 - Input ctrl */
131 	[0x2D] = { 0x0000, 0x01FF }, /* R45 - Left INP PGA gain ctrl */
132 	[0x2E] = { 0x0000, 0x01FF }, /* R46 - Right INP PGA gain ctrl */
133 	[0x2F] = { 0x0000, 0x0177 }, /* R47 - Left ADC BOOST ctrl */
134 	[0x30] = { 0x0000, 0x0177 }, /* R48 - Right ADC BOOST ctrl */
135 	[0x31] = { 0x0000, 0x007F }, /* R49 - Output ctrl */
136 	[0x32] = { 0x0000, 0x01FF }, /* R50 - Left mixer ctrl */
137 	[0x33] = { 0x0000, 0x01FF }, /* R51 - Right mixer ctrl */
138 	[0x34] = { 0x0000, 0x01FF }, /* R52 - LOUT1 (HP) volume ctrl */
139 	[0x35] = { 0x0000, 0x01FF }, /* R53 - ROUT1 (HP) volume ctrl */
140 	[0x36] = { 0x0000, 0x01FF }, /* R54 - LOUT2 (SPK) volume ctrl */
141 	[0x37] = { 0x0000, 0x01FF }, /* R55 - ROUT2 (SPK) volume ctrl */
142 	[0x38] = { 0x0000, 0x004F }, /* R56 - OUT3 mixer ctrl */
143 	[0x39] = { 0x0000, 0x00FF }, /* R57 - OUT4 (MONO) mix ctrl */
144 	[0x3D] = { 0x0000, 0x0100 }  /* R61 - BIAS CTRL */
145 };
146 
147 /* vol/gain update regs */
148 static const int vol_update_regs[] = {
149 	WM8983_LEFT_DAC_DIGITAL_VOL,
150 	WM8983_RIGHT_DAC_DIGITAL_VOL,
151 	WM8983_LEFT_ADC_DIGITAL_VOL,
152 	WM8983_RIGHT_ADC_DIGITAL_VOL,
153 	WM8983_LOUT1_HP_VOLUME_CTRL,
154 	WM8983_ROUT1_HP_VOLUME_CTRL,
155 	WM8983_LOUT2_SPK_VOLUME_CTRL,
156 	WM8983_ROUT2_SPK_VOLUME_CTRL,
157 	WM8983_LEFT_INP_PGA_GAIN_CTRL,
158 	WM8983_RIGHT_INP_PGA_GAIN_CTRL
159 };
160 
161 struct wm8983_priv {
162 	enum snd_soc_control_type control_type;
163 	u32 sysclk;
164 	u32 bclk;
165 };
166 
167 static const struct {
168 	int div;
169 	int ratio;
170 } fs_ratios[] = {
171 	{ 10, 128 },
172 	{ 15, 192 },
173 	{ 20, 256 },
174 	{ 30, 384 },
175 	{ 40, 512 },
176 	{ 60, 768 },
177 	{ 80, 1024 },
178 	{ 120, 1536 }
179 };
180 
181 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
182 
183 static const int bclk_divs[] = {
184 	1, 2, 4, 8, 16, 32
185 };
186 
187 static int eqmode_get(struct snd_kcontrol *kcontrol,
188 		      struct snd_ctl_elem_value *ucontrol);
189 static int eqmode_put(struct snd_kcontrol *kcontrol,
190 		      struct snd_ctl_elem_value *ucontrol);
191 
192 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
193 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
194 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
195 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
196 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
197 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
198 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
199 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
200 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
201 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
202 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
203 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
204 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
205 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
206 
207 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
208 static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7,
209 				  alc_sel_text);
210 
211 static const char *alc_mode_text[] = { "ALC", "Limiter" };
212 static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8,
213 				  alc_mode_text);
214 
215 static const char *filter_mode_text[] = { "Audio", "Application" };
216 static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7,
217 				  filter_mode_text);
218 
219 static const char *eq_bw_text[] = { "Narrow", "Wide" };
220 static const char *eqmode_text[] = { "Capture", "Playback" };
221 static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
222 
223 static const char *eq1_cutoff_text[] = {
224 	"80Hz", "105Hz", "135Hz", "175Hz"
225 };
226 static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5,
227 				  eq1_cutoff_text);
228 static const char *eq2_cutoff_text[] = {
229 	"230Hz", "300Hz", "385Hz", "500Hz"
230 };
231 static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text);
232 static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5,
233 				  eq2_cutoff_text);
234 static const char *eq3_cutoff_text[] = {
235 	"650Hz", "850Hz", "1.1kHz", "1.4kHz"
236 };
237 static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text);
238 static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5,
239 				  eq3_cutoff_text);
240 static const char *eq4_cutoff_text[] = {
241 	"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
242 };
243 static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text);
244 static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5,
245 				  eq4_cutoff_text);
246 static const char *eq5_cutoff_text[] = {
247 	"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
248 };
249 static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5,
250 				  eq5_cutoff_text);
251 
252 static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
253 static const SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
254 
255 static const char *depth_3d_text[] = {
256 	"Off",
257 	"6.67%",
258 	"13.3%",
259 	"20%",
260 	"26.7%",
261 	"33.3%",
262 	"40%",
263 	"46.6%",
264 	"53.3%",
265 	"60%",
266 	"66.7%",
267 	"73.3%",
268 	"80%",
269 	"86.7%",
270 	"93.3%",
271 	"100%"
272 };
273 static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0,
274 				  depth_3d_text);
275 
276 static const struct snd_kcontrol_new wm8983_snd_controls[] = {
277 	SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL,
278 		   0, 1, 0),
279 
280 	SOC_ENUM("ALC Capture Function", alc_sel),
281 	SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1,
282 		       3, 7, 0, alc_max_tlv),
283 	SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1,
284 		       0, 7, 0, alc_min_tlv),
285 	SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2,
286 		       0, 15, 0, alc_tar_tlv),
287 	SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0),
288 	SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0),
289 	SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0),
290 	SOC_ENUM("ALC Mode", alc_mode),
291 	SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE,
292 		   3, 1, 0),
293 	SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE,
294 		   0, 7, 1),
295 
296 	SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL,
297 			 WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
298 	SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL,
299 		     WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
300 	SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL,
301 			 WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
302 
303 	SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
304 			 WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL,
305 			 8, 1, 0, pga_boost_tlv),
306 
307 	SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0),
308 	SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0),
309 
310 	SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL,
311 			 WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
312 
313 	SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0),
314 	SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0),
315 	SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0),
316 	SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2,
317 		       4, 7, 1, lim_thresh_tlv),
318 	SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2,
319 		       0, 12, 0, lim_boost_tlv),
320 	SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0),
321 	SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0),
322 	SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0),
323 
324 	SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL,
325 			 WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
326 	SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
327 		     WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
328 	SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
329 		     WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
330 
331 	SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL,
332 			 WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
333 	SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
334 		     WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
335 	SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
336 		     WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
337 
338 	SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
339 		   6, 1, 1),
340 
341 	SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
342 		   6, 1, 1),
343 
344 	SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0),
345 	SOC_ENUM("High Pass Filter Mode", filter_mode),
346 	SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0),
347 
348 	SOC_DOUBLE_R_TLV("Aux Bypass Volume",
349 			 WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0,
350 			 aux_tlv),
351 
352 	SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
353 			 WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0,
354 			 bypass_tlv),
355 
356 	SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
357 	SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
358 	SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
359 	SOC_ENUM("EQ2 Bandwith", eq2_bw),
360 	SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
361 	SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
362 	SOC_ENUM("EQ3 Bandwith", eq3_bw),
363 	SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
364 	SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
365 	SOC_ENUM("EQ4 Bandwith", eq4_bw),
366 	SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
367 	SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
368 	SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
369 	SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
370 
371 	SOC_ENUM("3D Depth", depth_3d),
372 
373 	SOC_ENUM("Speaker Mode", speaker_mode)
374 };
375 
376 static const struct snd_kcontrol_new left_out_mixer[] = {
377 	SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0),
378 	SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0),
379 	SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0),
380 };
381 
382 static const struct snd_kcontrol_new right_out_mixer[] = {
383 	SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0),
384 	SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0),
385 	SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0),
386 };
387 
388 static const struct snd_kcontrol_new left_input_mixer[] = {
389 	SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
390 	SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0),
391 	SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0),
392 };
393 
394 static const struct snd_kcontrol_new right_input_mixer[] = {
395 	SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
396 	SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0),
397 	SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0),
398 };
399 
400 static const struct snd_kcontrol_new left_boost_mixer[] = {
401 	SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
402 			    4, 7, 0, boost_tlv),
403 	SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL,
404 			    0, 7, 0, boost_tlv)
405 };
406 
407 static const struct snd_kcontrol_new out3_mixer[] = {
408 	SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
409 			1, 1, 0),
410 	SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
411 			0, 1, 0),
412 };
413 
414 static const struct snd_kcontrol_new out4_mixer[] = {
415 	SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
416 			4, 1, 0),
417 	SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
418 			1, 1, 0),
419 	SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
420 			3, 1, 0),
421 	SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
422 			0, 1, 0),
423 };
424 
425 static const struct snd_kcontrol_new right_boost_mixer[] = {
426 	SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
427 			    4, 7, 0, boost_tlv),
428 	SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
429 			    0, 7, 0, boost_tlv)
430 };
431 
432 static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = {
433 	SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3,
434 			 0, 0),
435 	SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3,
436 			 1, 0),
437 	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2,
438 			 0, 0),
439 	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2,
440 			 1, 0),
441 
442 	SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3,
443 			   2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
444 	SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3,
445 			   3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
446 
447 	SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2,
448 			   2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
449 	SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2,
450 			   3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
451 
452 	SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2,
453 			   4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
454 	SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2,
455 			   5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
456 
457 	SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1,
458 			   6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)),
459 
460 	SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1,
461 			   7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)),
462 
463 	SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL,
464 			 6, 1, NULL, 0),
465 	SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL,
466 			 6, 1, NULL, 0),
467 
468 	SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2,
469 			 7, 0, NULL, 0),
470 	SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2,
471 			 8, 0, NULL, 0),
472 
473 	SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3,
474 			 5, 0, NULL, 0),
475 	SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3,
476 			 6, 0, NULL, 0),
477 
478 	SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3,
479 			 7, 0, NULL, 0),
480 
481 	SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3,
482 			 8, 0, NULL, 0),
483 
484 	SND_SOC_DAPM_MICBIAS("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0),
485 
486 	SND_SOC_DAPM_INPUT("LIN"),
487 	SND_SOC_DAPM_INPUT("LIP"),
488 	SND_SOC_DAPM_INPUT("RIN"),
489 	SND_SOC_DAPM_INPUT("RIP"),
490 	SND_SOC_DAPM_INPUT("AUXL"),
491 	SND_SOC_DAPM_INPUT("AUXR"),
492 	SND_SOC_DAPM_INPUT("L2"),
493 	SND_SOC_DAPM_INPUT("R2"),
494 	SND_SOC_DAPM_OUTPUT("HPL"),
495 	SND_SOC_DAPM_OUTPUT("HPR"),
496 	SND_SOC_DAPM_OUTPUT("SPKL"),
497 	SND_SOC_DAPM_OUTPUT("SPKR"),
498 	SND_SOC_DAPM_OUTPUT("OUT3"),
499 	SND_SOC_DAPM_OUTPUT("OUT4")
500 };
501 
502 static const struct snd_soc_dapm_route wm8983_audio_map[] = {
503 	{ "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" },
504 	{ "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" },
505 
506 	{ "OUT3 Out", NULL, "OUT3 Mixer" },
507 	{ "OUT3", NULL, "OUT3 Out" },
508 
509 	{ "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" },
510 	{ "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" },
511 	{ "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" },
512 	{ "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" },
513 
514 	{ "OUT4 Out", NULL, "OUT4 Mixer" },
515 	{ "OUT4", NULL, "OUT4 Out" },
516 
517 	{ "Right Output Mixer", "PCM Switch", "Right DAC" },
518 	{ "Right Output Mixer", "Aux Switch", "AUXR" },
519 	{ "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
520 
521 	{ "Left Output Mixer", "PCM Switch", "Left DAC" },
522 	{ "Left Output Mixer", "Aux Switch", "AUXL" },
523 	{ "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
524 
525 	{ "Right Headphone Out", NULL, "Right Output Mixer" },
526 	{ "HPR", NULL, "Right Headphone Out" },
527 
528 	{ "Left Headphone Out", NULL, "Left Output Mixer" },
529 	{ "HPL", NULL, "Left Headphone Out" },
530 
531 	{ "Right Speaker Out", NULL, "Right Output Mixer" },
532 	{ "SPKR", NULL, "Right Speaker Out" },
533 
534 	{ "Left Speaker Out", NULL, "Left Output Mixer" },
535 	{ "SPKL", NULL, "Left Speaker Out" },
536 
537 	{ "Right ADC", NULL, "Right Boost Mixer" },
538 
539 	{ "Right Boost Mixer", "AUXR Volume", "AUXR" },
540 	{ "Right Boost Mixer", NULL, "Right Capture PGA" },
541 	{ "Right Boost Mixer", "R2 Volume", "R2" },
542 
543 	{ "Left ADC", NULL, "Left Boost Mixer" },
544 
545 	{ "Left Boost Mixer", "AUXL Volume", "AUXL" },
546 	{ "Left Boost Mixer", NULL, "Left Capture PGA" },
547 	{ "Left Boost Mixer", "L2 Volume", "L2" },
548 
549 	{ "Right Capture PGA", NULL, "Right Input Mixer" },
550 	{ "Left Capture PGA", NULL, "Left Input Mixer" },
551 
552 	{ "Right Input Mixer", "R2 Switch", "R2" },
553 	{ "Right Input Mixer", "MicN Switch", "RIN" },
554 	{ "Right Input Mixer", "MicP Switch", "RIP" },
555 
556 	{ "Left Input Mixer", "L2 Switch", "L2" },
557 	{ "Left Input Mixer", "MicN Switch", "LIN" },
558 	{ "Left Input Mixer", "MicP Switch", "LIP" },
559 };
560 
561 static int eqmode_get(struct snd_kcontrol *kcontrol,
562 		      struct snd_ctl_elem_value *ucontrol)
563 {
564 	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
565 	unsigned int reg;
566 
567 	reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
568 	if (reg & WM8983_EQ3DMODE)
569 		ucontrol->value.integer.value[0] = 1;
570 	else
571 		ucontrol->value.integer.value[0] = 0;
572 
573 	return 0;
574 }
575 
576 static int eqmode_put(struct snd_kcontrol *kcontrol,
577 		      struct snd_ctl_elem_value *ucontrol)
578 {
579 	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
580 	unsigned int regpwr2, regpwr3;
581 	unsigned int reg_eq;
582 
583 	if (ucontrol->value.integer.value[0] != 0
584 	    && ucontrol->value.integer.value[0] != 1)
585 		return -EINVAL;
586 
587 	reg_eq = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
588 	switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) {
589 	case 0:
590 		if (!ucontrol->value.integer.value[0])
591 			return 0;
592 		break;
593 	case 1:
594 		if (ucontrol->value.integer.value[0])
595 			return 0;
596 		break;
597 	}
598 
599 	regpwr2 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_2);
600 	regpwr3 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_3);
601 	/* disable the DACs and ADCs */
602 	snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_2,
603 			    WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0);
604 	snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_3,
605 			    WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0);
606 	/* set the desired eqmode */
607 	snd_soc_update_bits(codec, WM8983_EQ1_LOW_SHELF,
608 			    WM8983_EQ3DMODE_MASK,
609 			    ucontrol->value.integer.value[0]
610 			    << WM8983_EQ3DMODE_SHIFT);
611 	/* restore DAC/ADC configuration */
612 	snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, regpwr2);
613 	snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, regpwr3);
614 	return 0;
615 }
616 
617 static int wm8983_readable(struct snd_soc_codec *codec, unsigned int reg)
618 {
619 	if (reg > WM8983_MAX_REGISTER)
620 		return 0;
621 
622 	return wm8983_access_masks[reg].read != 0;
623 }
624 
625 static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute)
626 {
627 	struct snd_soc_codec *codec = dai->codec;
628 
629 	return snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
630 				   WM8983_SOFTMUTE_MASK,
631 				   !!mute << WM8983_SOFTMUTE_SHIFT);
632 }
633 
634 static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
635 {
636 	struct snd_soc_codec *codec = dai->codec;
637 	u16 format, master, bcp, lrp;
638 
639 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
640 	case SND_SOC_DAIFMT_I2S:
641 		format = 0x2;
642 		break;
643 	case SND_SOC_DAIFMT_RIGHT_J:
644 		format = 0x0;
645 		break;
646 	case SND_SOC_DAIFMT_LEFT_J:
647 		format = 0x1;
648 		break;
649 	case SND_SOC_DAIFMT_DSP_A:
650 	case SND_SOC_DAIFMT_DSP_B:
651 		format = 0x3;
652 		break;
653 	default:
654 		dev_err(dai->dev, "Unknown dai format\n");
655 		return -EINVAL;
656 	}
657 
658 	snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
659 			    WM8983_FMT_MASK, format << WM8983_FMT_SHIFT);
660 
661 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
662 	case SND_SOC_DAIFMT_CBM_CFM:
663 		master = 1;
664 		break;
665 	case SND_SOC_DAIFMT_CBS_CFS:
666 		master = 0;
667 		break;
668 	default:
669 		dev_err(dai->dev, "Unknown master/slave configuration\n");
670 		return -EINVAL;
671 	}
672 
673 	snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
674 			    WM8983_MS_MASK, master << WM8983_MS_SHIFT);
675 
676 	/* FIXME: We don't currently support DSP A/B modes */
677 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
678 	case SND_SOC_DAIFMT_DSP_A:
679 	case SND_SOC_DAIFMT_DSP_B:
680 		dev_err(dai->dev, "DSP A/B modes are not supported\n");
681 		return -EINVAL;
682 	default:
683 		break;
684 	}
685 
686 	bcp = lrp = 0;
687 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
688 	case SND_SOC_DAIFMT_NB_NF:
689 		break;
690 	case SND_SOC_DAIFMT_IB_IF:
691 		bcp = lrp = 1;
692 		break;
693 	case SND_SOC_DAIFMT_IB_NF:
694 		bcp = 1;
695 		break;
696 	case SND_SOC_DAIFMT_NB_IF:
697 		lrp = 1;
698 		break;
699 	default:
700 		dev_err(dai->dev, "Unknown polarity configuration\n");
701 		return -EINVAL;
702 	}
703 
704 	snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
705 			    WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT);
706 	snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
707 			    WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT);
708 	return 0;
709 }
710 
711 static int wm8983_hw_params(struct snd_pcm_substream *substream,
712 			    struct snd_pcm_hw_params *params,
713 			    struct snd_soc_dai *dai)
714 {
715 	int i;
716 	struct snd_soc_codec *codec = dai->codec;
717 	struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
718 	u16 blen, srate_idx;
719 	u32 tmp;
720 	int srate_best;
721 	int ret;
722 
723 	ret = snd_soc_params_to_bclk(params);
724 	if (ret < 0) {
725 		dev_err(codec->dev, "Failed to convert params to bclk: %d\n", ret);
726 		return ret;
727 	}
728 
729 	wm8983->bclk = ret;
730 
731 	switch (params_format(params)) {
732 	case SNDRV_PCM_FORMAT_S16_LE:
733 		blen = 0x0;
734 		break;
735 	case SNDRV_PCM_FORMAT_S20_3LE:
736 		blen = 0x1;
737 		break;
738 	case SNDRV_PCM_FORMAT_S24_LE:
739 		blen = 0x2;
740 		break;
741 	case SNDRV_PCM_FORMAT_S32_LE:
742 		blen = 0x3;
743 		break;
744 	default:
745 		dev_err(dai->dev, "Unsupported word length %u\n",
746 			params_format(params));
747 		return -EINVAL;
748 	}
749 
750 	snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
751 			    WM8983_WL_MASK, blen << WM8983_WL_SHIFT);
752 
753 	/*
754 	 * match to the nearest possible sample rate and rely
755 	 * on the array index to configure the SR register
756 	 */
757 	srate_idx = 0;
758 	srate_best = abs(srates[0] - params_rate(params));
759 	for (i = 1; i < ARRAY_SIZE(srates); ++i) {
760 		if (abs(srates[i] - params_rate(params)) >= srate_best)
761 			continue;
762 		srate_idx = i;
763 		srate_best = abs(srates[i] - params_rate(params));
764 	}
765 
766 	dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
767 	snd_soc_update_bits(codec, WM8983_ADDITIONAL_CONTROL,
768 			    WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT);
769 
770 	dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk);
771 	dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk);
772 
773 	for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
774 		if (wm8983->sysclk / params_rate(params)
775 		    == fs_ratios[i].ratio)
776 			break;
777 	}
778 
779 	if (i == ARRAY_SIZE(fs_ratios)) {
780 		dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
781 			wm8983->sysclk, params_rate(params));
782 		return -EINVAL;
783 	}
784 
785 	dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
786 	snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
787 			    WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT);
788 
789 	/* select the appropriate bclk divider */
790 	tmp = (wm8983->sysclk / fs_ratios[i].div) * 10;
791 	for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
792 		if (wm8983->bclk == tmp / bclk_divs[i])
793 			break;
794 	}
795 
796 	if (i == ARRAY_SIZE(bclk_divs)) {
797 		dev_err(dai->dev, "No matching BCLK divider found\n");
798 		return -EINVAL;
799 	}
800 
801 	dev_dbg(dai->dev, "BCLK div = %d\n", i);
802 	snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
803 			    WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT);
804 
805 	return 0;
806 }
807 
808 struct pll_div {
809 	u32 div2:1;
810 	u32 n:4;
811 	u32 k:24;
812 };
813 
814 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
815 static int pll_factors(struct pll_div *pll_div, unsigned int target,
816 		       unsigned int source)
817 {
818 	u64 Kpart;
819 	unsigned long int K, Ndiv, Nmod;
820 
821 	pll_div->div2 = 0;
822 	Ndiv = target / source;
823 	if (Ndiv < 6) {
824 		source >>= 1;
825 		pll_div->div2 = 1;
826 		Ndiv = target / source;
827 	}
828 
829 	if (Ndiv < 6 || Ndiv > 12) {
830 		printk(KERN_ERR "%s: WM8983 N value is not within"
831 		       " the recommended range: %lu\n", __func__, Ndiv);
832 		return -EINVAL;
833 	}
834 	pll_div->n = Ndiv;
835 
836 	Nmod = target % source;
837 	Kpart = FIXED_PLL_SIZE * (u64)Nmod;
838 
839 	do_div(Kpart, source);
840 
841 	K = Kpart & 0xffffffff;
842 	if ((K % 10) >= 5)
843 		K += 5;
844 	K /= 10;
845 	pll_div->k = K;
846 	return 0;
847 }
848 
849 static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
850 			  int source, unsigned int freq_in,
851 			  unsigned int freq_out)
852 {
853 	int ret;
854 	struct snd_soc_codec *codec;
855 	struct pll_div pll_div;
856 
857 	codec = dai->codec;
858 	if (freq_in && freq_out) {
859 		ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
860 		if (ret)
861 			return ret;
862 	}
863 
864 	/* disable the PLL before re-programming it */
865 	snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
866 			    WM8983_PLLEN_MASK, 0);
867 
868 	if (!freq_in || !freq_out)
869 		return 0;
870 
871 	/* set PLLN and PRESCALE */
872 	snd_soc_write(codec, WM8983_PLL_N,
873 		      (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
874 		      | pll_div.n);
875 	/* set PLLK */
876 	snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff);
877 	snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
878 	snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18));
879 	/* enable the PLL */
880 	snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
881 			    WM8983_PLLEN_MASK, WM8983_PLLEN);
882 	return 0;
883 }
884 
885 static int wm8983_set_sysclk(struct snd_soc_dai *dai,
886 			     int clk_id, unsigned int freq, int dir)
887 {
888 	struct snd_soc_codec *codec = dai->codec;
889 	struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
890 
891 	switch (clk_id) {
892 	case WM8983_CLKSRC_MCLK:
893 		snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
894 				    WM8983_CLKSEL_MASK, 0);
895 		break;
896 	case WM8983_CLKSRC_PLL:
897 		snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
898 				    WM8983_CLKSEL_MASK, WM8983_CLKSEL);
899 		break;
900 	default:
901 		dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
902 		return -EINVAL;
903 	}
904 
905 	wm8983->sysclk = freq;
906 	return 0;
907 }
908 
909 static int wm8983_set_bias_level(struct snd_soc_codec *codec,
910 				 enum snd_soc_bias_level level)
911 {
912 	int ret;
913 
914 	switch (level) {
915 	case SND_SOC_BIAS_ON:
916 	case SND_SOC_BIAS_PREPARE:
917 		/* VMID at 100k */
918 		snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
919 				    WM8983_VMIDSEL_MASK,
920 				    1 << WM8983_VMIDSEL_SHIFT);
921 		break;
922 	case SND_SOC_BIAS_STANDBY:
923 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
924 			ret = snd_soc_cache_sync(codec);
925 			if (ret < 0) {
926 				dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
927 				return ret;
928 			}
929 			/* enable anti-pop features */
930 			snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
931 					    WM8983_POBCTRL_MASK | WM8983_DELEN_MASK,
932 					    WM8983_POBCTRL | WM8983_DELEN);
933 			/* enable thermal shutdown */
934 			snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
935 					    WM8983_TSDEN_MASK, WM8983_TSDEN);
936 			/* enable BIASEN */
937 			snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
938 					    WM8983_BIASEN_MASK, WM8983_BIASEN);
939 			/* VMID at 100k */
940 			snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
941 					    WM8983_VMIDSEL_MASK,
942 					    1 << WM8983_VMIDSEL_SHIFT);
943 			msleep(250);
944 			/* disable anti-pop features */
945 			snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
946 					    WM8983_POBCTRL_MASK |
947 					    WM8983_DELEN_MASK, 0);
948 		}
949 
950 		/* VMID at 500k */
951 		snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
952 				    WM8983_VMIDSEL_MASK,
953 				    2 << WM8983_VMIDSEL_SHIFT);
954 		break;
955 	case SND_SOC_BIAS_OFF:
956 		/* disable thermal shutdown */
957 		snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
958 				    WM8983_TSDEN_MASK, 0);
959 		/* disable VMIDSEL and BIASEN */
960 		snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
961 				    WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK,
962 				    0);
963 		/* wait for VMID to discharge */
964 		msleep(100);
965 		snd_soc_write(codec, WM8983_POWER_MANAGEMENT_1, 0);
966 		snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, 0);
967 		snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, 0);
968 		break;
969 	}
970 
971 	codec->dapm.bias_level = level;
972 	return 0;
973 }
974 
975 #ifdef CONFIG_PM
976 static int wm8983_suspend(struct snd_soc_codec *codec, pm_message_t state)
977 {
978 	wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF);
979 	return 0;
980 }
981 
982 static int wm8983_resume(struct snd_soc_codec *codec)
983 {
984 	wm8983_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
985 	return 0;
986 }
987 #else
988 #define wm8983_suspend NULL
989 #define wm8983_resume NULL
990 #endif
991 
992 static int wm8983_remove(struct snd_soc_codec *codec)
993 {
994 	wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF);
995 	return 0;
996 }
997 
998 static int wm8983_probe(struct snd_soc_codec *codec)
999 {
1000 	int ret;
1001 	struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
1002 	int i;
1003 
1004 	ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8983->control_type);
1005 	if (ret < 0) {
1006 		dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
1007 		return ret;
1008 	}
1009 
1010 	ret = snd_soc_write(codec, WM8983_SOFTWARE_RESET, 0x8983);
1011 	if (ret < 0) {
1012 		dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1013 		return ret;
1014 	}
1015 
1016 	/* set the vol/gain update bits */
1017 	for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i)
1018 		snd_soc_update_bits(codec, vol_update_regs[i],
1019 				    0x100, 0x100);
1020 
1021 	/* mute all outputs and set PGAs to minimum gain */
1022 	for (i = WM8983_LOUT1_HP_VOLUME_CTRL;
1023 	     i <= WM8983_OUT4_MONO_MIX_CTRL; ++i)
1024 		snd_soc_update_bits(codec, i, 0x40, 0x40);
1025 
1026 	/* enable soft mute */
1027 	snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
1028 			    WM8983_SOFTMUTE_MASK,
1029 			    WM8983_SOFTMUTE);
1030 
1031 	/* enable BIASCUT */
1032 	snd_soc_update_bits(codec, WM8983_BIAS_CTRL,
1033 			    WM8983_BIASCUT, WM8983_BIASCUT);
1034 	return 0;
1035 }
1036 
1037 static struct snd_soc_dai_ops wm8983_dai_ops = {
1038 	.digital_mute = wm8983_dac_mute,
1039 	.hw_params = wm8983_hw_params,
1040 	.set_fmt = wm8983_set_fmt,
1041 	.set_sysclk = wm8983_set_sysclk,
1042 	.set_pll = wm8983_set_pll
1043 };
1044 
1045 #define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1046 			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1047 
1048 static struct snd_soc_dai_driver wm8983_dai = {
1049 	.name = "wm8983-hifi",
1050 	.playback = {
1051 		.stream_name = "Playback",
1052 		.channels_min = 2,
1053 		.channels_max = 2,
1054 		.rates = SNDRV_PCM_RATE_8000_48000,
1055 		.formats = WM8983_FORMATS,
1056 	},
1057 	.capture = {
1058 		.stream_name = "Capture",
1059 		.channels_min = 2,
1060 		.channels_max = 2,
1061 		.rates = SNDRV_PCM_RATE_8000_48000,
1062 		.formats = WM8983_FORMATS,
1063 	},
1064 	.ops = &wm8983_dai_ops,
1065 	.symmetric_rates = 1
1066 };
1067 
1068 static struct snd_soc_codec_driver soc_codec_dev_wm8983 = {
1069 	.probe = wm8983_probe,
1070 	.remove = wm8983_remove,
1071 	.suspend = wm8983_suspend,
1072 	.resume = wm8983_resume,
1073 	.set_bias_level = wm8983_set_bias_level,
1074 	.reg_cache_size = ARRAY_SIZE(wm8983_reg_defs),
1075 	.reg_word_size = sizeof(u16),
1076 	.reg_cache_default = wm8983_reg_defs,
1077 	.controls = wm8983_snd_controls,
1078 	.num_controls = ARRAY_SIZE(wm8983_snd_controls),
1079 	.dapm_widgets = wm8983_dapm_widgets,
1080 	.num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets),
1081 	.dapm_routes = wm8983_audio_map,
1082 	.num_dapm_routes = ARRAY_SIZE(wm8983_audio_map),
1083 	.readable_register = wm8983_readable
1084 };
1085 
1086 #if defined(CONFIG_SPI_MASTER)
1087 static int __devinit wm8983_spi_probe(struct spi_device *spi)
1088 {
1089 	struct wm8983_priv *wm8983;
1090 	int ret;
1091 
1092 	wm8983 = kzalloc(sizeof *wm8983, GFP_KERNEL);
1093 	if (!wm8983)
1094 		return -ENOMEM;
1095 
1096 	wm8983->control_type = SND_SOC_SPI;
1097 	spi_set_drvdata(spi, wm8983);
1098 
1099 	ret = snd_soc_register_codec(&spi->dev,
1100 				     &soc_codec_dev_wm8983, &wm8983_dai, 1);
1101 	if (ret < 0)
1102 		kfree(wm8983);
1103 	return ret;
1104 }
1105 
1106 static int __devexit wm8983_spi_remove(struct spi_device *spi)
1107 {
1108 	snd_soc_unregister_codec(&spi->dev);
1109 	kfree(spi_get_drvdata(spi));
1110 	return 0;
1111 }
1112 
1113 static struct spi_driver wm8983_spi_driver = {
1114 	.driver = {
1115 		.name = "wm8983",
1116 		.owner = THIS_MODULE,
1117 	},
1118 	.probe = wm8983_spi_probe,
1119 	.remove = __devexit_p(wm8983_spi_remove)
1120 };
1121 #endif
1122 
1123 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1124 static __devinit int wm8983_i2c_probe(struct i2c_client *i2c,
1125 				      const struct i2c_device_id *id)
1126 {
1127 	struct wm8983_priv *wm8983;
1128 	int ret;
1129 
1130 	wm8983 = kzalloc(sizeof *wm8983, GFP_KERNEL);
1131 	if (!wm8983)
1132 		return -ENOMEM;
1133 
1134 	wm8983->control_type = SND_SOC_I2C;
1135 	i2c_set_clientdata(i2c, wm8983);
1136 
1137 	ret = snd_soc_register_codec(&i2c->dev,
1138 				     &soc_codec_dev_wm8983, &wm8983_dai, 1);
1139 	if (ret < 0)
1140 		kfree(wm8983);
1141 	return ret;
1142 }
1143 
1144 static __devexit int wm8983_i2c_remove(struct i2c_client *client)
1145 {
1146 	snd_soc_unregister_codec(&client->dev);
1147 	kfree(i2c_get_clientdata(client));
1148 	return 0;
1149 }
1150 
1151 static const struct i2c_device_id wm8983_i2c_id[] = {
1152 	{ "wm8983", 0 },
1153 	{ }
1154 };
1155 MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id);
1156 
1157 static struct i2c_driver wm8983_i2c_driver = {
1158 	.driver = {
1159 		.name = "wm8983",
1160 		.owner = THIS_MODULE,
1161 	},
1162 	.probe = wm8983_i2c_probe,
1163 	.remove = __devexit_p(wm8983_i2c_remove),
1164 	.id_table = wm8983_i2c_id
1165 };
1166 #endif
1167 
1168 static int __init wm8983_modinit(void)
1169 {
1170 	int ret = 0;
1171 
1172 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1173 	ret = i2c_add_driver(&wm8983_i2c_driver);
1174 	if (ret) {
1175 		printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n",
1176 		       ret);
1177 	}
1178 #endif
1179 #if defined(CONFIG_SPI_MASTER)
1180 	ret = spi_register_driver(&wm8983_spi_driver);
1181 	if (ret != 0) {
1182 		printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n",
1183 		       ret);
1184 	}
1185 #endif
1186 	return ret;
1187 }
1188 module_init(wm8983_modinit);
1189 
1190 static void __exit wm8983_exit(void)
1191 {
1192 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1193 	i2c_del_driver(&wm8983_i2c_driver);
1194 #endif
1195 #if defined(CONFIG_SPI_MASTER)
1196 	spi_unregister_driver(&wm8983_spi_driver);
1197 #endif
1198 }
1199 module_exit(wm8983_exit);
1200 
1201 MODULE_DESCRIPTION("ASoC WM8983 driver");
1202 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1203 MODULE_LICENSE("GPL");
1204