1 /* 2 * wm8904.c -- WM8904 ALSA SoC Audio driver 3 * 4 * Copyright 2009 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/i2c.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <sound/core.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <sound/wm8904.h> 29 30 #include "wm8904.h" 31 32 enum wm8904_type { 33 WM8904, 34 WM8912, 35 }; 36 37 #define WM8904_NUM_DCS_CHANNELS 4 38 39 #define WM8904_NUM_SUPPLIES 5 40 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { 41 "DCVDD", 42 "DBVDD", 43 "AVDD", 44 "CPVDD", 45 "MICVDD", 46 }; 47 48 /* codec private data */ 49 struct wm8904_priv { 50 51 enum wm8904_type devtype; 52 53 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; 54 55 struct wm8904_pdata *pdata; 56 57 int deemph; 58 59 /* Platform provided DRC configuration */ 60 const char **drc_texts; 61 int drc_cfg; 62 struct soc_enum drc_enum; 63 64 /* Platform provided ReTune mobile configuration */ 65 int num_retune_mobile_texts; 66 const char **retune_mobile_texts; 67 int retune_mobile_cfg; 68 struct soc_enum retune_mobile_enum; 69 70 /* FLL setup */ 71 int fll_src; 72 int fll_fref; 73 int fll_fout; 74 75 /* Clocking configuration */ 76 unsigned int mclk_rate; 77 int sysclk_src; 78 unsigned int sysclk_rate; 79 80 int tdm_width; 81 int tdm_slots; 82 int bclk; 83 int fs; 84 85 /* DC servo configuration - cached offset values */ 86 int dcs_state[WM8904_NUM_DCS_CHANNELS]; 87 }; 88 89 static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = { 90 0x8904, /* R0 - SW Reset and ID */ 91 0x0000, /* R1 - Revision */ 92 0x0000, /* R2 */ 93 0x0000, /* R3 */ 94 0x0018, /* R4 - Bias Control 0 */ 95 0x0000, /* R5 - VMID Control 0 */ 96 0x0000, /* R6 - Mic Bias Control 0 */ 97 0x0000, /* R7 - Mic Bias Control 1 */ 98 0x0001, /* R8 - Analogue DAC 0 */ 99 0x9696, /* R9 - mic Filter Control */ 100 0x0001, /* R10 - Analogue ADC 0 */ 101 0x0000, /* R11 */ 102 0x0000, /* R12 - Power Management 0 */ 103 0x0000, /* R13 */ 104 0x0000, /* R14 - Power Management 2 */ 105 0x0000, /* R15 - Power Management 3 */ 106 0x0000, /* R16 */ 107 0x0000, /* R17 */ 108 0x0000, /* R18 - Power Management 6 */ 109 0x0000, /* R19 */ 110 0x945E, /* R20 - Clock Rates 0 */ 111 0x0C05, /* R21 - Clock Rates 1 */ 112 0x0006, /* R22 - Clock Rates 2 */ 113 0x0000, /* R23 */ 114 0x0050, /* R24 - Audio Interface 0 */ 115 0x000A, /* R25 - Audio Interface 1 */ 116 0x00E4, /* R26 - Audio Interface 2 */ 117 0x0040, /* R27 - Audio Interface 3 */ 118 0x0000, /* R28 */ 119 0x0000, /* R29 */ 120 0x00C0, /* R30 - DAC Digital Volume Left */ 121 0x00C0, /* R31 - DAC Digital Volume Right */ 122 0x0000, /* R32 - DAC Digital 0 */ 123 0x0008, /* R33 - DAC Digital 1 */ 124 0x0000, /* R34 */ 125 0x0000, /* R35 */ 126 0x00C0, /* R36 - ADC Digital Volume Left */ 127 0x00C0, /* R37 - ADC Digital Volume Right */ 128 0x0010, /* R38 - ADC Digital 0 */ 129 0x0000, /* R39 - Digital Microphone 0 */ 130 0x01AF, /* R40 - DRC 0 */ 131 0x3248, /* R41 - DRC 1 */ 132 0x0000, /* R42 - DRC 2 */ 133 0x0000, /* R43 - DRC 3 */ 134 0x0085, /* R44 - Analogue Left Input 0 */ 135 0x0085, /* R45 - Analogue Right Input 0 */ 136 0x0044, /* R46 - Analogue Left Input 1 */ 137 0x0044, /* R47 - Analogue Right Input 1 */ 138 0x0000, /* R48 */ 139 0x0000, /* R49 */ 140 0x0000, /* R50 */ 141 0x0000, /* R51 */ 142 0x0000, /* R52 */ 143 0x0000, /* R53 */ 144 0x0000, /* R54 */ 145 0x0000, /* R55 */ 146 0x0000, /* R56 */ 147 0x002D, /* R57 - Analogue OUT1 Left */ 148 0x002D, /* R58 - Analogue OUT1 Right */ 149 0x0039, /* R59 - Analogue OUT2 Left */ 150 0x0039, /* R60 - Analogue OUT2 Right */ 151 0x0000, /* R61 - Analogue OUT12 ZC */ 152 0x0000, /* R62 */ 153 0x0000, /* R63 */ 154 0x0000, /* R64 */ 155 0x0000, /* R65 */ 156 0x0000, /* R66 */ 157 0x0000, /* R67 - DC Servo 0 */ 158 0x0000, /* R68 - DC Servo 1 */ 159 0xAAAA, /* R69 - DC Servo 2 */ 160 0x0000, /* R70 */ 161 0xAAAA, /* R71 - DC Servo 4 */ 162 0xAAAA, /* R72 - DC Servo 5 */ 163 0x0000, /* R73 - DC Servo 6 */ 164 0x0000, /* R74 - DC Servo 7 */ 165 0x0000, /* R75 - DC Servo 8 */ 166 0x0000, /* R76 - DC Servo 9 */ 167 0x0000, /* R77 - DC Servo Readback 0 */ 168 0x0000, /* R78 */ 169 0x0000, /* R79 */ 170 0x0000, /* R80 */ 171 0x0000, /* R81 */ 172 0x0000, /* R82 */ 173 0x0000, /* R83 */ 174 0x0000, /* R84 */ 175 0x0000, /* R85 */ 176 0x0000, /* R86 */ 177 0x0000, /* R87 */ 178 0x0000, /* R88 */ 179 0x0000, /* R89 */ 180 0x0000, /* R90 - Analogue HP 0 */ 181 0x0000, /* R91 */ 182 0x0000, /* R92 */ 183 0x0000, /* R93 */ 184 0x0000, /* R94 - Analogue Lineout 0 */ 185 0x0000, /* R95 */ 186 0x0000, /* R96 */ 187 0x0000, /* R97 */ 188 0x0000, /* R98 - Charge Pump 0 */ 189 0x0000, /* R99 */ 190 0x0000, /* R100 */ 191 0x0000, /* R101 */ 192 0x0000, /* R102 */ 193 0x0000, /* R103 */ 194 0x0004, /* R104 - Class W 0 */ 195 0x0000, /* R105 */ 196 0x0000, /* R106 */ 197 0x0000, /* R107 */ 198 0x0000, /* R108 - Write Sequencer 0 */ 199 0x0000, /* R109 - Write Sequencer 1 */ 200 0x0000, /* R110 - Write Sequencer 2 */ 201 0x0000, /* R111 - Write Sequencer 3 */ 202 0x0000, /* R112 - Write Sequencer 4 */ 203 0x0000, /* R113 */ 204 0x0000, /* R114 */ 205 0x0000, /* R115 */ 206 0x0000, /* R116 - FLL Control 1 */ 207 0x0007, /* R117 - FLL Control 2 */ 208 0x0000, /* R118 - FLL Control 3 */ 209 0x2EE0, /* R119 - FLL Control 4 */ 210 0x0004, /* R120 - FLL Control 5 */ 211 0x0014, /* R121 - GPIO Control 1 */ 212 0x0010, /* R122 - GPIO Control 2 */ 213 0x0010, /* R123 - GPIO Control 3 */ 214 0x0000, /* R124 - GPIO Control 4 */ 215 0x0000, /* R125 */ 216 0x0000, /* R126 - Digital Pulls */ 217 0x0000, /* R127 - Interrupt Status */ 218 0xFFFF, /* R128 - Interrupt Status Mask */ 219 0x0000, /* R129 - Interrupt Polarity */ 220 0x0000, /* R130 - Interrupt Debounce */ 221 0x0000, /* R131 */ 222 0x0000, /* R132 */ 223 0x0000, /* R133 */ 224 0x0000, /* R134 - EQ1 */ 225 0x000C, /* R135 - EQ2 */ 226 0x000C, /* R136 - EQ3 */ 227 0x000C, /* R137 - EQ4 */ 228 0x000C, /* R138 - EQ5 */ 229 0x000C, /* R139 - EQ6 */ 230 0x0FCA, /* R140 - EQ7 */ 231 0x0400, /* R141 - EQ8 */ 232 0x00D8, /* R142 - EQ9 */ 233 0x1EB5, /* R143 - EQ10 */ 234 0xF145, /* R144 - EQ11 */ 235 0x0B75, /* R145 - EQ12 */ 236 0x01C5, /* R146 - EQ13 */ 237 0x1C58, /* R147 - EQ14 */ 238 0xF373, /* R148 - EQ15 */ 239 0x0A54, /* R149 - EQ16 */ 240 0x0558, /* R150 - EQ17 */ 241 0x168E, /* R151 - EQ18 */ 242 0xF829, /* R152 - EQ19 */ 243 0x07AD, /* R153 - EQ20 */ 244 0x1103, /* R154 - EQ21 */ 245 0x0564, /* R155 - EQ22 */ 246 0x0559, /* R156 - EQ23 */ 247 0x4000, /* R157 - EQ24 */ 248 0x0000, /* R158 */ 249 0x0000, /* R159 */ 250 0x0000, /* R160 */ 251 0x0000, /* R161 - Control Interface Test 1 */ 252 0x0000, /* R162 */ 253 0x0000, /* R163 */ 254 0x0000, /* R164 */ 255 0x0000, /* R165 */ 256 0x0000, /* R166 */ 257 0x0000, /* R167 */ 258 0x0000, /* R168 */ 259 0x0000, /* R169 */ 260 0x0000, /* R170 */ 261 0x0000, /* R171 */ 262 0x0000, /* R172 */ 263 0x0000, /* R173 */ 264 0x0000, /* R174 */ 265 0x0000, /* R175 */ 266 0x0000, /* R176 */ 267 0x0000, /* R177 */ 268 0x0000, /* R178 */ 269 0x0000, /* R179 */ 270 0x0000, /* R180 */ 271 0x0000, /* R181 */ 272 0x0000, /* R182 */ 273 0x0000, /* R183 */ 274 0x0000, /* R184 */ 275 0x0000, /* R185 */ 276 0x0000, /* R186 */ 277 0x0000, /* R187 */ 278 0x0000, /* R188 */ 279 0x0000, /* R189 */ 280 0x0000, /* R190 */ 281 0x0000, /* R191 */ 282 0x0000, /* R192 */ 283 0x0000, /* R193 */ 284 0x0000, /* R194 */ 285 0x0000, /* R195 */ 286 0x0000, /* R196 */ 287 0x0000, /* R197 */ 288 0x0000, /* R198 */ 289 0x0000, /* R199 */ 290 0x0000, /* R200 */ 291 0x0000, /* R201 */ 292 0x0000, /* R202 */ 293 0x0000, /* R203 */ 294 0x0000, /* R204 - Analogue Output Bias 0 */ 295 0x0000, /* R205 */ 296 0x0000, /* R206 */ 297 0x0000, /* R207 */ 298 0x0000, /* R208 */ 299 0x0000, /* R209 */ 300 0x0000, /* R210 */ 301 0x0000, /* R211 */ 302 0x0000, /* R212 */ 303 0x0000, /* R213 */ 304 0x0000, /* R214 */ 305 0x0000, /* R215 */ 306 0x0000, /* R216 */ 307 0x0000, /* R217 */ 308 0x0000, /* R218 */ 309 0x0000, /* R219 */ 310 0x0000, /* R220 */ 311 0x0000, /* R221 */ 312 0x0000, /* R222 */ 313 0x0000, /* R223 */ 314 0x0000, /* R224 */ 315 0x0000, /* R225 */ 316 0x0000, /* R226 */ 317 0x0000, /* R227 */ 318 0x0000, /* R228 */ 319 0x0000, /* R229 */ 320 0x0000, /* R230 */ 321 0x0000, /* R231 */ 322 0x0000, /* R232 */ 323 0x0000, /* R233 */ 324 0x0000, /* R234 */ 325 0x0000, /* R235 */ 326 0x0000, /* R236 */ 327 0x0000, /* R237 */ 328 0x0000, /* R238 */ 329 0x0000, /* R239 */ 330 0x0000, /* R240 */ 331 0x0000, /* R241 */ 332 0x0000, /* R242 */ 333 0x0000, /* R243 */ 334 0x0000, /* R244 */ 335 0x0000, /* R245 */ 336 0x0000, /* R246 */ 337 0x0000, /* R247 - FLL NCO Test 0 */ 338 0x0019, /* R248 - FLL NCO Test 1 */ 339 }; 340 341 static struct { 342 int readable; 343 int writable; 344 int vol; 345 } wm8904_access[] = { 346 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */ 347 { 0x0000, 0x0000, 0 }, /* R1 - Revision */ 348 { 0x0000, 0x0000, 0 }, /* R2 */ 349 { 0x0000, 0x0000, 0 }, /* R3 */ 350 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */ 351 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */ 352 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */ 353 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */ 354 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */ 355 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */ 356 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */ 357 { 0x0000, 0x0000, 0 }, /* R11 */ 358 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */ 359 { 0x0000, 0x0000, 0 }, /* R13 */ 360 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */ 361 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */ 362 { 0x0000, 0x0000, 0 }, /* R16 */ 363 { 0x0000, 0x0000, 0 }, /* R17 */ 364 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */ 365 { 0x0000, 0x0000, 0 }, /* R19 */ 366 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */ 367 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */ 368 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */ 369 { 0x0000, 0x0000, 0 }, /* R23 */ 370 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */ 371 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */ 372 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */ 373 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */ 374 { 0x0000, 0x0000, 0 }, /* R28 */ 375 { 0x0000, 0x0000, 0 }, /* R29 */ 376 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */ 377 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */ 378 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */ 379 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */ 380 { 0x0000, 0x0000, 0 }, /* R34 */ 381 { 0x0000, 0x0000, 0 }, /* R35 */ 382 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */ 383 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */ 384 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */ 385 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */ 386 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */ 387 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */ 388 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */ 389 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */ 390 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */ 391 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */ 392 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */ 393 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */ 394 { 0x0000, 0x0000, 0 }, /* R48 */ 395 { 0x0000, 0x0000, 0 }, /* R49 */ 396 { 0x0000, 0x0000, 0 }, /* R50 */ 397 { 0x0000, 0x0000, 0 }, /* R51 */ 398 { 0x0000, 0x0000, 0 }, /* R52 */ 399 { 0x0000, 0x0000, 0 }, /* R53 */ 400 { 0x0000, 0x0000, 0 }, /* R54 */ 401 { 0x0000, 0x0000, 0 }, /* R55 */ 402 { 0x0000, 0x0000, 0 }, /* R56 */ 403 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */ 404 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */ 405 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */ 406 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */ 407 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */ 408 { 0x0000, 0x0000, 0 }, /* R62 */ 409 { 0x0000, 0x0000, 0 }, /* R63 */ 410 { 0x0000, 0x0000, 0 }, /* R64 */ 411 { 0x0000, 0x0000, 0 }, /* R65 */ 412 { 0x0000, 0x0000, 0 }, /* R66 */ 413 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */ 414 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */ 415 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */ 416 { 0x0000, 0x0000, 0 }, /* R70 */ 417 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */ 418 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */ 419 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */ 420 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */ 421 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */ 422 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */ 423 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */ 424 { 0x0000, 0x0000, 0 }, /* R78 */ 425 { 0x0000, 0x0000, 0 }, /* R79 */ 426 { 0x0000, 0x0000, 0 }, /* R80 */ 427 { 0x0000, 0x0000, 0 }, /* R81 */ 428 { 0x0000, 0x0000, 0 }, /* R82 */ 429 { 0x0000, 0x0000, 0 }, /* R83 */ 430 { 0x0000, 0x0000, 0 }, /* R84 */ 431 { 0x0000, 0x0000, 0 }, /* R85 */ 432 { 0x0000, 0x0000, 0 }, /* R86 */ 433 { 0x0000, 0x0000, 0 }, /* R87 */ 434 { 0x0000, 0x0000, 0 }, /* R88 */ 435 { 0x0000, 0x0000, 0 }, /* R89 */ 436 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */ 437 { 0x0000, 0x0000, 0 }, /* R91 */ 438 { 0x0000, 0x0000, 0 }, /* R92 */ 439 { 0x0000, 0x0000, 0 }, /* R93 */ 440 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */ 441 { 0x0000, 0x0000, 0 }, /* R95 */ 442 { 0x0000, 0x0000, 0 }, /* R96 */ 443 { 0x0000, 0x0000, 0 }, /* R97 */ 444 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */ 445 { 0x0000, 0x0000, 0 }, /* R99 */ 446 { 0x0000, 0x0000, 0 }, /* R100 */ 447 { 0x0000, 0x0000, 0 }, /* R101 */ 448 { 0x0000, 0x0000, 0 }, /* R102 */ 449 { 0x0000, 0x0000, 0 }, /* R103 */ 450 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */ 451 { 0x0000, 0x0000, 0 }, /* R105 */ 452 { 0x0000, 0x0000, 0 }, /* R106 */ 453 { 0x0000, 0x0000, 0 }, /* R107 */ 454 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */ 455 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */ 456 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */ 457 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */ 458 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */ 459 { 0x0000, 0x0000, 0 }, /* R113 */ 460 { 0x0000, 0x0000, 0 }, /* R114 */ 461 { 0x0000, 0x0000, 0 }, /* R115 */ 462 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */ 463 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */ 464 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */ 465 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */ 466 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */ 467 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */ 468 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */ 469 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */ 470 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */ 471 { 0x0000, 0x0000, 0 }, /* R125 */ 472 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */ 473 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */ 474 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */ 475 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */ 476 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */ 477 { 0x0000, 0x0000, 0 }, /* R131 */ 478 { 0x0000, 0x0000, 0 }, /* R132 */ 479 { 0x0000, 0x0000, 0 }, /* R133 */ 480 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */ 481 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */ 482 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */ 483 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */ 484 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */ 485 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */ 486 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */ 487 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */ 488 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */ 489 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */ 490 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */ 491 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */ 492 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */ 493 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */ 494 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */ 495 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */ 496 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */ 497 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */ 498 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */ 499 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */ 500 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */ 501 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */ 502 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */ 503 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */ 504 { 0x0000, 0x0000, 0 }, /* R158 */ 505 { 0x0000, 0x0000, 0 }, /* R159 */ 506 { 0x0000, 0x0000, 0 }, /* R160 */ 507 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */ 508 { 0x0000, 0x0000, 0 }, /* R162 */ 509 { 0x0000, 0x0000, 0 }, /* R163 */ 510 { 0x0000, 0x0000, 0 }, /* R164 */ 511 { 0x0000, 0x0000, 0 }, /* R165 */ 512 { 0x0000, 0x0000, 0 }, /* R166 */ 513 { 0x0000, 0x0000, 0 }, /* R167 */ 514 { 0x0000, 0x0000, 0 }, /* R168 */ 515 { 0x0000, 0x0000, 0 }, /* R169 */ 516 { 0x0000, 0x0000, 0 }, /* R170 */ 517 { 0x0000, 0x0000, 0 }, /* R171 */ 518 { 0x0000, 0x0000, 0 }, /* R172 */ 519 { 0x0000, 0x0000, 0 }, /* R173 */ 520 { 0x0000, 0x0000, 0 }, /* R174 */ 521 { 0x0000, 0x0000, 0 }, /* R175 */ 522 { 0x0000, 0x0000, 0 }, /* R176 */ 523 { 0x0000, 0x0000, 0 }, /* R177 */ 524 { 0x0000, 0x0000, 0 }, /* R178 */ 525 { 0x0000, 0x0000, 0 }, /* R179 */ 526 { 0x0000, 0x0000, 0 }, /* R180 */ 527 { 0x0000, 0x0000, 0 }, /* R181 */ 528 { 0x0000, 0x0000, 0 }, /* R182 */ 529 { 0x0000, 0x0000, 0 }, /* R183 */ 530 { 0x0000, 0x0000, 0 }, /* R184 */ 531 { 0x0000, 0x0000, 0 }, /* R185 */ 532 { 0x0000, 0x0000, 0 }, /* R186 */ 533 { 0x0000, 0x0000, 0 }, /* R187 */ 534 { 0x0000, 0x0000, 0 }, /* R188 */ 535 { 0x0000, 0x0000, 0 }, /* R189 */ 536 { 0x0000, 0x0000, 0 }, /* R190 */ 537 { 0x0000, 0x0000, 0 }, /* R191 */ 538 { 0x0000, 0x0000, 0 }, /* R192 */ 539 { 0x0000, 0x0000, 0 }, /* R193 */ 540 { 0x0000, 0x0000, 0 }, /* R194 */ 541 { 0x0000, 0x0000, 0 }, /* R195 */ 542 { 0x0000, 0x0000, 0 }, /* R196 */ 543 { 0x0000, 0x0000, 0 }, /* R197 */ 544 { 0x0000, 0x0000, 0 }, /* R198 */ 545 { 0x0000, 0x0000, 0 }, /* R199 */ 546 { 0x0000, 0x0000, 0 }, /* R200 */ 547 { 0x0000, 0x0000, 0 }, /* R201 */ 548 { 0x0000, 0x0000, 0 }, /* R202 */ 549 { 0x0000, 0x0000, 0 }, /* R203 */ 550 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */ 551 { 0x0000, 0x0000, 0 }, /* R205 */ 552 { 0x0000, 0x0000, 0 }, /* R206 */ 553 { 0x0000, 0x0000, 0 }, /* R207 */ 554 { 0x0000, 0x0000, 0 }, /* R208 */ 555 { 0x0000, 0x0000, 0 }, /* R209 */ 556 { 0x0000, 0x0000, 0 }, /* R210 */ 557 { 0x0000, 0x0000, 0 }, /* R211 */ 558 { 0x0000, 0x0000, 0 }, /* R212 */ 559 { 0x0000, 0x0000, 0 }, /* R213 */ 560 { 0x0000, 0x0000, 0 }, /* R214 */ 561 { 0x0000, 0x0000, 0 }, /* R215 */ 562 { 0x0000, 0x0000, 0 }, /* R216 */ 563 { 0x0000, 0x0000, 0 }, /* R217 */ 564 { 0x0000, 0x0000, 0 }, /* R218 */ 565 { 0x0000, 0x0000, 0 }, /* R219 */ 566 { 0x0000, 0x0000, 0 }, /* R220 */ 567 { 0x0000, 0x0000, 0 }, /* R221 */ 568 { 0x0000, 0x0000, 0 }, /* R222 */ 569 { 0x0000, 0x0000, 0 }, /* R223 */ 570 { 0x0000, 0x0000, 0 }, /* R224 */ 571 { 0x0000, 0x0000, 0 }, /* R225 */ 572 { 0x0000, 0x0000, 0 }, /* R226 */ 573 { 0x0000, 0x0000, 0 }, /* R227 */ 574 { 0x0000, 0x0000, 0 }, /* R228 */ 575 { 0x0000, 0x0000, 0 }, /* R229 */ 576 { 0x0000, 0x0000, 0 }, /* R230 */ 577 { 0x0000, 0x0000, 0 }, /* R231 */ 578 { 0x0000, 0x0000, 0 }, /* R232 */ 579 { 0x0000, 0x0000, 0 }, /* R233 */ 580 { 0x0000, 0x0000, 0 }, /* R234 */ 581 { 0x0000, 0x0000, 0 }, /* R235 */ 582 { 0x0000, 0x0000, 0 }, /* R236 */ 583 { 0x0000, 0x0000, 0 }, /* R237 */ 584 { 0x0000, 0x0000, 0 }, /* R238 */ 585 { 0x0000, 0x0000, 0 }, /* R239 */ 586 { 0x0000, 0x0000, 0 }, /* R240 */ 587 { 0x0000, 0x0000, 0 }, /* R241 */ 588 { 0x0000, 0x0000, 0 }, /* R242 */ 589 { 0x0000, 0x0000, 0 }, /* R243 */ 590 { 0x0000, 0x0000, 0 }, /* R244 */ 591 { 0x0000, 0x0000, 0 }, /* R245 */ 592 { 0x0000, 0x0000, 0 }, /* R246 */ 593 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */ 594 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */ 595 }; 596 597 static int wm8904_volatile_register(struct snd_soc_codec *codec, unsigned int reg) 598 { 599 return wm8904_access[reg].vol; 600 } 601 602 static int wm8904_reset(struct snd_soc_codec *codec) 603 { 604 return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0); 605 } 606 607 static int wm8904_configure_clocking(struct snd_soc_codec *codec) 608 { 609 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 610 unsigned int clock0, clock2, rate; 611 612 /* Gate the clock while we're updating to avoid misclocking */ 613 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 614 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 615 WM8904_SYSCLK_SRC, 0); 616 617 /* This should be done on init() for bypass paths */ 618 switch (wm8904->sysclk_src) { 619 case WM8904_CLK_MCLK: 620 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); 621 622 clock2 &= ~WM8904_SYSCLK_SRC; 623 rate = wm8904->mclk_rate; 624 625 /* Ensure the FLL is stopped */ 626 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 627 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 628 break; 629 630 case WM8904_CLK_FLL: 631 dev_dbg(codec->dev, "Using %dHz FLL clock\n", 632 wm8904->fll_fout); 633 634 clock2 |= WM8904_SYSCLK_SRC; 635 rate = wm8904->fll_fout; 636 break; 637 638 default: 639 dev_err(codec->dev, "System clock not configured\n"); 640 return -EINVAL; 641 } 642 643 /* SYSCLK shouldn't be over 13.5MHz */ 644 if (rate > 13500000) { 645 clock0 = WM8904_MCLK_DIV; 646 wm8904->sysclk_rate = rate / 2; 647 } else { 648 clock0 = 0; 649 wm8904->sysclk_rate = rate; 650 } 651 652 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, 653 clock0); 654 655 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 656 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); 657 658 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); 659 660 return 0; 661 } 662 663 static void wm8904_set_drc(struct snd_soc_codec *codec) 664 { 665 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 666 struct wm8904_pdata *pdata = wm8904->pdata; 667 int save, i; 668 669 /* Save any enables; the configuration should clear them. */ 670 save = snd_soc_read(codec, WM8904_DRC_0); 671 672 for (i = 0; i < WM8904_DRC_REGS; i++) 673 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, 674 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); 675 676 /* Reenable the DRC */ 677 snd_soc_update_bits(codec, WM8904_DRC_0, 678 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); 679 } 680 681 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 682 struct snd_ctl_elem_value *ucontrol) 683 { 684 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 685 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 686 struct wm8904_pdata *pdata = wm8904->pdata; 687 int value = ucontrol->value.integer.value[0]; 688 689 if (value >= pdata->num_drc_cfgs) 690 return -EINVAL; 691 692 wm8904->drc_cfg = value; 693 694 wm8904_set_drc(codec); 695 696 return 0; 697 } 698 699 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 700 struct snd_ctl_elem_value *ucontrol) 701 { 702 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 703 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 704 705 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 706 707 return 0; 708 } 709 710 static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) 711 { 712 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 713 struct wm8904_pdata *pdata = wm8904->pdata; 714 int best, best_val, save, i, cfg; 715 716 if (!pdata || !wm8904->num_retune_mobile_texts) 717 return; 718 719 /* Find the version of the currently selected configuration 720 * with the nearest sample rate. */ 721 cfg = wm8904->retune_mobile_cfg; 722 best = 0; 723 best_val = INT_MAX; 724 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 725 if (strcmp(pdata->retune_mobile_cfgs[i].name, 726 wm8904->retune_mobile_texts[cfg]) == 0 && 727 abs(pdata->retune_mobile_cfgs[i].rate 728 - wm8904->fs) < best_val) { 729 best = i; 730 best_val = abs(pdata->retune_mobile_cfgs[i].rate 731 - wm8904->fs); 732 } 733 } 734 735 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", 736 pdata->retune_mobile_cfgs[best].name, 737 pdata->retune_mobile_cfgs[best].rate, 738 wm8904->fs); 739 740 /* The EQ will be disabled while reconfiguring it, remember the 741 * current configuration. 742 */ 743 save = snd_soc_read(codec, WM8904_EQ1); 744 745 for (i = 0; i < WM8904_EQ_REGS; i++) 746 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, 747 pdata->retune_mobile_cfgs[best].regs[i]); 748 749 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); 750 } 751 752 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 753 struct snd_ctl_elem_value *ucontrol) 754 { 755 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 756 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 757 struct wm8904_pdata *pdata = wm8904->pdata; 758 int value = ucontrol->value.integer.value[0]; 759 760 if (value >= pdata->num_retune_mobile_cfgs) 761 return -EINVAL; 762 763 wm8904->retune_mobile_cfg = value; 764 765 wm8904_set_retune_mobile(codec); 766 767 return 0; 768 } 769 770 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 771 struct snd_ctl_elem_value *ucontrol) 772 { 773 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 774 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 775 776 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 777 778 return 0; 779 } 780 781 static int deemph_settings[] = { 0, 32000, 44100, 48000 }; 782 783 static int wm8904_set_deemph(struct snd_soc_codec *codec) 784 { 785 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 786 int val, i, best; 787 788 /* If we're using deemphasis select the nearest available sample 789 * rate. 790 */ 791 if (wm8904->deemph) { 792 best = 1; 793 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { 794 if (abs(deemph_settings[i] - wm8904->fs) < 795 abs(deemph_settings[best] - wm8904->fs)) 796 best = i; 797 } 798 799 val = best << WM8904_DEEMPH_SHIFT; 800 } else { 801 val = 0; 802 } 803 804 dev_dbg(codec->dev, "Set deemphasis %d\n", val); 805 806 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 807 WM8904_DEEMPH_MASK, val); 808 } 809 810 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 811 struct snd_ctl_elem_value *ucontrol) 812 { 813 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 814 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 815 816 ucontrol->value.enumerated.item[0] = wm8904->deemph; 817 return 0; 818 } 819 820 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 821 struct snd_ctl_elem_value *ucontrol) 822 { 823 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 824 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 825 int deemph = ucontrol->value.enumerated.item[0]; 826 827 if (deemph > 1) 828 return -EINVAL; 829 830 wm8904->deemph = deemph; 831 832 return wm8904_set_deemph(codec); 833 } 834 835 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 836 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 837 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 838 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); 839 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 840 841 static const char *input_mode_text[] = { 842 "Single-Ended", "Differential Line", "Differential Mic" 843 }; 844 845 static const struct soc_enum lin_mode = 846 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); 847 848 static const struct soc_enum rin_mode = 849 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); 850 851 static const char *hpf_mode_text[] = { 852 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 853 }; 854 855 static const struct soc_enum hpf_mode = 856 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); 857 858 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { 859 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, 860 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), 861 862 SOC_ENUM("Left Caputure Mode", lin_mode), 863 SOC_ENUM("Right Capture Mode", rin_mode), 864 865 /* No TLV since it depends on mode */ 866 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, 867 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), 868 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, 869 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1), 870 871 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), 872 SOC_ENUM("High Pass Filter Mode", hpf_mode), 873 874 SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0), 875 }; 876 877 static const char *drc_path_text[] = { 878 "ADC", "DAC" 879 }; 880 881 static const struct soc_enum drc_path = 882 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); 883 884 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { 885 SOC_SINGLE_TLV("Digital Playback Boost Volume", 886 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), 887 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, 888 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), 889 890 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, 891 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), 892 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, 893 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), 894 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, 895 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), 896 897 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, 898 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), 899 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, 900 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), 901 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, 902 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), 903 904 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), 905 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), 906 SOC_ENUM("DRC Path", drc_path), 907 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), 908 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, 909 wm8904_get_deemph, wm8904_put_deemph), 910 }; 911 912 static const struct snd_kcontrol_new wm8904_snd_controls[] = { 913 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, 914 sidetone_tlv), 915 }; 916 917 static const struct snd_kcontrol_new wm8904_eq_controls[] = { 918 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), 919 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), 920 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), 921 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), 922 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), 923 }; 924 925 static int cp_event(struct snd_soc_dapm_widget *w, 926 struct snd_kcontrol *kcontrol, int event) 927 { 928 BUG_ON(event != SND_SOC_DAPM_POST_PMU); 929 930 /* Maximum startup time */ 931 udelay(500); 932 933 return 0; 934 } 935 936 static int sysclk_event(struct snd_soc_dapm_widget *w, 937 struct snd_kcontrol *kcontrol, int event) 938 { 939 struct snd_soc_codec *codec = w->codec; 940 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 941 942 switch (event) { 943 case SND_SOC_DAPM_PRE_PMU: 944 /* If we're using the FLL then we only start it when 945 * required; we assume that the configuration has been 946 * done previously and all we need to do is kick it 947 * off. 948 */ 949 switch (wm8904->sysclk_src) { 950 case WM8904_CLK_FLL: 951 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 952 WM8904_FLL_OSC_ENA, 953 WM8904_FLL_OSC_ENA); 954 955 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 956 WM8904_FLL_ENA, 957 WM8904_FLL_ENA); 958 break; 959 960 default: 961 break; 962 } 963 break; 964 965 case SND_SOC_DAPM_POST_PMD: 966 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 967 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 968 break; 969 } 970 971 return 0; 972 } 973 974 static int out_pga_event(struct snd_soc_dapm_widget *w, 975 struct snd_kcontrol *kcontrol, int event) 976 { 977 struct snd_soc_codec *codec = w->codec; 978 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 979 int reg, val; 980 int dcs_mask; 981 int dcs_l, dcs_r; 982 int dcs_l_reg, dcs_r_reg; 983 int timeout; 984 int pwr_reg; 985 986 /* This code is shared between HP and LINEOUT; we do all our 987 * power management in stereo pairs to avoid latency issues so 988 * we reuse shift to identify which rather than strcmp() the 989 * name. */ 990 reg = w->shift; 991 992 switch (reg) { 993 case WM8904_ANALOGUE_HP_0: 994 pwr_reg = WM8904_POWER_MANAGEMENT_2; 995 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; 996 dcs_r_reg = WM8904_DC_SERVO_8; 997 dcs_l_reg = WM8904_DC_SERVO_9; 998 dcs_l = 0; 999 dcs_r = 1; 1000 break; 1001 case WM8904_ANALOGUE_LINEOUT_0: 1002 pwr_reg = WM8904_POWER_MANAGEMENT_3; 1003 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; 1004 dcs_r_reg = WM8904_DC_SERVO_6; 1005 dcs_l_reg = WM8904_DC_SERVO_7; 1006 dcs_l = 2; 1007 dcs_r = 3; 1008 break; 1009 default: 1010 BUG(); 1011 return -EINVAL; 1012 } 1013 1014 switch (event) { 1015 case SND_SOC_DAPM_PRE_PMU: 1016 /* Power on the PGAs */ 1017 snd_soc_update_bits(codec, pwr_reg, 1018 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1019 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); 1020 1021 /* Power on the amplifier */ 1022 snd_soc_update_bits(codec, reg, 1023 WM8904_HPL_ENA | WM8904_HPR_ENA, 1024 WM8904_HPL_ENA | WM8904_HPR_ENA); 1025 1026 1027 /* Enable the first stage */ 1028 snd_soc_update_bits(codec, reg, 1029 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, 1030 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); 1031 1032 /* Power up the DC servo */ 1033 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1034 dcs_mask, dcs_mask); 1035 1036 /* Either calibrate the DC servo or restore cached state 1037 * if we have that. 1038 */ 1039 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { 1040 dev_dbg(codec->dev, "Restoring DC servo state\n"); 1041 1042 snd_soc_write(codec, dcs_l_reg, 1043 wm8904->dcs_state[dcs_l]); 1044 snd_soc_write(codec, dcs_r_reg, 1045 wm8904->dcs_state[dcs_r]); 1046 1047 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); 1048 1049 timeout = 20; 1050 } else { 1051 dev_dbg(codec->dev, "Calibrating DC servo\n"); 1052 1053 snd_soc_write(codec, WM8904_DC_SERVO_1, 1054 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); 1055 1056 timeout = 500; 1057 } 1058 1059 /* Wait for DC servo to complete */ 1060 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; 1061 do { 1062 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); 1063 if ((val & dcs_mask) == dcs_mask) 1064 break; 1065 1066 msleep(1); 1067 } while (--timeout); 1068 1069 if ((val & dcs_mask) != dcs_mask) 1070 dev_warn(codec->dev, "DC servo timed out\n"); 1071 else 1072 dev_dbg(codec->dev, "DC servo ready\n"); 1073 1074 /* Enable the output stage */ 1075 snd_soc_update_bits(codec, reg, 1076 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1077 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); 1078 break; 1079 1080 case SND_SOC_DAPM_POST_PMU: 1081 /* Unshort the output itself */ 1082 snd_soc_update_bits(codec, reg, 1083 WM8904_HPL_RMV_SHORT | 1084 WM8904_HPR_RMV_SHORT, 1085 WM8904_HPL_RMV_SHORT | 1086 WM8904_HPR_RMV_SHORT); 1087 1088 break; 1089 1090 case SND_SOC_DAPM_PRE_PMD: 1091 /* Short the output */ 1092 snd_soc_update_bits(codec, reg, 1093 WM8904_HPL_RMV_SHORT | 1094 WM8904_HPR_RMV_SHORT, 0); 1095 break; 1096 1097 case SND_SOC_DAPM_POST_PMD: 1098 /* Cache the DC servo configuration; this will be 1099 * invalidated if we change the configuration. */ 1100 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); 1101 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); 1102 1103 snd_soc_update_bits(codec, WM8904_DC_SERVO_0, 1104 dcs_mask, 0); 1105 1106 /* Disable the amplifier input and output stages */ 1107 snd_soc_update_bits(codec, reg, 1108 WM8904_HPL_ENA | WM8904_HPR_ENA | 1109 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | 1110 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, 1111 0); 1112 1113 /* PGAs too */ 1114 snd_soc_update_bits(codec, pwr_reg, 1115 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, 1116 0); 1117 break; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static const char *lin_text[] = { 1124 "IN1L", "IN2L", "IN3L" 1125 }; 1126 1127 static const struct soc_enum lin_enum = 1128 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); 1129 1130 static const struct snd_kcontrol_new lin_mux = 1131 SOC_DAPM_ENUM("Left Capture Mux", lin_enum); 1132 1133 static const struct soc_enum lin_inv_enum = 1134 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); 1135 1136 static const struct snd_kcontrol_new lin_inv_mux = 1137 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); 1138 1139 static const char *rin_text[] = { 1140 "IN1R", "IN2R", "IN3R" 1141 }; 1142 1143 static const struct soc_enum rin_enum = 1144 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); 1145 1146 static const struct snd_kcontrol_new rin_mux = 1147 SOC_DAPM_ENUM("Right Capture Mux", rin_enum); 1148 1149 static const struct soc_enum rin_inv_enum = 1150 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); 1151 1152 static const struct snd_kcontrol_new rin_inv_mux = 1153 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); 1154 1155 static const char *aif_text[] = { 1156 "Left", "Right" 1157 }; 1158 1159 static const struct soc_enum aifoutl_enum = 1160 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); 1161 1162 static const struct snd_kcontrol_new aifoutl_mux = 1163 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); 1164 1165 static const struct soc_enum aifoutr_enum = 1166 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); 1167 1168 static const struct snd_kcontrol_new aifoutr_mux = 1169 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); 1170 1171 static const struct soc_enum aifinl_enum = 1172 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); 1173 1174 static const struct snd_kcontrol_new aifinl_mux = 1175 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); 1176 1177 static const struct soc_enum aifinr_enum = 1178 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); 1179 1180 static const struct snd_kcontrol_new aifinr_mux = 1181 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); 1182 1183 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { 1184 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, 1185 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1186 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), 1187 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), 1188 }; 1189 1190 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { 1191 SND_SOC_DAPM_INPUT("IN1L"), 1192 SND_SOC_DAPM_INPUT("IN1R"), 1193 SND_SOC_DAPM_INPUT("IN2L"), 1194 SND_SOC_DAPM_INPUT("IN2R"), 1195 SND_SOC_DAPM_INPUT("IN3L"), 1196 SND_SOC_DAPM_INPUT("IN3R"), 1197 1198 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 1199 1200 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), 1201 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1202 &lin_inv_mux), 1203 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), 1204 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, 1205 &rin_inv_mux), 1206 1207 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, 1208 NULL, 0), 1209 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, 1210 NULL, 0), 1211 1212 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), 1213 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), 1214 1215 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), 1216 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), 1217 1218 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), 1219 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), 1220 }; 1221 1222 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { 1223 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), 1224 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), 1225 1226 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), 1227 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), 1228 1229 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), 1230 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), 1231 1232 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, 1233 SND_SOC_DAPM_POST_PMU), 1234 1235 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1236 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1237 1238 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), 1239 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 1240 1241 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, 1242 0, NULL, 0, out_pga_event, 1243 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1244 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1245 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, 1246 0, NULL, 0, out_pga_event, 1247 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1248 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1249 1250 SND_SOC_DAPM_OUTPUT("HPOUTL"), 1251 SND_SOC_DAPM_OUTPUT("HPOUTR"), 1252 SND_SOC_DAPM_OUTPUT("LINEOUTL"), 1253 SND_SOC_DAPM_OUTPUT("LINEOUTR"), 1254 }; 1255 1256 static const char *out_mux_text[] = { 1257 "DAC", "Bypass" 1258 }; 1259 1260 static const struct soc_enum hpl_enum = 1261 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); 1262 1263 static const struct snd_kcontrol_new hpl_mux = 1264 SOC_DAPM_ENUM("HPL Mux", hpl_enum); 1265 1266 static const struct soc_enum hpr_enum = 1267 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); 1268 1269 static const struct snd_kcontrol_new hpr_mux = 1270 SOC_DAPM_ENUM("HPR Mux", hpr_enum); 1271 1272 static const struct soc_enum linel_enum = 1273 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); 1274 1275 static const struct snd_kcontrol_new linel_mux = 1276 SOC_DAPM_ENUM("LINEL Mux", linel_enum); 1277 1278 static const struct soc_enum liner_enum = 1279 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); 1280 1281 static const struct snd_kcontrol_new liner_mux = 1282 SOC_DAPM_ENUM("LINEL Mux", liner_enum); 1283 1284 static const char *sidetone_text[] = { 1285 "None", "Left", "Right" 1286 }; 1287 1288 static const struct soc_enum dacl_sidetone_enum = 1289 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); 1290 1291 static const struct snd_kcontrol_new dacl_sidetone_mux = 1292 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); 1293 1294 static const struct soc_enum dacr_sidetone_enum = 1295 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); 1296 1297 static const struct snd_kcontrol_new dacr_sidetone_mux = 1298 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); 1299 1300 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { 1301 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), 1302 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1303 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 1304 1305 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), 1306 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), 1307 1308 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1309 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1310 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), 1311 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), 1312 }; 1313 1314 static const struct snd_soc_dapm_route core_intercon[] = { 1315 { "CLK_DSP", NULL, "SYSCLK" }, 1316 { "TOCLK", NULL, "SYSCLK" }, 1317 }; 1318 1319 static const struct snd_soc_dapm_route adc_intercon[] = { 1320 { "Left Capture Mux", "IN1L", "IN1L" }, 1321 { "Left Capture Mux", "IN2L", "IN2L" }, 1322 { "Left Capture Mux", "IN3L", "IN3L" }, 1323 1324 { "Left Capture Inverting Mux", "IN1L", "IN1L" }, 1325 { "Left Capture Inverting Mux", "IN2L", "IN2L" }, 1326 { "Left Capture Inverting Mux", "IN3L", "IN3L" }, 1327 1328 { "Right Capture Mux", "IN1R", "IN1R" }, 1329 { "Right Capture Mux", "IN2R", "IN2R" }, 1330 { "Right Capture Mux", "IN3R", "IN3R" }, 1331 1332 { "Right Capture Inverting Mux", "IN1R", "IN1R" }, 1333 { "Right Capture Inverting Mux", "IN2R", "IN2R" }, 1334 { "Right Capture Inverting Mux", "IN3R", "IN3R" }, 1335 1336 { "Left Capture PGA", NULL, "Left Capture Mux" }, 1337 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, 1338 1339 { "Right Capture PGA", NULL, "Right Capture Mux" }, 1340 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, 1341 1342 { "AIFOUTL", "Left", "ADCL" }, 1343 { "AIFOUTL", "Right", "ADCR" }, 1344 { "AIFOUTR", "Left", "ADCL" }, 1345 { "AIFOUTR", "Right", "ADCR" }, 1346 1347 { "ADCL", NULL, "CLK_DSP" }, 1348 { "ADCL", NULL, "Left Capture PGA" }, 1349 1350 { "ADCR", NULL, "CLK_DSP" }, 1351 { "ADCR", NULL, "Right Capture PGA" }, 1352 }; 1353 1354 static const struct snd_soc_dapm_route dac_intercon[] = { 1355 { "DACL", "Right", "AIFINR" }, 1356 { "DACL", "Left", "AIFINL" }, 1357 { "DACL", NULL, "CLK_DSP" }, 1358 1359 { "DACR", "Right", "AIFINR" }, 1360 { "DACR", "Left", "AIFINL" }, 1361 { "DACR", NULL, "CLK_DSP" }, 1362 1363 { "Charge pump", NULL, "SYSCLK" }, 1364 1365 { "Headphone Output", NULL, "HPL PGA" }, 1366 { "Headphone Output", NULL, "HPR PGA" }, 1367 { "Headphone Output", NULL, "Charge pump" }, 1368 { "Headphone Output", NULL, "TOCLK" }, 1369 1370 { "Line Output", NULL, "LINEL PGA" }, 1371 { "Line Output", NULL, "LINER PGA" }, 1372 { "Line Output", NULL, "Charge pump" }, 1373 { "Line Output", NULL, "TOCLK" }, 1374 1375 { "HPOUTL", NULL, "Headphone Output" }, 1376 { "HPOUTR", NULL, "Headphone Output" }, 1377 1378 { "LINEOUTL", NULL, "Line Output" }, 1379 { "LINEOUTR", NULL, "Line Output" }, 1380 }; 1381 1382 static const struct snd_soc_dapm_route wm8904_intercon[] = { 1383 { "Left Sidetone", "Left", "ADCL" }, 1384 { "Left Sidetone", "Right", "ADCR" }, 1385 { "DACL", NULL, "Left Sidetone" }, 1386 1387 { "Right Sidetone", "Left", "ADCL" }, 1388 { "Right Sidetone", "Right", "ADCR" }, 1389 { "DACR", NULL, "Right Sidetone" }, 1390 1391 { "Left Bypass", NULL, "Class G" }, 1392 { "Left Bypass", NULL, "Left Capture PGA" }, 1393 1394 { "Right Bypass", NULL, "Class G" }, 1395 { "Right Bypass", NULL, "Right Capture PGA" }, 1396 1397 { "HPL Mux", "DAC", "DACL" }, 1398 { "HPL Mux", "Bypass", "Left Bypass" }, 1399 1400 { "HPR Mux", "DAC", "DACR" }, 1401 { "HPR Mux", "Bypass", "Right Bypass" }, 1402 1403 { "LINEL Mux", "DAC", "DACL" }, 1404 { "LINEL Mux", "Bypass", "Left Bypass" }, 1405 1406 { "LINER Mux", "DAC", "DACR" }, 1407 { "LINER Mux", "Bypass", "Right Bypass" }, 1408 1409 { "HPL PGA", NULL, "HPL Mux" }, 1410 { "HPR PGA", NULL, "HPR Mux" }, 1411 1412 { "LINEL PGA", NULL, "LINEL Mux" }, 1413 { "LINER PGA", NULL, "LINER Mux" }, 1414 }; 1415 1416 static const struct snd_soc_dapm_route wm8912_intercon[] = { 1417 { "HPL PGA", NULL, "DACL" }, 1418 { "HPR PGA", NULL, "DACR" }, 1419 1420 { "LINEL PGA", NULL, "DACL" }, 1421 { "LINER PGA", NULL, "DACR" }, 1422 }; 1423 1424 static int wm8904_add_widgets(struct snd_soc_codec *codec) 1425 { 1426 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1427 struct snd_soc_dapm_context *dapm = &codec->dapm; 1428 1429 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, 1430 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1431 snd_soc_dapm_add_routes(dapm, core_intercon, 1432 ARRAY_SIZE(core_intercon)); 1433 1434 switch (wm8904->devtype) { 1435 case WM8904: 1436 snd_soc_add_controls(codec, wm8904_adc_snd_controls, 1437 ARRAY_SIZE(wm8904_adc_snd_controls)); 1438 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1439 ARRAY_SIZE(wm8904_dac_snd_controls)); 1440 snd_soc_add_controls(codec, wm8904_snd_controls, 1441 ARRAY_SIZE(wm8904_snd_controls)); 1442 1443 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, 1444 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1445 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1446 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1447 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, 1448 ARRAY_SIZE(wm8904_dapm_widgets)); 1449 1450 snd_soc_dapm_add_routes(dapm, core_intercon, 1451 ARRAY_SIZE(core_intercon)); 1452 snd_soc_dapm_add_routes(dapm, adc_intercon, 1453 ARRAY_SIZE(adc_intercon)); 1454 snd_soc_dapm_add_routes(dapm, dac_intercon, 1455 ARRAY_SIZE(dac_intercon)); 1456 snd_soc_dapm_add_routes(dapm, wm8904_intercon, 1457 ARRAY_SIZE(wm8904_intercon)); 1458 break; 1459 1460 case WM8912: 1461 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1462 ARRAY_SIZE(wm8904_dac_snd_controls)); 1463 1464 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, 1465 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1466 1467 snd_soc_dapm_add_routes(dapm, dac_intercon, 1468 ARRAY_SIZE(dac_intercon)); 1469 snd_soc_dapm_add_routes(dapm, wm8912_intercon, 1470 ARRAY_SIZE(wm8912_intercon)); 1471 break; 1472 } 1473 1474 snd_soc_dapm_new_widgets(dapm); 1475 return 0; 1476 } 1477 1478 static struct { 1479 int ratio; 1480 unsigned int clk_sys_rate; 1481 } clk_sys_rates[] = { 1482 { 64, 0 }, 1483 { 128, 1 }, 1484 { 192, 2 }, 1485 { 256, 3 }, 1486 { 384, 4 }, 1487 { 512, 5 }, 1488 { 786, 6 }, 1489 { 1024, 7 }, 1490 { 1408, 8 }, 1491 { 1536, 9 }, 1492 }; 1493 1494 static struct { 1495 int rate; 1496 int sample_rate; 1497 } sample_rates[] = { 1498 { 8000, 0 }, 1499 { 11025, 1 }, 1500 { 12000, 1 }, 1501 { 16000, 2 }, 1502 { 22050, 3 }, 1503 { 24000, 3 }, 1504 { 32000, 4 }, 1505 { 44100, 5 }, 1506 { 48000, 5 }, 1507 }; 1508 1509 static struct { 1510 int div; /* *10 due to .5s */ 1511 int bclk_div; 1512 } bclk_divs[] = { 1513 { 10, 0 }, 1514 { 15, 1 }, 1515 { 20, 2 }, 1516 { 30, 3 }, 1517 { 40, 4 }, 1518 { 50, 5 }, 1519 { 55, 6 }, 1520 { 60, 7 }, 1521 { 80, 8 }, 1522 { 100, 9 }, 1523 { 110, 10 }, 1524 { 120, 11 }, 1525 { 160, 12 }, 1526 { 200, 13 }, 1527 { 220, 14 }, 1528 { 240, 16 }, 1529 { 200, 17 }, 1530 { 320, 18 }, 1531 { 440, 19 }, 1532 { 480, 20 }, 1533 }; 1534 1535 1536 static int wm8904_hw_params(struct snd_pcm_substream *substream, 1537 struct snd_pcm_hw_params *params, 1538 struct snd_soc_dai *dai) 1539 { 1540 struct snd_soc_codec *codec = dai->codec; 1541 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1542 int ret, i, best, best_val, cur_val; 1543 unsigned int aif1 = 0; 1544 unsigned int aif2 = 0; 1545 unsigned int aif3 = 0; 1546 unsigned int clock1 = 0; 1547 unsigned int dac_digital1 = 0; 1548 1549 /* What BCLK do we need? */ 1550 wm8904->fs = params_rate(params); 1551 if (wm8904->tdm_slots) { 1552 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", 1553 wm8904->tdm_slots, wm8904->tdm_width); 1554 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, 1555 wm8904->tdm_width, 2, 1556 wm8904->tdm_slots); 1557 } else { 1558 wm8904->bclk = snd_soc_params_to_bclk(params); 1559 } 1560 1561 switch (params_format(params)) { 1562 case SNDRV_PCM_FORMAT_S16_LE: 1563 break; 1564 case SNDRV_PCM_FORMAT_S20_3LE: 1565 aif1 |= 0x40; 1566 break; 1567 case SNDRV_PCM_FORMAT_S24_LE: 1568 aif1 |= 0x80; 1569 break; 1570 case SNDRV_PCM_FORMAT_S32_LE: 1571 aif1 |= 0xc0; 1572 break; 1573 default: 1574 return -EINVAL; 1575 } 1576 1577 1578 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); 1579 1580 ret = wm8904_configure_clocking(codec); 1581 if (ret != 0) 1582 return ret; 1583 1584 /* Select nearest CLK_SYS_RATE */ 1585 best = 0; 1586 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) 1587 - wm8904->fs); 1588 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1589 cur_val = abs((wm8904->sysclk_rate / 1590 clk_sys_rates[i].ratio) - wm8904->fs); 1591 if (cur_val < best_val) { 1592 best = i; 1593 best_val = cur_val; 1594 } 1595 } 1596 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", 1597 clk_sys_rates[best].ratio); 1598 clock1 |= (clk_sys_rates[best].clk_sys_rate 1599 << WM8904_CLK_SYS_RATE_SHIFT); 1600 1601 /* SAMPLE_RATE */ 1602 best = 0; 1603 best_val = abs(wm8904->fs - sample_rates[0].rate); 1604 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1605 /* Closest match */ 1606 cur_val = abs(wm8904->fs - sample_rates[i].rate); 1607 if (cur_val < best_val) { 1608 best = i; 1609 best_val = cur_val; 1610 } 1611 } 1612 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", 1613 sample_rates[best].rate); 1614 clock1 |= (sample_rates[best].sample_rate 1615 << WM8904_SAMPLE_RATE_SHIFT); 1616 1617 /* Enable sloping stopband filter for low sample rates */ 1618 if (wm8904->fs <= 24000) 1619 dac_digital1 |= WM8904_DAC_SB_FILT; 1620 1621 /* BCLK_DIV */ 1622 best = 0; 1623 best_val = INT_MAX; 1624 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1625 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) 1626 - wm8904->bclk; 1627 if (cur_val < 0) /* Table is sorted */ 1628 break; 1629 if (cur_val < best_val) { 1630 best = i; 1631 best_val = cur_val; 1632 } 1633 } 1634 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; 1635 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", 1636 bclk_divs[best].div, wm8904->bclk); 1637 aif2 |= bclk_divs[best].bclk_div; 1638 1639 /* LRCLK is a simple fraction of BCLK */ 1640 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); 1641 aif3 |= wm8904->bclk / wm8904->fs; 1642 1643 /* Apply the settings */ 1644 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, 1645 WM8904_DAC_SB_FILT, dac_digital1); 1646 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1647 WM8904_AIF_WL_MASK, aif1); 1648 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, 1649 WM8904_BCLK_DIV_MASK, aif2); 1650 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1651 WM8904_LRCLK_RATE_MASK, aif3); 1652 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, 1653 WM8904_SAMPLE_RATE_MASK | 1654 WM8904_CLK_SYS_RATE_MASK, clock1); 1655 1656 /* Update filters for the new settings */ 1657 wm8904_set_retune_mobile(codec); 1658 wm8904_set_deemph(codec); 1659 1660 return 0; 1661 } 1662 1663 1664 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, 1665 unsigned int freq, int dir) 1666 { 1667 struct snd_soc_codec *codec = dai->codec; 1668 struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); 1669 1670 switch (clk_id) { 1671 case WM8904_CLK_MCLK: 1672 priv->sysclk_src = clk_id; 1673 priv->mclk_rate = freq; 1674 break; 1675 1676 case WM8904_CLK_FLL: 1677 priv->sysclk_src = clk_id; 1678 break; 1679 1680 default: 1681 return -EINVAL; 1682 } 1683 1684 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1685 1686 wm8904_configure_clocking(codec); 1687 1688 return 0; 1689 } 1690 1691 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1692 { 1693 struct snd_soc_codec *codec = dai->codec; 1694 unsigned int aif1 = 0; 1695 unsigned int aif3 = 0; 1696 1697 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1698 case SND_SOC_DAIFMT_CBS_CFS: 1699 break; 1700 case SND_SOC_DAIFMT_CBS_CFM: 1701 aif3 |= WM8904_LRCLK_DIR; 1702 break; 1703 case SND_SOC_DAIFMT_CBM_CFS: 1704 aif1 |= WM8904_BCLK_DIR; 1705 break; 1706 case SND_SOC_DAIFMT_CBM_CFM: 1707 aif1 |= WM8904_BCLK_DIR; 1708 aif3 |= WM8904_LRCLK_DIR; 1709 break; 1710 default: 1711 return -EINVAL; 1712 } 1713 1714 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1715 case SND_SOC_DAIFMT_DSP_B: 1716 aif1 |= WM8904_AIF_LRCLK_INV; 1717 case SND_SOC_DAIFMT_DSP_A: 1718 aif1 |= 0x3; 1719 break; 1720 case SND_SOC_DAIFMT_I2S: 1721 aif1 |= 0x2; 1722 break; 1723 case SND_SOC_DAIFMT_RIGHT_J: 1724 break; 1725 case SND_SOC_DAIFMT_LEFT_J: 1726 aif1 |= 0x1; 1727 break; 1728 default: 1729 return -EINVAL; 1730 } 1731 1732 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1733 case SND_SOC_DAIFMT_DSP_A: 1734 case SND_SOC_DAIFMT_DSP_B: 1735 /* frame inversion not valid for DSP modes */ 1736 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1737 case SND_SOC_DAIFMT_NB_NF: 1738 break; 1739 case SND_SOC_DAIFMT_IB_NF: 1740 aif1 |= WM8904_AIF_BCLK_INV; 1741 break; 1742 default: 1743 return -EINVAL; 1744 } 1745 break; 1746 1747 case SND_SOC_DAIFMT_I2S: 1748 case SND_SOC_DAIFMT_RIGHT_J: 1749 case SND_SOC_DAIFMT_LEFT_J: 1750 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1751 case SND_SOC_DAIFMT_NB_NF: 1752 break; 1753 case SND_SOC_DAIFMT_IB_IF: 1754 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; 1755 break; 1756 case SND_SOC_DAIFMT_IB_NF: 1757 aif1 |= WM8904_AIF_BCLK_INV; 1758 break; 1759 case SND_SOC_DAIFMT_NB_IF: 1760 aif1 |= WM8904_AIF_LRCLK_INV; 1761 break; 1762 default: 1763 return -EINVAL; 1764 } 1765 break; 1766 default: 1767 return -EINVAL; 1768 } 1769 1770 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1771 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | 1772 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); 1773 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, 1774 WM8904_LRCLK_DIR, aif3); 1775 1776 return 0; 1777 } 1778 1779 1780 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 1781 unsigned int rx_mask, int slots, int slot_width) 1782 { 1783 struct snd_soc_codec *codec = dai->codec; 1784 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1785 int aif1 = 0; 1786 1787 /* Don't need to validate anything if we're turning off TDM */ 1788 if (slots == 0) 1789 goto out; 1790 1791 /* Note that we allow configurations we can't handle ourselves - 1792 * for example, we can generate clocks for slots 2 and up even if 1793 * we can't use those slots ourselves. 1794 */ 1795 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; 1796 1797 switch (rx_mask) { 1798 case 3: 1799 break; 1800 case 0xc: 1801 aif1 |= WM8904_AIFADC_TDM_CHAN; 1802 break; 1803 default: 1804 return -EINVAL; 1805 } 1806 1807 1808 switch (tx_mask) { 1809 case 3: 1810 break; 1811 case 0xc: 1812 aif1 |= WM8904_AIFDAC_TDM_CHAN; 1813 break; 1814 default: 1815 return -EINVAL; 1816 } 1817 1818 out: 1819 wm8904->tdm_width = slot_width; 1820 wm8904->tdm_slots = slots / 2; 1821 1822 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, 1823 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | 1824 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); 1825 1826 return 0; 1827 } 1828 1829 struct _fll_div { 1830 u16 fll_fratio; 1831 u16 fll_outdiv; 1832 u16 fll_clk_ref_div; 1833 u16 n; 1834 u16 k; 1835 }; 1836 1837 /* The size in bits of the FLL divide multiplied by 10 1838 * to allow rounding later */ 1839 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1840 1841 static struct { 1842 unsigned int min; 1843 unsigned int max; 1844 u16 fll_fratio; 1845 int ratio; 1846 } fll_fratios[] = { 1847 { 0, 64000, 4, 16 }, 1848 { 64000, 128000, 3, 8 }, 1849 { 128000, 256000, 2, 4 }, 1850 { 256000, 1000000, 1, 2 }, 1851 { 1000000, 13500000, 0, 1 }, 1852 }; 1853 1854 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1855 unsigned int Fout) 1856 { 1857 u64 Kpart; 1858 unsigned int K, Ndiv, Nmod, target; 1859 unsigned int div; 1860 int i; 1861 1862 /* Fref must be <=13.5MHz */ 1863 div = 1; 1864 fll_div->fll_clk_ref_div = 0; 1865 while ((Fref / div) > 13500000) { 1866 div *= 2; 1867 fll_div->fll_clk_ref_div++; 1868 1869 if (div > 8) { 1870 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1871 Fref); 1872 return -EINVAL; 1873 } 1874 } 1875 1876 pr_debug("Fref=%u Fout=%u\n", Fref, Fout); 1877 1878 /* Apply the division for our remaining calculations */ 1879 Fref /= div; 1880 1881 /* Fvco should be 90-100MHz; don't check the upper bound */ 1882 div = 4; 1883 while (Fout * div < 90000000) { 1884 div++; 1885 if (div > 64) { 1886 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1887 Fout); 1888 return -EINVAL; 1889 } 1890 } 1891 target = Fout * div; 1892 fll_div->fll_outdiv = div - 1; 1893 1894 pr_debug("Fvco=%dHz\n", target); 1895 1896 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 1897 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1898 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1899 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1900 target /= fll_fratios[i].ratio; 1901 break; 1902 } 1903 } 1904 if (i == ARRAY_SIZE(fll_fratios)) { 1905 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1906 return -EINVAL; 1907 } 1908 1909 /* Now, calculate N.K */ 1910 Ndiv = target / Fref; 1911 1912 fll_div->n = Ndiv; 1913 Nmod = target % Fref; 1914 pr_debug("Nmod=%d\n", Nmod); 1915 1916 /* Calculate fractional part - scale up so we can round. */ 1917 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1918 1919 do_div(Kpart, Fref); 1920 1921 K = Kpart & 0xFFFFFFFF; 1922 1923 if ((K % 10) >= 5) 1924 K += 5; 1925 1926 /* Move down to proper range now rounding is done */ 1927 fll_div->k = K / 10; 1928 1929 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", 1930 fll_div->n, fll_div->k, 1931 fll_div->fll_fratio, fll_div->fll_outdiv, 1932 fll_div->fll_clk_ref_div); 1933 1934 return 0; 1935 } 1936 1937 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, 1938 unsigned int Fref, unsigned int Fout) 1939 { 1940 struct snd_soc_codec *codec = dai->codec; 1941 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1942 struct _fll_div fll_div; 1943 int ret, val; 1944 int clock2, fll1; 1945 1946 /* Any change? */ 1947 if (source == wm8904->fll_src && Fref == wm8904->fll_fref && 1948 Fout == wm8904->fll_fout) 1949 return 0; 1950 1951 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); 1952 1953 if (Fout == 0) { 1954 dev_dbg(codec->dev, "FLL disabled\n"); 1955 1956 wm8904->fll_fref = 0; 1957 wm8904->fll_fout = 0; 1958 1959 /* Gate SYSCLK to avoid glitches */ 1960 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 1961 WM8904_CLK_SYS_ENA, 0); 1962 1963 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 1964 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 1965 1966 goto out; 1967 } 1968 1969 /* Validate the FLL ID */ 1970 switch (source) { 1971 case WM8904_FLL_MCLK: 1972 case WM8904_FLL_LRCLK: 1973 case WM8904_FLL_BCLK: 1974 ret = fll_factors(&fll_div, Fref, Fout); 1975 if (ret != 0) 1976 return ret; 1977 break; 1978 1979 case WM8904_FLL_FREE_RUNNING: 1980 dev_dbg(codec->dev, "Using free running FLL\n"); 1981 /* Force 12MHz and output/4 for now */ 1982 Fout = 12000000; 1983 Fref = 12000000; 1984 1985 memset(&fll_div, 0, sizeof(fll_div)); 1986 fll_div.fll_outdiv = 3; 1987 break; 1988 1989 default: 1990 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); 1991 return -EINVAL; 1992 } 1993 1994 /* Save current state then disable the FLL and SYSCLK to avoid 1995 * misclocking */ 1996 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); 1997 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 1998 WM8904_CLK_SYS_ENA, 0); 1999 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2000 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); 2001 2002 /* Unlock forced oscilator control to switch it on/off */ 2003 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2004 WM8904_USER_KEY, WM8904_USER_KEY); 2005 2006 if (fll_id == WM8904_FLL_FREE_RUNNING) { 2007 val = WM8904_FLL_FRC_NCO; 2008 } else { 2009 val = 0; 2010 } 2011 2012 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, 2013 val); 2014 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, 2015 WM8904_USER_KEY, 0); 2016 2017 switch (fll_id) { 2018 case WM8904_FLL_MCLK: 2019 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2020 WM8904_FLL_CLK_REF_SRC_MASK, 0); 2021 break; 2022 2023 case WM8904_FLL_LRCLK: 2024 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2025 WM8904_FLL_CLK_REF_SRC_MASK, 1); 2026 break; 2027 2028 case WM8904_FLL_BCLK: 2029 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2030 WM8904_FLL_CLK_REF_SRC_MASK, 2); 2031 break; 2032 } 2033 2034 if (fll_div.k) 2035 val = WM8904_FLL_FRACN_ENA; 2036 else 2037 val = 0; 2038 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2039 WM8904_FLL_FRACN_ENA, val); 2040 2041 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, 2042 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, 2043 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | 2044 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); 2045 2046 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); 2047 2048 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, 2049 fll_div.n << WM8904_FLL_N_SHIFT); 2050 2051 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, 2052 WM8904_FLL_CLK_REF_DIV_MASK, 2053 fll_div.fll_clk_ref_div 2054 << WM8904_FLL_CLK_REF_DIV_SHIFT); 2055 2056 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2057 2058 wm8904->fll_fref = Fref; 2059 wm8904->fll_fout = Fout; 2060 wm8904->fll_src = source; 2061 2062 /* Enable the FLL if it was previously active */ 2063 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2064 WM8904_FLL_OSC_ENA, fll1); 2065 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, 2066 WM8904_FLL_ENA, fll1); 2067 2068 out: 2069 /* Reenable SYSCLK if it was previously active */ 2070 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, 2071 WM8904_CLK_SYS_ENA, clock2); 2072 2073 return 0; 2074 } 2075 2076 static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) 2077 { 2078 struct snd_soc_codec *codec = codec_dai->codec; 2079 int val; 2080 2081 if (mute) 2082 val = WM8904_DAC_MUTE; 2083 else 2084 val = 0; 2085 2086 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); 2087 2088 return 0; 2089 } 2090 2091 static void wm8904_sync_cache(struct snd_soc_codec *codec) 2092 { 2093 u16 *reg_cache = codec->reg_cache; 2094 int i; 2095 2096 if (!codec->cache_sync) 2097 return; 2098 2099 codec->cache_only = 0; 2100 2101 /* Sync back cached values if they're different from the 2102 * hardware default. 2103 */ 2104 for (i = 1; i < codec->driver->reg_cache_size; i++) { 2105 if (!wm8904_access[i].writable) 2106 continue; 2107 2108 if (reg_cache[i] == wm8904_reg[i]) 2109 continue; 2110 2111 snd_soc_write(codec, i, reg_cache[i]); 2112 } 2113 2114 codec->cache_sync = 0; 2115 } 2116 2117 static int wm8904_set_bias_level(struct snd_soc_codec *codec, 2118 enum snd_soc_bias_level level) 2119 { 2120 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2121 int ret; 2122 2123 switch (level) { 2124 case SND_SOC_BIAS_ON: 2125 break; 2126 2127 case SND_SOC_BIAS_PREPARE: 2128 /* VMID resistance 2*50k */ 2129 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2130 WM8904_VMID_RES_MASK, 2131 0x1 << WM8904_VMID_RES_SHIFT); 2132 2133 /* Normal bias current */ 2134 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2135 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); 2136 break; 2137 2138 case SND_SOC_BIAS_STANDBY: 2139 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 2140 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2141 wm8904->supplies); 2142 if (ret != 0) { 2143 dev_err(codec->dev, 2144 "Failed to enable supplies: %d\n", 2145 ret); 2146 return ret; 2147 } 2148 2149 wm8904_sync_cache(codec); 2150 2151 /* Enable bias */ 2152 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2153 WM8904_BIAS_ENA, WM8904_BIAS_ENA); 2154 2155 /* Enable VMID, VMID buffering, 2*5k resistance */ 2156 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2157 WM8904_VMID_ENA | 2158 WM8904_VMID_RES_MASK, 2159 WM8904_VMID_ENA | 2160 0x3 << WM8904_VMID_RES_SHIFT); 2161 2162 /* Let VMID ramp */ 2163 msleep(1); 2164 } 2165 2166 /* Maintain VMID with 2*250k */ 2167 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2168 WM8904_VMID_RES_MASK, 2169 0x2 << WM8904_VMID_RES_SHIFT); 2170 2171 /* Bias current *0.5 */ 2172 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2173 WM8904_ISEL_MASK, 0); 2174 break; 2175 2176 case SND_SOC_BIAS_OFF: 2177 /* Turn off VMID */ 2178 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, 2179 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); 2180 2181 /* Stop bias generation */ 2182 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2183 WM8904_BIAS_ENA, 0); 2184 2185 #ifdef CONFIG_REGULATOR 2186 /* Post 2.6.34 we will be able to get a callback when 2187 * the regulators are disabled which we can use but 2188 * for now just assume that the power will be cut if 2189 * the regulator API is in use. 2190 */ 2191 codec->cache_sync = 1; 2192 #endif 2193 2194 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), 2195 wm8904->supplies); 2196 break; 2197 } 2198 codec->dapm.bias_level = level; 2199 return 0; 2200 } 2201 2202 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 2203 2204 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2205 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2206 2207 static const struct snd_soc_dai_ops wm8904_dai_ops = { 2208 .set_sysclk = wm8904_set_sysclk, 2209 .set_fmt = wm8904_set_fmt, 2210 .set_tdm_slot = wm8904_set_tdm_slot, 2211 .set_pll = wm8904_set_fll, 2212 .hw_params = wm8904_hw_params, 2213 .digital_mute = wm8904_digital_mute, 2214 }; 2215 2216 static struct snd_soc_dai_driver wm8904_dai = { 2217 .name = "wm8904-hifi", 2218 .playback = { 2219 .stream_name = "Playback", 2220 .channels_min = 2, 2221 .channels_max = 2, 2222 .rates = WM8904_RATES, 2223 .formats = WM8904_FORMATS, 2224 }, 2225 .capture = { 2226 .stream_name = "Capture", 2227 .channels_min = 2, 2228 .channels_max = 2, 2229 .rates = WM8904_RATES, 2230 .formats = WM8904_FORMATS, 2231 }, 2232 .ops = &wm8904_dai_ops, 2233 .symmetric_rates = 1, 2234 }; 2235 2236 #ifdef CONFIG_PM 2237 static int wm8904_suspend(struct snd_soc_codec *codec) 2238 { 2239 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); 2240 2241 return 0; 2242 } 2243 2244 static int wm8904_resume(struct snd_soc_codec *codec) 2245 { 2246 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2247 2248 return 0; 2249 } 2250 #else 2251 #define wm8904_suspend NULL 2252 #define wm8904_resume NULL 2253 #endif 2254 2255 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec) 2256 { 2257 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2258 struct wm8904_pdata *pdata = wm8904->pdata; 2259 struct snd_kcontrol_new control = 2260 SOC_ENUM_EXT("EQ Mode", 2261 wm8904->retune_mobile_enum, 2262 wm8904_get_retune_mobile_enum, 2263 wm8904_put_retune_mobile_enum); 2264 int ret, i, j; 2265 const char **t; 2266 2267 /* We need an array of texts for the enum API but the number 2268 * of texts is likely to be less than the number of 2269 * configurations due to the sample rate dependency of the 2270 * configurations. */ 2271 wm8904->num_retune_mobile_texts = 0; 2272 wm8904->retune_mobile_texts = NULL; 2273 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2274 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { 2275 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2276 wm8904->retune_mobile_texts[j]) == 0) 2277 break; 2278 } 2279 2280 if (j != wm8904->num_retune_mobile_texts) 2281 continue; 2282 2283 /* Expand the array... */ 2284 t = krealloc(wm8904->retune_mobile_texts, 2285 sizeof(char *) * 2286 (wm8904->num_retune_mobile_texts + 1), 2287 GFP_KERNEL); 2288 if (t == NULL) 2289 continue; 2290 2291 /* ...store the new entry... */ 2292 t[wm8904->num_retune_mobile_texts] = 2293 pdata->retune_mobile_cfgs[i].name; 2294 2295 /* ...and remember the new version. */ 2296 wm8904->num_retune_mobile_texts++; 2297 wm8904->retune_mobile_texts = t; 2298 } 2299 2300 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2301 wm8904->num_retune_mobile_texts); 2302 2303 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; 2304 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; 2305 2306 ret = snd_soc_add_controls(codec, &control, 1); 2307 if (ret != 0) 2308 dev_err(codec->dev, 2309 "Failed to add ReTune Mobile control: %d\n", ret); 2310 } 2311 2312 static void wm8904_handle_pdata(struct snd_soc_codec *codec) 2313 { 2314 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2315 struct wm8904_pdata *pdata = wm8904->pdata; 2316 int ret, i; 2317 2318 if (!pdata) { 2319 snd_soc_add_controls(codec, wm8904_eq_controls, 2320 ARRAY_SIZE(wm8904_eq_controls)); 2321 return; 2322 } 2323 2324 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); 2325 2326 if (pdata->num_drc_cfgs) { 2327 struct snd_kcontrol_new control = 2328 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, 2329 wm8904_get_drc_enum, wm8904_put_drc_enum); 2330 2331 /* We need an array of texts for the enum API */ 2332 wm8904->drc_texts = kmalloc(sizeof(char *) 2333 * pdata->num_drc_cfgs, GFP_KERNEL); 2334 if (!wm8904->drc_texts) { 2335 dev_err(codec->dev, 2336 "Failed to allocate %d DRC config texts\n", 2337 pdata->num_drc_cfgs); 2338 return; 2339 } 2340 2341 for (i = 0; i < pdata->num_drc_cfgs; i++) 2342 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; 2343 2344 wm8904->drc_enum.max = pdata->num_drc_cfgs; 2345 wm8904->drc_enum.texts = wm8904->drc_texts; 2346 2347 ret = snd_soc_add_controls(codec, &control, 1); 2348 if (ret != 0) 2349 dev_err(codec->dev, 2350 "Failed to add DRC mode control: %d\n", ret); 2351 2352 wm8904_set_drc(codec); 2353 } 2354 2355 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2356 pdata->num_retune_mobile_cfgs); 2357 2358 if (pdata->num_retune_mobile_cfgs) 2359 wm8904_handle_retune_mobile_pdata(codec); 2360 else 2361 snd_soc_add_controls(codec, wm8904_eq_controls, 2362 ARRAY_SIZE(wm8904_eq_controls)); 2363 } 2364 2365 2366 static int wm8904_probe(struct snd_soc_codec *codec) 2367 { 2368 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2369 struct wm8904_pdata *pdata = wm8904->pdata; 2370 u16 *reg_cache = codec->reg_cache; 2371 int ret, i; 2372 2373 codec->cache_sync = 1; 2374 codec->dapm.idle_bias_off = 1; 2375 2376 switch (wm8904->devtype) { 2377 case WM8904: 2378 break; 2379 case WM8912: 2380 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); 2381 break; 2382 default: 2383 dev_err(codec->dev, "Unknown device type %d\n", 2384 wm8904->devtype); 2385 return -EINVAL; 2386 } 2387 2388 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 2389 if (ret != 0) { 2390 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2391 return ret; 2392 } 2393 2394 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) 2395 wm8904->supplies[i].supply = wm8904_supply_names[i]; 2396 2397 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), 2398 wm8904->supplies); 2399 if (ret != 0) { 2400 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2401 return ret; 2402 } 2403 2404 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2405 wm8904->supplies); 2406 if (ret != 0) { 2407 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2408 goto err_get; 2409 } 2410 2411 ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID); 2412 if (ret < 0) { 2413 dev_err(codec->dev, "Failed to read ID register\n"); 2414 goto err_enable; 2415 } 2416 if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) { 2417 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); 2418 ret = -EINVAL; 2419 goto err_enable; 2420 } 2421 2422 ret = snd_soc_read(codec, WM8904_REVISION); 2423 if (ret < 0) { 2424 dev_err(codec->dev, "Failed to read device revision: %d\n", 2425 ret); 2426 goto err_enable; 2427 } 2428 dev_info(codec->dev, "revision %c\n", ret + 'A'); 2429 2430 ret = wm8904_reset(codec); 2431 if (ret < 0) { 2432 dev_err(codec->dev, "Failed to issue reset\n"); 2433 goto err_enable; 2434 } 2435 2436 /* Change some default settings - latch VU and enable ZC */ 2437 snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_LEFT, 2438 WM8904_ADC_VU, WM8904_ADC_VU); 2439 snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_RIGHT, 2440 WM8904_ADC_VU, WM8904_ADC_VU); 2441 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_LEFT, 2442 WM8904_DAC_VU, WM8904_DAC_VU); 2443 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_RIGHT, 2444 WM8904_DAC_VU, WM8904_DAC_VU); 2445 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_LEFT, 2446 WM8904_HPOUT_VU | WM8904_HPOUTLZC, 2447 WM8904_HPOUT_VU | WM8904_HPOUTLZC); 2448 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_RIGHT, 2449 WM8904_HPOUT_VU | WM8904_HPOUTRZC, 2450 WM8904_HPOUT_VU | WM8904_HPOUTRZC); 2451 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_LEFT, 2452 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC, 2453 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC); 2454 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_RIGHT, 2455 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC, 2456 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC); 2457 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, 2458 WM8904_SR_MODE, 0); 2459 2460 /* Apply configuration from the platform data. */ 2461 if (wm8904->pdata) { 2462 for (i = 0; i < WM8904_GPIO_REGS; i++) { 2463 if (!pdata->gpio_cfg[i]) 2464 continue; 2465 2466 reg_cache[WM8904_GPIO_CONTROL_1 + i] 2467 = pdata->gpio_cfg[i] & 0xffff; 2468 } 2469 2470 /* Zero is the default value for these anyway */ 2471 for (i = 0; i < WM8904_MIC_REGS; i++) 2472 reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i] 2473 = pdata->mic_cfg[i]; 2474 } 2475 2476 /* Set Class W by default - this will be managed by the Class 2477 * G widget at runtime where bypass paths are available. 2478 */ 2479 snd_soc_update_bits(codec, WM8904_CLASS_W_0, 2480 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR); 2481 2482 /* Use normal bias source */ 2483 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, 2484 WM8904_POBCTRL, 0); 2485 2486 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2487 2488 /* Bias level configuration will have done an extra enable */ 2489 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2490 2491 wm8904_handle_pdata(codec); 2492 2493 wm8904_add_widgets(codec); 2494 2495 return 0; 2496 2497 err_enable: 2498 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2499 err_get: 2500 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2501 return ret; 2502 } 2503 2504 static int wm8904_remove(struct snd_soc_codec *codec) 2505 { 2506 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 2507 2508 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); 2509 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); 2510 kfree(wm8904->retune_mobile_texts); 2511 kfree(wm8904->drc_texts); 2512 2513 return 0; 2514 } 2515 2516 static struct snd_soc_codec_driver soc_codec_dev_wm8904 = { 2517 .probe = wm8904_probe, 2518 .remove = wm8904_remove, 2519 .suspend = wm8904_suspend, 2520 .resume = wm8904_resume, 2521 .set_bias_level = wm8904_set_bias_level, 2522 .reg_cache_size = ARRAY_SIZE(wm8904_reg), 2523 .reg_word_size = sizeof(u16), 2524 .reg_cache_default = wm8904_reg, 2525 .volatile_register = wm8904_volatile_register, 2526 }; 2527 2528 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2529 static __devinit int wm8904_i2c_probe(struct i2c_client *i2c, 2530 const struct i2c_device_id *id) 2531 { 2532 struct wm8904_priv *wm8904; 2533 int ret; 2534 2535 wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL); 2536 if (wm8904 == NULL) 2537 return -ENOMEM; 2538 2539 wm8904->devtype = id->driver_data; 2540 i2c_set_clientdata(i2c, wm8904); 2541 wm8904->pdata = i2c->dev.platform_data; 2542 2543 ret = snd_soc_register_codec(&i2c->dev, 2544 &soc_codec_dev_wm8904, &wm8904_dai, 1); 2545 if (ret < 0) 2546 kfree(wm8904); 2547 return ret; 2548 } 2549 2550 static __devexit int wm8904_i2c_remove(struct i2c_client *client) 2551 { 2552 snd_soc_unregister_codec(&client->dev); 2553 kfree(i2c_get_clientdata(client)); 2554 return 0; 2555 } 2556 2557 static const struct i2c_device_id wm8904_i2c_id[] = { 2558 { "wm8904", WM8904 }, 2559 { "wm8912", WM8912 }, 2560 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */ 2561 { } 2562 }; 2563 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); 2564 2565 static struct i2c_driver wm8904_i2c_driver = { 2566 .driver = { 2567 .name = "wm8904", 2568 .owner = THIS_MODULE, 2569 }, 2570 .probe = wm8904_i2c_probe, 2571 .remove = __devexit_p(wm8904_i2c_remove), 2572 .id_table = wm8904_i2c_id, 2573 }; 2574 #endif 2575 2576 static int __init wm8904_modinit(void) 2577 { 2578 int ret = 0; 2579 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2580 ret = i2c_add_driver(&wm8904_i2c_driver); 2581 if (ret != 0) { 2582 printk(KERN_ERR "Failed to register wm8904 I2C driver: %d\n", 2583 ret); 2584 } 2585 #endif 2586 return ret; 2587 } 2588 module_init(wm8904_modinit); 2589 2590 static void __exit wm8904_exit(void) 2591 { 2592 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 2593 i2c_del_driver(&wm8904_i2c_driver); 2594 #endif 2595 } 2596 module_exit(wm8904_exit); 2597 2598 MODULE_DESCRIPTION("ASoC WM8904 driver"); 2599 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2600 MODULE_LICENSE("GPL"); 2601