1*f1c0a02fSMark Brown /* 2*f1c0a02fSMark Brown * wm8903.h - WM8903 audio codec interface 3*f1c0a02fSMark Brown * 4*f1c0a02fSMark Brown * Copyright 2008 Wolfson Microelectronics PLC. 5*f1c0a02fSMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6*f1c0a02fSMark Brown * 7*f1c0a02fSMark Brown * This program is free software; you can redistribute it and/or modify it 8*f1c0a02fSMark Brown * under the terms of the GNU General Public License as published by the 9*f1c0a02fSMark Brown * Free Software Foundation; either version 2 of the License, or (at your 10*f1c0a02fSMark Brown * option) any later version. 11*f1c0a02fSMark Brown */ 12*f1c0a02fSMark Brown 13*f1c0a02fSMark Brown #ifndef _WM8903_H 14*f1c0a02fSMark Brown #define _WM8903_H 15*f1c0a02fSMark Brown 16*f1c0a02fSMark Brown #include <linux/i2c.h> 17*f1c0a02fSMark Brown 18*f1c0a02fSMark Brown extern struct snd_soc_dai wm8903_dai; 19*f1c0a02fSMark Brown extern struct snd_soc_codec_device soc_codec_dev_wm8903; 20*f1c0a02fSMark Brown 21*f1c0a02fSMark Brown struct wm8903_setup_data { 22*f1c0a02fSMark Brown int i2c_bus; 23*f1c0a02fSMark Brown int i2c_address; 24*f1c0a02fSMark Brown }; 25*f1c0a02fSMark Brown 26*f1c0a02fSMark Brown #define WM8903_MCLK_DIV_2 1 27*f1c0a02fSMark Brown #define WM8903_CLK_SYS 2 28*f1c0a02fSMark Brown #define WM8903_BCLK 3 29*f1c0a02fSMark Brown #define WM8903_LRCLK 4 30*f1c0a02fSMark Brown 31*f1c0a02fSMark Brown /* 32*f1c0a02fSMark Brown * Register values. 33*f1c0a02fSMark Brown */ 34*f1c0a02fSMark Brown #define WM8903_SW_RESET_AND_ID 0x00 35*f1c0a02fSMark Brown #define WM8903_REVISION_NUMBER 0x01 36*f1c0a02fSMark Brown #define WM8903_BIAS_CONTROL_0 0x04 37*f1c0a02fSMark Brown #define WM8903_VMID_CONTROL_0 0x05 38*f1c0a02fSMark Brown #define WM8903_MIC_BIAS_CONTROL_0 0x06 39*f1c0a02fSMark Brown #define WM8903_ANALOGUE_DAC_0 0x08 40*f1c0a02fSMark Brown #define WM8903_ANALOGUE_ADC_0 0x0A 41*f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_0 0x0C 42*f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_1 0x0D 43*f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_2 0x0E 44*f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_3 0x0F 45*f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_4 0x10 46*f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_5 0x11 47*f1c0a02fSMark Brown #define WM8903_POWER_MANAGEMENT_6 0x12 48*f1c0a02fSMark Brown #define WM8903_CLOCK_RATES_0 0x14 49*f1c0a02fSMark Brown #define WM8903_CLOCK_RATES_1 0x15 50*f1c0a02fSMark Brown #define WM8903_CLOCK_RATES_2 0x16 51*f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_0 0x18 52*f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_1 0x19 53*f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_2 0x1A 54*f1c0a02fSMark Brown #define WM8903_AUDIO_INTERFACE_3 0x1B 55*f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_VOLUME_LEFT 0x1E 56*f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_VOLUME_RIGHT 0x1F 57*f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_0 0x20 58*f1c0a02fSMark Brown #define WM8903_DAC_DIGITAL_1 0x21 59*f1c0a02fSMark Brown #define WM8903_ADC_DIGITAL_VOLUME_LEFT 0x24 60*f1c0a02fSMark Brown #define WM8903_ADC_DIGITAL_VOLUME_RIGHT 0x25 61*f1c0a02fSMark Brown #define WM8903_ADC_DIGITAL_0 0x26 62*f1c0a02fSMark Brown #define WM8903_DIGITAL_MICROPHONE_0 0x27 63*f1c0a02fSMark Brown #define WM8903_DRC_0 0x28 64*f1c0a02fSMark Brown #define WM8903_DRC_1 0x29 65*f1c0a02fSMark Brown #define WM8903_DRC_2 0x2A 66*f1c0a02fSMark Brown #define WM8903_DRC_3 0x2B 67*f1c0a02fSMark Brown #define WM8903_ANALOGUE_LEFT_INPUT_0 0x2C 68*f1c0a02fSMark Brown #define WM8903_ANALOGUE_RIGHT_INPUT_0 0x2D 69*f1c0a02fSMark Brown #define WM8903_ANALOGUE_LEFT_INPUT_1 0x2E 70*f1c0a02fSMark Brown #define WM8903_ANALOGUE_RIGHT_INPUT_1 0x2F 71*f1c0a02fSMark Brown #define WM8903_ANALOGUE_LEFT_MIX_0 0x32 72*f1c0a02fSMark Brown #define WM8903_ANALOGUE_RIGHT_MIX_0 0x33 73*f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_LEFT_0 0x34 74*f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_LEFT_1 0x35 75*f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_RIGHT_0 0x36 76*f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_MIX_RIGHT_1 0x37 77*f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT1_LEFT 0x39 78*f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT1_RIGHT 0x3A 79*f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT2_LEFT 0x3B 80*f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT2_RIGHT 0x3C 81*f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT3_LEFT 0x3E 82*f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUT3_RIGHT 0x3F 83*f1c0a02fSMark Brown #define WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0 0x41 84*f1c0a02fSMark Brown #define WM8903_DC_SERVO_0 0x43 85*f1c0a02fSMark Brown #define WM8903_DC_SERVO_2 0x45 86*f1c0a02fSMark Brown #define WM8903_ANALOGUE_HP_0 0x5A 87*f1c0a02fSMark Brown #define WM8903_ANALOGUE_LINEOUT_0 0x5E 88*f1c0a02fSMark Brown #define WM8903_CHARGE_PUMP_0 0x62 89*f1c0a02fSMark Brown #define WM8903_CLASS_W_0 0x68 90*f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_0 0x6C 91*f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_1 0x6D 92*f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_2 0x6E 93*f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_3 0x6F 94*f1c0a02fSMark Brown #define WM8903_WRITE_SEQUENCER_4 0x70 95*f1c0a02fSMark Brown #define WM8903_CONTROL_INTERFACE 0x72 96*f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_1 0x74 97*f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_2 0x75 98*f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_3 0x76 99*f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_4 0x77 100*f1c0a02fSMark Brown #define WM8903_GPIO_CONTROL_5 0x78 101*f1c0a02fSMark Brown #define WM8903_INTERRUPT_STATUS_1 0x79 102*f1c0a02fSMark Brown #define WM8903_INTERRUPT_STATUS_1_MASK 0x7A 103*f1c0a02fSMark Brown #define WM8903_INTERRUPT_POLARITY_1 0x7B 104*f1c0a02fSMark Brown #define WM8903_INTERRUPT_CONTROL 0x7E 105*f1c0a02fSMark Brown #define WM8903_CONTROL_INTERFACE_TEST_1 0x81 106*f1c0a02fSMark Brown #define WM8903_CHARGE_PUMP_TEST_1 0x95 107*f1c0a02fSMark Brown #define WM8903_CLOCK_RATE_TEST_4 0xA4 108*f1c0a02fSMark Brown #define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC 109*f1c0a02fSMark Brown 110*f1c0a02fSMark Brown #define WM8903_REGISTER_COUNT 75 111*f1c0a02fSMark Brown #define WM8903_MAX_REGISTER 0xAC 112*f1c0a02fSMark Brown 113*f1c0a02fSMark Brown /* 114*f1c0a02fSMark Brown * Field Definitions. 115*f1c0a02fSMark Brown */ 116*f1c0a02fSMark Brown 117*f1c0a02fSMark Brown /* 118*f1c0a02fSMark Brown * R0 (0x00) - SW Reset and ID 119*f1c0a02fSMark Brown */ 120*f1c0a02fSMark Brown #define WM8903_SW_RESET_DEV_ID1_MASK 0xFFFF /* SW_RESET_DEV_ID1 - [15:0] */ 121*f1c0a02fSMark Brown #define WM8903_SW_RESET_DEV_ID1_SHIFT 0 /* SW_RESET_DEV_ID1 - [15:0] */ 122*f1c0a02fSMark Brown #define WM8903_SW_RESET_DEV_ID1_WIDTH 16 /* SW_RESET_DEV_ID1 - [15:0] */ 123*f1c0a02fSMark Brown 124*f1c0a02fSMark Brown /* 125*f1c0a02fSMark Brown * R1 (0x01) - Revision Number 126*f1c0a02fSMark Brown */ 127*f1c0a02fSMark Brown #define WM8903_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 128*f1c0a02fSMark Brown #define WM8903_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 129*f1c0a02fSMark Brown #define WM8903_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 130*f1c0a02fSMark Brown 131*f1c0a02fSMark Brown /* 132*f1c0a02fSMark Brown * R4 (0x04) - Bias Control 0 133*f1c0a02fSMark Brown */ 134*f1c0a02fSMark Brown #define WM8903_POBCTRL 0x0010 /* POBCTRL */ 135*f1c0a02fSMark Brown #define WM8903_POBCTRL_MASK 0x0010 /* POBCTRL */ 136*f1c0a02fSMark Brown #define WM8903_POBCTRL_SHIFT 4 /* POBCTRL */ 137*f1c0a02fSMark Brown #define WM8903_POBCTRL_WIDTH 1 /* POBCTRL */ 138*f1c0a02fSMark Brown #define WM8903_ISEL_MASK 0x000C /* ISEL - [3:2] */ 139*f1c0a02fSMark Brown #define WM8903_ISEL_SHIFT 2 /* ISEL - [3:2] */ 140*f1c0a02fSMark Brown #define WM8903_ISEL_WIDTH 2 /* ISEL - [3:2] */ 141*f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */ 142*f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */ 143*f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */ 144*f1c0a02fSMark Brown #define WM8903_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 145*f1c0a02fSMark Brown #define WM8903_BIAS_ENA 0x0001 /* BIAS_ENA */ 146*f1c0a02fSMark Brown #define WM8903_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 147*f1c0a02fSMark Brown #define WM8903_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 148*f1c0a02fSMark Brown #define WM8903_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 149*f1c0a02fSMark Brown 150*f1c0a02fSMark Brown /* 151*f1c0a02fSMark Brown * R5 (0x05) - VMID Control 0 152*f1c0a02fSMark Brown */ 153*f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA 0x0080 /* VMID_TIE_ENA */ 154*f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA_MASK 0x0080 /* VMID_TIE_ENA */ 155*f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA_SHIFT 7 /* VMID_TIE_ENA */ 156*f1c0a02fSMark Brown #define WM8903_VMID_TIE_ENA_WIDTH 1 /* VMID_TIE_ENA */ 157*f1c0a02fSMark Brown #define WM8903_BUFIO_ENA 0x0040 /* BUFIO_ENA */ 158*f1c0a02fSMark Brown #define WM8903_BUFIO_ENA_MASK 0x0040 /* BUFIO_ENA */ 159*f1c0a02fSMark Brown #define WM8903_BUFIO_ENA_SHIFT 6 /* BUFIO_ENA */ 160*f1c0a02fSMark Brown #define WM8903_BUFIO_ENA_WIDTH 1 /* BUFIO_ENA */ 161*f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA 0x0020 /* VMID_IO_ENA */ 162*f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA_MASK 0x0020 /* VMID_IO_ENA */ 163*f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA_SHIFT 5 /* VMID_IO_ENA */ 164*f1c0a02fSMark Brown #define WM8903_VMID_IO_ENA_WIDTH 1 /* VMID_IO_ENA */ 165*f1c0a02fSMark Brown #define WM8903_VMID_SOFT_MASK 0x0018 /* VMID_SOFT - [4:3] */ 166*f1c0a02fSMark Brown #define WM8903_VMID_SOFT_SHIFT 3 /* VMID_SOFT - [4:3] */ 167*f1c0a02fSMark Brown #define WM8903_VMID_SOFT_WIDTH 2 /* VMID_SOFT - [4:3] */ 168*f1c0a02fSMark Brown #define WM8903_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */ 169*f1c0a02fSMark Brown #define WM8903_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */ 170*f1c0a02fSMark Brown #define WM8903_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */ 171*f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA 0x0001 /* VMID_BUF_ENA */ 172*f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA_MASK 0x0001 /* VMID_BUF_ENA */ 173*f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA_SHIFT 0 /* VMID_BUF_ENA */ 174*f1c0a02fSMark Brown #define WM8903_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 175*f1c0a02fSMark Brown 176*f1c0a02fSMark Brown #define WM8903_VMID_RES_50K 2 177*f1c0a02fSMark Brown #define WM8903_VMID_RES_250K 3 178*f1c0a02fSMark Brown #define WM8903_VMID_RES_5K 4 179*f1c0a02fSMark Brown 180*f1c0a02fSMark Brown /* 181*f1c0a02fSMark Brown * R6 (0x06) - Mic Bias Control 0 182*f1c0a02fSMark Brown */ 183*f1c0a02fSMark Brown #define WM8903_MICDET_HYST_ENA 0x0080 /* MICDET_HYST_ENA */ 184*f1c0a02fSMark Brown #define WM8903_MICDET_HYST_ENA_MASK 0x0080 /* MICDET_HYST_ENA */ 185*f1c0a02fSMark Brown #define WM8903_MICDET_HYST_ENA_SHIFT 7 /* MICDET_HYST_ENA */ 186*f1c0a02fSMark Brown #define WM8903_MICDET_HYST_ENA_WIDTH 1 /* MICDET_HYST_ENA */ 187*f1c0a02fSMark Brown #define WM8903_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */ 188*f1c0a02fSMark Brown #define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */ 189*f1c0a02fSMark Brown #define WM8903_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */ 190*f1c0a02fSMark Brown #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ 191*f1c0a02fSMark Brown #define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ 192*f1c0a02fSMark Brown #define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ 193*f1c0a02fSMark Brown #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ 194*f1c0a02fSMark Brown #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ 195*f1c0a02fSMark Brown #define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ 196*f1c0a02fSMark Brown #define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ 197*f1c0a02fSMark Brown #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ 198*f1c0a02fSMark Brown #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ 199*f1c0a02fSMark Brown #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ 200*f1c0a02fSMark Brown #define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ 201*f1c0a02fSMark Brown 202*f1c0a02fSMark Brown /* 203*f1c0a02fSMark Brown * R8 (0x08) - Analogue DAC 0 204*f1c0a02fSMark Brown */ 205*f1c0a02fSMark Brown #define WM8903_DACBIAS_SEL_MASK 0x0018 /* DACBIAS_SEL - [4:3] */ 206*f1c0a02fSMark Brown #define WM8903_DACBIAS_SEL_SHIFT 3 /* DACBIAS_SEL - [4:3] */ 207*f1c0a02fSMark Brown #define WM8903_DACBIAS_SEL_WIDTH 2 /* DACBIAS_SEL - [4:3] */ 208*f1c0a02fSMark Brown #define WM8903_DACVMID_BIAS_SEL_MASK 0x0006 /* DACVMID_BIAS_SEL - [2:1] */ 209*f1c0a02fSMark Brown #define WM8903_DACVMID_BIAS_SEL_SHIFT 1 /* DACVMID_BIAS_SEL - [2:1] */ 210*f1c0a02fSMark Brown #define WM8903_DACVMID_BIAS_SEL_WIDTH 2 /* DACVMID_BIAS_SEL - [2:1] */ 211*f1c0a02fSMark Brown 212*f1c0a02fSMark Brown /* 213*f1c0a02fSMark Brown * R10 (0x0A) - Analogue ADC 0 214*f1c0a02fSMark Brown */ 215*f1c0a02fSMark Brown #define WM8903_ADC_OSR128 0x0001 /* ADC_OSR128 */ 216*f1c0a02fSMark Brown #define WM8903_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */ 217*f1c0a02fSMark Brown #define WM8903_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */ 218*f1c0a02fSMark Brown #define WM8903_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 219*f1c0a02fSMark Brown 220*f1c0a02fSMark Brown /* 221*f1c0a02fSMark Brown * R12 (0x0C) - Power Management 0 222*f1c0a02fSMark Brown */ 223*f1c0a02fSMark Brown #define WM8903_INL_ENA 0x0002 /* INL_ENA */ 224*f1c0a02fSMark Brown #define WM8903_INL_ENA_MASK 0x0002 /* INL_ENA */ 225*f1c0a02fSMark Brown #define WM8903_INL_ENA_SHIFT 1 /* INL_ENA */ 226*f1c0a02fSMark Brown #define WM8903_INL_ENA_WIDTH 1 /* INL_ENA */ 227*f1c0a02fSMark Brown #define WM8903_INR_ENA 0x0001 /* INR_ENA */ 228*f1c0a02fSMark Brown #define WM8903_INR_ENA_MASK 0x0001 /* INR_ENA */ 229*f1c0a02fSMark Brown #define WM8903_INR_ENA_SHIFT 0 /* INR_ENA */ 230*f1c0a02fSMark Brown #define WM8903_INR_ENA_WIDTH 1 /* INR_ENA */ 231*f1c0a02fSMark Brown 232*f1c0a02fSMark Brown /* 233*f1c0a02fSMark Brown * R13 (0x0D) - Power Management 1 234*f1c0a02fSMark Brown */ 235*f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA 0x0002 /* MIXOUTL_ENA */ 236*f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA_MASK 0x0002 /* MIXOUTL_ENA */ 237*f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA_SHIFT 1 /* MIXOUTL_ENA */ 238*f1c0a02fSMark Brown #define WM8903_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */ 239*f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA 0x0001 /* MIXOUTR_ENA */ 240*f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA_MASK 0x0001 /* MIXOUTR_ENA */ 241*f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA_SHIFT 0 /* MIXOUTR_ENA */ 242*f1c0a02fSMark Brown #define WM8903_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */ 243*f1c0a02fSMark Brown 244*f1c0a02fSMark Brown /* 245*f1c0a02fSMark Brown * R14 (0x0E) - Power Management 2 246*f1c0a02fSMark Brown */ 247*f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */ 248*f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */ 249*f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */ 250*f1c0a02fSMark Brown #define WM8903_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */ 251*f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */ 252*f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */ 253*f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */ 254*f1c0a02fSMark Brown #define WM8903_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */ 255*f1c0a02fSMark Brown 256*f1c0a02fSMark Brown /* 257*f1c0a02fSMark Brown * R15 (0x0F) - Power Management 3 258*f1c0a02fSMark Brown */ 259*f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */ 260*f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */ 261*f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */ 262*f1c0a02fSMark Brown #define WM8903_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */ 263*f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */ 264*f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */ 265*f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */ 266*f1c0a02fSMark Brown #define WM8903_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */ 267*f1c0a02fSMark Brown 268*f1c0a02fSMark Brown /* 269*f1c0a02fSMark Brown * R16 (0x10) - Power Management 4 270*f1c0a02fSMark Brown */ 271*f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA 0x0002 /* MIXSPKL_ENA */ 272*f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA_MASK 0x0002 /* MIXSPKL_ENA */ 273*f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA_SHIFT 1 /* MIXSPKL_ENA */ 274*f1c0a02fSMark Brown #define WM8903_MIXSPKL_ENA_WIDTH 1 /* MIXSPKL_ENA */ 275*f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA 0x0001 /* MIXSPKR_ENA */ 276*f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA_MASK 0x0001 /* MIXSPKR_ENA */ 277*f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA_SHIFT 0 /* MIXSPKR_ENA */ 278*f1c0a02fSMark Brown #define WM8903_MIXSPKR_ENA_WIDTH 1 /* MIXSPKR_ENA */ 279*f1c0a02fSMark Brown 280*f1c0a02fSMark Brown /* 281*f1c0a02fSMark Brown * R17 (0x11) - Power Management 5 282*f1c0a02fSMark Brown */ 283*f1c0a02fSMark Brown #define WM8903_SPKL_ENA 0x0002 /* SPKL_ENA */ 284*f1c0a02fSMark Brown #define WM8903_SPKL_ENA_MASK 0x0002 /* SPKL_ENA */ 285*f1c0a02fSMark Brown #define WM8903_SPKL_ENA_SHIFT 1 /* SPKL_ENA */ 286*f1c0a02fSMark Brown #define WM8903_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 287*f1c0a02fSMark Brown #define WM8903_SPKR_ENA 0x0001 /* SPKR_ENA */ 288*f1c0a02fSMark Brown #define WM8903_SPKR_ENA_MASK 0x0001 /* SPKR_ENA */ 289*f1c0a02fSMark Brown #define WM8903_SPKR_ENA_SHIFT 0 /* SPKR_ENA */ 290*f1c0a02fSMark Brown #define WM8903_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 291*f1c0a02fSMark Brown 292*f1c0a02fSMark Brown /* 293*f1c0a02fSMark Brown * R18 (0x12) - Power Management 6 294*f1c0a02fSMark Brown */ 295*f1c0a02fSMark Brown #define WM8903_DACL_ENA 0x0008 /* DACL_ENA */ 296*f1c0a02fSMark Brown #define WM8903_DACL_ENA_MASK 0x0008 /* DACL_ENA */ 297*f1c0a02fSMark Brown #define WM8903_DACL_ENA_SHIFT 3 /* DACL_ENA */ 298*f1c0a02fSMark Brown #define WM8903_DACL_ENA_WIDTH 1 /* DACL_ENA */ 299*f1c0a02fSMark Brown #define WM8903_DACR_ENA 0x0004 /* DACR_ENA */ 300*f1c0a02fSMark Brown #define WM8903_DACR_ENA_MASK 0x0004 /* DACR_ENA */ 301*f1c0a02fSMark Brown #define WM8903_DACR_ENA_SHIFT 2 /* DACR_ENA */ 302*f1c0a02fSMark Brown #define WM8903_DACR_ENA_WIDTH 1 /* DACR_ENA */ 303*f1c0a02fSMark Brown #define WM8903_ADCL_ENA 0x0002 /* ADCL_ENA */ 304*f1c0a02fSMark Brown #define WM8903_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 305*f1c0a02fSMark Brown #define WM8903_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 306*f1c0a02fSMark Brown #define WM8903_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 307*f1c0a02fSMark Brown #define WM8903_ADCR_ENA 0x0001 /* ADCR_ENA */ 308*f1c0a02fSMark Brown #define WM8903_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 309*f1c0a02fSMark Brown #define WM8903_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 310*f1c0a02fSMark Brown #define WM8903_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 311*f1c0a02fSMark Brown 312*f1c0a02fSMark Brown /* 313*f1c0a02fSMark Brown * R20 (0x14) - Clock Rates 0 314*f1c0a02fSMark Brown */ 315*f1c0a02fSMark Brown #define WM8903_MCLKDIV2 0x0001 /* MCLKDIV2 */ 316*f1c0a02fSMark Brown #define WM8903_MCLKDIV2_MASK 0x0001 /* MCLKDIV2 */ 317*f1c0a02fSMark Brown #define WM8903_MCLKDIV2_SHIFT 0 /* MCLKDIV2 */ 318*f1c0a02fSMark Brown #define WM8903_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */ 319*f1c0a02fSMark Brown 320*f1c0a02fSMark Brown /* 321*f1c0a02fSMark Brown * R21 (0x15) - Clock Rates 1 322*f1c0a02fSMark Brown */ 323*f1c0a02fSMark Brown #define WM8903_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */ 324*f1c0a02fSMark Brown #define WM8903_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */ 325*f1c0a02fSMark Brown #define WM8903_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */ 326*f1c0a02fSMark Brown #define WM8903_CLK_SYS_MODE_MASK 0x0300 /* CLK_SYS_MODE - [9:8] */ 327*f1c0a02fSMark Brown #define WM8903_CLK_SYS_MODE_SHIFT 8 /* CLK_SYS_MODE - [9:8] */ 328*f1c0a02fSMark Brown #define WM8903_CLK_SYS_MODE_WIDTH 2 /* CLK_SYS_MODE - [9:8] */ 329*f1c0a02fSMark Brown #define WM8903_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */ 330*f1c0a02fSMark Brown #define WM8903_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */ 331*f1c0a02fSMark Brown #define WM8903_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */ 332*f1c0a02fSMark Brown 333*f1c0a02fSMark Brown /* 334*f1c0a02fSMark Brown * R22 (0x16) - Clock Rates 2 335*f1c0a02fSMark Brown */ 336*f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */ 337*f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */ 338*f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */ 339*f1c0a02fSMark Brown #define WM8903_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 340*f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ 341*f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ 342*f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ 343*f1c0a02fSMark Brown #define WM8903_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 344*f1c0a02fSMark Brown #define WM8903_TO_ENA 0x0001 /* TO_ENA */ 345*f1c0a02fSMark Brown #define WM8903_TO_ENA_MASK 0x0001 /* TO_ENA */ 346*f1c0a02fSMark Brown #define WM8903_TO_ENA_SHIFT 0 /* TO_ENA */ 347*f1c0a02fSMark Brown #define WM8903_TO_ENA_WIDTH 1 /* TO_ENA */ 348*f1c0a02fSMark Brown 349*f1c0a02fSMark Brown /* 350*f1c0a02fSMark Brown * R24 (0x18) - Audio Interface 0 351*f1c0a02fSMark Brown */ 352*f1c0a02fSMark Brown #define WM8903_DACL_DATINV 0x1000 /* DACL_DATINV */ 353*f1c0a02fSMark Brown #define WM8903_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */ 354*f1c0a02fSMark Brown #define WM8903_DACL_DATINV_SHIFT 12 /* DACL_DATINV */ 355*f1c0a02fSMark Brown #define WM8903_DACL_DATINV_WIDTH 1 /* DACL_DATINV */ 356*f1c0a02fSMark Brown #define WM8903_DACR_DATINV 0x0800 /* DACR_DATINV */ 357*f1c0a02fSMark Brown #define WM8903_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */ 358*f1c0a02fSMark Brown #define WM8903_DACR_DATINV_SHIFT 11 /* DACR_DATINV */ 359*f1c0a02fSMark Brown #define WM8903_DACR_DATINV_WIDTH 1 /* DACR_DATINV */ 360*f1c0a02fSMark Brown #define WM8903_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */ 361*f1c0a02fSMark Brown #define WM8903_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */ 362*f1c0a02fSMark Brown #define WM8903_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */ 363*f1c0a02fSMark Brown #define WM8903_LOOPBACK 0x0100 /* LOOPBACK */ 364*f1c0a02fSMark Brown #define WM8903_LOOPBACK_MASK 0x0100 /* LOOPBACK */ 365*f1c0a02fSMark Brown #define WM8903_LOOPBACK_SHIFT 8 /* LOOPBACK */ 366*f1c0a02fSMark Brown #define WM8903_LOOPBACK_WIDTH 1 /* LOOPBACK */ 367*f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */ 368*f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */ 369*f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */ 370*f1c0a02fSMark Brown #define WM8903_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */ 371*f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */ 372*f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */ 373*f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */ 374*f1c0a02fSMark Brown #define WM8903_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */ 375*f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */ 376*f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */ 377*f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */ 378*f1c0a02fSMark Brown #define WM8903_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */ 379*f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */ 380*f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */ 381*f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */ 382*f1c0a02fSMark Brown #define WM8903_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */ 383*f1c0a02fSMark Brown #define WM8903_ADC_COMP 0x0008 /* ADC_COMP */ 384*f1c0a02fSMark Brown #define WM8903_ADC_COMP_MASK 0x0008 /* ADC_COMP */ 385*f1c0a02fSMark Brown #define WM8903_ADC_COMP_SHIFT 3 /* ADC_COMP */ 386*f1c0a02fSMark Brown #define WM8903_ADC_COMP_WIDTH 1 /* ADC_COMP */ 387*f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */ 388*f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */ 389*f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */ 390*f1c0a02fSMark Brown #define WM8903_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ 391*f1c0a02fSMark Brown #define WM8903_DAC_COMP 0x0002 /* DAC_COMP */ 392*f1c0a02fSMark Brown #define WM8903_DAC_COMP_MASK 0x0002 /* DAC_COMP */ 393*f1c0a02fSMark Brown #define WM8903_DAC_COMP_SHIFT 1 /* DAC_COMP */ 394*f1c0a02fSMark Brown #define WM8903_DAC_COMP_WIDTH 1 /* DAC_COMP */ 395*f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ 396*f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ 397*f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ 398*f1c0a02fSMark Brown #define WM8903_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ 399*f1c0a02fSMark Brown 400*f1c0a02fSMark Brown /* 401*f1c0a02fSMark Brown * R25 (0x19) - Audio Interface 1 402*f1c0a02fSMark Brown */ 403*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ 404*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */ 405*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */ 406*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */ 407*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ 408*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */ 409*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */ 410*f1c0a02fSMark Brown #define WM8903_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */ 411*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM 0x0800 /* AIFADC_TDM */ 412*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */ 413*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */ 414*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */ 415*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */ 416*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */ 417*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */ 418*f1c0a02fSMark Brown #define WM8903_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */ 419*f1c0a02fSMark Brown #define WM8903_LRCLK_DIR 0x0200 /* LRCLK_DIR */ 420*f1c0a02fSMark Brown #define WM8903_LRCLK_DIR_MASK 0x0200 /* LRCLK_DIR */ 421*f1c0a02fSMark Brown #define WM8903_LRCLK_DIR_SHIFT 9 /* LRCLK_DIR */ 422*f1c0a02fSMark Brown #define WM8903_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ 423*f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ 424*f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ 425*f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ 426*f1c0a02fSMark Brown #define WM8903_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ 427*f1c0a02fSMark Brown #define WM8903_BCLK_DIR 0x0040 /* BCLK_DIR */ 428*f1c0a02fSMark Brown #define WM8903_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ 429*f1c0a02fSMark Brown #define WM8903_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ 430*f1c0a02fSMark Brown #define WM8903_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ 431*f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ 432*f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ 433*f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ 434*f1c0a02fSMark Brown #define WM8903_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ 435*f1c0a02fSMark Brown #define WM8903_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ 436*f1c0a02fSMark Brown #define WM8903_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ 437*f1c0a02fSMark Brown #define WM8903_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ 438*f1c0a02fSMark Brown #define WM8903_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ 439*f1c0a02fSMark Brown #define WM8903_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ 440*f1c0a02fSMark Brown #define WM8903_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ 441*f1c0a02fSMark Brown 442*f1c0a02fSMark Brown /* 443*f1c0a02fSMark Brown * R26 (0x1A) - Audio Interface 2 444*f1c0a02fSMark Brown */ 445*f1c0a02fSMark Brown #define WM8903_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ 446*f1c0a02fSMark Brown #define WM8903_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ 447*f1c0a02fSMark Brown #define WM8903_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ 448*f1c0a02fSMark Brown 449*f1c0a02fSMark Brown /* 450*f1c0a02fSMark Brown * R27 (0x1B) - Audio Interface 3 451*f1c0a02fSMark Brown */ 452*f1c0a02fSMark Brown #define WM8903_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ 453*f1c0a02fSMark Brown #define WM8903_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ 454*f1c0a02fSMark Brown #define WM8903_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ 455*f1c0a02fSMark Brown 456*f1c0a02fSMark Brown /* 457*f1c0a02fSMark Brown * R30 (0x1E) - DAC Digital Volume Left 458*f1c0a02fSMark Brown */ 459*f1c0a02fSMark Brown #define WM8903_DACVU 0x0100 /* DACVU */ 460*f1c0a02fSMark Brown #define WM8903_DACVU_MASK 0x0100 /* DACVU */ 461*f1c0a02fSMark Brown #define WM8903_DACVU_SHIFT 8 /* DACVU */ 462*f1c0a02fSMark Brown #define WM8903_DACVU_WIDTH 1 /* DACVU */ 463*f1c0a02fSMark Brown #define WM8903_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ 464*f1c0a02fSMark Brown #define WM8903_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ 465*f1c0a02fSMark Brown #define WM8903_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ 466*f1c0a02fSMark Brown 467*f1c0a02fSMark Brown /* 468*f1c0a02fSMark Brown * R31 (0x1F) - DAC Digital Volume Right 469*f1c0a02fSMark Brown */ 470*f1c0a02fSMark Brown #define WM8903_DACVU 0x0100 /* DACVU */ 471*f1c0a02fSMark Brown #define WM8903_DACVU_MASK 0x0100 /* DACVU */ 472*f1c0a02fSMark Brown #define WM8903_DACVU_SHIFT 8 /* DACVU */ 473*f1c0a02fSMark Brown #define WM8903_DACVU_WIDTH 1 /* DACVU */ 474*f1c0a02fSMark Brown #define WM8903_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ 475*f1c0a02fSMark Brown #define WM8903_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ 476*f1c0a02fSMark Brown #define WM8903_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ 477*f1c0a02fSMark Brown 478*f1c0a02fSMark Brown /* 479*f1c0a02fSMark Brown * R32 (0x20) - DAC Digital 0 480*f1c0a02fSMark Brown */ 481*f1c0a02fSMark Brown #define WM8903_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */ 482*f1c0a02fSMark Brown #define WM8903_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */ 483*f1c0a02fSMark Brown #define WM8903_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */ 484*f1c0a02fSMark Brown #define WM8903_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 485*f1c0a02fSMark Brown #define WM8903_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 486*f1c0a02fSMark Brown #define WM8903_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 487*f1c0a02fSMark Brown #define WM8903_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 488*f1c0a02fSMark Brown #define WM8903_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 489*f1c0a02fSMark Brown #define WM8903_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 490*f1c0a02fSMark Brown #define WM8903_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */ 491*f1c0a02fSMark Brown #define WM8903_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */ 492*f1c0a02fSMark Brown #define WM8903_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */ 493*f1c0a02fSMark Brown 494*f1c0a02fSMark Brown /* 495*f1c0a02fSMark Brown * R33 (0x21) - DAC Digital 1 496*f1c0a02fSMark Brown */ 497*f1c0a02fSMark Brown #define WM8903_DAC_MONO 0x1000 /* DAC_MONO */ 498*f1c0a02fSMark Brown #define WM8903_DAC_MONO_MASK 0x1000 /* DAC_MONO */ 499*f1c0a02fSMark Brown #define WM8903_DAC_MONO_SHIFT 12 /* DAC_MONO */ 500*f1c0a02fSMark Brown #define WM8903_DAC_MONO_WIDTH 1 /* DAC_MONO */ 501*f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */ 502*f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */ 503*f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */ 504*f1c0a02fSMark Brown #define WM8903_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */ 505*f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ 506*f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ 507*f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ 508*f1c0a02fSMark Brown #define WM8903_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 509*f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */ 510*f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */ 511*f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */ 512*f1c0a02fSMark Brown #define WM8903_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */ 513*f1c0a02fSMark Brown #define WM8903_DAC_MUTE 0x0008 /* DAC_MUTE */ 514*f1c0a02fSMark Brown #define WM8903_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ 515*f1c0a02fSMark Brown #define WM8903_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ 516*f1c0a02fSMark Brown #define WM8903_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ 517*f1c0a02fSMark Brown #define WM8903_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 518*f1c0a02fSMark Brown #define WM8903_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 519*f1c0a02fSMark Brown #define WM8903_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 520*f1c0a02fSMark Brown 521*f1c0a02fSMark Brown /* 522*f1c0a02fSMark Brown * R36 (0x24) - ADC Digital Volume Left 523*f1c0a02fSMark Brown */ 524*f1c0a02fSMark Brown #define WM8903_ADCVU 0x0100 /* ADCVU */ 525*f1c0a02fSMark Brown #define WM8903_ADCVU_MASK 0x0100 /* ADCVU */ 526*f1c0a02fSMark Brown #define WM8903_ADCVU_SHIFT 8 /* ADCVU */ 527*f1c0a02fSMark Brown #define WM8903_ADCVU_WIDTH 1 /* ADCVU */ 528*f1c0a02fSMark Brown #define WM8903_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ 529*f1c0a02fSMark Brown #define WM8903_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ 530*f1c0a02fSMark Brown #define WM8903_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ 531*f1c0a02fSMark Brown 532*f1c0a02fSMark Brown /* 533*f1c0a02fSMark Brown * R37 (0x25) - ADC Digital Volume Right 534*f1c0a02fSMark Brown */ 535*f1c0a02fSMark Brown #define WM8903_ADCVU 0x0100 /* ADCVU */ 536*f1c0a02fSMark Brown #define WM8903_ADCVU_MASK 0x0100 /* ADCVU */ 537*f1c0a02fSMark Brown #define WM8903_ADCVU_SHIFT 8 /* ADCVU */ 538*f1c0a02fSMark Brown #define WM8903_ADCVU_WIDTH 1 /* ADCVU */ 539*f1c0a02fSMark Brown #define WM8903_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ 540*f1c0a02fSMark Brown #define WM8903_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ 541*f1c0a02fSMark Brown #define WM8903_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ 542*f1c0a02fSMark Brown 543*f1c0a02fSMark Brown /* 544*f1c0a02fSMark Brown * R38 (0x26) - ADC Digital 0 545*f1c0a02fSMark Brown */ 546*f1c0a02fSMark Brown #define WM8903_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */ 547*f1c0a02fSMark Brown #define WM8903_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */ 548*f1c0a02fSMark Brown #define WM8903_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */ 549*f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA 0x0010 /* ADC_HPF_ENA */ 550*f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA_MASK 0x0010 /* ADC_HPF_ENA */ 551*f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA_SHIFT 4 /* ADC_HPF_ENA */ 552*f1c0a02fSMark Brown #define WM8903_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */ 553*f1c0a02fSMark Brown #define WM8903_ADCL_DATINV 0x0002 /* ADCL_DATINV */ 554*f1c0a02fSMark Brown #define WM8903_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */ 555*f1c0a02fSMark Brown #define WM8903_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */ 556*f1c0a02fSMark Brown #define WM8903_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */ 557*f1c0a02fSMark Brown #define WM8903_ADCR_DATINV 0x0001 /* ADCR_DATINV */ 558*f1c0a02fSMark Brown #define WM8903_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */ 559*f1c0a02fSMark Brown #define WM8903_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */ 560*f1c0a02fSMark Brown #define WM8903_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */ 561*f1c0a02fSMark Brown 562*f1c0a02fSMark Brown /* 563*f1c0a02fSMark Brown * R39 (0x27) - Digital Microphone 0 564*f1c0a02fSMark Brown */ 565*f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL 0x0100 /* DIGMIC_MODE_SEL */ 566*f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL_MASK 0x0100 /* DIGMIC_MODE_SEL */ 567*f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL_SHIFT 8 /* DIGMIC_MODE_SEL */ 568*f1c0a02fSMark Brown #define WM8903_DIGMIC_MODE_SEL_WIDTH 1 /* DIGMIC_MODE_SEL */ 569*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_L_MASK 0x00C0 /* DIGMIC_CLK_SEL_L - [7:6] */ 570*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_L_SHIFT 6 /* DIGMIC_CLK_SEL_L - [7:6] */ 571*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_L_WIDTH 2 /* DIGMIC_CLK_SEL_L - [7:6] */ 572*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_R_MASK 0x0030 /* DIGMIC_CLK_SEL_R - [5:4] */ 573*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_R_SHIFT 4 /* DIGMIC_CLK_SEL_R - [5:4] */ 574*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_R_WIDTH 2 /* DIGMIC_CLK_SEL_R - [5:4] */ 575*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_RT_MASK 0x000C /* DIGMIC_CLK_SEL_RT - [3:2] */ 576*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_RT_SHIFT 2 /* DIGMIC_CLK_SEL_RT - [3:2] */ 577*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_RT_WIDTH 2 /* DIGMIC_CLK_SEL_RT - [3:2] */ 578*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_MASK 0x0003 /* DIGMIC_CLK_SEL - [1:0] */ 579*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_SHIFT 0 /* DIGMIC_CLK_SEL - [1:0] */ 580*f1c0a02fSMark Brown #define WM8903_DIGMIC_CLK_SEL_WIDTH 2 /* DIGMIC_CLK_SEL - [1:0] */ 581*f1c0a02fSMark Brown 582*f1c0a02fSMark Brown /* 583*f1c0a02fSMark Brown * R40 (0x28) - DRC 0 584*f1c0a02fSMark Brown */ 585*f1c0a02fSMark Brown #define WM8903_DRC_ENA 0x8000 /* DRC_ENA */ 586*f1c0a02fSMark Brown #define WM8903_DRC_ENA_MASK 0x8000 /* DRC_ENA */ 587*f1c0a02fSMark Brown #define WM8903_DRC_ENA_SHIFT 15 /* DRC_ENA */ 588*f1c0a02fSMark Brown #define WM8903_DRC_ENA_WIDTH 1 /* DRC_ENA */ 589*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_HYST_MASK 0x1800 /* DRC_THRESH_HYST - [12:11] */ 590*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_HYST_SHIFT 11 /* DRC_THRESH_HYST - [12:11] */ 591*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_HYST_WIDTH 2 /* DRC_THRESH_HYST - [12:11] */ 592*f1c0a02fSMark Brown #define WM8903_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ 593*f1c0a02fSMark Brown #define WM8903_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ 594*f1c0a02fSMark Brown #define WM8903_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ 595*f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */ 596*f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */ 597*f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */ 598*f1c0a02fSMark Brown #define WM8903_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */ 599*f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA 0x0008 /* DRC_SMOOTH_ENA */ 600*f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA_MASK 0x0008 /* DRC_SMOOTH_ENA */ 601*f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA_SHIFT 3 /* DRC_SMOOTH_ENA */ 602*f1c0a02fSMark Brown #define WM8903_DRC_SMOOTH_ENA_WIDTH 1 /* DRC_SMOOTH_ENA */ 603*f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA 0x0004 /* DRC_QR_ENA */ 604*f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA_MASK 0x0004 /* DRC_QR_ENA */ 605*f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA_SHIFT 2 /* DRC_QR_ENA */ 606*f1c0a02fSMark Brown #define WM8903_DRC_QR_ENA_WIDTH 1 /* DRC_QR_ENA */ 607*f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA 0x0002 /* DRC_ANTICLIP_ENA */ 608*f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA_MASK 0x0002 /* DRC_ANTICLIP_ENA */ 609*f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA_SHIFT 1 /* DRC_ANTICLIP_ENA */ 610*f1c0a02fSMark Brown #define WM8903_DRC_ANTICLIP_ENA_WIDTH 1 /* DRC_ANTICLIP_ENA */ 611*f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA 0x0001 /* DRC_HYST_ENA */ 612*f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA_MASK 0x0001 /* DRC_HYST_ENA */ 613*f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA_SHIFT 0 /* DRC_HYST_ENA */ 614*f1c0a02fSMark Brown #define WM8903_DRC_HYST_ENA_WIDTH 1 /* DRC_HYST_ENA */ 615*f1c0a02fSMark Brown 616*f1c0a02fSMark Brown /* 617*f1c0a02fSMark Brown * R41 (0x29) - DRC 1 618*f1c0a02fSMark Brown */ 619*f1c0a02fSMark Brown #define WM8903_DRC_ATTACK_RATE_MASK 0xF000 /* DRC_ATTACK_RATE - [15:12] */ 620*f1c0a02fSMark Brown #define WM8903_DRC_ATTACK_RATE_SHIFT 12 /* DRC_ATTACK_RATE - [15:12] */ 621*f1c0a02fSMark Brown #define WM8903_DRC_ATTACK_RATE_WIDTH 4 /* DRC_ATTACK_RATE - [15:12] */ 622*f1c0a02fSMark Brown #define WM8903_DRC_DECAY_RATE_MASK 0x0F00 /* DRC_DECAY_RATE - [11:8] */ 623*f1c0a02fSMark Brown #define WM8903_DRC_DECAY_RATE_SHIFT 8 /* DRC_DECAY_RATE - [11:8] */ 624*f1c0a02fSMark Brown #define WM8903_DRC_DECAY_RATE_WIDTH 4 /* DRC_DECAY_RATE - [11:8] */ 625*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_QR_MASK 0x00C0 /* DRC_THRESH_QR - [7:6] */ 626*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_QR_SHIFT 6 /* DRC_THRESH_QR - [7:6] */ 627*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_QR_WIDTH 2 /* DRC_THRESH_QR - [7:6] */ 628*f1c0a02fSMark Brown #define WM8903_DRC_RATE_QR_MASK 0x0030 /* DRC_RATE_QR - [5:4] */ 629*f1c0a02fSMark Brown #define WM8903_DRC_RATE_QR_SHIFT 4 /* DRC_RATE_QR - [5:4] */ 630*f1c0a02fSMark Brown #define WM8903_DRC_RATE_QR_WIDTH 2 /* DRC_RATE_QR - [5:4] */ 631*f1c0a02fSMark Brown #define WM8903_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ 632*f1c0a02fSMark Brown #define WM8903_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ 633*f1c0a02fSMark Brown #define WM8903_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ 634*f1c0a02fSMark Brown #define WM8903_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 635*f1c0a02fSMark Brown #define WM8903_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 636*f1c0a02fSMark Brown #define WM8903_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 637*f1c0a02fSMark Brown 638*f1c0a02fSMark Brown /* 639*f1c0a02fSMark Brown * R42 (0x2A) - DRC 2 640*f1c0a02fSMark Brown */ 641*f1c0a02fSMark Brown #define WM8903_DRC_R0_SLOPE_COMP_MASK 0x0038 /* DRC_R0_SLOPE_COMP - [5:3] */ 642*f1c0a02fSMark Brown #define WM8903_DRC_R0_SLOPE_COMP_SHIFT 3 /* DRC_R0_SLOPE_COMP - [5:3] */ 643*f1c0a02fSMark Brown #define WM8903_DRC_R0_SLOPE_COMP_WIDTH 3 /* DRC_R0_SLOPE_COMP - [5:3] */ 644*f1c0a02fSMark Brown #define WM8903_DRC_R1_SLOPE_COMP_MASK 0x0007 /* DRC_R1_SLOPE_COMP - [2:0] */ 645*f1c0a02fSMark Brown #define WM8903_DRC_R1_SLOPE_COMP_SHIFT 0 /* DRC_R1_SLOPE_COMP - [2:0] */ 646*f1c0a02fSMark Brown #define WM8903_DRC_R1_SLOPE_COMP_WIDTH 3 /* DRC_R1_SLOPE_COMP - [2:0] */ 647*f1c0a02fSMark Brown 648*f1c0a02fSMark Brown /* 649*f1c0a02fSMark Brown * R43 (0x2B) - DRC 3 650*f1c0a02fSMark Brown */ 651*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_COMP_MASK 0x07E0 /* DRC_THRESH_COMP - [10:5] */ 652*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_COMP_SHIFT 5 /* DRC_THRESH_COMP - [10:5] */ 653*f1c0a02fSMark Brown #define WM8903_DRC_THRESH_COMP_WIDTH 6 /* DRC_THRESH_COMP - [10:5] */ 654*f1c0a02fSMark Brown #define WM8903_DRC_AMP_COMP_MASK 0x001F /* DRC_AMP_COMP - [4:0] */ 655*f1c0a02fSMark Brown #define WM8903_DRC_AMP_COMP_SHIFT 0 /* DRC_AMP_COMP - [4:0] */ 656*f1c0a02fSMark Brown #define WM8903_DRC_AMP_COMP_WIDTH 5 /* DRC_AMP_COMP - [4:0] */ 657*f1c0a02fSMark Brown 658*f1c0a02fSMark Brown /* 659*f1c0a02fSMark Brown * R44 (0x2C) - Analogue Left Input 0 660*f1c0a02fSMark Brown */ 661*f1c0a02fSMark Brown #define WM8903_LINMUTE 0x0080 /* LINMUTE */ 662*f1c0a02fSMark Brown #define WM8903_LINMUTE_MASK 0x0080 /* LINMUTE */ 663*f1c0a02fSMark Brown #define WM8903_LINMUTE_SHIFT 7 /* LINMUTE */ 664*f1c0a02fSMark Brown #define WM8903_LINMUTE_WIDTH 1 /* LINMUTE */ 665*f1c0a02fSMark Brown #define WM8903_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */ 666*f1c0a02fSMark Brown #define WM8903_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */ 667*f1c0a02fSMark Brown #define WM8903_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */ 668*f1c0a02fSMark Brown 669*f1c0a02fSMark Brown /* 670*f1c0a02fSMark Brown * R45 (0x2D) - Analogue Right Input 0 671*f1c0a02fSMark Brown */ 672*f1c0a02fSMark Brown #define WM8903_RINMUTE 0x0080 /* RINMUTE */ 673*f1c0a02fSMark Brown #define WM8903_RINMUTE_MASK 0x0080 /* RINMUTE */ 674*f1c0a02fSMark Brown #define WM8903_RINMUTE_SHIFT 7 /* RINMUTE */ 675*f1c0a02fSMark Brown #define WM8903_RINMUTE_WIDTH 1 /* RINMUTE */ 676*f1c0a02fSMark Brown #define WM8903_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */ 677*f1c0a02fSMark Brown #define WM8903_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */ 678*f1c0a02fSMark Brown #define WM8903_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */ 679*f1c0a02fSMark Brown 680*f1c0a02fSMark Brown /* 681*f1c0a02fSMark Brown * R46 (0x2E) - Analogue Left Input 1 682*f1c0a02fSMark Brown */ 683*f1c0a02fSMark Brown #define WM8903_INL_CM_ENA 0x0040 /* INL_CM_ENA */ 684*f1c0a02fSMark Brown #define WM8903_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */ 685*f1c0a02fSMark Brown #define WM8903_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */ 686*f1c0a02fSMark Brown #define WM8903_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */ 687*f1c0a02fSMark Brown #define WM8903_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */ 688*f1c0a02fSMark Brown #define WM8903_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */ 689*f1c0a02fSMark Brown #define WM8903_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */ 690*f1c0a02fSMark Brown #define WM8903_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */ 691*f1c0a02fSMark Brown #define WM8903_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */ 692*f1c0a02fSMark Brown #define WM8903_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */ 693*f1c0a02fSMark Brown #define WM8903_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */ 694*f1c0a02fSMark Brown #define WM8903_L_MODE_SHIFT 0 /* L_MODE - [1:0] */ 695*f1c0a02fSMark Brown #define WM8903_L_MODE_WIDTH 2 /* L_MODE - [1:0] */ 696*f1c0a02fSMark Brown 697*f1c0a02fSMark Brown /* 698*f1c0a02fSMark Brown * R47 (0x2F) - Analogue Right Input 1 699*f1c0a02fSMark Brown */ 700*f1c0a02fSMark Brown #define WM8903_INR_CM_ENA 0x0040 /* INR_CM_ENA */ 701*f1c0a02fSMark Brown #define WM8903_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */ 702*f1c0a02fSMark Brown #define WM8903_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */ 703*f1c0a02fSMark Brown #define WM8903_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */ 704*f1c0a02fSMark Brown #define WM8903_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */ 705*f1c0a02fSMark Brown #define WM8903_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */ 706*f1c0a02fSMark Brown #define WM8903_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */ 707*f1c0a02fSMark Brown #define WM8903_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */ 708*f1c0a02fSMark Brown #define WM8903_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */ 709*f1c0a02fSMark Brown #define WM8903_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */ 710*f1c0a02fSMark Brown #define WM8903_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */ 711*f1c0a02fSMark Brown #define WM8903_R_MODE_SHIFT 0 /* R_MODE - [1:0] */ 712*f1c0a02fSMark Brown #define WM8903_R_MODE_WIDTH 2 /* R_MODE - [1:0] */ 713*f1c0a02fSMark Brown 714*f1c0a02fSMark Brown /* 715*f1c0a02fSMark Brown * R50 (0x32) - Analogue Left Mix 0 716*f1c0a02fSMark Brown */ 717*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL 0x0008 /* DACL_TO_MIXOUTL */ 718*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL_MASK 0x0008 /* DACL_TO_MIXOUTL */ 719*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL_SHIFT 3 /* DACL_TO_MIXOUTL */ 720*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTL_WIDTH 1 /* DACL_TO_MIXOUTL */ 721*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL 0x0004 /* DACR_TO_MIXOUTL */ 722*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL_MASK 0x0004 /* DACR_TO_MIXOUTL */ 723*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL_SHIFT 2 /* DACR_TO_MIXOUTL */ 724*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTL_WIDTH 1 /* DACR_TO_MIXOUTL */ 725*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL 0x0002 /* BYPASSL_TO_MIXOUTL */ 726*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL_MASK 0x0002 /* BYPASSL_TO_MIXOUTL */ 727*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL_SHIFT 1 /* BYPASSL_TO_MIXOUTL */ 728*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTL_WIDTH 1 /* BYPASSL_TO_MIXOUTL */ 729*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL 0x0001 /* BYPASSR_TO_MIXOUTL */ 730*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL_MASK 0x0001 /* BYPASSR_TO_MIXOUTL */ 731*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL_SHIFT 0 /* BYPASSR_TO_MIXOUTL */ 732*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTL_WIDTH 1 /* BYPASSR_TO_MIXOUTL */ 733*f1c0a02fSMark Brown 734*f1c0a02fSMark Brown /* 735*f1c0a02fSMark Brown * R51 (0x33) - Analogue Right Mix 0 736*f1c0a02fSMark Brown */ 737*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR 0x0008 /* DACL_TO_MIXOUTR */ 738*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR_MASK 0x0008 /* DACL_TO_MIXOUTR */ 739*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR_SHIFT 3 /* DACL_TO_MIXOUTR */ 740*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXOUTR_WIDTH 1 /* DACL_TO_MIXOUTR */ 741*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR 0x0004 /* DACR_TO_MIXOUTR */ 742*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR_MASK 0x0004 /* DACR_TO_MIXOUTR */ 743*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR_SHIFT 2 /* DACR_TO_MIXOUTR */ 744*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXOUTR_WIDTH 1 /* DACR_TO_MIXOUTR */ 745*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR 0x0002 /* BYPASSL_TO_MIXOUTR */ 746*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR_MASK 0x0002 /* BYPASSL_TO_MIXOUTR */ 747*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR_SHIFT 1 /* BYPASSL_TO_MIXOUTR */ 748*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXOUTR_WIDTH 1 /* BYPASSL_TO_MIXOUTR */ 749*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR 0x0001 /* BYPASSR_TO_MIXOUTR */ 750*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR_MASK 0x0001 /* BYPASSR_TO_MIXOUTR */ 751*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR_SHIFT 0 /* BYPASSR_TO_MIXOUTR */ 752*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXOUTR_WIDTH 1 /* BYPASSR_TO_MIXOUTR */ 753*f1c0a02fSMark Brown 754*f1c0a02fSMark Brown /* 755*f1c0a02fSMark Brown * R52 (0x34) - Analogue Spk Mix Left 0 756*f1c0a02fSMark Brown */ 757*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL 0x0008 /* DACL_TO_MIXSPKL */ 758*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL_MASK 0x0008 /* DACL_TO_MIXSPKL */ 759*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL_SHIFT 3 /* DACL_TO_MIXSPKL */ 760*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKL_WIDTH 1 /* DACL_TO_MIXSPKL */ 761*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL 0x0004 /* DACR_TO_MIXSPKL */ 762*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL_MASK 0x0004 /* DACR_TO_MIXSPKL */ 763*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL_SHIFT 2 /* DACR_TO_MIXSPKL */ 764*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKL_WIDTH 1 /* DACR_TO_MIXSPKL */ 765*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL 0x0002 /* BYPASSL_TO_MIXSPKL */ 766*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL_MASK 0x0002 /* BYPASSL_TO_MIXSPKL */ 767*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL_SHIFT 1 /* BYPASSL_TO_MIXSPKL */ 768*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKL_WIDTH 1 /* BYPASSL_TO_MIXSPKL */ 769*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL 0x0001 /* BYPASSR_TO_MIXSPKL */ 770*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL_MASK 0x0001 /* BYPASSR_TO_MIXSPKL */ 771*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL_SHIFT 0 /* BYPASSR_TO_MIXSPKL */ 772*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKL_WIDTH 1 /* BYPASSR_TO_MIXSPKL */ 773*f1c0a02fSMark Brown 774*f1c0a02fSMark Brown /* 775*f1c0a02fSMark Brown * R53 (0x35) - Analogue Spk Mix Left 1 776*f1c0a02fSMark Brown */ 777*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL 0x0008 /* DACL_MIXSPKL_VOL */ 778*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL_MASK 0x0008 /* DACL_MIXSPKL_VOL */ 779*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL_SHIFT 3 /* DACL_MIXSPKL_VOL */ 780*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKL_VOL_WIDTH 1 /* DACL_MIXSPKL_VOL */ 781*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL 0x0004 /* DACR_MIXSPKL_VOL */ 782*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL_MASK 0x0004 /* DACR_MIXSPKL_VOL */ 783*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL_SHIFT 2 /* DACR_MIXSPKL_VOL */ 784*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKL_VOL_WIDTH 1 /* DACR_MIXSPKL_VOL */ 785*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL 0x0002 /* BYPASSL_MIXSPKL_VOL */ 786*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL_MASK 0x0002 /* BYPASSL_MIXSPKL_VOL */ 787*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL_SHIFT 1 /* BYPASSL_MIXSPKL_VOL */ 788*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKL_VOL_WIDTH 1 /* BYPASSL_MIXSPKL_VOL */ 789*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL 0x0001 /* BYPASSR_MIXSPKL_VOL */ 790*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL_MASK 0x0001 /* BYPASSR_MIXSPKL_VOL */ 791*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL_SHIFT 0 /* BYPASSR_MIXSPKL_VOL */ 792*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKL_VOL_WIDTH 1 /* BYPASSR_MIXSPKL_VOL */ 793*f1c0a02fSMark Brown 794*f1c0a02fSMark Brown /* 795*f1c0a02fSMark Brown * R54 (0x36) - Analogue Spk Mix Right 0 796*f1c0a02fSMark Brown */ 797*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR 0x0008 /* DACL_TO_MIXSPKR */ 798*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR_MASK 0x0008 /* DACL_TO_MIXSPKR */ 799*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR_SHIFT 3 /* DACL_TO_MIXSPKR */ 800*f1c0a02fSMark Brown #define WM8903_DACL_TO_MIXSPKR_WIDTH 1 /* DACL_TO_MIXSPKR */ 801*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR 0x0004 /* DACR_TO_MIXSPKR */ 802*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR_MASK 0x0004 /* DACR_TO_MIXSPKR */ 803*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR_SHIFT 2 /* DACR_TO_MIXSPKR */ 804*f1c0a02fSMark Brown #define WM8903_DACR_TO_MIXSPKR_WIDTH 1 /* DACR_TO_MIXSPKR */ 805*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR 0x0002 /* BYPASSL_TO_MIXSPKR */ 806*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR_MASK 0x0002 /* BYPASSL_TO_MIXSPKR */ 807*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR_SHIFT 1 /* BYPASSL_TO_MIXSPKR */ 808*f1c0a02fSMark Brown #define WM8903_BYPASSL_TO_MIXSPKR_WIDTH 1 /* BYPASSL_TO_MIXSPKR */ 809*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR 0x0001 /* BYPASSR_TO_MIXSPKR */ 810*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR_MASK 0x0001 /* BYPASSR_TO_MIXSPKR */ 811*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR_SHIFT 0 /* BYPASSR_TO_MIXSPKR */ 812*f1c0a02fSMark Brown #define WM8903_BYPASSR_TO_MIXSPKR_WIDTH 1 /* BYPASSR_TO_MIXSPKR */ 813*f1c0a02fSMark Brown 814*f1c0a02fSMark Brown /* 815*f1c0a02fSMark Brown * R55 (0x37) - Analogue Spk Mix Right 1 816*f1c0a02fSMark Brown */ 817*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL 0x0008 /* DACL_MIXSPKR_VOL */ 818*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL_MASK 0x0008 /* DACL_MIXSPKR_VOL */ 819*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL_SHIFT 3 /* DACL_MIXSPKR_VOL */ 820*f1c0a02fSMark Brown #define WM8903_DACL_MIXSPKR_VOL_WIDTH 1 /* DACL_MIXSPKR_VOL */ 821*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL 0x0004 /* DACR_MIXSPKR_VOL */ 822*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL_MASK 0x0004 /* DACR_MIXSPKR_VOL */ 823*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL_SHIFT 2 /* DACR_MIXSPKR_VOL */ 824*f1c0a02fSMark Brown #define WM8903_DACR_MIXSPKR_VOL_WIDTH 1 /* DACR_MIXSPKR_VOL */ 825*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL 0x0002 /* BYPASSL_MIXSPKR_VOL */ 826*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL_MASK 0x0002 /* BYPASSL_MIXSPKR_VOL */ 827*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL_SHIFT 1 /* BYPASSL_MIXSPKR_VOL */ 828*f1c0a02fSMark Brown #define WM8903_BYPASSL_MIXSPKR_VOL_WIDTH 1 /* BYPASSL_MIXSPKR_VOL */ 829*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL 0x0001 /* BYPASSR_MIXSPKR_VOL */ 830*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL_MASK 0x0001 /* BYPASSR_MIXSPKR_VOL */ 831*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL_SHIFT 0 /* BYPASSR_MIXSPKR_VOL */ 832*f1c0a02fSMark Brown #define WM8903_BYPASSR_MIXSPKR_VOL_WIDTH 1 /* BYPASSR_MIXSPKR_VOL */ 833*f1c0a02fSMark Brown 834*f1c0a02fSMark Brown /* 835*f1c0a02fSMark Brown * R57 (0x39) - Analogue OUT1 Left 836*f1c0a02fSMark Brown */ 837*f1c0a02fSMark Brown #define WM8903_HPL_MUTE 0x0100 /* HPL_MUTE */ 838*f1c0a02fSMark Brown #define WM8903_HPL_MUTE_MASK 0x0100 /* HPL_MUTE */ 839*f1c0a02fSMark Brown #define WM8903_HPL_MUTE_SHIFT 8 /* HPL_MUTE */ 840*f1c0a02fSMark Brown #define WM8903_HPL_MUTE_WIDTH 1 /* HPL_MUTE */ 841*f1c0a02fSMark Brown #define WM8903_HPOUTVU 0x0080 /* HPOUTVU */ 842*f1c0a02fSMark Brown #define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */ 843*f1c0a02fSMark Brown #define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */ 844*f1c0a02fSMark Brown #define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */ 845*f1c0a02fSMark Brown #define WM8903_HPOUTLZC 0x0040 /* HPOUTLZC */ 846*f1c0a02fSMark Brown #define WM8903_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */ 847*f1c0a02fSMark Brown #define WM8903_HPOUTLZC_SHIFT 6 /* HPOUTLZC */ 848*f1c0a02fSMark Brown #define WM8903_HPOUTLZC_WIDTH 1 /* HPOUTLZC */ 849*f1c0a02fSMark Brown #define WM8903_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */ 850*f1c0a02fSMark Brown #define WM8903_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */ 851*f1c0a02fSMark Brown #define WM8903_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */ 852*f1c0a02fSMark Brown 853*f1c0a02fSMark Brown /* 854*f1c0a02fSMark Brown * R58 (0x3A) - Analogue OUT1 Right 855*f1c0a02fSMark Brown */ 856*f1c0a02fSMark Brown #define WM8903_HPR_MUTE 0x0100 /* HPR_MUTE */ 857*f1c0a02fSMark Brown #define WM8903_HPR_MUTE_MASK 0x0100 /* HPR_MUTE */ 858*f1c0a02fSMark Brown #define WM8903_HPR_MUTE_SHIFT 8 /* HPR_MUTE */ 859*f1c0a02fSMark Brown #define WM8903_HPR_MUTE_WIDTH 1 /* HPR_MUTE */ 860*f1c0a02fSMark Brown #define WM8903_HPOUTVU 0x0080 /* HPOUTVU */ 861*f1c0a02fSMark Brown #define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */ 862*f1c0a02fSMark Brown #define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */ 863*f1c0a02fSMark Brown #define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */ 864*f1c0a02fSMark Brown #define WM8903_HPOUTRZC 0x0040 /* HPOUTRZC */ 865*f1c0a02fSMark Brown #define WM8903_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */ 866*f1c0a02fSMark Brown #define WM8903_HPOUTRZC_SHIFT 6 /* HPOUTRZC */ 867*f1c0a02fSMark Brown #define WM8903_HPOUTRZC_WIDTH 1 /* HPOUTRZC */ 868*f1c0a02fSMark Brown #define WM8903_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */ 869*f1c0a02fSMark Brown #define WM8903_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */ 870*f1c0a02fSMark Brown #define WM8903_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */ 871*f1c0a02fSMark Brown 872*f1c0a02fSMark Brown /* 873*f1c0a02fSMark Brown * R59 (0x3B) - Analogue OUT2 Left 874*f1c0a02fSMark Brown */ 875*f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */ 876*f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */ 877*f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */ 878*f1c0a02fSMark Brown #define WM8903_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */ 879*f1c0a02fSMark Brown #define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */ 880*f1c0a02fSMark Brown #define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */ 881*f1c0a02fSMark Brown #define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */ 882*f1c0a02fSMark Brown #define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */ 883*f1c0a02fSMark Brown #define WM8903_LINEOUTLZC 0x0040 /* LINEOUTLZC */ 884*f1c0a02fSMark Brown #define WM8903_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */ 885*f1c0a02fSMark Brown #define WM8903_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */ 886*f1c0a02fSMark Brown #define WM8903_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */ 887*f1c0a02fSMark Brown #define WM8903_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */ 888*f1c0a02fSMark Brown #define WM8903_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */ 889*f1c0a02fSMark Brown #define WM8903_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */ 890*f1c0a02fSMark Brown 891*f1c0a02fSMark Brown /* 892*f1c0a02fSMark Brown * R60 (0x3C) - Analogue OUT2 Right 893*f1c0a02fSMark Brown */ 894*f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */ 895*f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */ 896*f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */ 897*f1c0a02fSMark Brown #define WM8903_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */ 898*f1c0a02fSMark Brown #define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */ 899*f1c0a02fSMark Brown #define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */ 900*f1c0a02fSMark Brown #define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */ 901*f1c0a02fSMark Brown #define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */ 902*f1c0a02fSMark Brown #define WM8903_LINEOUTRZC 0x0040 /* LINEOUTRZC */ 903*f1c0a02fSMark Brown #define WM8903_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */ 904*f1c0a02fSMark Brown #define WM8903_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */ 905*f1c0a02fSMark Brown #define WM8903_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */ 906*f1c0a02fSMark Brown #define WM8903_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */ 907*f1c0a02fSMark Brown #define WM8903_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */ 908*f1c0a02fSMark Brown #define WM8903_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */ 909*f1c0a02fSMark Brown 910*f1c0a02fSMark Brown /* 911*f1c0a02fSMark Brown * R62 (0x3E) - Analogue OUT3 Left 912*f1c0a02fSMark Brown */ 913*f1c0a02fSMark Brown #define WM8903_SPKL_MUTE 0x0100 /* SPKL_MUTE */ 914*f1c0a02fSMark Brown #define WM8903_SPKL_MUTE_MASK 0x0100 /* SPKL_MUTE */ 915*f1c0a02fSMark Brown #define WM8903_SPKL_MUTE_SHIFT 8 /* SPKL_MUTE */ 916*f1c0a02fSMark Brown #define WM8903_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */ 917*f1c0a02fSMark Brown #define WM8903_SPKVU 0x0080 /* SPKVU */ 918*f1c0a02fSMark Brown #define WM8903_SPKVU_MASK 0x0080 /* SPKVU */ 919*f1c0a02fSMark Brown #define WM8903_SPKVU_SHIFT 7 /* SPKVU */ 920*f1c0a02fSMark Brown #define WM8903_SPKVU_WIDTH 1 /* SPKVU */ 921*f1c0a02fSMark Brown #define WM8903_SPKLZC 0x0040 /* SPKLZC */ 922*f1c0a02fSMark Brown #define WM8903_SPKLZC_MASK 0x0040 /* SPKLZC */ 923*f1c0a02fSMark Brown #define WM8903_SPKLZC_SHIFT 6 /* SPKLZC */ 924*f1c0a02fSMark Brown #define WM8903_SPKLZC_WIDTH 1 /* SPKLZC */ 925*f1c0a02fSMark Brown #define WM8903_SPKL_VOL_MASK 0x003F /* SPKL_VOL - [5:0] */ 926*f1c0a02fSMark Brown #define WM8903_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [5:0] */ 927*f1c0a02fSMark Brown #define WM8903_SPKL_VOL_WIDTH 6 /* SPKL_VOL - [5:0] */ 928*f1c0a02fSMark Brown 929*f1c0a02fSMark Brown /* 930*f1c0a02fSMark Brown * R63 (0x3F) - Analogue OUT3 Right 931*f1c0a02fSMark Brown */ 932*f1c0a02fSMark Brown #define WM8903_SPKR_MUTE 0x0100 /* SPKR_MUTE */ 933*f1c0a02fSMark Brown #define WM8903_SPKR_MUTE_MASK 0x0100 /* SPKR_MUTE */ 934*f1c0a02fSMark Brown #define WM8903_SPKR_MUTE_SHIFT 8 /* SPKR_MUTE */ 935*f1c0a02fSMark Brown #define WM8903_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */ 936*f1c0a02fSMark Brown #define WM8903_SPKVU 0x0080 /* SPKVU */ 937*f1c0a02fSMark Brown #define WM8903_SPKVU_MASK 0x0080 /* SPKVU */ 938*f1c0a02fSMark Brown #define WM8903_SPKVU_SHIFT 7 /* SPKVU */ 939*f1c0a02fSMark Brown #define WM8903_SPKVU_WIDTH 1 /* SPKVU */ 940*f1c0a02fSMark Brown #define WM8903_SPKRZC 0x0040 /* SPKRZC */ 941*f1c0a02fSMark Brown #define WM8903_SPKRZC_MASK 0x0040 /* SPKRZC */ 942*f1c0a02fSMark Brown #define WM8903_SPKRZC_SHIFT 6 /* SPKRZC */ 943*f1c0a02fSMark Brown #define WM8903_SPKRZC_WIDTH 1 /* SPKRZC */ 944*f1c0a02fSMark Brown #define WM8903_SPKR_VOL_MASK 0x003F /* SPKR_VOL - [5:0] */ 945*f1c0a02fSMark Brown #define WM8903_SPKR_VOL_SHIFT 0 /* SPKR_VOL - [5:0] */ 946*f1c0a02fSMark Brown #define WM8903_SPKR_VOL_WIDTH 6 /* SPKR_VOL - [5:0] */ 947*f1c0a02fSMark Brown 948*f1c0a02fSMark Brown /* 949*f1c0a02fSMark Brown * R65 (0x41) - Analogue SPK Output Control 0 950*f1c0a02fSMark Brown */ 951*f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE 0x0002 /* SPK_DISCHARGE */ 952*f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE_MASK 0x0002 /* SPK_DISCHARGE */ 953*f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE_SHIFT 1 /* SPK_DISCHARGE */ 954*f1c0a02fSMark Brown #define WM8903_SPK_DISCHARGE_WIDTH 1 /* SPK_DISCHARGE */ 955*f1c0a02fSMark Brown #define WM8903_VROI 0x0001 /* VROI */ 956*f1c0a02fSMark Brown #define WM8903_VROI_MASK 0x0001 /* VROI */ 957*f1c0a02fSMark Brown #define WM8903_VROI_SHIFT 0 /* VROI */ 958*f1c0a02fSMark Brown #define WM8903_VROI_WIDTH 1 /* VROI */ 959*f1c0a02fSMark Brown 960*f1c0a02fSMark Brown /* 961*f1c0a02fSMark Brown * R67 (0x43) - DC Servo 0 962*f1c0a02fSMark Brown */ 963*f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA 0x0010 /* DCS_MASTER_ENA */ 964*f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA_MASK 0x0010 /* DCS_MASTER_ENA */ 965*f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA_SHIFT 4 /* DCS_MASTER_ENA */ 966*f1c0a02fSMark Brown #define WM8903_DCS_MASTER_ENA_WIDTH 1 /* DCS_MASTER_ENA */ 967*f1c0a02fSMark Brown #define WM8903_DCS_ENA_MASK 0x000F /* DCS_ENA - [3:0] */ 968*f1c0a02fSMark Brown #define WM8903_DCS_ENA_SHIFT 0 /* DCS_ENA - [3:0] */ 969*f1c0a02fSMark Brown #define WM8903_DCS_ENA_WIDTH 4 /* DCS_ENA - [3:0] */ 970*f1c0a02fSMark Brown 971*f1c0a02fSMark Brown /* 972*f1c0a02fSMark Brown * R69 (0x45) - DC Servo 2 973*f1c0a02fSMark Brown */ 974*f1c0a02fSMark Brown #define WM8903_DCS_MODE_MASK 0x0003 /* DCS_MODE - [1:0] */ 975*f1c0a02fSMark Brown #define WM8903_DCS_MODE_SHIFT 0 /* DCS_MODE - [1:0] */ 976*f1c0a02fSMark Brown #define WM8903_DCS_MODE_WIDTH 2 /* DCS_MODE - [1:0] */ 977*f1c0a02fSMark Brown 978*f1c0a02fSMark Brown /* 979*f1c0a02fSMark Brown * R90 (0x5A) - Analogue HP 0 980*f1c0a02fSMark Brown */ 981*f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 982*f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 983*f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 984*f1c0a02fSMark Brown #define WM8903_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 985*f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 986*f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 987*f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 988*f1c0a02fSMark Brown #define WM8903_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 989*f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 990*f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 991*f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 992*f1c0a02fSMark Brown #define WM8903_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 993*f1c0a02fSMark Brown #define WM8903_HPL_ENA 0x0010 /* HPL_ENA */ 994*f1c0a02fSMark Brown #define WM8903_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 995*f1c0a02fSMark Brown #define WM8903_HPL_ENA_SHIFT 4 /* HPL_ENA */ 996*f1c0a02fSMark Brown #define WM8903_HPL_ENA_WIDTH 1 /* HPL_ENA */ 997*f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 998*f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 999*f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 1000*f1c0a02fSMark Brown #define WM8903_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 1001*f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 1002*f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 1003*f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 1004*f1c0a02fSMark Brown #define WM8903_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 1005*f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ 1006*f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 1007*f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 1008*f1c0a02fSMark Brown #define WM8903_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 1009*f1c0a02fSMark Brown #define WM8903_HPR_ENA 0x0001 /* HPR_ENA */ 1010*f1c0a02fSMark Brown #define WM8903_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 1011*f1c0a02fSMark Brown #define WM8903_HPR_ENA_SHIFT 0 /* HPR_ENA */ 1012*f1c0a02fSMark Brown #define WM8903_HPR_ENA_WIDTH 1 /* HPR_ENA */ 1013*f1c0a02fSMark Brown 1014*f1c0a02fSMark Brown /* 1015*f1c0a02fSMark Brown * R94 (0x5E) - Analogue Lineout 0 1016*f1c0a02fSMark Brown */ 1017*f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */ 1018*f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */ 1019*f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */ 1020*f1c0a02fSMark Brown #define WM8903_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */ 1021*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */ 1022*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */ 1023*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */ 1024*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */ 1025*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */ 1026*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */ 1027*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */ 1028*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */ 1029*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */ 1030*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */ 1031*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */ 1032*f1c0a02fSMark Brown #define WM8903_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */ 1033*f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */ 1034*f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */ 1035*f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */ 1036*f1c0a02fSMark Brown #define WM8903_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */ 1037*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */ 1038*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */ 1039*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */ 1040*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */ 1041*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */ 1042*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */ 1043*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */ 1044*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */ 1045*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */ 1046*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */ 1047*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */ 1048*f1c0a02fSMark Brown #define WM8903_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */ 1049*f1c0a02fSMark Brown 1050*f1c0a02fSMark Brown /* 1051*f1c0a02fSMark Brown * R98 (0x62) - Charge Pump 0 1052*f1c0a02fSMark Brown */ 1053*f1c0a02fSMark Brown #define WM8903_CP_ENA 0x0001 /* CP_ENA */ 1054*f1c0a02fSMark Brown #define WM8903_CP_ENA_MASK 0x0001 /* CP_ENA */ 1055*f1c0a02fSMark Brown #define WM8903_CP_ENA_SHIFT 0 /* CP_ENA */ 1056*f1c0a02fSMark Brown #define WM8903_CP_ENA_WIDTH 1 /* CP_ENA */ 1057*f1c0a02fSMark Brown 1058*f1c0a02fSMark Brown /* 1059*f1c0a02fSMark Brown * R104 (0x68) - Class W 0 1060*f1c0a02fSMark Brown */ 1061*f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ 0x0002 /* CP_DYN_FREQ */ 1062*f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ_MASK 0x0002 /* CP_DYN_FREQ */ 1063*f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ_SHIFT 1 /* CP_DYN_FREQ */ 1064*f1c0a02fSMark Brown #define WM8903_CP_DYN_FREQ_WIDTH 1 /* CP_DYN_FREQ */ 1065*f1c0a02fSMark Brown #define WM8903_CP_DYN_V 0x0001 /* CP_DYN_V */ 1066*f1c0a02fSMark Brown #define WM8903_CP_DYN_V_MASK 0x0001 /* CP_DYN_V */ 1067*f1c0a02fSMark Brown #define WM8903_CP_DYN_V_SHIFT 0 /* CP_DYN_V */ 1068*f1c0a02fSMark Brown #define WM8903_CP_DYN_V_WIDTH 1 /* CP_DYN_V */ 1069*f1c0a02fSMark Brown 1070*f1c0a02fSMark Brown /* 1071*f1c0a02fSMark Brown * R108 (0x6C) - Write Sequencer 0 1072*f1c0a02fSMark Brown */ 1073*f1c0a02fSMark Brown #define WM8903_WSEQ_ENA 0x0100 /* WSEQ_ENA */ 1074*f1c0a02fSMark Brown #define WM8903_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */ 1075*f1c0a02fSMark Brown #define WM8903_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */ 1076*f1c0a02fSMark Brown #define WM8903_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1077*f1c0a02fSMark Brown #define WM8903_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 1078*f1c0a02fSMark Brown #define WM8903_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 1079*f1c0a02fSMark Brown #define WM8903_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 1080*f1c0a02fSMark Brown 1081*f1c0a02fSMark Brown /* 1082*f1c0a02fSMark Brown * R109 (0x6D) - Write Sequencer 1 1083*f1c0a02fSMark Brown */ 1084*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */ 1085*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */ 1086*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */ 1087*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */ 1088*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */ 1089*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */ 1090*f1c0a02fSMark Brown #define WM8903_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 1091*f1c0a02fSMark Brown #define WM8903_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 1092*f1c0a02fSMark Brown #define WM8903_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 1093*f1c0a02fSMark Brown 1094*f1c0a02fSMark Brown /* 1095*f1c0a02fSMark Brown * R110 (0x6E) - Write Sequencer 2 1096*f1c0a02fSMark Brown */ 1097*f1c0a02fSMark Brown #define WM8903_WSEQ_EOS 0x4000 /* WSEQ_EOS */ 1098*f1c0a02fSMark Brown #define WM8903_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */ 1099*f1c0a02fSMark Brown #define WM8903_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */ 1100*f1c0a02fSMark Brown #define WM8903_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 1101*f1c0a02fSMark Brown #define WM8903_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */ 1102*f1c0a02fSMark Brown #define WM8903_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */ 1103*f1c0a02fSMark Brown #define WM8903_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */ 1104*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 1105*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 1106*f1c0a02fSMark Brown #define WM8903_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 1107*f1c0a02fSMark Brown 1108*f1c0a02fSMark Brown /* 1109*f1c0a02fSMark Brown * R111 (0x6F) - Write Sequencer 3 1110*f1c0a02fSMark Brown */ 1111*f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1112*f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1113*f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1114*f1c0a02fSMark Brown #define WM8903_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1115*f1c0a02fSMark Brown #define WM8903_WSEQ_START 0x0100 /* WSEQ_START */ 1116*f1c0a02fSMark Brown #define WM8903_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1117*f1c0a02fSMark Brown #define WM8903_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1118*f1c0a02fSMark Brown #define WM8903_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1119*f1c0a02fSMark Brown #define WM8903_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 1120*f1c0a02fSMark Brown #define WM8903_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 1121*f1c0a02fSMark Brown #define WM8903_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 1122*f1c0a02fSMark Brown 1123*f1c0a02fSMark Brown /* 1124*f1c0a02fSMark Brown * R112 (0x70) - Write Sequencer 4 1125*f1c0a02fSMark Brown */ 1126*f1c0a02fSMark Brown #define WM8903_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */ 1127*f1c0a02fSMark Brown #define WM8903_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */ 1128*f1c0a02fSMark Brown #define WM8903_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */ 1129*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 1130*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 1131*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 1132*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1133*f1c0a02fSMark Brown 1134*f1c0a02fSMark Brown /* 1135*f1c0a02fSMark Brown * R114 (0x72) - Control Interface 1136*f1c0a02fSMark Brown */ 1137*f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA 0x0001 /* MASK_WRITE_ENA */ 1138*f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA_MASK 0x0001 /* MASK_WRITE_ENA */ 1139*f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA_SHIFT 0 /* MASK_WRITE_ENA */ 1140*f1c0a02fSMark Brown #define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */ 1141*f1c0a02fSMark Brown 1142*f1c0a02fSMark Brown /* 1143*f1c0a02fSMark Brown * R116 (0x74) - GPIO Control 1 1144*f1c0a02fSMark Brown */ 1145*f1c0a02fSMark Brown #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ 1146*f1c0a02fSMark Brown #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ 1147*f1c0a02fSMark Brown #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ 1148*f1c0a02fSMark Brown #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ 1149*f1c0a02fSMark Brown #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ 1150*f1c0a02fSMark Brown #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ 1151*f1c0a02fSMark Brown #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ 1152*f1c0a02fSMark Brown #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ 1153*f1c0a02fSMark Brown #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ 1154*f1c0a02fSMark Brown #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ 1155*f1c0a02fSMark Brown #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 1156*f1c0a02fSMark Brown #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ 1157*f1c0a02fSMark Brown #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ 1158*f1c0a02fSMark Brown #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ 1159*f1c0a02fSMark Brown #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ 1160*f1c0a02fSMark Brown #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ 1161*f1c0a02fSMark Brown #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ 1162*f1c0a02fSMark Brown #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ 1163*f1c0a02fSMark Brown #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ 1164*f1c0a02fSMark Brown #define WM8903_GP1_PD 0x0008 /* GP1_PD */ 1165*f1c0a02fSMark Brown #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ 1166*f1c0a02fSMark Brown #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ 1167*f1c0a02fSMark Brown #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ 1168*f1c0a02fSMark Brown #define WM8903_GP1_PU 0x0004 /* GP1_PU */ 1169*f1c0a02fSMark Brown #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ 1170*f1c0a02fSMark Brown #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ 1171*f1c0a02fSMark Brown #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ 1172*f1c0a02fSMark Brown #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ 1173*f1c0a02fSMark Brown #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ 1174*f1c0a02fSMark Brown #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ 1175*f1c0a02fSMark Brown #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ 1176*f1c0a02fSMark Brown #define WM8903_GP1_DB 0x0001 /* GP1_DB */ 1177*f1c0a02fSMark Brown #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ 1178*f1c0a02fSMark Brown #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ 1179*f1c0a02fSMark Brown #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ 1180*f1c0a02fSMark Brown 1181*f1c0a02fSMark Brown /* 1182*f1c0a02fSMark Brown * R117 (0x75) - GPIO Control 2 1183*f1c0a02fSMark Brown */ 1184*f1c0a02fSMark Brown #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ 1185*f1c0a02fSMark Brown #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ 1186*f1c0a02fSMark Brown #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ 1187*f1c0a02fSMark Brown #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ 1188*f1c0a02fSMark Brown #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ 1189*f1c0a02fSMark Brown #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ 1190*f1c0a02fSMark Brown #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ 1191*f1c0a02fSMark Brown #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ 1192*f1c0a02fSMark Brown #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ 1193*f1c0a02fSMark Brown #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ 1194*f1c0a02fSMark Brown #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 1195*f1c0a02fSMark Brown #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ 1196*f1c0a02fSMark Brown #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ 1197*f1c0a02fSMark Brown #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ 1198*f1c0a02fSMark Brown #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ 1199*f1c0a02fSMark Brown #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ 1200*f1c0a02fSMark Brown #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ 1201*f1c0a02fSMark Brown #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ 1202*f1c0a02fSMark Brown #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ 1203*f1c0a02fSMark Brown #define WM8903_GP2_PD 0x0008 /* GP2_PD */ 1204*f1c0a02fSMark Brown #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ 1205*f1c0a02fSMark Brown #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ 1206*f1c0a02fSMark Brown #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ 1207*f1c0a02fSMark Brown #define WM8903_GP2_PU 0x0004 /* GP2_PU */ 1208*f1c0a02fSMark Brown #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ 1209*f1c0a02fSMark Brown #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ 1210*f1c0a02fSMark Brown #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ 1211*f1c0a02fSMark Brown #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ 1212*f1c0a02fSMark Brown #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ 1213*f1c0a02fSMark Brown #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ 1214*f1c0a02fSMark Brown #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ 1215*f1c0a02fSMark Brown #define WM8903_GP2_DB 0x0001 /* GP2_DB */ 1216*f1c0a02fSMark Brown #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ 1217*f1c0a02fSMark Brown #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ 1218*f1c0a02fSMark Brown #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ 1219*f1c0a02fSMark Brown 1220*f1c0a02fSMark Brown /* 1221*f1c0a02fSMark Brown * R118 (0x76) - GPIO Control 3 1222*f1c0a02fSMark Brown */ 1223*f1c0a02fSMark Brown #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ 1224*f1c0a02fSMark Brown #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ 1225*f1c0a02fSMark Brown #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ 1226*f1c0a02fSMark Brown #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ 1227*f1c0a02fSMark Brown #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ 1228*f1c0a02fSMark Brown #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ 1229*f1c0a02fSMark Brown #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ 1230*f1c0a02fSMark Brown #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ 1231*f1c0a02fSMark Brown #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ 1232*f1c0a02fSMark Brown #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ 1233*f1c0a02fSMark Brown #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 1234*f1c0a02fSMark Brown #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ 1235*f1c0a02fSMark Brown #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ 1236*f1c0a02fSMark Brown #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ 1237*f1c0a02fSMark Brown #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ 1238*f1c0a02fSMark Brown #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ 1239*f1c0a02fSMark Brown #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ 1240*f1c0a02fSMark Brown #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ 1241*f1c0a02fSMark Brown #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ 1242*f1c0a02fSMark Brown #define WM8903_GP3_PD 0x0008 /* GP3_PD */ 1243*f1c0a02fSMark Brown #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ 1244*f1c0a02fSMark Brown #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ 1245*f1c0a02fSMark Brown #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ 1246*f1c0a02fSMark Brown #define WM8903_GP3_PU 0x0004 /* GP3_PU */ 1247*f1c0a02fSMark Brown #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ 1248*f1c0a02fSMark Brown #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ 1249*f1c0a02fSMark Brown #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ 1250*f1c0a02fSMark Brown #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ 1251*f1c0a02fSMark Brown #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ 1252*f1c0a02fSMark Brown #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ 1253*f1c0a02fSMark Brown #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ 1254*f1c0a02fSMark Brown #define WM8903_GP3_DB 0x0001 /* GP3_DB */ 1255*f1c0a02fSMark Brown #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ 1256*f1c0a02fSMark Brown #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ 1257*f1c0a02fSMark Brown #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ 1258*f1c0a02fSMark Brown 1259*f1c0a02fSMark Brown /* 1260*f1c0a02fSMark Brown * R119 (0x77) - GPIO Control 4 1261*f1c0a02fSMark Brown */ 1262*f1c0a02fSMark Brown #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ 1263*f1c0a02fSMark Brown #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ 1264*f1c0a02fSMark Brown #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ 1265*f1c0a02fSMark Brown #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ 1266*f1c0a02fSMark Brown #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ 1267*f1c0a02fSMark Brown #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ 1268*f1c0a02fSMark Brown #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ 1269*f1c0a02fSMark Brown #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ 1270*f1c0a02fSMark Brown #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ 1271*f1c0a02fSMark Brown #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ 1272*f1c0a02fSMark Brown #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 1273*f1c0a02fSMark Brown #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ 1274*f1c0a02fSMark Brown #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ 1275*f1c0a02fSMark Brown #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ 1276*f1c0a02fSMark Brown #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ 1277*f1c0a02fSMark Brown #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ 1278*f1c0a02fSMark Brown #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ 1279*f1c0a02fSMark Brown #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ 1280*f1c0a02fSMark Brown #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ 1281*f1c0a02fSMark Brown #define WM8903_GP4_PD 0x0008 /* GP4_PD */ 1282*f1c0a02fSMark Brown #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ 1283*f1c0a02fSMark Brown #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ 1284*f1c0a02fSMark Brown #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ 1285*f1c0a02fSMark Brown #define WM8903_GP4_PU 0x0004 /* GP4_PU */ 1286*f1c0a02fSMark Brown #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ 1287*f1c0a02fSMark Brown #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ 1288*f1c0a02fSMark Brown #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ 1289*f1c0a02fSMark Brown #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ 1290*f1c0a02fSMark Brown #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ 1291*f1c0a02fSMark Brown #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ 1292*f1c0a02fSMark Brown #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ 1293*f1c0a02fSMark Brown #define WM8903_GP4_DB 0x0001 /* GP4_DB */ 1294*f1c0a02fSMark Brown #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ 1295*f1c0a02fSMark Brown #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ 1296*f1c0a02fSMark Brown #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ 1297*f1c0a02fSMark Brown 1298*f1c0a02fSMark Brown /* 1299*f1c0a02fSMark Brown * R120 (0x78) - GPIO Control 5 1300*f1c0a02fSMark Brown */ 1301*f1c0a02fSMark Brown #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ 1302*f1c0a02fSMark Brown #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ 1303*f1c0a02fSMark Brown #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ 1304*f1c0a02fSMark Brown #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ 1305*f1c0a02fSMark Brown #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ 1306*f1c0a02fSMark Brown #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ 1307*f1c0a02fSMark Brown #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ 1308*f1c0a02fSMark Brown #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ 1309*f1c0a02fSMark Brown #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ 1310*f1c0a02fSMark Brown #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ 1311*f1c0a02fSMark Brown #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 1312*f1c0a02fSMark Brown #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ 1313*f1c0a02fSMark Brown #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ 1314*f1c0a02fSMark Brown #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ 1315*f1c0a02fSMark Brown #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ 1316*f1c0a02fSMark Brown #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ 1317*f1c0a02fSMark Brown #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ 1318*f1c0a02fSMark Brown #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ 1319*f1c0a02fSMark Brown #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ 1320*f1c0a02fSMark Brown #define WM8903_GP5_PD 0x0008 /* GP5_PD */ 1321*f1c0a02fSMark Brown #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ 1322*f1c0a02fSMark Brown #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ 1323*f1c0a02fSMark Brown #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ 1324*f1c0a02fSMark Brown #define WM8903_GP5_PU 0x0004 /* GP5_PU */ 1325*f1c0a02fSMark Brown #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ 1326*f1c0a02fSMark Brown #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ 1327*f1c0a02fSMark Brown #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ 1328*f1c0a02fSMark Brown #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ 1329*f1c0a02fSMark Brown #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ 1330*f1c0a02fSMark Brown #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ 1331*f1c0a02fSMark Brown #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ 1332*f1c0a02fSMark Brown #define WM8903_GP5_DB 0x0001 /* GP5_DB */ 1333*f1c0a02fSMark Brown #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ 1334*f1c0a02fSMark Brown #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ 1335*f1c0a02fSMark Brown #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ 1336*f1c0a02fSMark Brown 1337*f1c0a02fSMark Brown /* 1338*f1c0a02fSMark Brown * R121 (0x79) - Interrupt Status 1 1339*f1c0a02fSMark Brown */ 1340*f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */ 1341*f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT_MASK 0x8000 /* MICSHRT_EINT */ 1342*f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT_SHIFT 15 /* MICSHRT_EINT */ 1343*f1c0a02fSMark Brown #define WM8903_MICSHRT_EINT_WIDTH 1 /* MICSHRT_EINT */ 1344*f1c0a02fSMark Brown #define WM8903_MICDET_EINT 0x4000 /* MICDET_EINT */ 1345*f1c0a02fSMark Brown #define WM8903_MICDET_EINT_MASK 0x4000 /* MICDET_EINT */ 1346*f1c0a02fSMark Brown #define WM8903_MICDET_EINT_SHIFT 14 /* MICDET_EINT */ 1347*f1c0a02fSMark Brown #define WM8903_MICDET_EINT_WIDTH 1 /* MICDET_EINT */ 1348*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT 0x2000 /* WSEQ_BUSY_EINT */ 1349*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT_MASK 0x2000 /* WSEQ_BUSY_EINT */ 1350*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT_SHIFT 13 /* WSEQ_BUSY_EINT */ 1351*f1c0a02fSMark Brown #define WM8903_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ 1352*f1c0a02fSMark Brown #define WM8903_GP5_EINT 0x0010 /* GP5_EINT */ 1353*f1c0a02fSMark Brown #define WM8903_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 1354*f1c0a02fSMark Brown #define WM8903_GP5_EINT_SHIFT 4 /* GP5_EINT */ 1355*f1c0a02fSMark Brown #define WM8903_GP5_EINT_WIDTH 1 /* GP5_EINT */ 1356*f1c0a02fSMark Brown #define WM8903_GP4_EINT 0x0008 /* GP4_EINT */ 1357*f1c0a02fSMark Brown #define WM8903_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 1358*f1c0a02fSMark Brown #define WM8903_GP4_EINT_SHIFT 3 /* GP4_EINT */ 1359*f1c0a02fSMark Brown #define WM8903_GP4_EINT_WIDTH 1 /* GP4_EINT */ 1360*f1c0a02fSMark Brown #define WM8903_GP3_EINT 0x0004 /* GP3_EINT */ 1361*f1c0a02fSMark Brown #define WM8903_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 1362*f1c0a02fSMark Brown #define WM8903_GP3_EINT_SHIFT 2 /* GP3_EINT */ 1363*f1c0a02fSMark Brown #define WM8903_GP3_EINT_WIDTH 1 /* GP3_EINT */ 1364*f1c0a02fSMark Brown #define WM8903_GP2_EINT 0x0002 /* GP2_EINT */ 1365*f1c0a02fSMark Brown #define WM8903_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 1366*f1c0a02fSMark Brown #define WM8903_GP2_EINT_SHIFT 1 /* GP2_EINT */ 1367*f1c0a02fSMark Brown #define WM8903_GP2_EINT_WIDTH 1 /* GP2_EINT */ 1368*f1c0a02fSMark Brown #define WM8903_GP1_EINT 0x0001 /* GP1_EINT */ 1369*f1c0a02fSMark Brown #define WM8903_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 1370*f1c0a02fSMark Brown #define WM8903_GP1_EINT_SHIFT 0 /* GP1_EINT */ 1371*f1c0a02fSMark Brown #define WM8903_GP1_EINT_WIDTH 1 /* GP1_EINT */ 1372*f1c0a02fSMark Brown 1373*f1c0a02fSMark Brown /* 1374*f1c0a02fSMark Brown * R122 (0x7A) - Interrupt Status 1 Mask 1375*f1c0a02fSMark Brown */ 1376*f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT 0x8000 /* IM_MICSHRT_EINT */ 1377*f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT_MASK 0x8000 /* IM_MICSHRT_EINT */ 1378*f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT_SHIFT 15 /* IM_MICSHRT_EINT */ 1379*f1c0a02fSMark Brown #define WM8903_IM_MICSHRT_EINT_WIDTH 1 /* IM_MICSHRT_EINT */ 1380*f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT 0x4000 /* IM_MICDET_EINT */ 1381*f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT_MASK 0x4000 /* IM_MICDET_EINT */ 1382*f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT_SHIFT 14 /* IM_MICDET_EINT */ 1383*f1c0a02fSMark Brown #define WM8903_IM_MICDET_EINT_WIDTH 1 /* IM_MICDET_EINT */ 1384*f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT 0x2000 /* IM_WSEQ_BUSY_EINT */ 1385*f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT_MASK 0x2000 /* IM_WSEQ_BUSY_EINT */ 1386*f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT_SHIFT 13 /* IM_WSEQ_BUSY_EINT */ 1387*f1c0a02fSMark Brown #define WM8903_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ 1388*f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 1389*f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 1390*f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 1391*f1c0a02fSMark Brown #define WM8903_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 1392*f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 1393*f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 1394*f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 1395*f1c0a02fSMark Brown #define WM8903_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 1396*f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 1397*f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 1398*f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 1399*f1c0a02fSMark Brown #define WM8903_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 1400*f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 1401*f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 1402*f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 1403*f1c0a02fSMark Brown #define WM8903_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 1404*f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 1405*f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 1406*f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 1407*f1c0a02fSMark Brown #define WM8903_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 1408*f1c0a02fSMark Brown 1409*f1c0a02fSMark Brown /* 1410*f1c0a02fSMark Brown * R123 (0x7B) - Interrupt Polarity 1 1411*f1c0a02fSMark Brown */ 1412*f1c0a02fSMark Brown #define WM8903_MICSHRT_INV 0x8000 /* MICSHRT_INV */ 1413*f1c0a02fSMark Brown #define WM8903_MICSHRT_INV_MASK 0x8000 /* MICSHRT_INV */ 1414*f1c0a02fSMark Brown #define WM8903_MICSHRT_INV_SHIFT 15 /* MICSHRT_INV */ 1415*f1c0a02fSMark Brown #define WM8903_MICSHRT_INV_WIDTH 1 /* MICSHRT_INV */ 1416*f1c0a02fSMark Brown #define WM8903_MICDET_INV 0x4000 /* MICDET_INV */ 1417*f1c0a02fSMark Brown #define WM8903_MICDET_INV_MASK 0x4000 /* MICDET_INV */ 1418*f1c0a02fSMark Brown #define WM8903_MICDET_INV_SHIFT 14 /* MICDET_INV */ 1419*f1c0a02fSMark Brown #define WM8903_MICDET_INV_WIDTH 1 /* MICDET_INV */ 1420*f1c0a02fSMark Brown 1421*f1c0a02fSMark Brown /* 1422*f1c0a02fSMark Brown * R126 (0x7E) - Interrupt Control 1423*f1c0a02fSMark Brown */ 1424*f1c0a02fSMark Brown #define WM8903_IRQ_POL 0x0001 /* IRQ_POL */ 1425*f1c0a02fSMark Brown #define WM8903_IRQ_POL_MASK 0x0001 /* IRQ_POL */ 1426*f1c0a02fSMark Brown #define WM8903_IRQ_POL_SHIFT 0 /* IRQ_POL */ 1427*f1c0a02fSMark Brown #define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ 1428*f1c0a02fSMark Brown 1429*f1c0a02fSMark Brown /* 1430*f1c0a02fSMark Brown * R129 (0x81) - Control Interface Test 1 1431*f1c0a02fSMark Brown */ 1432*f1c0a02fSMark Brown #define WM8903_USER_KEY 0x0002 /* USER_KEY */ 1433*f1c0a02fSMark Brown #define WM8903_USER_KEY_MASK 0x0002 /* USER_KEY */ 1434*f1c0a02fSMark Brown #define WM8903_USER_KEY_SHIFT 1 /* USER_KEY */ 1435*f1c0a02fSMark Brown #define WM8903_USER_KEY_WIDTH 1 /* USER_KEY */ 1436*f1c0a02fSMark Brown #define WM8903_TEST_KEY 0x0001 /* TEST_KEY */ 1437*f1c0a02fSMark Brown #define WM8903_TEST_KEY_MASK 0x0001 /* TEST_KEY */ 1438*f1c0a02fSMark Brown #define WM8903_TEST_KEY_SHIFT 0 /* TEST_KEY */ 1439*f1c0a02fSMark Brown #define WM8903_TEST_KEY_WIDTH 1 /* TEST_KEY */ 1440*f1c0a02fSMark Brown 1441*f1c0a02fSMark Brown /* 1442*f1c0a02fSMark Brown * R149 (0x95) - Charge Pump Test 1 1443*f1c0a02fSMark Brown */ 1444*f1c0a02fSMark Brown #define WM8903_CP_SW_KELVIN_MODE_MASK 0x0006 /* CP_SW_KELVIN_MODE - [2:1] */ 1445*f1c0a02fSMark Brown #define WM8903_CP_SW_KELVIN_MODE_SHIFT 1 /* CP_SW_KELVIN_MODE - [2:1] */ 1446*f1c0a02fSMark Brown #define WM8903_CP_SW_KELVIN_MODE_WIDTH 2 /* CP_SW_KELVIN_MODE - [2:1] */ 1447*f1c0a02fSMark Brown 1448*f1c0a02fSMark Brown /* 1449*f1c0a02fSMark Brown * R164 (0xA4) - Clock Rate Test 4 1450*f1c0a02fSMark Brown */ 1451*f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */ 1452*f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC_MASK 0x0200 /* ADC_DIG_MIC */ 1453*f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC_SHIFT 9 /* ADC_DIG_MIC */ 1454*f1c0a02fSMark Brown #define WM8903_ADC_DIG_MIC_WIDTH 1 /* ADC_DIG_MIC */ 1455*f1c0a02fSMark Brown 1456*f1c0a02fSMark Brown /* 1457*f1c0a02fSMark Brown * R172 (0xAC) - Analogue Output Bias 0 1458*f1c0a02fSMark Brown */ 1459*f1c0a02fSMark Brown #define WM8903_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */ 1460*f1c0a02fSMark Brown #define WM8903_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */ 1461*f1c0a02fSMark Brown #define WM8903_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */ 1462*f1c0a02fSMark Brown 1463*f1c0a02fSMark Brown #endif 1464