1 /* 2 * wm8400.c -- WM8400 ALSA Soc Audio driver 3 * 4 * Copyright 2008-11 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/pm.h> 21 #include <linux/platform_device.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/mfd/wm8400-audio.h> 24 #include <linux/mfd/wm8400-private.h> 25 #include <linux/mfd/core.h> 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 33 #include "wm8400.h" 34 35 static struct regulator_bulk_data power[] = { 36 { 37 .supply = "I2S1VDD", 38 }, 39 { 40 .supply = "I2S2VDD", 41 }, 42 { 43 .supply = "DCVDD", 44 }, 45 { 46 .supply = "AVDD", 47 }, 48 { 49 .supply = "FLLVDD", 50 }, 51 { 52 .supply = "HPVDD", 53 }, 54 { 55 .supply = "SPKVDD", 56 }, 57 }; 58 59 /* codec private data */ 60 struct wm8400_priv { 61 struct snd_soc_codec *codec; 62 struct wm8400 *wm8400; 63 u16 fake_register; 64 unsigned int sysclk; 65 unsigned int pcmclk; 66 struct work_struct work; 67 int fll_in, fll_out; 68 }; 69 70 static void wm8400_codec_reset(struct snd_soc_codec *codec) 71 { 72 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 73 74 wm8400_reset_codec_reg_cache(wm8400->wm8400); 75 } 76 77 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); 78 79 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); 80 81 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0); 82 83 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); 84 85 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); 86 87 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); 88 89 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); 90 91 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); 92 93 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 94 struct snd_ctl_elem_value *ucontrol) 95 { 96 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 97 struct soc_mixer_control *mc = 98 (struct soc_mixer_control *)kcontrol->private_value; 99 int reg = mc->reg; 100 int ret; 101 u16 val; 102 103 ret = snd_soc_put_volsw(kcontrol, ucontrol); 104 if (ret < 0) 105 return ret; 106 107 /* now hit the volume update bits (always bit 8) */ 108 val = snd_soc_read(codec, reg); 109 return snd_soc_write(codec, reg, val | 0x0100); 110 } 111 112 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ 113 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ 114 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array) 115 116 117 static const char *wm8400_digital_sidetone[] = 118 {"None", "Left ADC", "Right ADC", "Reserved"}; 119 120 static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum, 121 WM8400_DIGITAL_SIDE_TONE, 122 WM8400_ADC_TO_DACL_SHIFT, 123 wm8400_digital_sidetone); 124 125 static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum, 126 WM8400_DIGITAL_SIDE_TONE, 127 WM8400_ADC_TO_DACR_SHIFT, 128 wm8400_digital_sidetone); 129 130 static const char *wm8400_adcmode[] = 131 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 132 133 static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum, 134 WM8400_ADC_CTRL, 135 WM8400_ADC_HPF_CUT_SHIFT, 136 wm8400_adcmode); 137 138 static const struct snd_kcontrol_new wm8400_snd_controls[] = { 139 /* INMIXL */ 140 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT, 141 1, 0), 142 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT, 143 1, 0), 144 /* INMIXR */ 145 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT, 146 1, 0), 147 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT, 148 1, 0), 149 150 /* LOMIX */ 151 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3, 152 WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv), 153 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, 154 WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv), 155 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, 156 WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv), 157 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5, 158 WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv), 159 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5, 160 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), 161 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5, 162 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), 163 164 /* ROMIX */ 165 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4, 166 WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv), 167 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, 168 WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv), 169 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, 170 WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv), 171 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6, 172 WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv), 173 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6, 174 WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv), 175 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6, 176 WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv), 177 178 /* LOUT */ 179 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME, 180 WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv), 181 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0), 182 183 /* ROUT */ 184 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME, 185 WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv), 186 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0), 187 188 /* LOPGA */ 189 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME, 190 WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv), 191 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME, 192 WM8400_LOPGAZC_SHIFT, 1, 0), 193 194 /* ROPGA */ 195 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME, 196 WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv), 197 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME, 198 WM8400_ROPGAZC_SHIFT, 1, 0), 199 200 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 201 WM8400_LONMUTE_SHIFT, 1, 0), 202 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 203 WM8400_LOPMUTE_SHIFT, 1, 0), 204 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, 205 WM8400_LOATTN_SHIFT, 1, 0), 206 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 207 WM8400_RONMUTE_SHIFT, 1, 0), 208 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, 209 WM8400_ROPMUTE_SHIFT, 1, 0), 210 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, 211 WM8400_ROATTN_SHIFT, 1, 0), 212 213 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME, 214 WM8400_OUT3MUTE_SHIFT, 1, 0), 215 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME, 216 WM8400_OUT3ATTN_SHIFT, 1, 0), 217 218 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME, 219 WM8400_OUT4MUTE_SHIFT, 1, 0), 220 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME, 221 WM8400_OUT4ATTN_SHIFT, 1, 0), 222 223 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1, 224 WM8400_CDMODE_SHIFT, 1, 0), 225 226 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME, 227 WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0), 228 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3, 229 WM8400_DCGAIN_SHIFT, 6, 0), 230 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3, 231 WM8400_ACGAIN_SHIFT, 6, 0), 232 233 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 234 WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT, 235 127, 0, out_dac_tlv), 236 237 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 238 WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT, 239 127, 0, out_dac_tlv), 240 241 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum), 242 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum), 243 244 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, 245 WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), 246 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, 247 WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), 248 249 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL, 250 WM8400_ADC_HPF_ENA_SHIFT, 1, 0), 251 252 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum), 253 254 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 255 WM8400_LEFT_ADC_DIGITAL_VOLUME, 256 WM8400_ADCL_VOL_SHIFT, 257 WM8400_ADCL_VOL_MASK, 258 0, 259 in_adc_tlv), 260 261 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 262 WM8400_RIGHT_ADC_DIGITAL_VOLUME, 263 WM8400_ADCR_VOL_SHIFT, 264 WM8400_ADCR_VOL_MASK, 265 0, 266 in_adc_tlv), 267 268 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 269 WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 270 WM8400_LIN12VOL_SHIFT, 271 WM8400_LIN12VOL_MASK, 272 0, 273 in_pga_tlv), 274 275 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 276 WM8400_LI12ZC_SHIFT, 1, 0), 277 278 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 279 WM8400_LI12MUTE_SHIFT, 1, 0), 280 281 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 282 WM8400_LEFT_LINE_INPUT_3_4_VOLUME, 283 WM8400_LIN34VOL_SHIFT, 284 WM8400_LIN34VOL_MASK, 285 0, 286 in_pga_tlv), 287 288 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, 289 WM8400_LI34ZC_SHIFT, 1, 0), 290 291 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, 292 WM8400_LI34MUTE_SHIFT, 1, 0), 293 294 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 295 WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 296 WM8400_RIN12VOL_SHIFT, 297 WM8400_RIN12VOL_MASK, 298 0, 299 in_pga_tlv), 300 301 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 302 WM8400_RI12ZC_SHIFT, 1, 0), 303 304 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 305 WM8400_RI12MUTE_SHIFT, 1, 0), 306 307 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 308 WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, 309 WM8400_RIN34VOL_SHIFT, 310 WM8400_RIN34VOL_MASK, 311 0, 312 in_pga_tlv), 313 314 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, 315 WM8400_RI34ZC_SHIFT, 1, 0), 316 317 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, 318 WM8400_RI34MUTE_SHIFT, 1, 0), 319 320 }; 321 322 /* 323 * _DAPM_ Controls 324 */ 325 326 static int outmixer_event (struct snd_soc_dapm_widget *w, 327 struct snd_kcontrol * kcontrol, int event) 328 { 329 struct soc_mixer_control *mc = 330 (struct soc_mixer_control *)kcontrol->private_value; 331 u32 reg_shift = mc->shift; 332 int ret = 0; 333 u16 reg; 334 335 switch (reg_shift) { 336 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) : 337 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER1); 338 if (reg & WM8400_LDLO) { 339 printk(KERN_WARNING 340 "Cannot set as Output Mixer 1 LDLO Set\n"); 341 ret = -1; 342 } 343 break; 344 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8): 345 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER2); 346 if (reg & WM8400_RDRO) { 347 printk(KERN_WARNING 348 "Cannot set as Output Mixer 2 RDRO Set\n"); 349 ret = -1; 350 } 351 break; 352 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8): 353 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER); 354 if (reg & WM8400_LDSPK) { 355 printk(KERN_WARNING 356 "Cannot set as Speaker Mixer LDSPK Set\n"); 357 ret = -1; 358 } 359 break; 360 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8): 361 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER); 362 if (reg & WM8400_RDSPK) { 363 printk(KERN_WARNING 364 "Cannot set as Speaker Mixer RDSPK Set\n"); 365 ret = -1; 366 } 367 break; 368 } 369 370 return ret; 371 } 372 373 /* INMIX dB values */ 374 static const unsigned int in_mix_tlv[] = { 375 TLV_DB_RANGE_HEAD(1), 376 0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0), 377 }; 378 379 /* Left In PGA Connections */ 380 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = { 381 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0), 382 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0), 383 }; 384 385 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = { 386 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0), 387 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0), 388 }; 389 390 /* Right In PGA Connections */ 391 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = { 392 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0), 393 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0), 394 }; 395 396 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = { 397 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0), 398 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0), 399 }; 400 401 /* INMIXL */ 402 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = { 403 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3, 404 WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv), 405 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT, 406 7, 0, in_mix_tlv), 407 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, 408 1, 0), 409 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, 410 1, 0), 411 }; 412 413 /* INMIXR */ 414 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = { 415 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4, 416 WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv), 417 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT, 418 7, 0, in_mix_tlv), 419 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, 420 1, 0), 421 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, 422 1, 0), 423 }; 424 425 /* AINLMUX */ 426 static const char *wm8400_ainlmux[] = 427 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 428 429 static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum, 430 WM8400_INPUT_MIXER1, 431 WM8400_AINLMODE_SHIFT, 432 wm8400_ainlmux); 433 434 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls = 435 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum); 436 437 /* DIFFINL */ 438 439 /* AINRMUX */ 440 static const char *wm8400_ainrmux[] = 441 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 442 443 static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum, 444 WM8400_INPUT_MIXER1, 445 WM8400_AINRMODE_SHIFT, 446 wm8400_ainrmux); 447 448 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls = 449 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum); 450 451 /* RXVOICE */ 452 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = { 453 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT, 454 WM8400_LR4BVOL_MASK, 0, in_mix_tlv), 455 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT, 456 WM8400_RL4BVOL_MASK, 0, in_mix_tlv), 457 }; 458 459 /* LOMIX */ 460 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = { 461 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1, 462 WM8400_LRBLO_SHIFT, 1, 0), 463 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1, 464 WM8400_LLBLO_SHIFT, 1, 0), 465 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, 466 WM8400_LRI3LO_SHIFT, 1, 0), 467 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, 468 WM8400_LLI3LO_SHIFT, 1, 0), 469 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, 470 WM8400_LR12LO_SHIFT, 1, 0), 471 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, 472 WM8400_LL12LO_SHIFT, 1, 0), 473 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1, 474 WM8400_LDLO_SHIFT, 1, 0), 475 }; 476 477 /* ROMIX */ 478 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = { 479 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2, 480 WM8400_RLBRO_SHIFT, 1, 0), 481 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2, 482 WM8400_RRBRO_SHIFT, 1, 0), 483 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, 484 WM8400_RLI3RO_SHIFT, 1, 0), 485 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, 486 WM8400_RRI3RO_SHIFT, 1, 0), 487 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, 488 WM8400_RL12RO_SHIFT, 1, 0), 489 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, 490 WM8400_RR12RO_SHIFT, 1, 0), 491 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2, 492 WM8400_RDRO_SHIFT, 1, 0), 493 }; 494 495 /* LONMIX */ 496 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = { 497 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, 498 WM8400_LLOPGALON_SHIFT, 1, 0), 499 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1, 500 WM8400_LROPGALON_SHIFT, 1, 0), 501 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1, 502 WM8400_LOPLON_SHIFT, 1, 0), 503 }; 504 505 /* LOPMIX */ 506 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = { 507 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1, 508 WM8400_LR12LOP_SHIFT, 1, 0), 509 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1, 510 WM8400_LL12LOP_SHIFT, 1, 0), 511 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, 512 WM8400_LLOPGALOP_SHIFT, 1, 0), 513 }; 514 515 /* RONMIX */ 516 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = { 517 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, 518 WM8400_RROPGARON_SHIFT, 1, 0), 519 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2, 520 WM8400_RLOPGARON_SHIFT, 1, 0), 521 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2, 522 WM8400_ROPRON_SHIFT, 1, 0), 523 }; 524 525 /* ROPMIX */ 526 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = { 527 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2, 528 WM8400_RL12ROP_SHIFT, 1, 0), 529 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2, 530 WM8400_RR12ROP_SHIFT, 1, 0), 531 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, 532 WM8400_RROPGAROP_SHIFT, 1, 0), 533 }; 534 535 /* OUT3MIX */ 536 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = { 537 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, 538 WM8400_LI4O3_SHIFT, 1, 0), 539 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER, 540 WM8400_LPGAO3_SHIFT, 1, 0), 541 }; 542 543 /* OUT4MIX */ 544 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = { 545 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER, 546 WM8400_RPGAO4_SHIFT, 1, 0), 547 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, 548 WM8400_RI4O4_SHIFT, 1, 0), 549 }; 550 551 /* SPKMIX */ 552 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = { 553 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER, 554 WM8400_LI2SPK_SHIFT, 1, 0), 555 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER, 556 WM8400_LB2SPK_SHIFT, 1, 0), 557 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER, 558 WM8400_LOPGASPK_SHIFT, 1, 0), 559 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER, 560 WM8400_LDSPK_SHIFT, 1, 0), 561 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER, 562 WM8400_RDSPK_SHIFT, 1, 0), 563 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER, 564 WM8400_ROPGASPK_SHIFT, 1, 0), 565 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER, 566 WM8400_RL12ROP_SHIFT, 1, 0), 567 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER, 568 WM8400_RI2SPK_SHIFT, 1, 0), 569 }; 570 571 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = { 572 /* Input Side */ 573 /* Input Lines */ 574 SND_SOC_DAPM_INPUT("LIN1"), 575 SND_SOC_DAPM_INPUT("LIN2"), 576 SND_SOC_DAPM_INPUT("LIN3"), 577 SND_SOC_DAPM_INPUT("LIN4/RXN"), 578 SND_SOC_DAPM_INPUT("RIN3"), 579 SND_SOC_DAPM_INPUT("RIN4/RXP"), 580 SND_SOC_DAPM_INPUT("RIN1"), 581 SND_SOC_DAPM_INPUT("RIN2"), 582 SND_SOC_DAPM_INPUT("Internal ADC Source"), 583 584 /* DACs */ 585 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2, 586 WM8400_ADCL_ENA_SHIFT, 0), 587 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2, 588 WM8400_ADCR_ENA_SHIFT, 0), 589 590 /* Input PGAs */ 591 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2, 592 WM8400_LIN12_ENA_SHIFT, 593 0, &wm8400_dapm_lin12_pga_controls[0], 594 ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)), 595 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2, 596 WM8400_LIN34_ENA_SHIFT, 597 0, &wm8400_dapm_lin34_pga_controls[0], 598 ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)), 599 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2, 600 WM8400_RIN12_ENA_SHIFT, 601 0, &wm8400_dapm_rin12_pga_controls[0], 602 ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)), 603 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2, 604 WM8400_RIN34_ENA_SHIFT, 605 0, &wm8400_dapm_rin34_pga_controls[0], 606 ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)), 607 608 SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT, 609 0, NULL, 0), 610 SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT, 611 0, NULL, 0), 612 613 /* INMIXL */ 614 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0, 615 &wm8400_dapm_inmixl_controls[0], 616 ARRAY_SIZE(wm8400_dapm_inmixl_controls)), 617 618 /* AINLMUX */ 619 SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls), 620 621 /* INMIXR */ 622 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0, 623 &wm8400_dapm_inmixr_controls[0], 624 ARRAY_SIZE(wm8400_dapm_inmixr_controls)), 625 626 /* AINRMUX */ 627 SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls), 628 629 /* Output Side */ 630 /* DACs */ 631 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3, 632 WM8400_DACL_ENA_SHIFT, 0), 633 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3, 634 WM8400_DACR_ENA_SHIFT, 0), 635 636 /* LOMIX */ 637 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3, 638 WM8400_LOMIX_ENA_SHIFT, 639 0, &wm8400_dapm_lomix_controls[0], 640 ARRAY_SIZE(wm8400_dapm_lomix_controls), 641 outmixer_event, SND_SOC_DAPM_PRE_REG), 642 643 /* LONMIX */ 644 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT, 645 0, &wm8400_dapm_lonmix_controls[0], 646 ARRAY_SIZE(wm8400_dapm_lonmix_controls)), 647 648 /* LOPMIX */ 649 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT, 650 0, &wm8400_dapm_lopmix_controls[0], 651 ARRAY_SIZE(wm8400_dapm_lopmix_controls)), 652 653 /* OUT3MIX */ 654 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT, 655 0, &wm8400_dapm_out3mix_controls[0], 656 ARRAY_SIZE(wm8400_dapm_out3mix_controls)), 657 658 /* SPKMIX */ 659 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT, 660 0, &wm8400_dapm_spkmix_controls[0], 661 ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event, 662 SND_SOC_DAPM_PRE_REG), 663 664 /* OUT4MIX */ 665 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT, 666 0, &wm8400_dapm_out4mix_controls[0], 667 ARRAY_SIZE(wm8400_dapm_out4mix_controls)), 668 669 /* ROPMIX */ 670 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT, 671 0, &wm8400_dapm_ropmix_controls[0], 672 ARRAY_SIZE(wm8400_dapm_ropmix_controls)), 673 674 /* RONMIX */ 675 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT, 676 0, &wm8400_dapm_ronmix_controls[0], 677 ARRAY_SIZE(wm8400_dapm_ronmix_controls)), 678 679 /* ROMIX */ 680 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3, 681 WM8400_ROMIX_ENA_SHIFT, 682 0, &wm8400_dapm_romix_controls[0], 683 ARRAY_SIZE(wm8400_dapm_romix_controls), 684 outmixer_event, SND_SOC_DAPM_PRE_REG), 685 686 /* LOUT PGA */ 687 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT, 688 0, NULL, 0), 689 690 /* ROUT PGA */ 691 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT, 692 0, NULL, 0), 693 694 /* LOPGA */ 695 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0, 696 NULL, 0), 697 698 /* ROPGA */ 699 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0, 700 NULL, 0), 701 702 /* MICBIAS */ 703 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1, 704 WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0), 705 706 SND_SOC_DAPM_OUTPUT("LON"), 707 SND_SOC_DAPM_OUTPUT("LOP"), 708 SND_SOC_DAPM_OUTPUT("OUT3"), 709 SND_SOC_DAPM_OUTPUT("LOUT"), 710 SND_SOC_DAPM_OUTPUT("SPKN"), 711 SND_SOC_DAPM_OUTPUT("SPKP"), 712 SND_SOC_DAPM_OUTPUT("ROUT"), 713 SND_SOC_DAPM_OUTPUT("OUT4"), 714 SND_SOC_DAPM_OUTPUT("ROP"), 715 SND_SOC_DAPM_OUTPUT("RON"), 716 717 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 718 }; 719 720 static const struct snd_soc_dapm_route wm8400_dapm_routes[] = { 721 /* Make DACs turn on when playing even if not mixed into any outputs */ 722 {"Internal DAC Sink", NULL, "Left DAC"}, 723 {"Internal DAC Sink", NULL, "Right DAC"}, 724 725 /* Make ADCs turn on when recording 726 * even if not mixed from any inputs */ 727 {"Left ADC", NULL, "Internal ADC Source"}, 728 {"Right ADC", NULL, "Internal ADC Source"}, 729 730 /* Input Side */ 731 /* LIN12 PGA */ 732 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 733 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 734 /* LIN34 PGA */ 735 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 736 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, 737 /* INMIXL */ 738 {"INMIXL", NULL, "INL"}, 739 {"INMIXL", "Record Left Volume", "LOMIX"}, 740 {"INMIXL", "LIN2 Volume", "LIN2"}, 741 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 742 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 743 /* AILNMUX */ 744 {"AILNMUX", NULL, "INL"}, 745 {"AILNMUX", "INMIXL Mix", "INMIXL"}, 746 {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"}, 747 {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"}, 748 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"}, 749 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"}, 750 /* ADC */ 751 {"Left ADC", NULL, "AILNMUX"}, 752 753 /* RIN12 PGA */ 754 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 755 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 756 /* RIN34 PGA */ 757 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 758 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, 759 /* INMIXR */ 760 {"INMIXR", NULL, "INR"}, 761 {"INMIXR", "Record Right Volume", "ROMIX"}, 762 {"INMIXR", "RIN2 Volume", "RIN2"}, 763 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 764 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 765 /* AIRNMUX */ 766 {"AIRNMUX", NULL, "INR"}, 767 {"AIRNMUX", "INMIXR Mix", "INMIXR"}, 768 {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"}, 769 {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"}, 770 {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"}, 771 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"}, 772 /* ADC */ 773 {"Right ADC", NULL, "AIRNMUX"}, 774 775 /* LOMIX */ 776 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 777 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 778 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 779 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 780 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"}, 781 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"}, 782 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 783 784 /* ROMIX */ 785 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 786 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 787 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 788 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 789 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"}, 790 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"}, 791 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 792 793 /* SPKMIX */ 794 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 795 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 796 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"}, 797 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"}, 798 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 799 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 800 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 801 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, 802 803 /* LONMIX */ 804 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 805 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 806 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 807 808 /* LOPMIX */ 809 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 810 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 811 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 812 813 /* OUT3MIX */ 814 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, 815 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 816 817 /* OUT4MIX */ 818 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 819 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, 820 821 /* RONMIX */ 822 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 823 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 824 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 825 826 /* ROPMIX */ 827 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 828 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 829 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 830 831 /* Out Mixer PGAs */ 832 {"LOPGA", NULL, "LOMIX"}, 833 {"ROPGA", NULL, "ROMIX"}, 834 835 {"LOUT PGA", NULL, "LOMIX"}, 836 {"ROUT PGA", NULL, "ROMIX"}, 837 838 /* Output Pins */ 839 {"LON", NULL, "LONMIX"}, 840 {"LOP", NULL, "LOPMIX"}, 841 {"OUT3", NULL, "OUT3MIX"}, 842 {"LOUT", NULL, "LOUT PGA"}, 843 {"SPKN", NULL, "SPKMIX"}, 844 {"ROUT", NULL, "ROUT PGA"}, 845 {"OUT4", NULL, "OUT4MIX"}, 846 {"ROP", NULL, "ROPMIX"}, 847 {"RON", NULL, "RONMIX"}, 848 }; 849 850 /* 851 * Clock after FLL and dividers 852 */ 853 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai, 854 int clk_id, unsigned int freq, int dir) 855 { 856 struct snd_soc_codec *codec = codec_dai->codec; 857 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 858 859 wm8400->sysclk = freq; 860 return 0; 861 } 862 863 struct fll_factors { 864 u16 n; 865 u16 k; 866 u16 outdiv; 867 u16 fratio; 868 u16 freq_ref; 869 }; 870 871 #define FIXED_FLL_SIZE ((1 << 16) * 10) 872 873 static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors, 874 unsigned int Fref, unsigned int Fout) 875 { 876 u64 Kpart; 877 unsigned int K, Nmod, target; 878 879 factors->outdiv = 2; 880 while (Fout * factors->outdiv < 90000000 || 881 Fout * factors->outdiv > 100000000) { 882 factors->outdiv *= 2; 883 if (factors->outdiv > 32) { 884 dev_err(wm8400->wm8400->dev, 885 "Unsupported FLL output frequency %uHz\n", 886 Fout); 887 return -EINVAL; 888 } 889 } 890 target = Fout * factors->outdiv; 891 factors->outdiv = factors->outdiv >> 2; 892 893 if (Fref < 48000) 894 factors->freq_ref = 1; 895 else 896 factors->freq_ref = 0; 897 898 if (Fref < 1000000) 899 factors->fratio = 9; 900 else 901 factors->fratio = 0; 902 903 /* Ensure we have a fractional part */ 904 do { 905 if (Fref < 1000000) 906 factors->fratio--; 907 else 908 factors->fratio++; 909 910 if (factors->fratio < 1 || factors->fratio > 8) { 911 dev_err(wm8400->wm8400->dev, 912 "Unable to calculate FRATIO\n"); 913 return -EINVAL; 914 } 915 916 factors->n = target / (Fref * factors->fratio); 917 Nmod = target % (Fref * factors->fratio); 918 } while (Nmod == 0); 919 920 /* Calculate fractional part - scale up so we can round. */ 921 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 922 923 do_div(Kpart, (Fref * factors->fratio)); 924 925 K = Kpart & 0xFFFFFFFF; 926 927 if ((K % 10) >= 5) 928 K += 5; 929 930 /* Move down to proper range now rounding is done */ 931 factors->k = K / 10; 932 933 dev_dbg(wm8400->wm8400->dev, 934 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n", 935 Fref, Fout, 936 factors->n, factors->k, factors->fratio, factors->outdiv); 937 938 return 0; 939 } 940 941 static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 942 int source, unsigned int freq_in, 943 unsigned int freq_out) 944 { 945 struct snd_soc_codec *codec = codec_dai->codec; 946 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 947 struct fll_factors factors; 948 int ret; 949 u16 reg; 950 951 if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out) 952 return 0; 953 954 if (freq_out) { 955 ret = fll_factors(wm8400, &factors, freq_in, freq_out); 956 if (ret != 0) 957 return ret; 958 } else { 959 /* Bodge GCC 4.4.0 uninitialised variable warning - it 960 * doesn't seem capable of working out that we exit if 961 * freq_out is 0 before any of the uses. */ 962 memset(&factors, 0, sizeof(factors)); 963 } 964 965 wm8400->fll_out = freq_out; 966 wm8400->fll_in = freq_in; 967 968 /* We *must* disable the FLL before any changes */ 969 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2); 970 reg &= ~WM8400_FLL_ENA; 971 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg); 972 973 reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1); 974 reg &= ~WM8400_FLL_OSC_ENA; 975 snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg); 976 977 if (!freq_out) 978 return 0; 979 980 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK); 981 reg |= WM8400_FLL_FRAC | factors.fratio; 982 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT; 983 snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg); 984 985 snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k); 986 snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n); 987 988 reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4); 989 reg &= ~WM8400_FLL_OUTDIV_MASK; 990 reg |= factors.outdiv; 991 snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg); 992 993 return 0; 994 } 995 996 /* 997 * Sets ADC and Voice DAC format. 998 */ 999 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai, 1000 unsigned int fmt) 1001 { 1002 struct snd_soc_codec *codec = codec_dai->codec; 1003 u16 audio1, audio3; 1004 1005 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1); 1006 audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3); 1007 1008 /* set master/slave audio interface */ 1009 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1010 case SND_SOC_DAIFMT_CBS_CFS: 1011 audio3 &= ~WM8400_AIF_MSTR1; 1012 break; 1013 case SND_SOC_DAIFMT_CBM_CFM: 1014 audio3 |= WM8400_AIF_MSTR1; 1015 break; 1016 default: 1017 return -EINVAL; 1018 } 1019 1020 audio1 &= ~WM8400_AIF_FMT_MASK; 1021 1022 /* interface format */ 1023 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1024 case SND_SOC_DAIFMT_I2S: 1025 audio1 |= WM8400_AIF_FMT_I2S; 1026 audio1 &= ~WM8400_AIF_LRCLK_INV; 1027 break; 1028 case SND_SOC_DAIFMT_RIGHT_J: 1029 audio1 |= WM8400_AIF_FMT_RIGHTJ; 1030 audio1 &= ~WM8400_AIF_LRCLK_INV; 1031 break; 1032 case SND_SOC_DAIFMT_LEFT_J: 1033 audio1 |= WM8400_AIF_FMT_LEFTJ; 1034 audio1 &= ~WM8400_AIF_LRCLK_INV; 1035 break; 1036 case SND_SOC_DAIFMT_DSP_A: 1037 audio1 |= WM8400_AIF_FMT_DSP; 1038 audio1 &= ~WM8400_AIF_LRCLK_INV; 1039 break; 1040 case SND_SOC_DAIFMT_DSP_B: 1041 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV; 1042 break; 1043 default: 1044 return -EINVAL; 1045 } 1046 1047 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); 1048 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3); 1049 return 0; 1050 } 1051 1052 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1053 int div_id, int div) 1054 { 1055 struct snd_soc_codec *codec = codec_dai->codec; 1056 u16 reg; 1057 1058 switch (div_id) { 1059 case WM8400_MCLK_DIV: 1060 reg = snd_soc_read(codec, WM8400_CLOCKING_2) & 1061 ~WM8400_MCLK_DIV_MASK; 1062 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); 1063 break; 1064 case WM8400_DACCLK_DIV: 1065 reg = snd_soc_read(codec, WM8400_CLOCKING_2) & 1066 ~WM8400_DAC_CLKDIV_MASK; 1067 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); 1068 break; 1069 case WM8400_ADCCLK_DIV: 1070 reg = snd_soc_read(codec, WM8400_CLOCKING_2) & 1071 ~WM8400_ADC_CLKDIV_MASK; 1072 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); 1073 break; 1074 case WM8400_BCLK_DIV: 1075 reg = snd_soc_read(codec, WM8400_CLOCKING_1) & 1076 ~WM8400_BCLK_DIV_MASK; 1077 snd_soc_write(codec, WM8400_CLOCKING_1, reg | div); 1078 break; 1079 default: 1080 return -EINVAL; 1081 } 1082 1083 return 0; 1084 } 1085 1086 /* 1087 * Set PCM DAI bit size and sample rate. 1088 */ 1089 static int wm8400_hw_params(struct snd_pcm_substream *substream, 1090 struct snd_pcm_hw_params *params, 1091 struct snd_soc_dai *dai) 1092 { 1093 struct snd_soc_codec *codec = dai->codec; 1094 u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1); 1095 1096 audio1 &= ~WM8400_AIF_WL_MASK; 1097 /* bit size */ 1098 switch (params_format(params)) { 1099 case SNDRV_PCM_FORMAT_S16_LE: 1100 break; 1101 case SNDRV_PCM_FORMAT_S20_3LE: 1102 audio1 |= WM8400_AIF_WL_20BITS; 1103 break; 1104 case SNDRV_PCM_FORMAT_S24_LE: 1105 audio1 |= WM8400_AIF_WL_24BITS; 1106 break; 1107 case SNDRV_PCM_FORMAT_S32_LE: 1108 audio1 |= WM8400_AIF_WL_32BITS; 1109 break; 1110 } 1111 1112 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); 1113 return 0; 1114 } 1115 1116 static int wm8400_mute(struct snd_soc_dai *dai, int mute) 1117 { 1118 struct snd_soc_codec *codec = dai->codec; 1119 u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE; 1120 1121 if (mute) 1122 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); 1123 else 1124 snd_soc_write(codec, WM8400_DAC_CTRL, val); 1125 1126 return 0; 1127 } 1128 1129 /* TODO: set bias for best performance at standby */ 1130 static int wm8400_set_bias_level(struct snd_soc_codec *codec, 1131 enum snd_soc_bias_level level) 1132 { 1133 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); 1134 u16 val; 1135 int ret; 1136 1137 switch (level) { 1138 case SND_SOC_BIAS_ON: 1139 break; 1140 1141 case SND_SOC_BIAS_PREPARE: 1142 /* VMID=2*50k */ 1143 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & 1144 ~WM8400_VMID_MODE_MASK; 1145 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2); 1146 break; 1147 1148 case SND_SOC_BIAS_STANDBY: 1149 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1150 ret = regulator_bulk_enable(ARRAY_SIZE(power), 1151 &power[0]); 1152 if (ret != 0) { 1153 dev_err(wm8400->wm8400->dev, 1154 "Failed to enable regulators: %d\n", 1155 ret); 1156 return ret; 1157 } 1158 1159 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, 1160 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA); 1161 1162 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1163 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1164 WM8400_BUFDCOPEN | WM8400_POBCTRL); 1165 1166 msleep(50); 1167 1168 /* Enable VREF & VMID at 2x50k */ 1169 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); 1170 val |= 0x2 | WM8400_VREF_ENA; 1171 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1172 1173 /* Enable BUFIOEN */ 1174 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1175 WM8400_BUFDCOPEN | WM8400_POBCTRL | 1176 WM8400_BUFIOEN); 1177 1178 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1179 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN); 1180 } 1181 1182 /* VMID=2*300k */ 1183 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & 1184 ~WM8400_VMID_MODE_MASK; 1185 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4); 1186 break; 1187 1188 case SND_SOC_BIAS_OFF: 1189 /* Enable POBCTRL and SOFT_ST */ 1190 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1191 WM8400_POBCTRL | WM8400_BUFIOEN); 1192 1193 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1194 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1195 WM8400_BUFDCOPEN | WM8400_POBCTRL | 1196 WM8400_BUFIOEN); 1197 1198 /* mute DAC */ 1199 val = snd_soc_read(codec, WM8400_DAC_CTRL); 1200 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); 1201 1202 /* Enable any disabled outputs */ 1203 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); 1204 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA | 1205 WM8400_OUT4_ENA | WM8400_LOUT_ENA | 1206 WM8400_ROUT_ENA; 1207 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1208 1209 /* Disable VMID */ 1210 val &= ~WM8400_VMID_MODE_MASK; 1211 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1212 1213 msleep(300); 1214 1215 /* Enable all output discharge bits */ 1216 snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE | 1217 WM8400_DIS_RLINE | WM8400_DIS_OUT3 | 1218 WM8400_DIS_OUT4 | WM8400_DIS_LOUT | 1219 WM8400_DIS_ROUT); 1220 1221 /* Disable VREF */ 1222 val &= ~WM8400_VREF_ENA; 1223 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1224 1225 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1226 snd_soc_write(codec, WM8400_ANTIPOP2, 0x0); 1227 1228 ret = regulator_bulk_disable(ARRAY_SIZE(power), 1229 &power[0]); 1230 if (ret != 0) 1231 return ret; 1232 1233 break; 1234 } 1235 1236 codec->dapm.bias_level = level; 1237 return 0; 1238 } 1239 1240 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000 1241 1242 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1243 SNDRV_PCM_FMTBIT_S24_LE) 1244 1245 static const struct snd_soc_dai_ops wm8400_dai_ops = { 1246 .hw_params = wm8400_hw_params, 1247 .digital_mute = wm8400_mute, 1248 .set_fmt = wm8400_set_dai_fmt, 1249 .set_clkdiv = wm8400_set_dai_clkdiv, 1250 .set_sysclk = wm8400_set_dai_sysclk, 1251 .set_pll = wm8400_set_dai_pll, 1252 }; 1253 1254 /* 1255 * The WM8400 supports 2 different and mutually exclusive DAI 1256 * configurations. 1257 * 1258 * 1. ADC/DAC on Primary Interface 1259 * 2. ADC on Primary Interface/DAC on secondary 1260 */ 1261 static struct snd_soc_dai_driver wm8400_dai = { 1262 /* ADC/DAC on primary */ 1263 .name = "wm8400-hifi", 1264 .playback = { 1265 .stream_name = "Playback", 1266 .channels_min = 1, 1267 .channels_max = 2, 1268 .rates = WM8400_RATES, 1269 .formats = WM8400_FORMATS, 1270 }, 1271 .capture = { 1272 .stream_name = "Capture", 1273 .channels_min = 1, 1274 .channels_max = 2, 1275 .rates = WM8400_RATES, 1276 .formats = WM8400_FORMATS, 1277 }, 1278 .ops = &wm8400_dai_ops, 1279 }; 1280 1281 static int wm8400_suspend(struct snd_soc_codec *codec) 1282 { 1283 wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF); 1284 1285 return 0; 1286 } 1287 1288 static int wm8400_resume(struct snd_soc_codec *codec) 1289 { 1290 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1291 1292 return 0; 1293 } 1294 1295 static void wm8400_probe_deferred(struct work_struct *work) 1296 { 1297 struct wm8400_priv *priv = container_of(work, struct wm8400_priv, 1298 work); 1299 struct snd_soc_codec *codec = priv->codec; 1300 1301 /* charge output caps */ 1302 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1303 } 1304 1305 static int wm8400_codec_probe(struct snd_soc_codec *codec) 1306 { 1307 struct wm8400 *wm8400 = dev_get_platdata(codec->dev); 1308 struct wm8400_priv *priv; 1309 int ret; 1310 u16 reg; 1311 1312 priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv), 1313 GFP_KERNEL); 1314 if (priv == NULL) 1315 return -ENOMEM; 1316 1317 snd_soc_codec_set_drvdata(codec, priv); 1318 priv->wm8400 = wm8400; 1319 priv->codec = codec; 1320 1321 ret = devm_regulator_bulk_get(wm8400->dev, 1322 ARRAY_SIZE(power), &power[0]); 1323 if (ret != 0) { 1324 dev_err(codec->dev, "Failed to get regulators: %d\n", ret); 1325 return ret; 1326 } 1327 1328 INIT_WORK(&priv->work, wm8400_probe_deferred); 1329 1330 wm8400_codec_reset(codec); 1331 1332 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); 1333 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA); 1334 1335 /* Latch volume update bits */ 1336 reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME); 1337 snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 1338 reg & WM8400_IPVU); 1339 reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME); 1340 snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 1341 reg & WM8400_IPVU); 1342 1343 snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1344 snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1345 1346 if (!schedule_work(&priv->work)) 1347 return -EINVAL; 1348 return 0; 1349 } 1350 1351 static int wm8400_codec_remove(struct snd_soc_codec *codec) 1352 { 1353 u16 reg; 1354 1355 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); 1356 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, 1357 reg & (~WM8400_CODEC_ENA)); 1358 1359 return 0; 1360 } 1361 1362 static struct regmap *wm8400_get_regmap(struct device *dev) 1363 { 1364 struct wm8400 *wm8400 = dev_get_platdata(dev); 1365 1366 return wm8400->regmap; 1367 } 1368 1369 static struct snd_soc_codec_driver soc_codec_dev_wm8400 = { 1370 .probe = wm8400_codec_probe, 1371 .remove = wm8400_codec_remove, 1372 .suspend = wm8400_suspend, 1373 .resume = wm8400_resume, 1374 .get_regmap = wm8400_get_regmap, 1375 .set_bias_level = wm8400_set_bias_level, 1376 1377 .controls = wm8400_snd_controls, 1378 .num_controls = ARRAY_SIZE(wm8400_snd_controls), 1379 .dapm_widgets = wm8400_dapm_widgets, 1380 .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets), 1381 .dapm_routes = wm8400_dapm_routes, 1382 .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes), 1383 }; 1384 1385 static int wm8400_probe(struct platform_device *pdev) 1386 { 1387 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400, 1388 &wm8400_dai, 1); 1389 } 1390 1391 static int wm8400_remove(struct platform_device *pdev) 1392 { 1393 snd_soc_unregister_codec(&pdev->dev); 1394 return 0; 1395 } 1396 1397 static struct platform_driver wm8400_codec_driver = { 1398 .driver = { 1399 .name = "wm8400-codec", 1400 .owner = THIS_MODULE, 1401 }, 1402 .probe = wm8400_probe, 1403 .remove = wm8400_remove, 1404 }; 1405 1406 module_platform_driver(wm8400_codec_driver); 1407 1408 MODULE_DESCRIPTION("ASoC WM8400 driver"); 1409 MODULE_AUTHOR("Mark Brown"); 1410 MODULE_LICENSE("GPL"); 1411 MODULE_ALIAS("platform:wm8400-codec"); 1412