1 /* 2 * wm8350.c -- WM8350 ALSA SoC audio driver 3 * 4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC. 5 * 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/platform_device.h> 20 #include <linux/mfd/wm8350/audio.h> 21 #include <linux/mfd/wm8350/core.h> 22 #include <linux/regulator/consumer.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <trace/events/asoc.h> 30 31 #include "wm8350.h" 32 33 #define WM8350_OUTn_0dB 0x39 34 35 #define WM8350_RAMP_NONE 0 36 #define WM8350_RAMP_UP 1 37 #define WM8350_RAMP_DOWN 2 38 39 /* We only include the analogue supplies here; the digital supplies 40 * need to be available well before this driver can be probed. 41 */ 42 static const char *supply_names[] = { 43 "AVDD", 44 "HPVDD", 45 }; 46 47 struct wm8350_output { 48 u16 active; 49 u16 left_vol; 50 u16 right_vol; 51 u16 ramp; 52 u16 mute; 53 }; 54 55 struct wm8350_jack_data { 56 struct snd_soc_jack *jack; 57 struct delayed_work work; 58 int report; 59 int short_report; 60 }; 61 62 struct wm8350_data { 63 struct wm8350 *wm8350; 64 struct wm8350_output out1; 65 struct wm8350_output out2; 66 struct wm8350_jack_data hpl; 67 struct wm8350_jack_data hpr; 68 struct wm8350_jack_data mic; 69 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 70 int fll_freq_out; 71 int fll_freq_in; 72 }; 73 74 static unsigned int wm8350_codec_read(struct snd_soc_codec *codec, 75 unsigned int reg) 76 { 77 struct wm8350 *wm8350 = codec->control_data; 78 return wm8350_reg_read(wm8350, reg); 79 } 80 81 static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg, 82 unsigned int value) 83 { 84 struct wm8350 *wm8350 = codec->control_data; 85 return wm8350_reg_write(wm8350, reg, value); 86 } 87 88 /* 89 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown. 90 */ 91 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec) 92 { 93 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 94 struct wm8350_output *out1 = &wm8350_data->out1; 95 struct wm8350 *wm8350 = wm8350_data->wm8350; 96 int left_complete = 0, right_complete = 0; 97 u16 reg, val; 98 99 /* left channel */ 100 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME); 101 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 102 103 if (out1->ramp == WM8350_RAMP_UP) { 104 /* ramp step up */ 105 if (val < out1->left_vol) { 106 val++; 107 reg &= ~WM8350_OUT1L_VOL_MASK; 108 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 109 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 110 } else 111 left_complete = 1; 112 } else if (out1->ramp == WM8350_RAMP_DOWN) { 113 /* ramp step down */ 114 if (val > 0) { 115 val--; 116 reg &= ~WM8350_OUT1L_VOL_MASK; 117 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 118 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 119 } else 120 left_complete = 1; 121 } else 122 return 1; 123 124 /* right channel */ 125 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME); 126 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 127 if (out1->ramp == WM8350_RAMP_UP) { 128 /* ramp step up */ 129 if (val < out1->right_vol) { 130 val++; 131 reg &= ~WM8350_OUT1R_VOL_MASK; 132 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 133 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 134 } else 135 right_complete = 1; 136 } else if (out1->ramp == WM8350_RAMP_DOWN) { 137 /* ramp step down */ 138 if (val > 0) { 139 val--; 140 reg &= ~WM8350_OUT1R_VOL_MASK; 141 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 142 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 143 } else 144 right_complete = 1; 145 } 146 147 /* only hit the update bit if either volume has changed this step */ 148 if (!left_complete || !right_complete) 149 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU); 150 151 return left_complete & right_complete; 152 } 153 154 /* 155 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown. 156 */ 157 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec) 158 { 159 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 160 struct wm8350_output *out2 = &wm8350_data->out2; 161 struct wm8350 *wm8350 = wm8350_data->wm8350; 162 int left_complete = 0, right_complete = 0; 163 u16 reg, val; 164 165 /* left channel */ 166 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME); 167 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 168 if (out2->ramp == WM8350_RAMP_UP) { 169 /* ramp step up */ 170 if (val < out2->left_vol) { 171 val++; 172 reg &= ~WM8350_OUT2L_VOL_MASK; 173 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 174 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 175 } else 176 left_complete = 1; 177 } else if (out2->ramp == WM8350_RAMP_DOWN) { 178 /* ramp step down */ 179 if (val > 0) { 180 val--; 181 reg &= ~WM8350_OUT2L_VOL_MASK; 182 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 183 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 184 } else 185 left_complete = 1; 186 } else 187 return 1; 188 189 /* right channel */ 190 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME); 191 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 192 if (out2->ramp == WM8350_RAMP_UP) { 193 /* ramp step up */ 194 if (val < out2->right_vol) { 195 val++; 196 reg &= ~WM8350_OUT2R_VOL_MASK; 197 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 198 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 199 } else 200 right_complete = 1; 201 } else if (out2->ramp == WM8350_RAMP_DOWN) { 202 /* ramp step down */ 203 if (val > 0) { 204 val--; 205 reg &= ~WM8350_OUT2R_VOL_MASK; 206 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 207 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 208 } else 209 right_complete = 1; 210 } 211 212 /* only hit the update bit if either volume has changed this step */ 213 if (!left_complete || !right_complete) 214 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU); 215 216 return left_complete & right_complete; 217 } 218 219 /* 220 * This work ramps both output PGAs at stream start/stop time to 221 * minimise pop associated with DAPM power switching. 222 * It's best to enable Zero Cross when ramping occurs to minimise any 223 * zipper noises. 224 */ 225 static void wm8350_pga_work(struct work_struct *work) 226 { 227 struct snd_soc_dapm_context *dapm = 228 container_of(work, struct snd_soc_dapm_context, delayed_work.work); 229 struct snd_soc_codec *codec = dapm->codec; 230 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 231 struct wm8350_output *out1 = &wm8350_data->out1, 232 *out2 = &wm8350_data->out2; 233 int i, out1_complete, out2_complete; 234 235 /* do we need to ramp at all ? */ 236 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE) 237 return; 238 239 /* PGA volumes have 6 bits of resolution to ramp */ 240 for (i = 0; i <= 63; i++) { 241 out1_complete = 1, out2_complete = 1; 242 if (out1->ramp != WM8350_RAMP_NONE) 243 out1_complete = wm8350_out1_ramp_step(codec); 244 if (out2->ramp != WM8350_RAMP_NONE) 245 out2_complete = wm8350_out2_ramp_step(codec); 246 247 /* ramp finished ? */ 248 if (out1_complete && out2_complete) 249 break; 250 251 /* we need to delay longer on the up ramp */ 252 if (out1->ramp == WM8350_RAMP_UP || 253 out2->ramp == WM8350_RAMP_UP) { 254 /* delay is longer over 0dB as increases are larger */ 255 if (i >= WM8350_OUTn_0dB) 256 schedule_timeout_interruptible(msecs_to_jiffies 257 (2)); 258 else 259 schedule_timeout_interruptible(msecs_to_jiffies 260 (1)); 261 } else 262 udelay(50); /* doesn't matter if we delay longer */ 263 } 264 265 out1->ramp = WM8350_RAMP_NONE; 266 out2->ramp = WM8350_RAMP_NONE; 267 } 268 269 /* 270 * WM8350 Controls 271 */ 272 273 static int pga_event(struct snd_soc_dapm_widget *w, 274 struct snd_kcontrol *kcontrol, int event) 275 { 276 struct snd_soc_codec *codec = w->codec; 277 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 278 struct wm8350_output *out; 279 280 switch (w->shift) { 281 case 0: 282 case 1: 283 out = &wm8350_data->out1; 284 break; 285 case 2: 286 case 3: 287 out = &wm8350_data->out2; 288 break; 289 290 default: 291 BUG(); 292 return -1; 293 } 294 295 switch (event) { 296 case SND_SOC_DAPM_POST_PMU: 297 out->ramp = WM8350_RAMP_UP; 298 out->active = 1; 299 300 if (!delayed_work_pending(&codec->dapm.delayed_work)) 301 schedule_delayed_work(&codec->dapm.delayed_work, 302 msecs_to_jiffies(1)); 303 break; 304 305 case SND_SOC_DAPM_PRE_PMD: 306 out->ramp = WM8350_RAMP_DOWN; 307 out->active = 0; 308 309 if (!delayed_work_pending(&codec->dapm.delayed_work)) 310 schedule_delayed_work(&codec->dapm.delayed_work, 311 msecs_to_jiffies(1)); 312 break; 313 } 314 315 return 0; 316 } 317 318 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, 319 struct snd_ctl_elem_value *ucontrol) 320 { 321 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 322 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 323 struct wm8350_output *out = NULL; 324 struct soc_mixer_control *mc = 325 (struct soc_mixer_control *)kcontrol->private_value; 326 int ret; 327 unsigned int reg = mc->reg; 328 u16 val; 329 330 /* For OUT1 and OUT2 we shadow the values and only actually write 331 * them out when active in order to ensure the amplifier comes on 332 * as quietly as possible. */ 333 switch (reg) { 334 case WM8350_LOUT1_VOLUME: 335 out = &wm8350_priv->out1; 336 break; 337 case WM8350_LOUT2_VOLUME: 338 out = &wm8350_priv->out2; 339 break; 340 default: 341 break; 342 } 343 344 if (out) { 345 out->left_vol = ucontrol->value.integer.value[0]; 346 out->right_vol = ucontrol->value.integer.value[1]; 347 if (!out->active) 348 return 1; 349 } 350 351 ret = snd_soc_put_volsw(kcontrol, ucontrol); 352 if (ret < 0) 353 return ret; 354 355 /* now hit the volume update bits (always bit 8) */ 356 val = snd_soc_read(codec, reg); 357 snd_soc_write(codec, reg, val | WM8350_OUT1_VU); 358 return 1; 359 } 360 361 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol, 362 struct snd_ctl_elem_value *ucontrol) 363 { 364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 365 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 366 struct wm8350_output *out1 = &wm8350_priv->out1; 367 struct wm8350_output *out2 = &wm8350_priv->out2; 368 struct soc_mixer_control *mc = 369 (struct soc_mixer_control *)kcontrol->private_value; 370 unsigned int reg = mc->reg; 371 372 /* If these are cached registers use the cache */ 373 switch (reg) { 374 case WM8350_LOUT1_VOLUME: 375 ucontrol->value.integer.value[0] = out1->left_vol; 376 ucontrol->value.integer.value[1] = out1->right_vol; 377 return 0; 378 379 case WM8350_LOUT2_VOLUME: 380 ucontrol->value.integer.value[0] = out2->left_vol; 381 ucontrol->value.integer.value[1] = out2->right_vol; 382 return 0; 383 384 default: 385 break; 386 } 387 388 return snd_soc_get_volsw(kcontrol, ucontrol); 389 } 390 391 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; 392 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" }; 393 static const char *wm8350_dacmutem[] = { "Normal", "Soft" }; 394 static const char *wm8350_dacmutes[] = { "Fast", "Slow" }; 395 static const char *wm8350_adcfilter[] = { "None", "High Pass" }; 396 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" }; 397 static const char *wm8350_lr[] = { "Left", "Right" }; 398 399 static const struct soc_enum wm8350_enum[] = { 400 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp), 401 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol), 402 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem), 403 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes), 404 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter), 405 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp), 406 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol), 407 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr), 408 }; 409 410 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0); 411 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0); 412 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1); 413 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1); 414 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1); 415 416 static const unsigned int capture_sd_tlv[] = { 417 TLV_DB_RANGE_HEAD(2), 418 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1), 419 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0), 420 }; 421 422 static const struct snd_kcontrol_new wm8350_snd_controls[] = { 423 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]), 424 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]), 425 SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume", 426 WM8350_DAC_DIGITAL_VOLUME_L, 427 WM8350_DAC_DIGITAL_VOLUME_R, 428 0, 255, 0, wm8350_get_volsw_2r, 429 wm8350_put_volsw_2r_vu, dac_pcm_tlv), 430 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]), 431 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]), 432 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]), 433 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]), 434 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]), 435 SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume", 436 WM8350_ADC_DIGITAL_VOLUME_L, 437 WM8350_ADC_DIGITAL_VOLUME_R, 438 0, 255, 0, wm8350_get_volsw_2r, 439 wm8350_put_volsw_2r_vu, adc_pcm_tlv), 440 SOC_DOUBLE_TLV("Capture Sidetone Volume", 441 WM8350_ADC_DIVIDER, 442 8, 4, 15, 1, capture_sd_tlv), 443 SOC_DOUBLE_R_EXT_TLV("Capture Volume", 444 WM8350_LEFT_INPUT_VOLUME, 445 WM8350_RIGHT_INPUT_VOLUME, 446 2, 63, 0, wm8350_get_volsw_2r, 447 wm8350_put_volsw_2r_vu, pre_amp_tlv), 448 SOC_DOUBLE_R("Capture ZC Switch", 449 WM8350_LEFT_INPUT_VOLUME, 450 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0), 451 SOC_SINGLE_TLV("Left Input Left Sidetone Volume", 452 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv), 453 SOC_SINGLE_TLV("Left Input Right Sidetone Volume", 454 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 455 5, 7, 0, out_mix_tlv), 456 SOC_SINGLE_TLV("Left Input Bypass Volume", 457 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 458 9, 7, 0, out_mix_tlv), 459 SOC_SINGLE_TLV("Right Input Left Sidetone Volume", 460 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 461 1, 7, 0, out_mix_tlv), 462 SOC_SINGLE_TLV("Right Input Right Sidetone Volume", 463 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 464 5, 7, 0, out_mix_tlv), 465 SOC_SINGLE_TLV("Right Input Bypass Volume", 466 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 467 13, 7, 0, out_mix_tlv), 468 SOC_SINGLE("Left Input Mixer +20dB Switch", 469 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0), 470 SOC_SINGLE("Right Input Mixer +20dB Switch", 471 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0), 472 SOC_SINGLE_TLV("Out4 Capture Volume", 473 WM8350_INPUT_MIXER_VOLUME, 474 1, 7, 0, out_mix_tlv), 475 SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume", 476 WM8350_LOUT1_VOLUME, 477 WM8350_ROUT1_VOLUME, 478 2, 63, 0, wm8350_get_volsw_2r, 479 wm8350_put_volsw_2r_vu, out_pga_tlv), 480 SOC_DOUBLE_R("Out1 Playback ZC Switch", 481 WM8350_LOUT1_VOLUME, 482 WM8350_ROUT1_VOLUME, 13, 1, 0), 483 SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume", 484 WM8350_LOUT2_VOLUME, 485 WM8350_ROUT2_VOLUME, 486 2, 63, 0, wm8350_get_volsw_2r, 487 wm8350_put_volsw_2r_vu, out_pga_tlv), 488 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME, 489 WM8350_ROUT2_VOLUME, 13, 1, 0), 490 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0), 491 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME, 492 5, 7, 0, out_mix_tlv), 493 494 SOC_DOUBLE_R("Out1 Playback Switch", 495 WM8350_LOUT1_VOLUME, 496 WM8350_ROUT1_VOLUME, 497 14, 1, 1), 498 SOC_DOUBLE_R("Out2 Playback Switch", 499 WM8350_LOUT2_VOLUME, 500 WM8350_ROUT2_VOLUME, 501 14, 1, 1), 502 }; 503 504 /* 505 * DAPM Controls 506 */ 507 508 /* Left Playback Mixer */ 509 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = { 510 SOC_DAPM_SINGLE("Playback Switch", 511 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0), 512 SOC_DAPM_SINGLE("Left Bypass Switch", 513 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0), 514 SOC_DAPM_SINGLE("Right Playback Switch", 515 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0), 516 SOC_DAPM_SINGLE("Left Sidetone Switch", 517 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0), 518 SOC_DAPM_SINGLE("Right Sidetone Switch", 519 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0), 520 }; 521 522 /* Right Playback Mixer */ 523 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = { 524 SOC_DAPM_SINGLE("Playback Switch", 525 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0), 526 SOC_DAPM_SINGLE("Right Bypass Switch", 527 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0), 528 SOC_DAPM_SINGLE("Left Playback Switch", 529 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0), 530 SOC_DAPM_SINGLE("Left Sidetone Switch", 531 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0), 532 SOC_DAPM_SINGLE("Right Sidetone Switch", 533 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0), 534 }; 535 536 /* Out4 Mixer */ 537 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = { 538 SOC_DAPM_SINGLE("Right Playback Switch", 539 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0), 540 SOC_DAPM_SINGLE("Left Playback Switch", 541 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0), 542 SOC_DAPM_SINGLE("Right Capture Switch", 543 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0), 544 SOC_DAPM_SINGLE("Out3 Playback Switch", 545 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0), 546 SOC_DAPM_SINGLE("Right Mixer Switch", 547 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0), 548 SOC_DAPM_SINGLE("Left Mixer Switch", 549 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0), 550 }; 551 552 /* Out3 Mixer */ 553 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = { 554 SOC_DAPM_SINGLE("Left Playback Switch", 555 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0), 556 SOC_DAPM_SINGLE("Left Capture Switch", 557 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0), 558 SOC_DAPM_SINGLE("Out4 Playback Switch", 559 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0), 560 SOC_DAPM_SINGLE("Left Mixer Switch", 561 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0), 562 }; 563 564 /* Left Input Mixer */ 565 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = { 566 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 567 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv), 568 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 569 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv), 570 SOC_DAPM_SINGLE("PGA Capture Switch", 571 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1), 572 }; 573 574 /* Right Input Mixer */ 575 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = { 576 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 577 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv), 578 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 579 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv), 580 SOC_DAPM_SINGLE("PGA Capture Switch", 581 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1), 582 }; 583 584 /* Left Mic Mixer */ 585 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = { 586 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0), 587 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0), 588 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0), 589 }; 590 591 /* Right Mic Mixer */ 592 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = { 593 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0), 594 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0), 595 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0), 596 }; 597 598 /* Beep Switch */ 599 static const struct snd_kcontrol_new wm8350_beep_switch_controls = 600 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1); 601 602 /* Out4 Capture Mux */ 603 static const struct snd_kcontrol_new wm8350_out4_capture_controls = 604 SOC_DAPM_ENUM("Route", wm8350_enum[7]); 605 606 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = { 607 608 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0), 609 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0), 610 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL, 611 0, pga_event, 612 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 613 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0, 614 pga_event, 615 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 616 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL, 617 0, pga_event, 618 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 619 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0, 620 pga_event, 621 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 622 623 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2, 624 7, 0, &wm8350_right_capt_mixer_controls[0], 625 ARRAY_SIZE(wm8350_right_capt_mixer_controls)), 626 627 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2, 628 6, 0, &wm8350_left_capt_mixer_controls[0], 629 ARRAY_SIZE(wm8350_left_capt_mixer_controls)), 630 631 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0, 632 &wm8350_out4_mixer_controls[0], 633 ARRAY_SIZE(wm8350_out4_mixer_controls)), 634 635 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0, 636 &wm8350_out3_mixer_controls[0], 637 ARRAY_SIZE(wm8350_out3_mixer_controls)), 638 639 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0, 640 &wm8350_right_play_mixer_controls[0], 641 ARRAY_SIZE(wm8350_right_play_mixer_controls)), 642 643 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0, 644 &wm8350_left_play_mixer_controls[0], 645 ARRAY_SIZE(wm8350_left_play_mixer_controls)), 646 647 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0, 648 &wm8350_left_mic_mixer_controls[0], 649 ARRAY_SIZE(wm8350_left_mic_mixer_controls)), 650 651 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0, 652 &wm8350_right_mic_mixer_controls[0], 653 ARRAY_SIZE(wm8350_right_mic_mixer_controls)), 654 655 /* virtual mixer for Beep and Out2R */ 656 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 657 658 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0, 659 &wm8350_beep_switch_controls), 660 661 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 662 WM8350_POWER_MGMT_4, 3, 0), 663 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", 664 WM8350_POWER_MGMT_4, 2, 0), 665 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", 666 WM8350_POWER_MGMT_4, 5, 0), 667 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", 668 WM8350_POWER_MGMT_4, 4, 0), 669 670 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0), 671 672 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0, 673 &wm8350_out4_capture_controls), 674 675 SND_SOC_DAPM_OUTPUT("OUT1R"), 676 SND_SOC_DAPM_OUTPUT("OUT1L"), 677 SND_SOC_DAPM_OUTPUT("OUT2R"), 678 SND_SOC_DAPM_OUTPUT("OUT2L"), 679 SND_SOC_DAPM_OUTPUT("OUT3"), 680 SND_SOC_DAPM_OUTPUT("OUT4"), 681 682 SND_SOC_DAPM_INPUT("IN1RN"), 683 SND_SOC_DAPM_INPUT("IN1RP"), 684 SND_SOC_DAPM_INPUT("IN2R"), 685 SND_SOC_DAPM_INPUT("IN1LP"), 686 SND_SOC_DAPM_INPUT("IN1LN"), 687 SND_SOC_DAPM_INPUT("IN2L"), 688 SND_SOC_DAPM_INPUT("IN3R"), 689 SND_SOC_DAPM_INPUT("IN3L"), 690 }; 691 692 static const struct snd_soc_dapm_route wm8350_dapm_routes[] = { 693 694 /* left playback mixer */ 695 {"Left Playback Mixer", "Playback Switch", "Left DAC"}, 696 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"}, 697 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"}, 698 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 699 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 700 701 /* right playback mixer */ 702 {"Right Playback Mixer", "Playback Switch", "Right DAC"}, 703 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"}, 704 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"}, 705 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 706 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 707 708 /* out4 playback mixer */ 709 {"Out4 Mixer", "Right Playback Switch", "Right DAC"}, 710 {"Out4 Mixer", "Left Playback Switch", "Left DAC"}, 711 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"}, 712 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"}, 713 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"}, 714 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 715 {"OUT4", NULL, "Out4 Mixer"}, 716 717 /* out3 playback mixer */ 718 {"Out3 Mixer", "Left Playback Switch", "Left DAC"}, 719 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"}, 720 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 721 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"}, 722 {"OUT3", NULL, "Out3 Mixer"}, 723 724 /* out2 */ 725 {"Right Out2 PGA", NULL, "Right Playback Mixer"}, 726 {"Left Out2 PGA", NULL, "Left Playback Mixer"}, 727 {"OUT2L", NULL, "Left Out2 PGA"}, 728 {"OUT2R", NULL, "Right Out2 PGA"}, 729 730 /* out1 */ 731 {"Right Out1 PGA", NULL, "Right Playback Mixer"}, 732 {"Left Out1 PGA", NULL, "Left Playback Mixer"}, 733 {"OUT1L", NULL, "Left Out1 PGA"}, 734 {"OUT1R", NULL, "Right Out1 PGA"}, 735 736 /* ADCs */ 737 {"Left ADC", NULL, "Left Capture Mixer"}, 738 {"Right ADC", NULL, "Right Capture Mixer"}, 739 740 /* Left capture mixer */ 741 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"}, 742 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"}, 743 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"}, 744 {"Left Capture Mixer", NULL, "Out4 Capture Channel"}, 745 746 /* Right capture mixer */ 747 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"}, 748 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"}, 749 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"}, 750 {"Right Capture Mixer", NULL, "Out4 Capture Channel"}, 751 752 /* L3 Inputs */ 753 {"IN3L PGA", NULL, "IN3L"}, 754 {"IN3R PGA", NULL, "IN3R"}, 755 756 /* Left Mic mixer */ 757 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"}, 758 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"}, 759 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"}, 760 761 /* Right Mic mixer */ 762 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"}, 763 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"}, 764 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"}, 765 766 /* out 4 capture */ 767 {"Out4 Capture Channel", NULL, "Out4 Mixer"}, 768 769 /* Beep */ 770 {"Beep", NULL, "IN3R PGA"}, 771 }; 772 773 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai, 774 int clk_id, unsigned int freq, int dir) 775 { 776 struct snd_soc_codec *codec = codec_dai->codec; 777 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 778 struct wm8350 *wm8350 = wm8350_data->wm8350; 779 u16 fll_4; 780 781 switch (clk_id) { 782 case WM8350_MCLK_SEL_MCLK: 783 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1, 784 WM8350_MCLK_SEL); 785 break; 786 case WM8350_MCLK_SEL_PLL_MCLK: 787 case WM8350_MCLK_SEL_PLL_DAC: 788 case WM8350_MCLK_SEL_PLL_ADC: 789 case WM8350_MCLK_SEL_PLL_32K: 790 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1, 791 WM8350_MCLK_SEL); 792 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) & 793 ~WM8350_FLL_CLK_SRC_MASK; 794 snd_soc_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id); 795 break; 796 } 797 798 /* MCLK direction */ 799 if (dir == SND_SOC_CLOCK_OUT) 800 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, 801 WM8350_MCLK_DIR); 802 else 803 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, 804 WM8350_MCLK_DIR); 805 806 return 0; 807 } 808 809 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) 810 { 811 struct snd_soc_codec *codec = codec_dai->codec; 812 u16 val; 813 814 switch (div_id) { 815 case WM8350_ADC_CLKDIV: 816 val = snd_soc_read(codec, WM8350_ADC_DIVIDER) & 817 ~WM8350_ADC_CLKDIV_MASK; 818 snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div); 819 break; 820 case WM8350_DAC_CLKDIV: 821 val = snd_soc_read(codec, WM8350_DAC_CLOCK_CONTROL) & 822 ~WM8350_DAC_CLKDIV_MASK; 823 snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); 824 break; 825 case WM8350_BCLK_CLKDIV: 826 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) & 827 ~WM8350_BCLK_DIV_MASK; 828 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 829 break; 830 case WM8350_OPCLK_CLKDIV: 831 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) & 832 ~WM8350_OPCLK_DIV_MASK; 833 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 834 break; 835 case WM8350_SYS_CLKDIV: 836 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) & 837 ~WM8350_MCLK_DIV_MASK; 838 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 839 break; 840 case WM8350_DACLR_CLKDIV: 841 val = snd_soc_read(codec, WM8350_DAC_LR_RATE) & 842 ~WM8350_DACLRC_RATE_MASK; 843 snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div); 844 break; 845 case WM8350_ADCLR_CLKDIV: 846 val = snd_soc_read(codec, WM8350_ADC_LR_RATE) & 847 ~WM8350_ADCLRC_RATE_MASK; 848 snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div); 849 break; 850 default: 851 return -EINVAL; 852 } 853 854 return 0; 855 } 856 857 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 858 { 859 struct snd_soc_codec *codec = codec_dai->codec; 860 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) & 861 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK); 862 u16 master = snd_soc_read(codec, WM8350_AI_DAC_CONTROL) & 863 ~WM8350_BCLK_MSTR; 864 u16 dac_lrc = snd_soc_read(codec, WM8350_DAC_LR_RATE) & 865 ~WM8350_DACLRC_ENA; 866 u16 adc_lrc = snd_soc_read(codec, WM8350_ADC_LR_RATE) & 867 ~WM8350_ADCLRC_ENA; 868 869 /* set master/slave audio interface */ 870 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 871 case SND_SOC_DAIFMT_CBM_CFM: 872 master |= WM8350_BCLK_MSTR; 873 dac_lrc |= WM8350_DACLRC_ENA; 874 adc_lrc |= WM8350_ADCLRC_ENA; 875 break; 876 case SND_SOC_DAIFMT_CBS_CFS: 877 break; 878 default: 879 return -EINVAL; 880 } 881 882 /* interface format */ 883 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 884 case SND_SOC_DAIFMT_I2S: 885 iface |= 0x2 << 8; 886 break; 887 case SND_SOC_DAIFMT_RIGHT_J: 888 break; 889 case SND_SOC_DAIFMT_LEFT_J: 890 iface |= 0x1 << 8; 891 break; 892 case SND_SOC_DAIFMT_DSP_A: 893 iface |= 0x3 << 8; 894 break; 895 case SND_SOC_DAIFMT_DSP_B: 896 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV; 897 break; 898 default: 899 return -EINVAL; 900 } 901 902 /* clock inversion */ 903 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 904 case SND_SOC_DAIFMT_NB_NF: 905 break; 906 case SND_SOC_DAIFMT_IB_IF: 907 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV; 908 break; 909 case SND_SOC_DAIFMT_IB_NF: 910 iface |= WM8350_AIF_BCLK_INV; 911 break; 912 case SND_SOC_DAIFMT_NB_IF: 913 iface |= WM8350_AIF_LRCLK_INV; 914 break; 915 default: 916 return -EINVAL; 917 } 918 919 snd_soc_write(codec, WM8350_AI_FORMATING, iface); 920 snd_soc_write(codec, WM8350_AI_DAC_CONTROL, master); 921 snd_soc_write(codec, WM8350_DAC_LR_RATE, dac_lrc); 922 snd_soc_write(codec, WM8350_ADC_LR_RATE, adc_lrc); 923 return 0; 924 } 925 926 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream, 927 struct snd_pcm_hw_params *params, 928 struct snd_soc_dai *codec_dai) 929 { 930 struct snd_soc_codec *codec = codec_dai->codec; 931 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 932 struct wm8350 *wm8350 = wm8350_data->wm8350; 933 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) & 934 ~WM8350_AIF_WL_MASK; 935 936 /* bit size */ 937 switch (params_format(params)) { 938 case SNDRV_PCM_FORMAT_S16_LE: 939 break; 940 case SNDRV_PCM_FORMAT_S20_3LE: 941 iface |= 0x1 << 10; 942 break; 943 case SNDRV_PCM_FORMAT_S24_LE: 944 iface |= 0x2 << 10; 945 break; 946 case SNDRV_PCM_FORMAT_S32_LE: 947 iface |= 0x3 << 10; 948 break; 949 } 950 951 snd_soc_write(codec, WM8350_AI_FORMATING, iface); 952 953 /* The sloping stopband filter is recommended for use with 954 * lower sample rates to improve performance. 955 */ 956 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 957 if (params_rate(params) < 24000) 958 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 959 WM8350_DAC_SB_FILT); 960 else 961 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 962 WM8350_DAC_SB_FILT); 963 } 964 965 return 0; 966 } 967 968 static int wm8350_mute(struct snd_soc_dai *dai, int mute) 969 { 970 struct snd_soc_codec *codec = dai->codec; 971 unsigned int val; 972 973 if (mute) 974 val = WM8350_DAC_MUTE_ENA; 975 else 976 val = 0; 977 978 snd_soc_update_bits(codec, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val); 979 980 return 0; 981 } 982 983 /* FLL divisors */ 984 struct _fll_div { 985 int div; /* FLL_OUTDIV */ 986 int n; 987 int k; 988 int ratio; /* FLL_FRATIO */ 989 }; 990 991 /* The size in bits of the fll divide multiplied by 10 992 * to allow rounding later */ 993 #define FIXED_FLL_SIZE ((1 << 16) * 10) 994 995 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input, 996 unsigned int output) 997 { 998 u64 Kpart; 999 unsigned int t1, t2, K, Nmod; 1000 1001 if (output >= 2815250 && output <= 3125000) 1002 fll_div->div = 0x4; 1003 else if (output >= 5625000 && output <= 6250000) 1004 fll_div->div = 0x3; 1005 else if (output >= 11250000 && output <= 12500000) 1006 fll_div->div = 0x2; 1007 else if (output >= 22500000 && output <= 25000000) 1008 fll_div->div = 0x1; 1009 else { 1010 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output); 1011 return -EINVAL; 1012 } 1013 1014 if (input > 48000) 1015 fll_div->ratio = 1; 1016 else 1017 fll_div->ratio = 8; 1018 1019 t1 = output * (1 << (fll_div->div + 1)); 1020 t2 = input * fll_div->ratio; 1021 1022 fll_div->n = t1 / t2; 1023 Nmod = t1 % t2; 1024 1025 if (Nmod) { 1026 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1027 do_div(Kpart, t2); 1028 K = Kpart & 0xFFFFFFFF; 1029 1030 /* Check if we need to round */ 1031 if ((K % 10) >= 5) 1032 K += 5; 1033 1034 /* Move down to proper range now rounding is done */ 1035 K /= 10; 1036 fll_div->k = K; 1037 } else 1038 fll_div->k = 0; 1039 1040 return 0; 1041 } 1042 1043 static int wm8350_set_fll(struct snd_soc_dai *codec_dai, 1044 int pll_id, int source, unsigned int freq_in, 1045 unsigned int freq_out) 1046 { 1047 struct snd_soc_codec *codec = codec_dai->codec; 1048 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1049 struct wm8350 *wm8350 = priv->wm8350; 1050 struct _fll_div fll_div; 1051 int ret = 0; 1052 u16 fll_1, fll_4; 1053 1054 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out) 1055 return 0; 1056 1057 /* power down FLL - we need to do this for reconfiguration */ 1058 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1059 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA); 1060 1061 if (freq_out == 0 || freq_in == 0) 1062 return ret; 1063 1064 ret = fll_factors(&fll_div, freq_in, freq_out); 1065 if (ret < 0) 1066 return ret; 1067 dev_dbg(wm8350->dev, 1068 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d", 1069 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, 1070 fll_div.ratio); 1071 1072 /* set up N.K & dividers */ 1073 fll_1 = snd_soc_read(codec, WM8350_FLL_CONTROL_1) & 1074 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); 1075 snd_soc_write(codec, WM8350_FLL_CONTROL_1, 1076 fll_1 | (fll_div.div << 8) | 0x50); 1077 snd_soc_write(codec, WM8350_FLL_CONTROL_2, 1078 (fll_div.ratio << 11) | (fll_div. 1079 n & WM8350_FLL_N_MASK)); 1080 snd_soc_write(codec, WM8350_FLL_CONTROL_3, fll_div.k); 1081 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) & 1082 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF); 1083 snd_soc_write(codec, WM8350_FLL_CONTROL_4, 1084 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | 1085 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0)); 1086 1087 /* power FLL on */ 1088 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA); 1089 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA); 1090 1091 priv->fll_freq_out = freq_out; 1092 priv->fll_freq_in = freq_in; 1093 1094 return 0; 1095 } 1096 1097 static int wm8350_set_bias_level(struct snd_soc_codec *codec, 1098 enum snd_soc_bias_level level) 1099 { 1100 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1101 struct wm8350 *wm8350 = priv->wm8350; 1102 struct wm8350_audio_platform_data *platform = 1103 wm8350->codec.platform_data; 1104 u16 pm1; 1105 int ret; 1106 1107 switch (level) { 1108 case SND_SOC_BIAS_ON: 1109 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1110 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1111 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1112 pm1 | WM8350_VMID_50K | 1113 platform->codec_current_on << 14); 1114 break; 1115 1116 case SND_SOC_BIAS_PREPARE: 1117 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1); 1118 pm1 &= ~WM8350_VMID_MASK; 1119 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1120 pm1 | WM8350_VMID_50K); 1121 break; 1122 1123 case SND_SOC_BIAS_STANDBY: 1124 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1125 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), 1126 priv->supplies); 1127 if (ret != 0) 1128 return ret; 1129 1130 /* Enable the system clock */ 1131 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, 1132 WM8350_SYSCLK_ENA); 1133 1134 /* mute DAC & outputs */ 1135 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, 1136 WM8350_DAC_MUTE_ENA); 1137 1138 /* discharge cap memory */ 1139 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1140 platform->dis_out1 | 1141 (platform->dis_out2 << 2) | 1142 (platform->dis_out3 << 4) | 1143 (platform->dis_out4 << 6)); 1144 1145 /* wait for discharge */ 1146 schedule_timeout_interruptible(msecs_to_jiffies 1147 (platform-> 1148 cap_discharge_msecs)); 1149 1150 /* enable antipop */ 1151 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1152 (platform->vmid_s_curve << 8)); 1153 1154 /* ramp up vmid */ 1155 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1156 (platform-> 1157 codec_current_charge << 14) | 1158 WM8350_VMID_5K | WM8350_VMIDEN | 1159 WM8350_VBUFEN); 1160 1161 /* wait for vmid */ 1162 schedule_timeout_interruptible(msecs_to_jiffies 1163 (platform-> 1164 vmid_charge_msecs)); 1165 1166 /* turn on vmid 300k */ 1167 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1168 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1169 pm1 |= WM8350_VMID_300K | 1170 (platform->codec_current_standby << 14); 1171 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1172 pm1); 1173 1174 1175 /* enable analogue bias */ 1176 pm1 |= WM8350_BIASEN; 1177 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1178 1179 /* disable antipop */ 1180 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1181 1182 } else { 1183 /* turn on vmid 300k and reduce current */ 1184 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1185 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1186 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1187 pm1 | WM8350_VMID_300K | 1188 (platform-> 1189 codec_current_standby << 14)); 1190 1191 } 1192 break; 1193 1194 case SND_SOC_BIAS_OFF: 1195 1196 /* mute DAC & enable outputs */ 1197 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1198 1199 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3, 1200 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA | 1201 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA); 1202 1203 /* enable anti pop S curve */ 1204 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1205 (platform->vmid_s_curve << 8)); 1206 1207 /* turn off vmid */ 1208 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1209 ~WM8350_VMIDEN; 1210 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1211 1212 /* wait */ 1213 schedule_timeout_interruptible(msecs_to_jiffies 1214 (platform-> 1215 vmid_discharge_msecs)); 1216 1217 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1218 (platform->vmid_s_curve << 8) | 1219 platform->dis_out1 | 1220 (platform->dis_out2 << 2) | 1221 (platform->dis_out3 << 4) | 1222 (platform->dis_out4 << 6)); 1223 1224 /* turn off VBuf and drain */ 1225 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1226 ~(WM8350_VBUFEN | WM8350_VMID_MASK); 1227 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1228 pm1 | WM8350_OUTPUT_DRAIN_EN); 1229 1230 /* wait */ 1231 schedule_timeout_interruptible(msecs_to_jiffies 1232 (platform->drain_msecs)); 1233 1234 pm1 &= ~WM8350_BIASEN; 1235 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1236 1237 /* disable anti-pop */ 1238 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1239 1240 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME, 1241 WM8350_OUT1L_ENA); 1242 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME, 1243 WM8350_OUT1R_ENA); 1244 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME, 1245 WM8350_OUT2L_ENA); 1246 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME, 1247 WM8350_OUT2R_ENA); 1248 1249 /* disable clock gen */ 1250 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1251 WM8350_SYSCLK_ENA); 1252 1253 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 1254 priv->supplies); 1255 break; 1256 } 1257 codec->dapm.bias_level = level; 1258 return 0; 1259 } 1260 1261 static int wm8350_suspend(struct snd_soc_codec *codec) 1262 { 1263 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1264 return 0; 1265 } 1266 1267 static int wm8350_resume(struct snd_soc_codec *codec) 1268 { 1269 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1270 1271 return 0; 1272 } 1273 1274 static void wm8350_hp_work(struct wm8350_data *priv, 1275 struct wm8350_jack_data *jack, 1276 u16 mask) 1277 { 1278 struct wm8350 *wm8350 = priv->wm8350; 1279 u16 reg; 1280 int report; 1281 1282 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1283 if (reg & mask) 1284 report = jack->report; 1285 else 1286 report = 0; 1287 1288 snd_soc_jack_report(jack->jack, report, jack->report); 1289 1290 } 1291 1292 static void wm8350_hpl_work(struct work_struct *work) 1293 { 1294 struct wm8350_data *priv = 1295 container_of(work, struct wm8350_data, hpl.work.work); 1296 1297 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL); 1298 } 1299 1300 static void wm8350_hpr_work(struct work_struct *work) 1301 { 1302 struct wm8350_data *priv = 1303 container_of(work, struct wm8350_data, hpr.work.work); 1304 1305 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL); 1306 } 1307 1308 static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data) 1309 { 1310 struct wm8350_data *priv = data; 1311 struct wm8350 *wm8350 = priv->wm8350; 1312 1313 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1314 trace_snd_soc_jack_irq("WM8350 HPL"); 1315 #endif 1316 1317 if (device_may_wakeup(wm8350->dev)) 1318 pm_wakeup_event(wm8350->dev, 250); 1319 1320 schedule_delayed_work(&priv->hpl.work, 200); 1321 1322 return IRQ_HANDLED; 1323 } 1324 1325 static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data) 1326 { 1327 struct wm8350_data *priv = data; 1328 struct wm8350 *wm8350 = priv->wm8350; 1329 1330 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1331 trace_snd_soc_jack_irq("WM8350 HPR"); 1332 #endif 1333 1334 if (device_may_wakeup(wm8350->dev)) 1335 pm_wakeup_event(wm8350->dev, 250); 1336 1337 schedule_delayed_work(&priv->hpr.work, 200); 1338 1339 return IRQ_HANDLED; 1340 } 1341 1342 /** 1343 * wm8350_hp_jack_detect - Enable headphone jack detection. 1344 * 1345 * @codec: WM8350 codec 1346 * @which: left or right jack detect signal 1347 * @jack: jack to report detection events on 1348 * @report: value to report 1349 * 1350 * Enables the headphone jack detection of the WM8350. If no report 1351 * is specified then detection is disabled. 1352 */ 1353 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, 1354 struct snd_soc_jack *jack, int report) 1355 { 1356 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1357 struct wm8350 *wm8350 = priv->wm8350; 1358 int irq; 1359 int ena; 1360 1361 switch (which) { 1362 case WM8350_JDL: 1363 priv->hpl.jack = jack; 1364 priv->hpl.report = report; 1365 irq = WM8350_IRQ_CODEC_JCK_DET_L; 1366 ena = WM8350_JDL_ENA; 1367 break; 1368 1369 case WM8350_JDR: 1370 priv->hpr.jack = jack; 1371 priv->hpr.report = report; 1372 irq = WM8350_IRQ_CODEC_JCK_DET_R; 1373 ena = WM8350_JDR_ENA; 1374 break; 1375 1376 default: 1377 return -EINVAL; 1378 } 1379 1380 if (report) { 1381 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1382 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); 1383 } else { 1384 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena); 1385 } 1386 1387 /* Sync status */ 1388 switch (which) { 1389 case WM8350_JDL: 1390 wm8350_hpl_jack_handler(0, priv); 1391 break; 1392 case WM8350_JDR: 1393 wm8350_hpr_jack_handler(0, priv); 1394 break; 1395 } 1396 1397 return 0; 1398 } 1399 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect); 1400 1401 static irqreturn_t wm8350_mic_handler(int irq, void *data) 1402 { 1403 struct wm8350_data *priv = data; 1404 struct wm8350 *wm8350 = priv->wm8350; 1405 u16 reg; 1406 int report = 0; 1407 1408 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1409 trace_snd_soc_jack_irq("WM8350 mic"); 1410 #endif 1411 1412 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1413 if (reg & WM8350_JACK_MICSCD_LVL) 1414 report |= priv->mic.short_report; 1415 if (reg & WM8350_JACK_MICSD_LVL) 1416 report |= priv->mic.report; 1417 1418 snd_soc_jack_report(priv->mic.jack, report, 1419 priv->mic.report | priv->mic.short_report); 1420 1421 return IRQ_HANDLED; 1422 } 1423 1424 /** 1425 * wm8350_mic_jack_detect - Enable microphone jack detection. 1426 * 1427 * @codec: WM8350 codec 1428 * @jack: jack to report detection events on 1429 * @detect_report: value to report when presence detected 1430 * @short_report: value to report when microphone short detected 1431 * 1432 * Enables the microphone jack detection of the WM8350. If both reports 1433 * are specified as zero then detection is disabled. 1434 */ 1435 int wm8350_mic_jack_detect(struct snd_soc_codec *codec, 1436 struct snd_soc_jack *jack, 1437 int detect_report, int short_report) 1438 { 1439 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1440 struct wm8350 *wm8350 = priv->wm8350; 1441 1442 priv->mic.jack = jack; 1443 priv->mic.report = detect_report; 1444 priv->mic.short_report = short_report; 1445 1446 if (detect_report || short_report) { 1447 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1448 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1, 1449 WM8350_MIC_DET_ENA); 1450 } else { 1451 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1, 1452 WM8350_MIC_DET_ENA); 1453 } 1454 1455 return 0; 1456 } 1457 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect); 1458 1459 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000) 1460 1461 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1462 SNDRV_PCM_FMTBIT_S20_3LE |\ 1463 SNDRV_PCM_FMTBIT_S24_LE) 1464 1465 static const struct snd_soc_dai_ops wm8350_dai_ops = { 1466 .hw_params = wm8350_pcm_hw_params, 1467 .digital_mute = wm8350_mute, 1468 .set_fmt = wm8350_set_dai_fmt, 1469 .set_sysclk = wm8350_set_dai_sysclk, 1470 .set_pll = wm8350_set_fll, 1471 .set_clkdiv = wm8350_set_clkdiv, 1472 }; 1473 1474 static struct snd_soc_dai_driver wm8350_dai = { 1475 .name = "wm8350-hifi", 1476 .playback = { 1477 .stream_name = "Playback", 1478 .channels_min = 1, 1479 .channels_max = 2, 1480 .rates = WM8350_RATES, 1481 .formats = WM8350_FORMATS, 1482 }, 1483 .capture = { 1484 .stream_name = "Capture", 1485 .channels_min = 1, 1486 .channels_max = 2, 1487 .rates = WM8350_RATES, 1488 .formats = WM8350_FORMATS, 1489 }, 1490 .ops = &wm8350_dai_ops, 1491 }; 1492 1493 static int wm8350_codec_probe(struct snd_soc_codec *codec) 1494 { 1495 struct wm8350 *wm8350 = dev_get_platdata(codec->dev); 1496 struct wm8350_data *priv; 1497 struct wm8350_output *out1; 1498 struct wm8350_output *out2; 1499 int ret, i; 1500 1501 if (wm8350->codec.platform_data == NULL) { 1502 dev_err(codec->dev, "No audio platform data supplied\n"); 1503 return -EINVAL; 1504 } 1505 1506 priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data), 1507 GFP_KERNEL); 1508 if (priv == NULL) 1509 return -ENOMEM; 1510 snd_soc_codec_set_drvdata(codec, priv); 1511 1512 priv->wm8350 = wm8350; 1513 1514 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1515 priv->supplies[i].supply = supply_names[i]; 1516 1517 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies), 1518 priv->supplies); 1519 if (ret != 0) 1520 return ret; 1521 1522 codec->control_data = wm8350; 1523 1524 /* Put the codec into reset if it wasn't already */ 1525 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1526 1527 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); 1528 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work); 1529 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work); 1530 1531 /* Enable the codec */ 1532 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1533 1534 /* Enable robust clocking mode in ADC */ 1535 snd_soc_write(codec, WM8350_SECURITY, 0xa7); 1536 snd_soc_write(codec, 0xde, 0x13); 1537 snd_soc_write(codec, WM8350_SECURITY, 0); 1538 1539 /* read OUT1 & OUT2 volumes */ 1540 out1 = &priv->out1; 1541 out2 = &priv->out2; 1542 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) & 1543 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1544 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) & 1545 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1546 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) & 1547 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1548 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) & 1549 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1550 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0); 1551 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0); 1552 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0); 1553 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0); 1554 1555 /* Latch VU bits & mute */ 1556 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, 1557 WM8350_OUT1_VU | WM8350_OUT1L_MUTE); 1558 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, 1559 WM8350_OUT2_VU | WM8350_OUT2L_MUTE); 1560 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME, 1561 WM8350_OUT1_VU | WM8350_OUT1R_MUTE); 1562 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, 1563 WM8350_OUT2_VU | WM8350_OUT2R_MUTE); 1564 1565 /* Make sure AIF tristating is disabled by default */ 1566 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI); 1567 1568 /* Make sure we've got a sane companding setup too */ 1569 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP, 1570 WM8350_DAC_COMP | WM8350_LOOPBACK); 1571 1572 /* Make sure jack detect is disabled to start off with */ 1573 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1574 WM8350_JDL_ENA | WM8350_JDR_ENA); 1575 1576 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, 1577 wm8350_hpl_jack_handler, 0, "Left jack detect", 1578 priv); 1579 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, 1580 wm8350_hpr_jack_handler, 0, "Right jack detect", 1581 priv); 1582 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, 1583 wm8350_mic_handler, 0, "Microphone short", priv); 1584 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD, 1585 wm8350_mic_handler, 0, "Microphone detect", priv); 1586 1587 1588 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1589 1590 return 0; 1591 } 1592 1593 static int wm8350_codec_remove(struct snd_soc_codec *codec) 1594 { 1595 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1596 struct wm8350 *wm8350 = dev_get_platdata(codec->dev); 1597 1598 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1599 WM8350_JDL_ENA | WM8350_JDR_ENA); 1600 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1601 1602 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv); 1603 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv); 1604 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv); 1605 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv); 1606 1607 priv->hpl.jack = NULL; 1608 priv->hpr.jack = NULL; 1609 priv->mic.jack = NULL; 1610 1611 cancel_delayed_work_sync(&priv->hpl.work); 1612 cancel_delayed_work_sync(&priv->hpr.work); 1613 1614 /* if there was any work waiting then we run it now and 1615 * wait for its completion */ 1616 flush_delayed_work_sync(&codec->dapm.delayed_work); 1617 1618 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1619 1620 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1621 1622 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); 1623 1624 return 0; 1625 } 1626 1627 static struct snd_soc_codec_driver soc_codec_dev_wm8350 = { 1628 .probe = wm8350_codec_probe, 1629 .remove = wm8350_codec_remove, 1630 .suspend = wm8350_suspend, 1631 .resume = wm8350_resume, 1632 .read = wm8350_codec_read, 1633 .write = wm8350_codec_write, 1634 .set_bias_level = wm8350_set_bias_level, 1635 1636 .controls = wm8350_snd_controls, 1637 .num_controls = ARRAY_SIZE(wm8350_snd_controls), 1638 .dapm_widgets = wm8350_dapm_widgets, 1639 .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets), 1640 .dapm_routes = wm8350_dapm_routes, 1641 .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes), 1642 }; 1643 1644 static int __devinit wm8350_probe(struct platform_device *pdev) 1645 { 1646 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350, 1647 &wm8350_dai, 1); 1648 } 1649 1650 static int __devexit wm8350_remove(struct platform_device *pdev) 1651 { 1652 snd_soc_unregister_codec(&pdev->dev); 1653 return 0; 1654 } 1655 1656 static struct platform_driver wm8350_codec_driver = { 1657 .driver = { 1658 .name = "wm8350-codec", 1659 .owner = THIS_MODULE, 1660 }, 1661 .probe = wm8350_probe, 1662 .remove = __devexit_p(wm8350_remove), 1663 }; 1664 1665 module_platform_driver(wm8350_codec_driver); 1666 1667 MODULE_DESCRIPTION("ASoC WM8350 driver"); 1668 MODULE_AUTHOR("Liam Girdwood"); 1669 MODULE_LICENSE("GPL"); 1670 MODULE_ALIAS("platform:wm8350-codec"); 1671