1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm0010.c -- WM0010 DSP Driver 4 * 5 * Copyright 2012 Wolfson Microelectronics PLC. 6 * 7 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 9 * Scott Ling <sl@opensource.wolfsonmicro.com> 10 */ 11 12 #include <linux/cleanup.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/interrupt.h> 16 #include <linux/irqreturn.h> 17 #include <linux/init.h> 18 #include <linux/spi/spi.h> 19 #include <linux/firmware.h> 20 #include <linux/delay.h> 21 #include <linux/fs.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/mutex.h> 25 #include <linux/workqueue.h> 26 27 #include <sound/soc.h> 28 #include <sound/wm0010.h> 29 30 #define DEVICE_ID_WM0010 10 31 32 /* We only support v1 of the .dfw INFO record */ 33 #define INFO_VERSION 1 34 35 enum dfw_cmd { 36 DFW_CMD_FUSE = 0x01, 37 DFW_CMD_CODE_HDR, 38 DFW_CMD_CODE_DATA, 39 DFW_CMD_PLL, 40 DFW_CMD_INFO = 0xff 41 }; 42 43 struct dfw_binrec { 44 u8 command; 45 u32 length:24; 46 u32 address; 47 uint8_t data[]; 48 } __packed; 49 50 struct dfw_inforec { 51 u8 info_version; 52 u8 tool_major_version; 53 u8 tool_minor_version; 54 u8 dsp_target; 55 }; 56 57 struct dfw_pllrec { 58 u8 command; 59 u32 length:24; 60 u32 address; 61 u32 clkctrl1; 62 u32 clkctrl2; 63 u32 clkctrl3; 64 u32 ldetctrl; 65 u32 uart_div; 66 u32 spi_div; 67 } __packed; 68 69 static struct pll_clock_map { 70 int max_sysclk; 71 int max_pll_spi_speed; 72 u32 pll_clkctrl1; 73 } pll_clock_map[] = { /* Dividers */ 74 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 75 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 76 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 77 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 78 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 79 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 80 }; 81 82 enum wm0010_state { 83 WM0010_POWER_OFF, 84 WM0010_OUT_OF_RESET, 85 WM0010_BOOTROM, 86 WM0010_STAGE2, 87 WM0010_FIRMWARE, 88 }; 89 90 struct wm0010_priv { 91 struct snd_soc_component *component; 92 93 struct mutex lock; 94 struct device *dev; 95 96 struct wm0010_pdata pdata; 97 98 struct gpio_desc *reset; 99 100 struct regulator_bulk_data core_supplies[2]; 101 struct regulator *dbvdd; 102 103 int sysclk; 104 105 enum wm0010_state state; 106 bool boot_failed; 107 bool ready; 108 bool pll_running; 109 int max_spi_freq; 110 int board_max_spi_speed; 111 u32 pll_clkctrl1; 112 113 spinlock_t irq_lock; 114 int irq; 115 116 struct completion boot_completion; 117 }; 118 119 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 120 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 121 }; 122 123 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 124 { "SDI2 Capture", NULL, "SDI1 Playback" }, 125 { "SDI1 Capture", NULL, "SDI2 Playback" }, 126 127 { "SDI1 Capture", NULL, "CLKIN" }, 128 { "SDI2 Capture", NULL, "CLKIN" }, 129 { "SDI1 Playback", NULL, "CLKIN" }, 130 { "SDI2 Playback", NULL, "CLKIN" }, 131 }; 132 133 static const char *wm0010_state_to_str(enum wm0010_state state) 134 { 135 static const char * const state_to_str[] = { 136 "Power off", 137 "Out of reset", 138 "Boot ROM", 139 "Stage2", 140 "Firmware" 141 }; 142 143 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 144 return "null"; 145 return state_to_str[state]; 146 } 147 148 /* Called with wm0010->lock held */ 149 static void wm0010_halt(struct snd_soc_component *component) 150 { 151 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 152 enum wm0010_state state; 153 154 /* Fetch the wm0010 state */ 155 scoped_guard(spinlock_irqsave, &wm0010->irq_lock) 156 state = wm0010->state; 157 158 switch (state) { 159 case WM0010_POWER_OFF: 160 /* If there's nothing to do, bail out */ 161 return; 162 case WM0010_OUT_OF_RESET: 163 case WM0010_BOOTROM: 164 case WM0010_STAGE2: 165 case WM0010_FIRMWARE: 166 /* Remember to put chip back into reset */ 167 gpiod_set_value_cansleep(wm0010->reset, 1); 168 /* Disable the regulators */ 169 regulator_disable(wm0010->dbvdd); 170 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 171 wm0010->core_supplies); 172 break; 173 } 174 175 scoped_guard(spinlock_irqsave, &wm0010->irq_lock) 176 wm0010->state = WM0010_POWER_OFF; 177 } 178 179 struct wm0010_boot_xfer { 180 struct list_head list; 181 struct snd_soc_component *component; 182 struct completion *done; 183 struct spi_message m; 184 struct spi_transfer t; 185 }; 186 187 /* Called with wm0010->lock held */ 188 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 189 { 190 enum wm0010_state state; 191 192 scoped_guard(spinlock_irqsave, &wm0010->irq_lock) 193 state = wm0010->state; 194 195 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 196 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 197 198 wm0010->boot_failed = true; 199 } 200 201 static void wm0010_boot_xfer_complete(void *data) 202 { 203 struct wm0010_boot_xfer *xfer = data; 204 struct snd_soc_component *component = xfer->component; 205 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 206 u32 *out32 = xfer->t.rx_buf; 207 int i; 208 209 if (xfer->m.status != 0) { 210 dev_err(component->dev, "SPI transfer failed: %d\n", 211 xfer->m.status); 212 wm0010_mark_boot_failure(wm0010); 213 if (xfer->done) 214 complete(xfer->done); 215 return; 216 } 217 218 for (i = 0; i < xfer->t.len / 4; i++) { 219 dev_dbg(component->dev, "%d: %04x\n", i, out32[i]); 220 221 switch (be32_to_cpu(out32[i])) { 222 case 0xe0e0e0e0: 223 dev_err(component->dev, 224 "%d: ROM error reported in stage 2\n", i); 225 wm0010_mark_boot_failure(wm0010); 226 break; 227 228 case 0x55555555: 229 if (wm0010->state < WM0010_STAGE2) 230 break; 231 dev_err(component->dev, 232 "%d: ROM bootloader running in stage 2\n", i); 233 wm0010_mark_boot_failure(wm0010); 234 break; 235 236 case 0x0fed0000: 237 dev_dbg(component->dev, "Stage2 loader running\n"); 238 break; 239 240 case 0x0fed0007: 241 dev_dbg(component->dev, "CODE_HDR packet received\n"); 242 break; 243 244 case 0x0fed0008: 245 dev_dbg(component->dev, "CODE_DATA packet received\n"); 246 break; 247 248 case 0x0fed0009: 249 dev_dbg(component->dev, "Download complete\n"); 250 break; 251 252 case 0x0fed000c: 253 dev_dbg(component->dev, "Application start\n"); 254 break; 255 256 case 0x0fed000e: 257 dev_dbg(component->dev, "PLL packet received\n"); 258 wm0010->pll_running = true; 259 break; 260 261 case 0x0fed0025: 262 dev_err(component->dev, "Device reports image too long\n"); 263 wm0010_mark_boot_failure(wm0010); 264 break; 265 266 case 0x0fed002c: 267 dev_err(component->dev, "Device reports bad SPI packet\n"); 268 wm0010_mark_boot_failure(wm0010); 269 break; 270 271 case 0x0fed0031: 272 dev_err(component->dev, "Device reports SPI read overflow\n"); 273 wm0010_mark_boot_failure(wm0010); 274 break; 275 276 case 0x0fed0032: 277 dev_err(component->dev, "Device reports SPI underclock\n"); 278 wm0010_mark_boot_failure(wm0010); 279 break; 280 281 case 0x0fed0033: 282 dev_err(component->dev, "Device reports bad header packet\n"); 283 wm0010_mark_boot_failure(wm0010); 284 break; 285 286 case 0x0fed0034: 287 dev_err(component->dev, "Device reports invalid packet type\n"); 288 wm0010_mark_boot_failure(wm0010); 289 break; 290 291 case 0x0fed0035: 292 dev_err(component->dev, "Device reports data before header error\n"); 293 wm0010_mark_boot_failure(wm0010); 294 break; 295 296 case 0x0fed0038: 297 dev_err(component->dev, "Device reports invalid PLL packet\n"); 298 break; 299 300 case 0x0fed003a: 301 dev_err(component->dev, "Device reports packet alignment error\n"); 302 wm0010_mark_boot_failure(wm0010); 303 break; 304 305 default: 306 dev_err(component->dev, "Unrecognised return 0x%x\n", 307 be32_to_cpu(out32[i])); 308 wm0010_mark_boot_failure(wm0010); 309 break; 310 } 311 312 if (wm0010->boot_failed) 313 break; 314 } 315 316 if (xfer->done) 317 complete(xfer->done); 318 } 319 320 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 321 { 322 int i; 323 324 for (i = 0; i < len / 8; i++) 325 data_out[i] = swab64(data_in[i]); 326 } 327 328 static int wm0010_firmware_load(const char *name, struct snd_soc_component *component) 329 { 330 struct spi_device *spi = to_spi_device(component->dev); 331 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 332 struct list_head xfer_list; 333 struct wm0010_boot_xfer *xfer; 334 int ret; 335 DECLARE_COMPLETION_ONSTACK(done); 336 const struct firmware *fw; 337 const struct dfw_binrec *rec; 338 const struct dfw_inforec *inforec; 339 u64 *img; 340 u8 *out, dsp; 341 u32 len, offset; 342 343 INIT_LIST_HEAD(&xfer_list); 344 345 ret = request_firmware(&fw, name, component->dev); 346 if (ret != 0) { 347 dev_err(component->dev, "Failed to request application(%s): %d\n", 348 name, ret); 349 return ret; 350 } 351 352 rec = (const struct dfw_binrec *)fw->data; 353 inforec = (const struct dfw_inforec *)rec->data; 354 offset = 0; 355 dsp = inforec->dsp_target; 356 wm0010->boot_failed = false; 357 if (WARN_ON(!list_empty(&xfer_list))) 358 return -EINVAL; 359 360 /* First record should be INFO */ 361 if (rec->command != DFW_CMD_INFO) { 362 dev_err(component->dev, "First record not INFO\r\n"); 363 ret = -EINVAL; 364 goto abort; 365 } 366 367 if (inforec->info_version != INFO_VERSION) { 368 dev_err(component->dev, 369 "Unsupported version (%02d) of INFO record\r\n", 370 inforec->info_version); 371 ret = -EINVAL; 372 goto abort; 373 } 374 375 dev_dbg(component->dev, "Version v%02d INFO record found\r\n", 376 inforec->info_version); 377 378 /* Check it's a DSP file */ 379 if (dsp != DEVICE_ID_WM0010) { 380 dev_err(component->dev, "Not a WM0010 firmware file.\r\n"); 381 ret = -EINVAL; 382 goto abort; 383 } 384 385 /* Skip the info record as we don't need to send it */ 386 offset += ((rec->length) + 8); 387 rec = (void *)&rec->data[rec->length]; 388 389 while (offset < fw->size) { 390 dev_dbg(component->dev, 391 "Packet: command %d, data length = 0x%x\r\n", 392 rec->command, rec->length); 393 len = rec->length + 8; 394 395 xfer = kzalloc_obj(*xfer); 396 if (!xfer) { 397 ret = -ENOMEM; 398 goto abort; 399 } 400 401 xfer->component = component; 402 list_add_tail(&xfer->list, &xfer_list); 403 404 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 405 if (!out) { 406 ret = -ENOMEM; 407 goto abort1; 408 } 409 xfer->t.rx_buf = out; 410 411 img = kzalloc(len, GFP_KERNEL | GFP_DMA); 412 if (!img) { 413 ret = -ENOMEM; 414 goto abort1; 415 } 416 xfer->t.tx_buf = img; 417 418 byte_swap_64((u64 *)&rec->command, img, len); 419 420 spi_message_init(&xfer->m); 421 xfer->m.complete = wm0010_boot_xfer_complete; 422 xfer->m.context = xfer; 423 xfer->t.len = len; 424 xfer->t.bits_per_word = 8; 425 426 if (!wm0010->pll_running) { 427 xfer->t.speed_hz = wm0010->sysclk / 6; 428 } else { 429 xfer->t.speed_hz = wm0010->max_spi_freq; 430 431 if (wm0010->board_max_spi_speed && 432 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 433 xfer->t.speed_hz = wm0010->board_max_spi_speed; 434 } 435 436 /* Store max usable spi frequency for later use */ 437 wm0010->max_spi_freq = xfer->t.speed_hz; 438 439 spi_message_add_tail(&xfer->t, &xfer->m); 440 441 offset += ((rec->length) + 8); 442 rec = (void *)&rec->data[rec->length]; 443 444 if (offset >= fw->size) { 445 dev_dbg(component->dev, "All transfers scheduled\n"); 446 xfer->done = &done; 447 } 448 449 ret = spi_async(spi, &xfer->m); 450 if (ret != 0) { 451 dev_err(component->dev, "Write failed: %d\n", ret); 452 goto abort1; 453 } 454 455 if (wm0010->boot_failed) { 456 dev_dbg(component->dev, "Boot fail!\n"); 457 ret = -EINVAL; 458 goto abort1; 459 } 460 } 461 462 wait_for_completion(&done); 463 464 ret = 0; 465 466 abort1: 467 while (!list_empty(&xfer_list)) { 468 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 469 list); 470 kfree(xfer->t.rx_buf); 471 kfree(xfer->t.tx_buf); 472 list_del(&xfer->list); 473 kfree(xfer); 474 } 475 476 abort: 477 release_firmware(fw); 478 return ret; 479 } 480 481 static int wm0010_stage2_load(struct snd_soc_component *component) 482 { 483 struct spi_device *spi = to_spi_device(component->dev); 484 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 485 const struct firmware *fw; 486 struct spi_message m; 487 struct spi_transfer t; 488 u32 *img; 489 u8 *out; 490 int i; 491 int ret = 0; 492 493 ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev); 494 if (ret != 0) { 495 dev_err(component->dev, "Failed to request stage2 loader: %d\n", 496 ret); 497 return ret; 498 } 499 500 dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 501 502 /* Copy to local buffer first as vmalloc causes problems for dma */ 503 img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA); 504 if (!img) { 505 ret = -ENOMEM; 506 goto abort2; 507 } 508 509 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA); 510 if (!out) { 511 ret = -ENOMEM; 512 goto abort1; 513 } 514 515 spi_message_init(&m); 516 memset(&t, 0, sizeof(t)); 517 t.rx_buf = out; 518 t.tx_buf = img; 519 t.len = fw->size; 520 t.bits_per_word = 8; 521 t.speed_hz = wm0010->sysclk / 10; 522 spi_message_add_tail(&t, &m); 523 524 dev_dbg(component->dev, "Starting initial download at %dHz\n", 525 t.speed_hz); 526 527 ret = spi_sync(spi, &m); 528 if (ret != 0) { 529 dev_err(component->dev, "Initial download failed: %d\n", ret); 530 goto abort; 531 } 532 533 /* Look for errors from the boot ROM */ 534 for (i = 0; i < fw->size; i++) { 535 if (out[i] != 0x55) { 536 dev_err(component->dev, "Boot ROM error: %x in %d\n", 537 out[i], i); 538 wm0010_mark_boot_failure(wm0010); 539 ret = -EBUSY; 540 goto abort; 541 } 542 } 543 abort: 544 kfree(out); 545 abort1: 546 kfree(img); 547 abort2: 548 release_firmware(fw); 549 550 return ret; 551 } 552 553 static int wm0010_boot(struct snd_soc_component *component) 554 { 555 struct spi_device *spi = to_spi_device(component->dev); 556 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 557 unsigned long flags; 558 int ret; 559 struct spi_message m; 560 struct spi_transfer t; 561 struct dfw_pllrec pll_rec; 562 u32 *p, len; 563 u64 *img_swap; 564 u8 *out; 565 int i; 566 567 spin_lock_irqsave(&wm0010->irq_lock, flags); 568 if (wm0010->state != WM0010_POWER_OFF) 569 dev_warn(wm0010->dev, "DSP already powered up!\n"); 570 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 571 572 if (wm0010->sysclk > 26000000) { 573 dev_err(component->dev, "Max DSP clock frequency is 26MHz\n"); 574 ret = -ECANCELED; 575 goto err; 576 } 577 578 mutex_lock(&wm0010->lock); 579 wm0010->pll_running = false; 580 581 dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 582 583 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 584 wm0010->core_supplies); 585 if (ret != 0) { 586 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 587 ret); 588 mutex_unlock(&wm0010->lock); 589 goto err; 590 } 591 592 ret = regulator_enable(wm0010->dbvdd); 593 if (ret != 0) { 594 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 595 goto err_core; 596 } 597 598 /* Release reset */ 599 gpiod_set_value_cansleep(wm0010->reset, 0); 600 spin_lock_irqsave(&wm0010->irq_lock, flags); 601 wm0010->state = WM0010_OUT_OF_RESET; 602 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 603 604 if (!wait_for_completion_timeout(&wm0010->boot_completion, 605 msecs_to_jiffies(20))) 606 dev_err(component->dev, "Failed to get interrupt from DSP\n"); 607 608 spin_lock_irqsave(&wm0010->irq_lock, flags); 609 wm0010->state = WM0010_BOOTROM; 610 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 611 612 ret = wm0010_stage2_load(component); 613 if (ret) 614 goto abort; 615 616 if (!wait_for_completion_timeout(&wm0010->boot_completion, 617 msecs_to_jiffies(20))) 618 dev_err(component->dev, "Failed to get interrupt from DSP loader.\n"); 619 620 spin_lock_irqsave(&wm0010->irq_lock, flags); 621 wm0010->state = WM0010_STAGE2; 622 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 623 624 /* Only initialise PLL if max_spi_freq initialised */ 625 if (wm0010->max_spi_freq) { 626 627 /* Initialise a PLL record */ 628 memset(&pll_rec, 0, sizeof(pll_rec)); 629 pll_rec.command = DFW_CMD_PLL; 630 pll_rec.length = (sizeof(pll_rec) - 8); 631 632 /* On wm0010 only the CLKCTRL1 value is used */ 633 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 634 635 ret = -ENOMEM; 636 len = pll_rec.length + 8; 637 out = kzalloc(len, GFP_KERNEL | GFP_DMA); 638 if (!out) 639 goto abort; 640 641 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA); 642 if (!img_swap) 643 goto abort_out; 644 645 /* We need to re-order for 0010 */ 646 byte_swap_64((u64 *)&pll_rec, img_swap, len); 647 648 spi_message_init(&m); 649 memset(&t, 0, sizeof(t)); 650 t.rx_buf = out; 651 t.tx_buf = img_swap; 652 t.len = len; 653 t.bits_per_word = 8; 654 t.speed_hz = wm0010->sysclk / 6; 655 spi_message_add_tail(&t, &m); 656 657 ret = spi_sync(spi, &m); 658 if (ret) { 659 dev_err(component->dev, "First PLL write failed: %d\n", ret); 660 goto abort_swap; 661 } 662 663 /* Use a second send of the message to get the return status */ 664 ret = spi_sync(spi, &m); 665 if (ret) { 666 dev_err(component->dev, "Second PLL write failed: %d\n", ret); 667 goto abort_swap; 668 } 669 670 p = (u32 *)out; 671 672 /* Look for PLL active code from the DSP */ 673 for (i = 0; i < len / 4; i++) { 674 if (*p == 0x0e00ed0f) { 675 dev_dbg(component->dev, "PLL packet received\n"); 676 wm0010->pll_running = true; 677 break; 678 } 679 p++; 680 } 681 682 kfree(img_swap); 683 kfree(out); 684 } else 685 dev_dbg(component->dev, "Not enabling DSP PLL."); 686 687 ret = wm0010_firmware_load("wm0010.dfw", component); 688 689 if (ret != 0) 690 goto abort; 691 692 spin_lock_irqsave(&wm0010->irq_lock, flags); 693 wm0010->state = WM0010_FIRMWARE; 694 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 695 696 mutex_unlock(&wm0010->lock); 697 698 return 0; 699 700 abort_swap: 701 kfree(img_swap); 702 abort_out: 703 kfree(out); 704 abort: 705 /* Put the chip back into reset */ 706 wm0010_halt(component); 707 mutex_unlock(&wm0010->lock); 708 return ret; 709 710 err_core: 711 mutex_unlock(&wm0010->lock); 712 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 713 wm0010->core_supplies); 714 err: 715 return ret; 716 } 717 718 static int wm0010_set_bias_level(struct snd_soc_component *component, 719 enum snd_soc_bias_level level) 720 { 721 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 722 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 723 724 switch (level) { 725 case SND_SOC_BIAS_ON: 726 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_PREPARE) 727 wm0010_boot(component); 728 break; 729 case SND_SOC_BIAS_PREPARE: 730 break; 731 case SND_SOC_BIAS_STANDBY: 732 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_PREPARE) { 733 scoped_guard(mutex, &wm0010->lock) 734 wm0010_halt(component); 735 } 736 break; 737 case SND_SOC_BIAS_OFF: 738 break; 739 } 740 741 return 0; 742 } 743 744 static int wm0010_set_sysclk(struct snd_soc_component *component, int source, 745 int clk_id, unsigned int freq, int dir) 746 { 747 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 748 unsigned int i; 749 750 wm0010->sysclk = freq; 751 752 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 753 wm0010->max_spi_freq = 0; 754 } else { 755 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 756 if (freq >= pll_clock_map[i].max_sysclk) { 757 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 758 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 759 break; 760 } 761 } 762 763 return 0; 764 } 765 766 static int wm0010_probe(struct snd_soc_component *component); 767 768 static const struct snd_soc_component_driver soc_component_dev_wm0010 = { 769 .probe = wm0010_probe, 770 .set_bias_level = wm0010_set_bias_level, 771 .set_sysclk = wm0010_set_sysclk, 772 .dapm_widgets = wm0010_dapm_widgets, 773 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 774 .dapm_routes = wm0010_dapm_routes, 775 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 776 .use_pmdown_time = 1, 777 .endianness = 1, 778 }; 779 780 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 781 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 782 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 783 SNDRV_PCM_FMTBIT_S32_LE) 784 785 static struct snd_soc_dai_driver wm0010_dai[] = { 786 { 787 .name = "wm0010-sdi1", 788 .playback = { 789 .stream_name = "SDI1 Playback", 790 .channels_min = 1, 791 .channels_max = 2, 792 .rates = WM0010_RATES, 793 .formats = WM0010_FORMATS, 794 }, 795 .capture = { 796 .stream_name = "SDI1 Capture", 797 .channels_min = 1, 798 .channels_max = 2, 799 .rates = WM0010_RATES, 800 .formats = WM0010_FORMATS, 801 }, 802 }, 803 { 804 .name = "wm0010-sdi2", 805 .playback = { 806 .stream_name = "SDI2 Playback", 807 .channels_min = 1, 808 .channels_max = 2, 809 .rates = WM0010_RATES, 810 .formats = WM0010_FORMATS, 811 }, 812 .capture = { 813 .stream_name = "SDI2 Capture", 814 .channels_min = 1, 815 .channels_max = 2, 816 .rates = WM0010_RATES, 817 .formats = WM0010_FORMATS, 818 }, 819 }, 820 }; 821 822 static irqreturn_t wm0010_irq(int irq, void *data) 823 { 824 struct wm0010_priv *wm0010 = data; 825 826 switch (wm0010->state) { 827 case WM0010_OUT_OF_RESET: 828 case WM0010_BOOTROM: 829 case WM0010_STAGE2: 830 scoped_guard(spinlock, &wm0010->irq_lock) 831 complete(&wm0010->boot_completion); 832 return IRQ_HANDLED; 833 default: 834 return IRQ_NONE; 835 } 836 837 return IRQ_NONE; 838 } 839 840 static int wm0010_probe(struct snd_soc_component *component) 841 { 842 struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component); 843 844 wm0010->component = component; 845 846 return 0; 847 } 848 849 static int wm0010_spi_probe(struct spi_device *spi) 850 { 851 int ret; 852 int trigger; 853 int irq; 854 struct wm0010_priv *wm0010; 855 856 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 857 GFP_KERNEL); 858 if (!wm0010) 859 return -ENOMEM; 860 861 mutex_init(&wm0010->lock); 862 spin_lock_init(&wm0010->irq_lock); 863 864 spi_set_drvdata(spi, wm0010); 865 wm0010->dev = &spi->dev; 866 867 if (dev_get_platdata(&spi->dev)) 868 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 869 sizeof(wm0010->pdata)); 870 871 init_completion(&wm0010->boot_completion); 872 873 wm0010->core_supplies[0].supply = "AVDD"; 874 wm0010->core_supplies[1].supply = "DCVDD"; 875 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 876 wm0010->core_supplies); 877 if (ret != 0) { 878 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 879 ret); 880 return ret; 881 } 882 883 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 884 if (IS_ERR(wm0010->dbvdd)) { 885 ret = PTR_ERR(wm0010->dbvdd); 886 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 887 return ret; 888 } 889 890 wm0010->reset = devm_gpiod_get(wm0010->dev, "reset", GPIOD_OUT_HIGH); 891 if (IS_ERR(wm0010->reset)) 892 return dev_err_probe(wm0010->dev, PTR_ERR(wm0010->reset), 893 "could not get RESET GPIO\n"); 894 gpiod_set_consumer_name(wm0010->reset, "wm0010 reset"); 895 896 wm0010->state = WM0010_POWER_OFF; 897 898 irq = spi->irq; 899 if (wm0010->pdata.irq_flags) 900 trigger = wm0010->pdata.irq_flags; 901 else 902 trigger = IRQF_TRIGGER_FALLING; 903 trigger |= IRQF_ONESHOT; 904 905 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger, 906 "wm0010", wm0010); 907 if (ret) { 908 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 909 irq, ret); 910 return ret; 911 } 912 wm0010->irq = irq; 913 914 ret = irq_set_irq_wake(irq, 1); 915 if (ret) { 916 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n", 917 irq, ret); 918 goto free_irq; 919 } 920 921 if (spi->max_speed_hz) 922 wm0010->board_max_spi_speed = spi->max_speed_hz; 923 else 924 wm0010->board_max_spi_speed = 0; 925 926 ret = devm_snd_soc_register_component(&spi->dev, 927 &soc_component_dev_wm0010, wm0010_dai, 928 ARRAY_SIZE(wm0010_dai)); 929 if (ret < 0) 930 goto disable_irq_wake; 931 932 return 0; 933 934 disable_irq_wake: 935 irq_set_irq_wake(wm0010->irq, 0); 936 937 free_irq: 938 if (wm0010->irq) 939 free_irq(wm0010->irq, wm0010); 940 941 return ret; 942 } 943 944 static void wm0010_spi_remove(struct spi_device *spi) 945 { 946 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 947 948 gpiod_set_value_cansleep(wm0010->reset, 1); 949 950 irq_set_irq_wake(wm0010->irq, 0); 951 952 if (wm0010->irq) 953 free_irq(wm0010->irq, wm0010); 954 } 955 956 static struct spi_driver wm0010_spi_driver = { 957 .driver = { 958 .name = "wm0010", 959 }, 960 .probe = wm0010_spi_probe, 961 .remove = wm0010_spi_remove, 962 }; 963 964 module_spi_driver(wm0010_spi_driver); 965 966 MODULE_DESCRIPTION("ASoC WM0010 driver"); 967 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 968 MODULE_LICENSE("GPL"); 969 970 MODULE_FIRMWARE("wm0010.dfw"); 971 MODULE_FIRMWARE("wm0010_stage2.bin"); 972