1 /* 2 * wm0010.c -- WM0010 DSP Driver 3 * 4 * Copyright 2012 Wolfson Microelectronics PLC. 5 * 6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 8 * Scott Ling <sl@opensource.wolfsonmicro.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/irqreturn.h> 18 #include <linux/init.h> 19 #include <linux/spi/spi.h> 20 #include <linux/firmware.h> 21 #include <linux/delay.h> 22 #include <linux/fs.h> 23 #include <linux/miscdevice.h> 24 #include <linux/gpio.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/mutex.h> 27 #include <linux/workqueue.h> 28 29 #include <sound/soc.h> 30 #include <sound/wm0010.h> 31 32 #define DEVICE_ID_WM0010 10 33 34 /* We only support v1 of the .dfw INFO record */ 35 #define INFO_VERSION 1 36 37 enum dfw_cmd { 38 DFW_CMD_FUSE = 0x01, 39 DFW_CMD_CODE_HDR, 40 DFW_CMD_CODE_DATA, 41 DFW_CMD_PLL, 42 DFW_CMD_INFO = 0xff 43 }; 44 45 struct dfw_binrec { 46 u8 command; 47 u32 length:24; 48 u32 address; 49 uint8_t data[0]; 50 } __packed; 51 52 struct dfw_inforec { 53 u8 info_version; 54 u8 tool_major_version; 55 u8 tool_minor_version; 56 u8 dsp_target; 57 }; 58 59 struct dfw_pllrec { 60 u8 command; 61 u32 length:24; 62 u32 address; 63 u32 clkctrl1; 64 u32 clkctrl2; 65 u32 clkctrl3; 66 u32 ldetctrl; 67 u32 uart_div; 68 u32 spi_div; 69 } __packed; 70 71 static struct pll_clock_map { 72 int max_sysclk; 73 int max_pll_spi_speed; 74 u32 pll_clkctrl1; 75 } pll_clock_map[] = { /* Dividers */ 76 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */ 77 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */ 78 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */ 79 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */ 80 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */ 81 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */ 82 }; 83 84 enum wm0010_state { 85 WM0010_POWER_OFF, 86 WM0010_OUT_OF_RESET, 87 WM0010_BOOTROM, 88 WM0010_STAGE2, 89 WM0010_FIRMWARE, 90 }; 91 92 struct wm0010_priv { 93 struct snd_soc_codec *codec; 94 95 struct mutex lock; 96 struct device *dev; 97 98 struct wm0010_pdata pdata; 99 100 int gpio_reset; 101 int gpio_reset_value; 102 103 struct regulator_bulk_data core_supplies[2]; 104 struct regulator *dbvdd; 105 106 int sysclk; 107 108 enum wm0010_state state; 109 bool boot_failed; 110 bool ready; 111 bool pll_running; 112 int max_spi_freq; 113 int board_max_spi_speed; 114 u32 pll_clkctrl1; 115 116 spinlock_t irq_lock; 117 int irq; 118 119 struct completion boot_completion; 120 }; 121 122 struct wm0010_spi_msg { 123 struct spi_message m; 124 struct spi_transfer t; 125 u8 *tx_buf; 126 u8 *rx_buf; 127 size_t len; 128 }; 129 130 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = { 131 SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0), 132 }; 133 134 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = { 135 { "SDI2 Capture", NULL, "SDI1 Playback" }, 136 { "SDI1 Capture", NULL, "SDI2 Playback" }, 137 138 { "SDI1 Capture", NULL, "CLKIN" }, 139 { "SDI2 Capture", NULL, "CLKIN" }, 140 { "SDI1 Playback", NULL, "CLKIN" }, 141 { "SDI2 Playback", NULL, "CLKIN" }, 142 }; 143 144 static const char *wm0010_state_to_str(enum wm0010_state state) 145 { 146 const char *state_to_str[] = { 147 "Power off", 148 "Out of reset", 149 "Boot ROM", 150 "Stage2", 151 "Firmware" 152 }; 153 154 if (state < 0 || state >= ARRAY_SIZE(state_to_str)) 155 return "null"; 156 return state_to_str[state]; 157 } 158 159 /* Called with wm0010->lock held */ 160 static void wm0010_halt(struct snd_soc_codec *codec) 161 { 162 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 163 unsigned long flags; 164 enum wm0010_state state; 165 166 /* Fetch the wm0010 state */ 167 spin_lock_irqsave(&wm0010->irq_lock, flags); 168 state = wm0010->state; 169 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 170 171 switch (state) { 172 case WM0010_POWER_OFF: 173 /* If there's nothing to do, bail out */ 174 return; 175 case WM0010_OUT_OF_RESET: 176 case WM0010_BOOTROM: 177 case WM0010_STAGE2: 178 case WM0010_FIRMWARE: 179 /* Remember to put chip back into reset */ 180 gpio_set_value_cansleep(wm0010->gpio_reset, 181 wm0010->gpio_reset_value); 182 /* Disable the regulators */ 183 regulator_disable(wm0010->dbvdd); 184 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 185 wm0010->core_supplies); 186 break; 187 } 188 189 spin_lock_irqsave(&wm0010->irq_lock, flags); 190 wm0010->state = WM0010_POWER_OFF; 191 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 192 } 193 194 struct wm0010_boot_xfer { 195 struct list_head list; 196 struct snd_soc_codec *codec; 197 struct completion *done; 198 struct spi_message m; 199 struct spi_transfer t; 200 }; 201 202 /* Called with wm0010->lock held */ 203 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010) 204 { 205 enum wm0010_state state; 206 unsigned long flags; 207 208 spin_lock_irqsave(&wm0010->irq_lock, flags); 209 state = wm0010->state; 210 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 211 212 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n", 213 wm0010_state_to_str(state), wm0010_state_to_str(state + 1)); 214 215 wm0010->boot_failed = true; 216 } 217 218 static void wm0010_boot_xfer_complete(void *data) 219 { 220 struct wm0010_boot_xfer *xfer = data; 221 struct snd_soc_codec *codec = xfer->codec; 222 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 223 u32 *out32 = xfer->t.rx_buf; 224 int i; 225 226 if (xfer->m.status != 0) { 227 dev_err(codec->dev, "SPI transfer failed: %d\n", 228 xfer->m.status); 229 wm0010_mark_boot_failure(wm0010); 230 if (xfer->done) 231 complete(xfer->done); 232 return; 233 } 234 235 for (i = 0; i < xfer->t.len / 4; i++) { 236 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]); 237 238 switch (be32_to_cpu(out32[i])) { 239 case 0xe0e0e0e0: 240 dev_err(codec->dev, 241 "%d: ROM error reported in stage 2\n", i); 242 wm0010_mark_boot_failure(wm0010); 243 break; 244 245 case 0x55555555: 246 if (wm0010->state < WM0010_STAGE2) 247 break; 248 dev_err(codec->dev, 249 "%d: ROM bootloader running in stage 2\n", i); 250 wm0010_mark_boot_failure(wm0010); 251 break; 252 253 case 0x0fed0000: 254 dev_dbg(codec->dev, "Stage2 loader running\n"); 255 break; 256 257 case 0x0fed0007: 258 dev_dbg(codec->dev, "CODE_HDR packet received\n"); 259 break; 260 261 case 0x0fed0008: 262 dev_dbg(codec->dev, "CODE_DATA packet received\n"); 263 break; 264 265 case 0x0fed0009: 266 dev_dbg(codec->dev, "Download complete\n"); 267 break; 268 269 case 0x0fed000c: 270 dev_dbg(codec->dev, "Application start\n"); 271 break; 272 273 case 0x0fed000e: 274 dev_dbg(codec->dev, "PLL packet received\n"); 275 wm0010->pll_running = true; 276 break; 277 278 case 0x0fed0025: 279 dev_err(codec->dev, "Device reports image too long\n"); 280 wm0010_mark_boot_failure(wm0010); 281 break; 282 283 case 0x0fed002c: 284 dev_err(codec->dev, "Device reports bad SPI packet\n"); 285 wm0010_mark_boot_failure(wm0010); 286 break; 287 288 case 0x0fed0031: 289 dev_err(codec->dev, "Device reports SPI read overflow\n"); 290 wm0010_mark_boot_failure(wm0010); 291 break; 292 293 case 0x0fed0032: 294 dev_err(codec->dev, "Device reports SPI underclock\n"); 295 wm0010_mark_boot_failure(wm0010); 296 break; 297 298 case 0x0fed0033: 299 dev_err(codec->dev, "Device reports bad header packet\n"); 300 wm0010_mark_boot_failure(wm0010); 301 break; 302 303 case 0x0fed0034: 304 dev_err(codec->dev, "Device reports invalid packet type\n"); 305 wm0010_mark_boot_failure(wm0010); 306 break; 307 308 case 0x0fed0035: 309 dev_err(codec->dev, "Device reports data before header error\n"); 310 wm0010_mark_boot_failure(wm0010); 311 break; 312 313 case 0x0fed0038: 314 dev_err(codec->dev, "Device reports invalid PLL packet\n"); 315 break; 316 317 case 0x0fed003a: 318 dev_err(codec->dev, "Device reports packet alignment error\n"); 319 wm0010_mark_boot_failure(wm0010); 320 break; 321 322 default: 323 dev_err(codec->dev, "Unrecognised return 0x%x\n", 324 be32_to_cpu(out32[i])); 325 wm0010_mark_boot_failure(wm0010); 326 break; 327 } 328 329 if (wm0010->boot_failed) 330 break; 331 } 332 333 if (xfer->done) 334 complete(xfer->done); 335 } 336 337 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len) 338 { 339 int i; 340 341 for (i = 0; i < len / 8; i++) 342 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i])); 343 } 344 345 static int wm0010_firmware_load(char *name, struct snd_soc_codec *codec) 346 { 347 struct spi_device *spi = to_spi_device(codec->dev); 348 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 349 struct list_head xfer_list; 350 struct wm0010_boot_xfer *xfer; 351 int ret; 352 struct completion done; 353 const struct firmware *fw; 354 const struct dfw_binrec *rec; 355 const struct dfw_inforec *inforec; 356 u64 *img; 357 u8 *out, dsp; 358 u32 len, offset; 359 360 INIT_LIST_HEAD(&xfer_list); 361 362 ret = request_firmware(&fw, name, codec->dev); 363 if (ret != 0) { 364 dev_err(codec->dev, "Failed to request application: %d\n", 365 ret); 366 return ret; 367 } 368 369 rec = (const struct dfw_binrec *)fw->data; 370 inforec = (const struct dfw_inforec *)rec->data; 371 offset = 0; 372 dsp = inforec->dsp_target; 373 wm0010->boot_failed = false; 374 BUG_ON(!list_empty(&xfer_list)); 375 init_completion(&done); 376 377 /* First record should be INFO */ 378 if (rec->command != DFW_CMD_INFO) { 379 dev_err(codec->dev, "First record not INFO\r\n"); 380 ret = -EINVAL; 381 goto abort; 382 } 383 384 if (inforec->info_version != INFO_VERSION) { 385 dev_err(codec->dev, 386 "Unsupported version (%02d) of INFO record\r\n", 387 inforec->info_version); 388 ret = -EINVAL; 389 goto abort; 390 } 391 392 dev_dbg(codec->dev, "Version v%02d INFO record found\r\n", 393 inforec->info_version); 394 395 /* Check it's a DSP file */ 396 if (dsp != DEVICE_ID_WM0010) { 397 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n"); 398 ret = -EINVAL; 399 goto abort; 400 } 401 402 /* Skip the info record as we don't need to send it */ 403 offset += ((rec->length) + 8); 404 rec = (void *)&rec->data[rec->length]; 405 406 while (offset < fw->size) { 407 dev_dbg(codec->dev, 408 "Packet: command %d, data length = 0x%x\r\n", 409 rec->command, rec->length); 410 len = rec->length + 8; 411 412 out = kzalloc(len, GFP_KERNEL); 413 if (!out) { 414 dev_err(codec->dev, 415 "Failed to allocate RX buffer\n"); 416 ret = -ENOMEM; 417 goto abort1; 418 } 419 420 img = kzalloc(len, GFP_KERNEL); 421 if (!img) { 422 dev_err(codec->dev, 423 "Failed to allocate image buffer\n"); 424 ret = -ENOMEM; 425 goto abort1; 426 } 427 428 byte_swap_64((u64 *)&rec->command, img, len); 429 430 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL); 431 if (!xfer) { 432 dev_err(codec->dev, "Failed to allocate xfer\n"); 433 ret = -ENOMEM; 434 goto abort1; 435 } 436 437 xfer->codec = codec; 438 list_add_tail(&xfer->list, &xfer_list); 439 440 spi_message_init(&xfer->m); 441 xfer->m.complete = wm0010_boot_xfer_complete; 442 xfer->m.context = xfer; 443 xfer->t.tx_buf = img; 444 xfer->t.rx_buf = out; 445 xfer->t.len = len; 446 xfer->t.bits_per_word = 8; 447 448 if (!wm0010->pll_running) { 449 xfer->t.speed_hz = wm0010->sysclk / 6; 450 } else { 451 xfer->t.speed_hz = wm0010->max_spi_freq; 452 453 if (wm0010->board_max_spi_speed && 454 (wm0010->board_max_spi_speed < wm0010->max_spi_freq)) 455 xfer->t.speed_hz = wm0010->board_max_spi_speed; 456 } 457 458 /* Store max usable spi frequency for later use */ 459 wm0010->max_spi_freq = xfer->t.speed_hz; 460 461 spi_message_add_tail(&xfer->t, &xfer->m); 462 463 offset += ((rec->length) + 8); 464 rec = (void *)&rec->data[rec->length]; 465 466 if (offset >= fw->size) { 467 dev_dbg(codec->dev, "All transfers scheduled\n"); 468 xfer->done = &done; 469 } 470 471 ret = spi_async(spi, &xfer->m); 472 if (ret != 0) { 473 dev_err(codec->dev, "Write failed: %d\n", ret); 474 goto abort1; 475 } 476 477 if (wm0010->boot_failed) { 478 dev_dbg(codec->dev, "Boot fail!\n"); 479 ret = -EINVAL; 480 goto abort1; 481 } 482 } 483 484 wait_for_completion(&done); 485 486 ret = 0; 487 488 abort1: 489 while (!list_empty(&xfer_list)) { 490 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer, 491 list); 492 kfree(xfer->t.rx_buf); 493 kfree(xfer->t.tx_buf); 494 list_del(&xfer->list); 495 kfree(xfer); 496 } 497 498 abort: 499 release_firmware(fw); 500 return ret; 501 } 502 503 static int wm0010_stage2_load(struct snd_soc_codec *codec) 504 { 505 struct spi_device *spi = to_spi_device(codec->dev); 506 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 507 const struct firmware *fw; 508 struct spi_message m; 509 struct spi_transfer t; 510 u32 *img; 511 u8 *out; 512 int i; 513 int ret = 0; 514 515 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev); 516 if (ret != 0) { 517 dev_err(codec->dev, "Failed to request stage2 loader: %d\n", 518 ret); 519 return ret; 520 } 521 522 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size); 523 524 /* Copy to local buffer first as vmalloc causes problems for dma */ 525 img = kzalloc(fw->size, GFP_KERNEL); 526 if (!img) { 527 dev_err(codec->dev, "Failed to allocate image buffer\n"); 528 ret = -ENOMEM; 529 goto abort2; 530 } 531 532 out = kzalloc(fw->size, GFP_KERNEL); 533 if (!out) { 534 dev_err(codec->dev, "Failed to allocate output buffer\n"); 535 ret = -ENOMEM; 536 goto abort1; 537 } 538 539 memcpy(img, &fw->data[0], fw->size); 540 541 spi_message_init(&m); 542 memset(&t, 0, sizeof(t)); 543 t.rx_buf = out; 544 t.tx_buf = img; 545 t.len = fw->size; 546 t.bits_per_word = 8; 547 t.speed_hz = wm0010->sysclk / 10; 548 spi_message_add_tail(&t, &m); 549 550 dev_dbg(codec->dev, "Starting initial download at %dHz\n", 551 t.speed_hz); 552 553 ret = spi_sync(spi, &m); 554 if (ret != 0) { 555 dev_err(codec->dev, "Initial download failed: %d\n", ret); 556 goto abort; 557 } 558 559 /* Look for errors from the boot ROM */ 560 for (i = 0; i < fw->size; i++) { 561 if (out[i] != 0x55) { 562 dev_err(codec->dev, "Boot ROM error: %x in %d\n", 563 out[i], i); 564 wm0010_mark_boot_failure(wm0010); 565 ret = -EBUSY; 566 goto abort; 567 } 568 } 569 abort: 570 kfree(out); 571 abort1: 572 kfree(img); 573 abort2: 574 release_firmware(fw); 575 576 return ret; 577 } 578 579 static int wm0010_boot(struct snd_soc_codec *codec) 580 { 581 struct spi_device *spi = to_spi_device(codec->dev); 582 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 583 unsigned long flags; 584 int ret; 585 const struct firmware *fw; 586 struct spi_message m; 587 struct spi_transfer t; 588 struct dfw_pllrec pll_rec; 589 u32 *p, len; 590 u64 *img_swap; 591 u8 *out; 592 int i; 593 594 spin_lock_irqsave(&wm0010->irq_lock, flags); 595 if (wm0010->state != WM0010_POWER_OFF) 596 dev_warn(wm0010->dev, "DSP already powered up!\n"); 597 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 598 599 if (wm0010->sysclk > 26000000) { 600 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n"); 601 ret = -ECANCELED; 602 goto err; 603 } 604 605 mutex_lock(&wm0010->lock); 606 wm0010->pll_running = false; 607 608 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq); 609 610 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies), 611 wm0010->core_supplies); 612 if (ret != 0) { 613 dev_err(&spi->dev, "Failed to enable core supplies: %d\n", 614 ret); 615 mutex_unlock(&wm0010->lock); 616 goto err; 617 } 618 619 ret = regulator_enable(wm0010->dbvdd); 620 if (ret != 0) { 621 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret); 622 goto err_core; 623 } 624 625 /* Release reset */ 626 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value); 627 spin_lock_irqsave(&wm0010->irq_lock, flags); 628 wm0010->state = WM0010_OUT_OF_RESET; 629 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 630 631 /* First the bootloader */ 632 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev); 633 if (ret != 0) { 634 dev_err(codec->dev, "Failed to request stage2 loader: %d\n", 635 ret); 636 goto abort; 637 } 638 639 if (!wait_for_completion_timeout(&wm0010->boot_completion, 640 msecs_to_jiffies(20))) 641 dev_err(codec->dev, "Failed to get interrupt from DSP\n"); 642 643 spin_lock_irqsave(&wm0010->irq_lock, flags); 644 wm0010->state = WM0010_BOOTROM; 645 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 646 647 ret = wm0010_stage2_load(codec); 648 if (ret) 649 goto abort; 650 651 if (!wait_for_completion_timeout(&wm0010->boot_completion, 652 msecs_to_jiffies(20))) 653 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n"); 654 655 spin_lock_irqsave(&wm0010->irq_lock, flags); 656 wm0010->state = WM0010_STAGE2; 657 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 658 659 /* Only initialise PLL if max_spi_freq initialised */ 660 if (wm0010->max_spi_freq) { 661 662 /* Initialise a PLL record */ 663 memset(&pll_rec, 0, sizeof(pll_rec)); 664 pll_rec.command = DFW_CMD_PLL; 665 pll_rec.length = (sizeof(pll_rec) - 8); 666 667 /* On wm0010 only the CLKCTRL1 value is used */ 668 pll_rec.clkctrl1 = wm0010->pll_clkctrl1; 669 670 len = pll_rec.length + 8; 671 out = kzalloc(len, GFP_KERNEL); 672 if (!out) { 673 dev_err(codec->dev, 674 "Failed to allocate RX buffer\n"); 675 goto abort; 676 } 677 678 img_swap = kzalloc(len, GFP_KERNEL); 679 if (!img_swap) { 680 dev_err(codec->dev, 681 "Failed to allocate image buffer\n"); 682 goto abort; 683 } 684 685 /* We need to re-order for 0010 */ 686 byte_swap_64((u64 *)&pll_rec, img_swap, len); 687 688 spi_message_init(&m); 689 memset(&t, 0, sizeof(t)); 690 t.rx_buf = out; 691 t.tx_buf = img_swap; 692 t.len = len; 693 t.bits_per_word = 8; 694 t.speed_hz = wm0010->sysclk / 6; 695 spi_message_add_tail(&t, &m); 696 697 ret = spi_sync(spi, &m); 698 if (ret != 0) { 699 dev_err(codec->dev, "First PLL write failed: %d\n", ret); 700 goto abort; 701 } 702 703 /* Use a second send of the message to get the return status */ 704 ret = spi_sync(spi, &m); 705 if (ret != 0) { 706 dev_err(codec->dev, "Second PLL write failed: %d\n", ret); 707 goto abort; 708 } 709 710 p = (u32 *)out; 711 712 /* Look for PLL active code from the DSP */ 713 for (i = 0; i < len / 4; i++) { 714 if (*p == 0x0e00ed0f) { 715 dev_dbg(codec->dev, "PLL packet received\n"); 716 wm0010->pll_running = true; 717 break; 718 } 719 p++; 720 } 721 722 kfree(img_swap); 723 kfree(out); 724 } else 725 dev_dbg(codec->dev, "Not enabling DSP PLL."); 726 727 ret = wm0010_firmware_load("wm0010.dfw", codec); 728 729 if (ret != 0) 730 goto abort; 731 732 spin_lock_irqsave(&wm0010->irq_lock, flags); 733 wm0010->state = WM0010_FIRMWARE; 734 spin_unlock_irqrestore(&wm0010->irq_lock, flags); 735 736 mutex_unlock(&wm0010->lock); 737 738 return 0; 739 740 abort: 741 /* Put the chip back into reset */ 742 wm0010_halt(codec); 743 mutex_unlock(&wm0010->lock); 744 return ret; 745 746 err_core: 747 mutex_unlock(&wm0010->lock); 748 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies), 749 wm0010->core_supplies); 750 err: 751 return ret; 752 } 753 754 static int wm0010_set_bias_level(struct snd_soc_codec *codec, 755 enum snd_soc_bias_level level) 756 { 757 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 758 759 switch (level) { 760 case SND_SOC_BIAS_ON: 761 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) 762 wm0010_boot(codec); 763 break; 764 case SND_SOC_BIAS_PREPARE: 765 break; 766 case SND_SOC_BIAS_STANDBY: 767 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) { 768 mutex_lock(&wm0010->lock); 769 wm0010_halt(codec); 770 mutex_unlock(&wm0010->lock); 771 } 772 break; 773 case SND_SOC_BIAS_OFF: 774 break; 775 } 776 777 codec->dapm.bias_level = level; 778 779 return 0; 780 } 781 782 static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source, 783 int clk_id, unsigned int freq, int dir) 784 { 785 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 786 unsigned int i; 787 788 wm0010->sysclk = freq; 789 790 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) { 791 wm0010->max_spi_freq = 0; 792 } else { 793 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++) 794 if (freq >= pll_clock_map[i].max_sysclk) 795 break; 796 797 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed; 798 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1; 799 } 800 801 return 0; 802 } 803 804 static int wm0010_probe(struct snd_soc_codec *codec); 805 806 static struct snd_soc_codec_driver soc_codec_dev_wm0010 = { 807 .probe = wm0010_probe, 808 .set_bias_level = wm0010_set_bias_level, 809 .set_sysclk = wm0010_set_sysclk, 810 .idle_bias_off = true, 811 812 .dapm_widgets = wm0010_dapm_widgets, 813 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets), 814 .dapm_routes = wm0010_dapm_routes, 815 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes), 816 }; 817 818 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 819 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 820 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 821 SNDRV_PCM_FMTBIT_S32_LE) 822 823 static struct snd_soc_dai_driver wm0010_dai[] = { 824 { 825 .name = "wm0010-sdi1", 826 .playback = { 827 .stream_name = "SDI1 Playback", 828 .channels_min = 1, 829 .channels_max = 2, 830 .rates = WM0010_RATES, 831 .formats = WM0010_FORMATS, 832 }, 833 .capture = { 834 .stream_name = "SDI1 Capture", 835 .channels_min = 1, 836 .channels_max = 2, 837 .rates = WM0010_RATES, 838 .formats = WM0010_FORMATS, 839 }, 840 }, 841 { 842 .name = "wm0010-sdi2", 843 .playback = { 844 .stream_name = "SDI2 Playback", 845 .channels_min = 1, 846 .channels_max = 2, 847 .rates = WM0010_RATES, 848 .formats = WM0010_FORMATS, 849 }, 850 .capture = { 851 .stream_name = "SDI2 Capture", 852 .channels_min = 1, 853 .channels_max = 2, 854 .rates = WM0010_RATES, 855 .formats = WM0010_FORMATS, 856 }, 857 }, 858 }; 859 860 static irqreturn_t wm0010_irq(int irq, void *data) 861 { 862 struct wm0010_priv *wm0010 = data; 863 864 switch (wm0010->state) { 865 case WM0010_OUT_OF_RESET: 866 case WM0010_BOOTROM: 867 case WM0010_STAGE2: 868 spin_lock(&wm0010->irq_lock); 869 complete(&wm0010->boot_completion); 870 spin_unlock(&wm0010->irq_lock); 871 return IRQ_HANDLED; 872 default: 873 return IRQ_NONE; 874 } 875 876 return IRQ_NONE; 877 } 878 879 static int wm0010_probe(struct snd_soc_codec *codec) 880 { 881 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec); 882 883 wm0010->codec = codec; 884 885 return 0; 886 } 887 888 static int wm0010_spi_probe(struct spi_device *spi) 889 { 890 unsigned long gpio_flags; 891 int ret; 892 int trigger; 893 int irq; 894 struct wm0010_priv *wm0010; 895 896 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010), 897 GFP_KERNEL); 898 if (!wm0010) 899 return -ENOMEM; 900 901 mutex_init(&wm0010->lock); 902 spin_lock_init(&wm0010->irq_lock); 903 904 spi_set_drvdata(spi, wm0010); 905 wm0010->dev = &spi->dev; 906 907 if (dev_get_platdata(&spi->dev)) 908 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev), 909 sizeof(wm0010->pdata)); 910 911 init_completion(&wm0010->boot_completion); 912 913 wm0010->core_supplies[0].supply = "AVDD"; 914 wm0010->core_supplies[1].supply = "DCVDD"; 915 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies), 916 wm0010->core_supplies); 917 if (ret != 0) { 918 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n", 919 ret); 920 return ret; 921 } 922 923 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD"); 924 if (IS_ERR(wm0010->dbvdd)) { 925 ret = PTR_ERR(wm0010->dbvdd); 926 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret); 927 return ret; 928 } 929 930 if (wm0010->pdata.gpio_reset) { 931 wm0010->gpio_reset = wm0010->pdata.gpio_reset; 932 933 if (wm0010->pdata.reset_active_high) 934 wm0010->gpio_reset_value = 1; 935 else 936 wm0010->gpio_reset_value = 0; 937 938 if (wm0010->gpio_reset_value) 939 gpio_flags = GPIOF_OUT_INIT_HIGH; 940 else 941 gpio_flags = GPIOF_OUT_INIT_LOW; 942 943 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset, 944 gpio_flags, "wm0010 reset"); 945 if (ret < 0) { 946 dev_err(wm0010->dev, 947 "Failed to request GPIO for DSP reset: %d\n", 948 ret); 949 return ret; 950 } 951 } else { 952 dev_err(wm0010->dev, "No reset GPIO configured\n"); 953 return -EINVAL; 954 } 955 956 wm0010->state = WM0010_POWER_OFF; 957 958 irq = spi->irq; 959 if (wm0010->pdata.irq_flags) 960 trigger = wm0010->pdata.irq_flags; 961 else 962 trigger = IRQF_TRIGGER_FALLING; 963 trigger |= IRQF_ONESHOT; 964 965 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT, 966 "wm0010", wm0010); 967 if (ret) { 968 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n", 969 irq, ret); 970 return ret; 971 } 972 wm0010->irq = irq; 973 974 if (spi->max_speed_hz) 975 wm0010->board_max_spi_speed = spi->max_speed_hz; 976 else 977 wm0010->board_max_spi_speed = 0; 978 979 ret = snd_soc_register_codec(&spi->dev, 980 &soc_codec_dev_wm0010, wm0010_dai, 981 ARRAY_SIZE(wm0010_dai)); 982 if (ret < 0) 983 return ret; 984 985 return 0; 986 } 987 988 static int wm0010_spi_remove(struct spi_device *spi) 989 { 990 struct wm0010_priv *wm0010 = spi_get_drvdata(spi); 991 992 snd_soc_unregister_codec(&spi->dev); 993 994 gpio_set_value_cansleep(wm0010->gpio_reset, 995 wm0010->gpio_reset_value); 996 997 if (wm0010->irq) 998 free_irq(wm0010->irq, wm0010); 999 1000 return 0; 1001 } 1002 1003 static struct spi_driver wm0010_spi_driver = { 1004 .driver = { 1005 .name = "wm0010", 1006 .bus = &spi_bus_type, 1007 .owner = THIS_MODULE, 1008 }, 1009 .probe = wm0010_spi_probe, 1010 .remove = wm0010_spi_remove, 1011 }; 1012 1013 module_spi_driver(wm0010_spi_driver); 1014 1015 MODULE_DESCRIPTION("ASoC WM0010 driver"); 1016 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1017 MODULE_LICENSE("GPL"); 1018